Annealed transistor and method for annealing a field-effect transistor

Abstract

A method of forming a transistor includes providing a substrate with a silicon dioxide layer disposed thereon and a gate electrode on the silicon dioxide layer. A thin-film oxide layer is formed on the gate electrode and the silicon dioxide layer. The thin-film oxide layer is annealed by applying plasma generated from diatomic oxygen using an oxygen source. This plasma annealing process modifies the thin-film oxide layer, enhancing its dielectric properties and interface quality with the channel layer. The method results in various types of transistors, including thin-film transistors, amorphous oxide semiconductor transistors, and ferroelectric field-effect transistors, which can be configured as switches, amplifiers, or memory devices.

Description

Attorney Docket No. P24-189-SEC-WO01ANNEALED TRANSISTOR AND METHOD FOR ANNEALING A FIELD-EFFECT TRANSISTORCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 714,205, filed on October 31, 2024; and U.S. Provisional Patent Application No. 63 / 744,593, filed on January 13, 2025, the entire contents of both are hereby incorporated by reference in their entirety.BACKGROUNDRelevant FieldDescription of Related Art

[0002] Field-effect transistors (FETs) are components in modern electronic devices, used extensively in integrated circuits for a wide range of applications, including computing, communication, and data storage. Traditional FETs rely on silicon-based materials and processes to achieve desired electrical characteristics. However, as technology advances, there is a growing need for transistors with enhanced performance, such as lower power consumption, higher speed, and greater reliability.

[0003] One type of FETs uses ferroelectric materials leading to the development of ferroelectric field-effect transistors (FeFETs). FeFETs leverage the unique properties of ferroelectric materials. The ferroelectric effect in ferroelectric materials is a phenomenon where certain materials exhibit a spontaneous electric polarization that can be reversed by the application of an external electric field. This effect is analogous to ferromagnetism, where materials exhibit a spontaneous magnetic alignment. In ferroelectric materials, the electric dipoles within the crystal lattice align in a uniform direction, creating a net polarization. This polarization can be switched between different stable states by applying an electric field, making these materials highly suitable for non-volatile memory applications.

[0004] The ferroelectric effect is characterized by a hysteresis loop in the polarization versus electric field graph, indicating the material's ability to retain its polarization state even after the external field is removed. This property enables ferroelectric materials to function as memory elements in ferroelectric field-effect transistors (FeFETs), where they can store binary data or analog values with high retention and endurance. The manipulation of the ferroelectric effect through anAttorney Docket No. P24-189-SEC-WO01 annealing process used for optimizing the performance of FeFETs in some electronic devices.SUMMARY

[0005] In one embodiment, a method of forming a transistor may include providing a substrate with a silicon dioxide layer disposed on it, and a gate electrode disposed on the silicon dioxide layer. A thin-film oxide layer may be formed on the gate electrode and the silicon dioxide layer. Plasma may be generated from diatomic oxygen using an oxygen source, and this plasma may be applied to the thin-film oxide layer to anneal it. In some embodiments, the transistor formed may be a thin-film transistor or an amorphous oxide semiconductor (AOS) transistor. Optionally, the substrate may be a silicon substrate.

[0006] In certain embodiments, the oxygen source may comprise a 20% oxygen / gas mixture. In some instances, the plasma may be generated in a plasma chamber. The plasma may be generated using a remote plasma source in certain embodiments. Alternatively, the plasma may be generated using a direct plasma source.

[0007] In some embodiments, the method may further include applying radio frequency energy to the diatomic oxygen to generate and / or strike the plasma. Optionally, the radio frequency energy may be applied at approximately 800 watts of power. In certain embodiments, the radio frequency energy may be applied at about 500 to 800 watts of power. In other embodiments, the radio frequency energy may be applied at about 500 to 1 ,000 watts of power. Optionally, the application of the plasma may be performed for about 5 minutes. In some embodiments, the plasma may be applied for a duration ranging from 1 to 30 minutes.

[0008] Additionally, the method may involve placing the transistor in a chamber and setting the temperature to 200°C during annealing. Alternatively, the transistor may be placed in a chamber with a temperature set between 100°C and 500°C during annealing.

[0009] In certain embodiments, the transistor may have a gate electrode length of about 3 micrometers. Optionally, the transistor may have a length of about 3 micrometers. In some embodiments, the transistor may have a channel width selected from 5 micrometers, 10 micrometers, 20 micrometers, or 50 micrometers. Alternatively, the transistor may have a channel width less than 50 micrometers. Optionally, the transistor may have a width selected from 5 micrometers, 10Attorney Docket No. P24-189-SEC-WO01 micrometers, 20 micrometers, or 50 micrometers. In some cases, the transistor may have a width of less than 50 micrometers. The gate electrode may be made from the gate electrode includes at least one of a metal, tungsten (W), titanium nitride (TiN), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), ruthenium (Ru), hafnium (Hf), chromium (Cr), a poly silicon, a metal silicide, a nickel silicide, a cobalt silicide, a titanium silicide, a metal nitrides, and a metal alloy.

[0010] Additionally, the method may include forming a source region and a drain region adjacent to the gate electrode on the substrate. In some embodiments, the transistor may have an overlap of approximately 2 micrometers between the gate electrode and the source region. Alternatively, the overlap between the gate electrode and the source region may be less than 5 micrometers. Additionally, the transistor may have an overlap of approximately 2 micrometers between the gate electrode and the drain region. Alternatively, the overlap between the gate electrode and the drain region may be less than 5 micrometers.

[0011] Optionally, the thin-film oxide layer may be a high-k dielectric material. In some embodiments, the thin-film oxide layer may be a ferroelectric oxide. In certain embodiments, the transistor may be configured as a field-effect transistor. In some embodiments, where the transistor is configured as a field-effect transistor, the transistor may be configured as a switch, and the method may further include switching the transistor between at least two states. Alternatively, the transistor may be configured as an amplifier, and the method may further involve applying a signal to the transistor to amplify the signal. In other embodiments, the transistor may be configured as a memory device, and the method may include reading a state of the transistor and relating the state to a memory value. Additionally, the field-effect transistor may be a ferroelectric field-effect transistor.

[0012] In some embodiments, a transistor may include a substrate with a silicon dioxide layer disposed on it. A gate electrode may be disposed on the silicon dioxide layer, and a thin-film oxide layer may be formed on the gate electrode and the silicon dioxide layer. The thin-film oxide layer may have been plasma annealed by exposure to a plasma of diatomic oxygen generated from an oxygen source. The transistor may be a thin-film transistor or an amorphous oxide semiconductor (AOS) transistor. The substrate may be a silicon substrate, and the oxygen source may comprise a 20% oxygen / gas mixture.Attorney Docket No. P24-189-SEC-WO01

[0013] The plasma used for annealing the thin-film oxide layer may be generated in a plasma chamber. In some embodiments, the plasma may be generated using a remote plasma source or a direct plasma source. The plasma may be created by applying radio frequency energy to the diatomic oxygen. The radio frequency energy applied to generate the plasma may be about 800 watts of power, or it may range from about 500 to 800 watts, or about 500 to 1,000 watts of power.

[0014] The thin-film oxide layer may be annealed for about 5 minutes, or for a duration ranging from 1 to 30 minutes. The annealing process may occur at a temperature of 200°C, or within a temperature range from 100°C to 500°C.

[0015] The gate electrode may have a length of about 3 micrometers, and the transistor may have a length of about 3 micrometers. The transistor may have a channel width selected from 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers, or it may have a channel width less than 50 micrometers. Similarly, the transistor may have a width selected from 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers, or it may have a width of less than 50 micrometers.

[0016] In some embodiments, the transistor may further include a source region and a drain region adjacent to the gate electrode on the substrate. There may be an overlap between the gate electrode and the source region of about 2 micrometers, or less than 5 micrometers. Likewise, there may be an overlap between the gate electrode and the drain region of about 2 micrometers, or less than 5 micrometers.

[0017] The thin-film oxide layer may be a high-k dielectric material or a ferroelectric oxide. The transistor may be configured as a field-effect transistor. In some embodiments, the transistor may operate as a switch, capable of switching between at least two states, function as an amplifier to amplify an input signal, or be configured as a memory device capable of storing and representing a memory state corresponding to a state of the transistor. The field-effect transistor may be a ferroelectric field-effect transistor.

[0018] In some embodiments, a method of operating a transistor may involve providing a transistor as described herein. The method may include applying a first voltage to the gate electrode and then applying a second voltage to the gate electrode after applying the first voltage, wherein the first voltage and the second voltage are different. A voltage may be applied to a source and a drain region such that the gate voltage controls the current flowing between the source and drain region.Attorney Docket No. P24-189-SEC-WO01BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other aspects will become more apparent from the following detailed description of the various embodiments of the present disclosure with reference to the drawings wherein:

[0020] FIG. 1 shows a block diagram of an artificial intelligence accelerator that utilizes FeFET memory in accordance with an embodiment of the present disclosure;

[0021] FIG. 2 shows a diagram of a memory cell utilizing a FeFET transistor in accordance with an embodiment of the present disclosure;

[0022] FIG. 3 illustrates operating characteristics of the FeFET of FIG. 2 when used to store binary states in accordance with an embodiment of the present disclosure;

[0023] FIG. 4 illustrates operating characteristics of the FeFET of FIG. 2 when used to store a continuous value, such as a weight of a neuromorphic cell, in accordance with an embodiment of the present disclosure;

[0024] FIG. 5 shows a memory array utilizing FeFET transistors in accordance with an embodiment of the present disclosure;

[0025] FIG. 6 shows an illustration of a process of plasma annealing a FET in accordance with an embodiment of the present disclosure;

[0026] FIG. 7 shows a flow chart diagram of a method of annealing a FET in accordance with an embodiment of the present disclosure; and

[0027] Fig 8 shows a control, a plasma annealed, and a thermal annealed FET results in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0028] FIG. 1 shows a block diagram of an Artificial Intelligence (“Al”) accelerator 100 that utilizes FeFET memory 112 in accordance with an embodiment of the present disclosure. The Al accelerator 100 may be implemented on a semiconductor device, a custom integrate circuit, an application-specific integrated circuit (“ASIC”), a graphics processing unit (“GPU”), a field-programmable gate array (“FPGA”), any device known to one of ordinary skill in the art, or some combination thereof. The Al accelerator 100 includes a processing element (“PE”) array 102 that performs the majority of Al computation. The PE array 102 performs the Al computations using a plurality of processing elements 110. These processing elements 110 may form a manycore processor where each processing element 110 performs Al calculations inAttorney Docket No. P24-189-SEC-WO01 parallel with the other processing elements 110. Additionally or alternatively, the processing elements 110 may include an arithmetic logic unit, a neuromorphic computation element, a processor, a multicore processor, a manycore processor, a reduced instruction set computer (“RISC”) processor, and / or other computation device known to one of ordinary skill in the relevant art. The processing elements 110 may each be part of a neuromorphic circuit; for example, the processing elements 110 may each form a portion of an artificial neural network where each accompanying memory 112 is an analog memory configured to act as parameters for artificial neurons (e.g., weights), in some specific embodiments. Each processing element 110 and its respective memory 112 may form an in-memory processing architecture, e.g., to enable efficient and parallel execution of multiply-accumulate operations, in yet additional embodiments.

[0029] The memories 112 are implemented using FeFETs described in further detail below. The memories 112 may store binary data and / or may store analog data in some specific embodiments. Additionally or alternatively, the memories 112 may store a combination of binary and analog data in some embodiments.

[0030] The Al accelerator 100 may also include a shared memory 108. Computations computed by the PE array 102 may be stored and / or instructed by information stored on a shared memory 104 internal to the Al accelerator and / or shared memory 108 stored off of the Al accelerator 100. The shared memory 104 and / or the shared memory 108 may utilize the FeFET memory cells as described herein. The Al accelerator 100 also includes a Network-on-Chip 106 for communicating with other devices, e.g., via TCP / IP, Ethernet, Wifi, etc.

[0031] FIG. 2 shows a diagram of a memory cell 200 utilizing a FeFET 202 in accordance with an embodiment of the present disclosure. The memory cell 200 also includes a program-signal circuit 206 and a sense circuit 204. The program-signal circuit 206 may apply one or more positive-voltage pulse signals or negative-voltage pulse signals to program the FeFET 202. The FeFET 202 includes a drain 210, a source 212, and a gate 208. However, because of the symmetry of the FeFET 202, the operation of the drain 210 and source 212 may be reversed.

[0032] The FeFET 202 may be powered by a Vread voltage that is relative to a voltage SL. The Vread voltage may be a ground, may be a fixed voltage, may be a programmable voltage, may be a variable voltage, may be coupled to a ground or a voltage source via another transistor (not shown), etc. Similarly, the SL reference mayAttorney Docket No. P24-189-SEC-WO01 be a ground, may be a fixed voltage, may be a programmable voltage, may be a variable voltage, may be coupled to a ground or a voltage source via another transistor (not shown), etc. For example, the voltage Vread and the voltage SL may be predetermined values to enable a fixed voltage between the drain 210 and the source 212, for example, intermittently or continuously, etc. In other embodiments, the voltage Vread and the voltage SL may be set to enable a constant current from the drain 210 to the source 212, for example intermittently or continuously, etc.

[0033] The voltages applied to the gate 208 of the FeFET 202 by the programsignal circuit 206 can cause the ferroelectric material in the FeFET 202 to form an electric polarization. The ferroelectric polarization can remain (or substantially remains) long after the voltage applied to the gate 208 of the FeFET 202 is removed if the voltage was of sufficient magnitude and duration to change the state of the ferroelectric material. This is a result of a stable electric polarization in the ferroelectric material. The ferroelectric material is an insulator in which the electric polarization induced by an applied electric field from a voltage applied to the gate 208 remains after removal of that voltage.

[0034] Positive voltage biases (or pulses) from the program-signal circuit 206 applied to the gate 208 of the FeFET 202 results in a reduction in the threshold voltage of the FeFET 202 and brings the channel of the FeFET 202 into accumulation mode. And negative voltage bias (or pulses) from the program-signal circuit 206 applied to the gate 208 of the FeFET 202 results in an increase in the threshold voltage of the FeFET 202 and brings the channel of the FeFET 202 into depletion mode. The first state may correspond to a 0-value and the second state may correspond to a 1 -value, or visa-versa.

[0035] Referring to Figs. 2-3: FIG. 3 illustrates operating characteristics of the FeFET 202 of FIG. 2 in a graph 300 when used to store binary states in accordance with an embodiment of the present disclosure. The graph 300 shows an axis 302 that shows a current, Ids, that is the current from the drain 210, through the FeFET 202, and through the source 212 to ground. The current Ids passes through a channel of the FeFET 202 where the channel has characteristics based upon the polarization of the ferroelectric material. The graph 300 also includes an axis 304 that shows the voltage at the gate 208 of FIG. 2. The Vg values applied to the gate 208 may be within a range of voltages to determine the state of the FeFET without significantly disturbing the ferroelectric material’s polarization.Attorney Docket No. P24-189-SEC-WO01

[0036] FIG. 3 illustrates the relationship between the Ids and Vg based upon the state of the FeFET 202 in accordance with an embodiment of the present disclosure. A first curve 306 shows the FeFET 202 in a first state because it has a first threshold voltage 308. A second curve 310 shows the FeFET 202 in a second state because it has a second threshold voltage 312. The states of the FeFET 202 may be programmed by the program-signal circuit 206 to change the electric polarization of the ferroelectric material in the FeFET 202. These states may be detected by the sense circuit 204. In some embodiments, no Vg voltage needs to be applied to the FeFET 202 to determine the state; however, in other embodiments, a sufficient voltage needs to be applied to the gate 208 to determine the state of the FeFET, but without programming the FeFET 202.

[0037] Referring to Figs. 2 and 4: FIG. 4 illustrates operating characterizes of the FeFET 202 of FIG. 2 in a graph 400 when the FeFET 202 is used to store a continuous value, such as a weight of a neuromorphic cell, in accordance with an embodiment of the present disclosure.

[0038] The graph 400 shows an axis 402 for a current Ids. Ids is the current from the drain 210 through the FeFET 202 and through the source 212 to ground. The current Ids passes through a channel of the FeFET 202 where the channel has characteristics based upon the polarization of the ferroelectric material. The graph 400 also includes an axis 404 that shows the voltage at the gate 208 of FIG. 2. The Vg values applied to the gate 208 may be within a range of voltages to determine the state of the FeFET without significantly disturbing the ferroelectric material’s polarization.

[0039] FIG. 4 illustrates the relationship between the Ids and Vg based upon the polarization of the FeFET 202 in accordance with an embodiment of the present disclosure. As the polarization changes, the characteristic curve shifts as indicated by arrow 408. These shifting curves cause the threshold voltages 406 to shift as well. These values may be mapped to a weight of an artificial neural network. For example, an arithmetic logic unit may read these values for computation within a processing element of FIG. 1. In some embodiments, the memory is used as in-memory- computing, and along with other analog circuit, can perform the calculations of an artificial neural net in accordance with the mapped value corresponding to a weight of a neural network cell, e.g., neuron. During a neural network training phase, the Al accelerator 100 may use the program-signal circuit 206 to change the electric polarization of the ferroelectric material in the FeFET 202 to correspond to a neuron weight. These threshold voltages 406 may be detected by the sense circuit 204. In someAttorney Docket No. P24-189-SEC-WO01 embodiments, no Vg voltage needs to be applied to the FeFET 202 to determine its state; however, in other embodiments, a voltage is applied to the gate 208.

[0040] FIG. 5 shows a memory array 500 utilizing FeFET transistors 514 in accordance with an embodiment of the present disclosure. The FeFET transistors 514 each have a polarization state. An interface circuit (not shown) can select one of the word lines 502, 504, or 506, to activate a column of FeFET transistors 514. These activated FeFETs of the FeFETs 514 coupled to the activated word line, e.g., 504, causes each of the bit lines 508, 510, 512 to output the state (or value) that corresponds to the ferroelectric’s electric polarization in each respective one of the FeFETs 514. One of ordinary skill in the art will appreciate that the array of FeFETs 514 can be increased to have a target memory size. Additionally, one of ordinary skill in the relevant art will appreciate that programming circuitry may be added to the memory array 500.

[0041] The FeFET transistors 514 may be powered by a voltage from the bit lines 508, 510, 512 that is relative to the voltages SL. The SL references may be a ground, may be a fixed voltage, may be a programmable voltage, may be a variable voltage, may be coupled to a ground or a voltage source via another transistor (not shown), etc.

[0042] For Figs. 6-8, a FET is shown. In some specific embodiments, the FETs shown and described in the accompanying text description may be a FeFET, which may be used in the embodiments shown and described in the accompanying text for Figs. 1- 5.

[0043] FIG. 6 shows an illustration of a process of plasma annealing a FET in accordance with an embodiment of the present disclosure. In some specific embodiments, the transistor shown in FIG. 6 is a FeFET. However, in other embodiments, it is not a FeFET. The process includes a first stage 602, a second stage 604, and a third stage 606.

[0044] The first stage 602 represents the initial phase in the process of forming a transistor. In this stage, a substrate 608 is provided as the foundation for the transistor structure. The substrate 608 may be composed of silicon (Si) in some embodiments, although other suitable materials can be used depending on the specific application requirements. On top of the substrate 608, a silicon dioxide layer 610 is disposed. This silicon dioxide layer 610 can serve as an insulating layer between the substrate and subsequent layers of the transistor.Attorney Docket No. P24-189-SEC-WO01

[0045] A gate electrode 612, labeled as G(W), is positioned on the silicon dioxide layer 610. The gate electrode 612 can be made of various conductive materials, including any number of metals such as tungsten (W), titanium nitride (TiN), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), ruthenium (Ru), hafnium (Hf), chromium (Cr), and others. It may also be composed of a polysilicon, a metal, a metal silicide (e.g., a nickel silicide, cobalt silicide, titanium silicide), a metal nitride, or other metals and metal alloys. Its dimensions can vary depending on the desired transistor characteristics. In some embodiments, the gate electrode 612 may have a length in a range of nanometers to several 10s of micrometers. For example, the gate electrode length 612 may be about 3 micrometers, although other lengths can be used based on the specific design requirements.

[0046] Following the formation of the gate electrode 612, a thin-film oxide layer 614 is formed on both the gate electrode 612 and the exposed portions of the silicon dioxide layer 610. This thin-film oxide layer 614 can be composed of various materials, including high-k dielectric materials in some embodiments. The thickness and composition of this layer may be adjusted to achieve desired transistor properties.

[0047] It is worth noting that the first stage 602 sets the foundation for subsequent processing steps. The arrangement and composition of these initial layers can influence the final characteristics of the transistor. In some variations of this process, the dimensions and materials of each layer may be altered to suit specific applications or to achieve particular performance goals.

[0048] The first stage 602 may also include additional preparatory steps or treatments not explicitly shown in the figure. For instance, the surfaces of the various layers may undergo cleaning or conditioning processes to ensure proper adhesion and formation of subsequent layers. Additionally, the deposition methods for each layer can vary, potentially including techniques such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, among others.

[0049] In some embodiments, the transistor being formed in this process may be a thin-film transistor or an AOS (amorphous oxide semiconductor) transistor. The specific type of transistor can influence the chosen materials and dimensions used in this first stage, as well as the subsequent processing steps.

[0050] The second stage 604 of the transistor formation process represents a transformation from the initial stage. In this stage, the substrate 608, which can beAttorney Docket No. P24-189-SEC-WO01 composed of silicon, remains as the foundational layer of the structure. The silicon dioxide layer 610 continues to be positioned directly above the substrate 608, maintaining its role as an insulating layer. The gate electrode 612, labeled as G(W), retains its position on top of the silicon dioxide layer 610.

[0051] A notable change in this stage is the transformation of the initial thin- film oxide layer 614 into the annealed thin-film oxide layer 616. This transformation occurs as a result of the application of an Oxygen plasma anneal process. The annealing process can potentially alter the properties of the oxide layer, which may include changes in its crystalline structure, density, or electrical characteristics. In some embodiments, the annealed thin-film oxide layer 616 may be composed of a ferroelectric material, which would classify the transistor as a Ferroelectric Field-Effect Transistor (FeFET).

[0052] The choice of ferroelectric material for the annealed thin-film oxide layer 616 can vary depending on the specific requirements of the transistor. Some possible materials that may be used include hafnium oxide (HfCh), zirconium oxide (ZrO?), or various doped versions and combinations of these oxides. Comprehensive examples include hafnium zirconium oxide (Hfi .Zr .Ch J with varying compositions where x ranges from 0 to 1, such as Hfo.5Zro.5O2, Hfo.25Zro.75O2, and Hfo.75Zro.25O2. Additionally, doped hafnium oxide materials may incorporate elements like silicon (Si) resulting in HfSiO4, aluminum (Al) forming HfAlO2, lanthanum (La) creating HfLaO?. yttrium (Y) producing HfYO2, gadolinium (Gd) yielding HfGdO2, or nitrogen (N) to form hafnium oxynitride (HfON). Other ferroelectric materials include doped zirconium oxides like ZrSiO4, ZrAlO2, and ZrLaO2. These combinations and doped versions enhance ferroelectric properties, allowing the thin-film oxide layer to exhibit the target polarization characteristics. The ferroelectric properties of these materials enable a FeFET to function as a memory device, capable of storing binary states or even analog values in some embodiments. By selecting specific compositions and doping elements, the ferroelectric layer's properties such as remnant polarization, coercive field, and dielectric constant can be tailored to optimize the performance of the FeFET for various applications.

[0053] The annealing process applied in this stage may be carried out under various conditions. For instance, the duration of the annealing process can range from 1 to 30 minutes, with some embodiments utilizing an approximately 5-minute annealingAttorney Docket No. P24-189-SEC-WO01 time. The temperature during the annealing process may be set between 100°C to 500°C, with 200°C being a choice in some implementations.

[0054] The plasma used for the annealing process can be generated using different methods. In some embodiments, a remote plasma source may be employed, while in others, a direct plasma source might be utilized. The plasma chamber may use a gas mixture containing approximately 20% oxygen. The application of radio frequency energy, which can range from about 500 to 1,000 watts of power, with 800 watts being a choice in some implementations, may be used to strike the oxygen into a plasma state.

[0055] It's worth noting that while the annealed thin-film oxide layer 616 is a component of the transistor at this stage, the source and drain regions have not yet been formed. These regions will be introduced in the subsequent stage of the transistor formation process. The dimensions of the transistor, including the gate electrode length, channel width, and eventual overlaps between the gate and the source / drain regions, can vary based on the specific design requirements and intended application of the device.

[0056] In the third stage 606, the transistor is processed more. The source region 620 and the drain region 622 are added, for example. The source region 620, typically labeled as S, is positioned on one side of the gate electrode. The channel layer 618 and the annealed oxide layer 616 are situated between the source region 620 and the gate electrode 612. Similarly, the drain region 622, usually labeled as D, is formed on the opposite side of the gate electrode. The channel layer 618 and the annealed oxide layer 616 also separate the drain region 622 from the gate electrode 612.

[0057] In some embodiments, the source and drain regions may be doped to enhance their conductivity. The specific doping profile and concentrations can vary depending on the desired transistor characteristics. The positioning of these regions relative to the gate electrode can influence the transistor's performance, including factors such as switching speed and power consumption.

[0058] Thus, the structure formed in this third stage 606 represents a complete transistor, capable of controlling current flow between the source and drain regions through the application of voltage to the gate electrode. The unique inclusion of the ferroelectric layer in this structure may provide additional functionality, such as nonvolatile memory capabilities, in certain implementations.Attorney Docket No. P24-189-SEC-WO01

[0059] Referring now to all of FIG. 6, the substrate 608 can serve as the foundational layer in the transistor structure illustrated in FIG. 6. In some embodiments, the substrate 608 may be composed of silicon (Si), providing a stable base for the subsequent layers and components of the transistor. The substrate 608 can be seen consistently present throughout all three stages of the transistor formation process depicted in FIG. 6, indicating its role as a constant structural element.

[0060] As previously mentioned, the substrate 608 serves as the foundational layer in the transistor structure illustrated in FIG. 6. It is a silicon (Si) base layer that provides mechanical support and acts as the starting material for the fabrication of the semiconductor device. The substrate 608 can be made from high-purity, single-crystal silicon wafers, which are widely used in the semiconductor industry due to their excellent electrical properties and compatibility with existing manufacturing processes. In some embodiments, the substrate 608 may be doped with specific impurities to alter its electrical characteristics, such as improving its conductivity or creating regions with different charge carrier types.

[0061] The substrate 608 can interact with other elements in the system by serving as the foundation upon which subsequent layers are deposited or grown. It directly interfaces with the silicon dioxide layer 610, which is disposed on top of it. This interaction between the substrate 608 and the silicon dioxide layer 610 can influence the formation of the gate dielectric in the transistor structure. Additionally, the substrate 608 may play a role in the overall electrical behavior of the device, as it can influence charge carrier movement and distribution within the transistor. In some embodiments, the substrate 608 may also act as a heat sink, helping to dissipate thermal energy generated during device operation.

[0062] While the substrate 608 is described as being made of silicon in the primary embodiment, there can be variations and alternative embodiments. For instance, in some embodiments, the substrate 608 may be made from other semiconductor materials such as germanium, gallium arsenide, or silicon carbide, depending on the specific requirements of the device. In other embodiments, the substrate 608 may be a composite material or a layered structure, such as silicon-on- insulator (SOI). The thickness of the substrate 608 can also vary depending on the application, ranging from several hundred micrometers for standard wafers to just a few micrometers for ultra-thin substrates used in flexible electronics. Furthermore, in some embodiments, the substrate 608 may be pre-processed with specific features orAttorney Docket No. P24-189-SEC-WO01 structures before the subsequent layers are added, such as trenches for isolation or buried layers for specialized device functions.

[0063] The silicon dioxide layer 610 is a component of the transistor structure illustrated in FIG. 6. This layer is disposed directly on top of the substrate 608, which may be composed of silicon. In some embodiments, the silicon dioxide layer 610 can serve as an insulating layer between the substrate 608 and the subsequent layers of the transistor. The thickness of the silicon dioxide layer 610 may vary depending on the specific requirements of the transistor design. In certain implementations, the silicon dioxide layer 610 can be formed through thermal oxidation of the silicon substrate 608, while in other cases, it may be deposited using techniques such as chemical vapor deposition or atomic layer deposition.

[0064] The silicon dioxide layer 610 can play a role in determining the electrical characteristics of the transistor. It may influence the capacitance between the gate electrode 612 and the channel that forms in the substrate 608. In some embodiments, the silicon dioxide layer 610 can act as a barrier to prevent unwanted current flow between the gate electrode 612 and the substrate 608. The quality and uniformity of this layer may affect the overall performance and reliability of the transistor.

[0065] In certain variations of the transistor structure, the silicon dioxide layer 610 may be replaced or supplemented with other dielectric materials. These alternative materials can include high-k dielectrics, which may allow for a thicker physical layer while maintaining or improving the electrical properties of the transistor. The choice of material for this layer can depend on factors such as the desired transistor characteristics, manufacturing processes, and compatibility with other materials in the structure.

[0066] The silicon dioxide layer 610 can remain present throughout all stages of the transistor formation process illustrated in FIG. 6. Its presence and properties can affect the subsequent steps in the transistor fabrication, including the formation of the gate electrode 612, the deposition and annealing of the thin-film oxide layer 614 / 616, and the creation of the channel layer 618. The interaction between the silicon dioxide layer 610 and these other components may contribute to the overall functionality and performance of the completed transistor structure.

[0067] The gate electrode 612 is a component of the transistor structure illustrated in FIG. 6. In various embodiments, the gate electrode 612 may be composed of a conductive material, such as polysilicon, metal, or a combination thereof. The gateAttorney Docket No. P24-189-SEC-WO01 electrode 612 is positioned on top of the silicon dioxide layer 610, which acts as an insulating layer between the gate electrode 612 and the substrate 608. The thickness of the gate electrode 612 can vary depending on the specific application and desired transistor characteristics.

[0068] In some embodiments, the gate electrode 612 may have a length of approximately 3 micrometers, although this dimension can be adjusted based on the requirements of the transistor design. The width of the gate electrode 612 may correspond to the channel width of the transistor, which can range from 5 micrometers to 50 micrometers or even smaller in certain applications.

[0069] The gate electrode 612 plays a role in controlling the electrical characteristics of the transistor. When a voltage is applied to the gate electrode 612, it creates an electric field that influences the behavior of charge carriers in the channel region beneath it. This electric field can be used to modulate the conductivity of the channel, effectively turning the transistor on or off.

[0070] In the process of forming the transistor, the gate electrode 612 is present in all three stages shown in FIG. 6. Initially, in stage 602, the gate electrode 612 is formed directly on the silicon dioxide layer 610. Subsequently, in stages 604 and 606, additional layers are added above and around the gate electrode 612, but its position remains unchanged.

[0071] The gate electrode 612 may overlap with the source region 620 and drain region 622 to some extent. In some embodiments, this overlap can be approximately 2 micrometers on each side, although it may be less than 5 micrometers in other configurations. The precise amount of overlap can affect the electrical characteristics of the transistor, including its switching speed and current-carrying capacity.

[0072] In certain embodiments, the material composition of the gate electrode 612 can be selected to optimize the work function for specific transistor applications. For instance, different metals or metal alloys may be used to achieve desired threshold voltages for various types of transistors, such as NMOS or PMOS devices.

[0073] The shape and profile of the gate electrode 612 may also be tailored in some embodiments. For example, it may have a rectangular cross-section, or it could have tapered edges to influence the electric field distribution in the channel region. These variations in gate electrode geometry can be employed to fine-tune the transistor's performance characteristics.Attorney Docket No. P24-189-SEC-WO01

[0074] The initial oxide layer 614 is a thin-film oxide layer formed on the gate electrode 612 and the silicon dioxide layer 610 during the first stage 602 of the transistor formation process. This layer can be composed of various materials, depending on the specific requirements of the transistor being fabricated. In some embodiments, the initial oxide layer 614 may be a high-k dielectric material, which can provide improved electrical properties compared to traditional silicon dioxide. The thickness of the initial oxide layer 614 can vary depending on the desired characteristics of the transistor, and may range from a few nanometers to several tens of nanometers.

[0075] The initial oxide layer 614 serves as a precursor to the annealed oxide layer 616 that is formed in the second stage 604. The composition and structure of the initial oxide layer 614 can influence the properties of the resulting annealed oxide layer 616. In some embodiments, the initial oxide layer 614 may be deposited using various techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0076] The initial oxide layer 614 can be tailored to achieve specific electrical properties in the final transistor structure. For instance, in embodiments where the transistor is intended to function as a FeFET, the initial oxide layer 614 may contain ferroelectric materials or precursors that, upon annealing, form a ferroelectric layer. This ferroelectric property can enable the transistor to function as a memory device, capable of storing a state.

[0077] In other embodiments, the initial oxide layer 614 may be designed to enhance the overall performance of the transistor by improving characteristics such as carrier mobility, gate leakage, or threshold voltage stability. The composition of the initial oxide layer 614 can be adjusted to include various dopants or additives that can further modify its electrical and physical properties.

[0078] It's worth noting that the initial oxide layer 614 covers both the gate electrode 612 and the exposed areas of the silicon dioxide layer 610. This configuration can help to protect the underlying structures during subsequent processing steps and may contribute to the overall integrity of the transistor structure. The uniformity and quality of the initial oxide layer 614 can play a role in determining the consistency and reliability of the transistor's performance across the device, in some embodiments.

[0079] After the deposition of the initial oxide layer 614, a gate oxide patterning process may be employed to define specific regions where the oxide layer 614 remains on the transistor structure. This patterning may involve the use of photolithographyAttorney Docket No. P24-189-SEC-WO01 techniques to selectively remove portions of the oxide layer 614, thereby exposing underlying areas of the gate electrode 612 and the silicon dioxide layer 610. A photoresist layer may be first applied over the initial oxide layer 614, followed by exposure to ultraviolet light through a photomask that outlines the desired gate oxide pattern. The exposed photoresist is then developed, leaving a patterned photoresist that protects certain areas of the oxide layer 614 while exposing others. An etching process, such as wet chemical etching or dry plasma etching, can then carried out to remove the unprotected portions of the oxide layer 614. This gate oxide patterning allows for precise control over the dimensions and placement of the gate dielectric, which is used for achieving the desired electrical characteristics of the transistor. By selectively defining where the gate oxide remains, the process can optimize the transistor's performance by reducing parasitic capacitance, minimizing leakage currents, and enabling the formation of well-defined gate regions. This patterning step can be used in integrating multiple transistors on the same substrate with varying gate oxide thicknesses or compositions in some specific embodiments.

[0080] The annealed oxide layer 616 is a component in the transistor structure illustrated in FIG. 6. This layer is formed through the transformation of the initial thin- film oxide layer 614 after the application of an O plasma anneal process. In some embodiments, the annealed oxide layer 616 may be composed of a ferroelectric material, which can enable the transistor to function as a Ferroelectric Field-Effect Transistor (FeFET). The use of a ferroelectric material in this layer can allow the FeFET to be utilized as a memory device capable of storing a state.

[0081] The annealed oxide layer 616 is positioned on top of the gate electrode 612 and the silicon dioxide layer 610. Its placement and composition play a role in determining the electrical characteristics of the transistor. The thickness of the annealed oxide layer 616 may vary depending on the specific requirements of the transistor design and the intended application. In some embodiments, the thickness of this layer can be controlled through the annealing process parameters, such as temperature, duration, and plasma intensity.

[0082] The annealed oxide layer 616 can exhibit different properties compared to the initial thin-film oxide layer 614. The annealing process may alter the crystalline structure, density, or other physical properties of the oxide material, potentially enhancing ferroelectric properties or improving its overall performance as a gateAttorney Docket No. P24-189-SEC-WO01 dielectric. These changes can affect the transistor's threshold voltage, switching speed, and retention characteristics.

[0083] In various embodiments, the composition of the annealed oxide layer 616 may be tailored to achieve specific electrical properties. For instance, it may incorporate dopants or be formed from different high-k dielectric materials to optimize the transistor's performance for particular applications. The choice of material and annealing conditions can influence factors such as the remnant polarization, coercive field, and dielectric constant of the layer.

[0084] Additionally, it should be understood that the annealed oxide layer 616 is not limited to the specific materials previously mentioned and can, in various embodiments, comprise any suitable gate oxide known in the art. This includes conventional gate oxides such as silicon dioxide (SiCh) and silicon oxynitride (SiON), which have been used in semiconductor devices due to their insulating properties and compatibility with silicon substrates. The annealed oxide layer 616 may also be formed from other high-k dielectric materials like aluminum oxide (AI2O3), tantalum pentoxide (Ta2Os), titanium dioxide (TiO?), lanthanum oxide (I^Ch), or hafnium silicon oxynitride (HfSiON). The selection of the gate oxide material can be tailored to optimize various electrical properties of the transistor, such as carrier mobility, threshold voltage stability, gate leakage current, and dielectric reliability. Factors such as dielectric constant, band alignment with the channel material, thermal stability, and process compatibility can guide the choice of gate oxide. This approach allows the use of any suitable gate oxide that can achieve the desired electrical characteristics and enhance the overall performance of the transistor.

[0085] The annealed oxide layer 616 also serves as an interface between the gate electrode 612 and the channel layer 618 that is formed in subsequent processing steps. This interface can affect the operation of the transistor, as it affects the distribution of electric fields and the movement of charge carriers in the device. The quality and characteristics of this interface may be influenced by the annealing process used to form the annealed oxide layer 616.

[0086] In some embodiments, the annealed oxide layer 616 may extend beyond the boundaries of the gate electrode 612, covering portions of the silicon dioxide layer 610. This extension can affect the fringing fields at the edges of the gate and may influence the transistor's performance characteristics. The exact dimensions and shapeAttorney Docket No. P24-189-SEC-WO01 of the annealed oxide layer 616 can be controlled through careful masking and etching processes during fabrication.

[0087] The stability and reliability of the annealed oxide layer 616 over time and under various operating conditions are considerations in the transistor design. Factors such as temperature cycling, electrical stress, and radiation exposure may affect the long-term performance of this layer. In some embodiments, additional passivation or encapsulation layers may be applied over the annealed oxide layer 616 to protect it from environmental factors and enhance its stability.

[0088] As previously mentioned, the channel layer 618 is a semiconducting layer that forms the conductive path between the source and drain regions of the transistor. In the third stage 606 of the transistor formation process, the channel layer 618 is disposed on top of the annealed thin-film oxide layer 616. This layer can be made of various semiconductor materials such as silicon, germanium, or compound semiconductors like gallium arsenide or indium gallium zinc oxide. The channel layer 618 plays a role in the operation of the transistor by allowing the flow of current between the source and drain when an appropriate voltage is applied to the gate electrode.

[0089] Within the overall transistor structure, the channel layer 618 interacts closely with several other elements. It is in direct contact with the annealed thin-film oxide layer 616 below it, which serves as the gate dielectric. The channel layer 618 also interfaces with the source region 620 and drain region 622 on either side, forming the current path through the transistor. When a voltage is applied to the gate electrode 612, it creates an electric field that penetrates through the annealed thin-film oxide layer 616 and modulates the conductivity of the channel layer 618. This modulation controls the current flow between the source and drain regions, enabling the transistor's switching behavior.

[0090] The channel layer 618 can have various alternative embodiments and variations. In some implementations, it may be a single crystalline semiconductor layer, while in others, it could be polycrystalline or amorphous. The thickness of the channel layer 618 can be adjusted to optimize the transistor's performance characteristics. In certain embodiments, the channel layer 618 may be doped with specific impurities to alter its electrical properties. However, in other embodiments, the channel layer 618 may be undoped or lightly doped. Additionally, in some variations, the channel layer 618 could be formed from multiple sub-layers of different semiconductor materials,Attorney Docket No. P24-189-SEC-WO01 creating a heterostructure with unique electronic properties. The material composition of the channel layer 618 can also be varied to create different types of transistors, such as n-type or p-type devices, or to enhance specific performance attributes like carrier mobility or on / off current ratio.

[0091] The source region 620 is a component of the transistor structure illustrated in FIG. 6. Located adjacent to the gate electrode 612 on the channel layer 618, the source region 620 serves as the origin of charge carriers in the transistor's operation. In this configuration, the source region 620 may be composed of heavily doped semiconductor material, typically of the same type as the substrate 608 but with a higher concentration of dopants. The source region 620 can be formed through various processes such as ion implantation or diffusion of dopant atoms into the channel layer 618, followed by an activation anneal to incorporate the dopants into the crystal lattice. In some embodiments, the source region 620 may be undoped or lightly doped.

[0092] Within the transistor system, the source region 620 forms one end of the conductive channel that develops in the channel layer 618 when the transistor is in its on state. The source region 620 works in concert with the drain region 622, with charge carriers flowing between these two regions through the channel layer 618 when an appropriate voltage is applied to the gate electrode 612. The annealed oxide layer 616 and channel layer 618 separate the source region 620 from the gate electrode 612, which controls the flow of charge carriers from the source. This arrangement allows for precise control of the transistor's switching behavior and current flow.

[0093] The source region 620 can have several variations and alternative embodiments depending on the specific requirements of the transistor design. In some embodiments, the source region 620 may be formed with a graded doping profile, where the concentration of dopants gradually decreases towards the channel region, to optimize the device's electrical characteristics. In other embodiments, no doping may be used. Alternatively, the source region 620 could be fabricated using different materials or compounds to create specific band alignments or to enhance carrier mobility. In certain designs, the source region 620 may incorporate additional features such as raised source structures or silicide layers to reduce contact resistance. Moreover, the dimensions and shape of the source region 620 can be adjusted to finetune the transistor's performance characteristics, such as on-state current and switching speed.Attorney Docket No. P24-189-SEC-WO01

[0094] The drain region 622 is formed in the next stage of the transistor fabrication process, as shown in the third stage 606. The drain region 622 may be a heavily doped semiconductor region, created adjacent to the gate electrode 612 on the channel layer 618. This region serves as the terminal through which current exits the transistor during operation. The drain region 622 is designed to collect and conduct charge carriers (electrons or holes) that have traversed the channel layer 618 under the influence of the electric field created by the gate electrode 612. In some embodiments, the drain region 622 may be undoped or lightly doped.

[0095] The drain region 622 is positioned opposite to the source region 620, with the channel layer 618 and the annealed oxide layer 616 separating it from the gate electrode 612. This configuration allows for the controlled flow of current through the transistor. When a suitable voltage is applied to the gate electrode 612, it modulates the conductivity of the channel layer 618, which in turn affects the current flow between the source region 620 and the drain region 622. The effectiveness of this current modulation depends on the properties of the drain region 622, including its doping concentration and its proximity to the gate electrode 612.

[0096] In some embodiments, the drain region 622 may be formed using different dopant types or concentrations to optimize the transistor's performance characteristics. For instance, a lightly doped drain (LDD) structure might be employed to reduce hot carrier effects in high-performance devices. Alternatively, the shape and extent of the drain region 622 can be adjusted to modify the transistor's breakdown voltage or output resistance. In certain applications, the drain region 622 may be engineered to have a graded doping profile or to incorporate additional features such as halo implants. These variations in the drain region 622 design allow for customization of the transistor's electrical characteristics to suit different operational requirements.

[0097] FIG. 7 shows a flow chart diagram of a method 700 of annealing a FET, such as a FeFET, in accordance with an embodiment of the present disclosure. The method 700 includes acts 702 to 714.

[0098] Act 702 provides a substrate, which serves as the foundational layer for constructing the transistor structure. The substrate is typically a thin wafer of semiconductor material, most commonly silicon, although other materials such as germanium or gallium arsenide may be used in certain applications. The substrate acts as the base upon which subsequent layers of the transistor will be built, including the silicon dioxide layer, gate electrode, and thin-film oxide layer. The quality, purity, andAttorney Docket No. P24-189-SEC-WO01 crystalline structure of the substrate are factors that can influence the electrical characteristics and overall performance of the resulting transistor.

[0099] The substrate provided in Act 702 interacts closely with other elements and acts in the method. It directly interfaces with the silicon dioxide layer that is disposed on top of it in a subsequent step. The substrate also plays a role in the formation of the source and drain regions, which are typically created by doping specific areas of the substrate adjacent to the gate electrode. Furthermore, the substrate's properties can affect the annealing process applied to the thin-film oxide layer, as the thermal characteristics of the substrate material can influence heat distribution and dissipation during the annealing step.

[0100] In relation to the components described in FIG. 6, the substrate provided in Act 702 corresponds to the substrate 608 shown in all three stages of the transistor formation process. As illustrated in FIG. 6, the substrate remains a constant presence throughout the fabrication steps, supporting the various layers and structures that are added above it. The substrate's role is used in stage 606, where it forms the foundation for the completed transistor structure, including the channel layer, source region, and drain region.

[0101] There are several possible variations and alternative embodiments for the substrate provided in Act 702. While silicon is the most common substrate material, other semiconductor materials could be used to achieve specific device characteristics. For instance, germanium substrates might be employed for high-speed applications, or silicon carbide for high-power devices. The substrate could also be a composite structure, such as silicon-on-insulator (SOI), which consists of a thin layer of silicon on top of an insulating layer. Additionally, the substrate may be doped with specific impurities to alter its electrical properties, or it may undergo various surface treatments or polishing processes to prepare it for subsequent fabrication steps. The thickness of the substrate can also vary, ranging from several hundred micrometers for standard wafers to just a few micrometers for ultra-thin substrates used in flexible or transparent electronics.

[0102] Act 704 involves providing a silicon dioxide layer disposed on the substrate as part of the process of forming a transistor. The silicon dioxide layer serves as an insulating layer between the substrate and subsequent layers of the transistor structure. This layer is typically formed through thermal oxidation of the silicon substrate or deposited using techniques such as chemical vapor deposition (CVD) orAttorney Docket No. P24-189-SEC-WO01 atomic layer deposition (ALD). The thickness of the silicon dioxide layer can vary depending on the specific requirements of the transistor design, but it is generally in the range of a few nanometers to several hundred nanometers. The quality and uniformity of this layer directly impact the electrical characteristics and overall performance of the transistor.

[0103] Within the overall transistor formation process, Act 704 interacts closely with other steps and components. The silicon dioxide layer provided in this act serves as the foundation upon which the gate electrode (Act 706) is subsequently deposited. It also interfaces with the thin-film oxide layer formed in Act 708, which is deposited on both the gate electrode and the exposed portions of the silicon dioxide layer. The presence and properties of the silicon dioxide layer influence the formation and characteristics of these subsequent layers. Additionally, the silicon dioxide layer may play a role in isolating the gate electrode from the substrate, preventing unwanted current flow between these components and allowing for proper control of the transistor's channel region.

[0104] The silicon dioxide layer provided in Act 704 may be formed or processed by components described in FIG. 6 herein. For instance, the substrate 608 shown in FIG. 6 serves as the base upon which the silicon dioxide layer 610 is disposed. The process of forming this layer may involve thermal oxidation equipment or deposition systems capable of precise thickness control and uniformity. While not explicitly shown in FIG. 6, the formation of the silicon dioxide layer may require carefully controlled environmental conditions, such as specific temperatures, gas flows, and pressures, which would be managed by the fabrication equipment used in this stage of the transistor formation process.

[0105] There are several possible variations and alternative embodiments for Act 704. While silicon dioxide is the primary material mentioned, other dielectric materials could be used in place of or in combination with silicon dioxide. For example, high-k dielectric materials such as hafnium oxide or zirconium oxide might be employed to achieve higher capacitance without reducing the physical thickness of the layer. In some embodiments, the layer might consist of multiple sub-layers of different dielectric materials to optimize various electrical properties. The method of forming the layer could also vary, with some processes using plasma-enhanced chemical vapor deposition (PECVD) or sputtering techniques instead of thermal oxidation. The thickness of the layer could be adjusted based on the specific application, with someAttorney Docket No. P24-189-SEC-WO01 high-performance devices requiring ultra-thin layers of just a few atomic layers, while other applications might use thicker layers for improved isolation or reliability. In certain cases, the layer might be subjected to additional treatments such as annealing or doping to modify its electrical or physical properties.

[0106] Act 706 involves the provision of a gate electrode on the silicon dioxide layer. The gate electrode is a conductive structure that controls the flow of current through the transistor channel. It is typically made of a highly conductive material such as polysilicon, metal, or a combination of both. The gate electrode is carefully positioned on top of the silicon dioxide layer, which acts as an insulating barrier between the gate and the underlying substrate. The dimensions and shape of the gate electrode are factors in determining the transistor's performance characteristics. In some embodiments, the gate electrode may have a length of approximately 3 micrometers, although this can vary depending on the specific transistor design requirements.

[0107] The silicon dioxide layer, provided in act 704, serves as the gate dielectric, insulating the gate electrode from the substrate. The gate electrode's position determines where the channel will form in the substrate beneath it when the transistor is in operation. Following act 706, the thin-film oxide layer formed in act 708 will cover both the gate electrode and the exposed areas of the silicon dioxide layer. This configuration may facilitate the subsequent plasma annealing process in acts 710 and 712, which will affect the properties of the oxide layer directly above the gate electrode.

[0108] The gate electrode provided in act 706 may be formed by a component or system similar to those described in FIG. 6 described herein. For instance, the gate electrode could be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques. The exact method chosen may depend on the material of the gate electrode and the desired properties of the resulting structure. The deposition system would need to be capable of controlling the thickness and uniformity of the gate electrode layer, as these factors can impact the transistor's performance.

[0109] There are several possible variations and alternative embodiments for providing the gate electrode in act 706. The material of the gate electrode could be varied to optimize the work function for specific transistor types. For example, different metals or metal alloys might be used for NMOS versus PMOS devices. The shape and profile of the gate electrode could also be tailored. Some embodiments might use a T- shaped or mushroom-shaped gate to reduce resistance while maintaining a smallAttorney Docket No. P24-189-SEC-WO01 effective gate length. In other variations, the gate electrode might be formed using a replacement gate process, where a sacrificial gate is initially deposited and later replaced with the final gate material after high-temperature processing steps are completed. Additionally, the gate electrode could be formed with multiple layers or as part of a gate stack that includes additional layers for improved performance or reliability.

[0110] Act 708 involves the formation of a thin-film oxide layer on the gate electrode and the silicon dioxide layer of the transistor structure. This thin-film oxide layer may serve multiple purposes in the transistor's functionality and performance. The oxide layer is typically deposited using techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The thickness of this layer can range from a few nanometers to several tens of nanometers, depending on the specific requirements of the transistor design. The composition of the thin-film oxide layer may vary, but it often includes high-k dielectric materials to enhance the transistor's electrical properties.

[0111] The formation of the thin-film oxide layer interacts with other elements and acts within the method by building upon the existing structure and preparing the surface for subsequent steps. It can directly interface with both the gate electrode and the exposed portions of the silicon dioxide layer, creating a uniform covering over these surfaces. This act is for the subsequent annealing process (Act 712) as it provides the material that will be transformed by the plasma treatment. The quality and uniformity of this thin-film oxide layer can impact the effectiveness of the annealing process and, consequently, the final electrical characteristics of the transistor. Additionally, the formation of this layer may influence the dimensions and properties of the gate electrode, potentially affecting the transistor's channel length and width.

[0112] In relation to the components described in FIG. 6, the formation of the thin-film oxide layer corresponds to the transition from the first stage 602 to the second stage 604. The thin-film oxide layer 614 is deposited on the gate electrode 612 and the silicon dioxide layer 610. This process prepares the structure for the subsequent plasma annealing step, which transforms the initial thin-film oxide layer 614 into the annealed thin-film oxide layer 616. The deposition of this layer may be performed using equipment capable of precise thickness control and uniformity, such as ALD reactors or specialized CVD chambers, which are components that may be part of the overall fabrication system depicted in FIG. 6.Attorney Docket No. P24-189-SEC-WO01

[0113] There are several possible variations and alternative embodiments for the act of forming the thin-film oxide layer. The composition of the oxide layer can be varied to include different high-k materials such as hafnium oxide, zirconium oxide, or their doped variants, each offering specific benefits in terms of dielectric constant, leakage current, or compatibility with subsequent processing steps. The deposition technique can also be altered; for instance, instead of a single -layer deposition, a multilayer stack of different oxides could be formed to fine-tune the electrical properties of the transistor. The thickness of the layer can be adjusted based on the desired capacitance and leakage current targets. In some embodiments, the thin-film oxide layer may be subjected to intermediate treatments such as rapid thermal annealing or UV exposure before the plasma annealing step to modify its structure or composition. Furthermore, the coverage area of the thin-film oxide layer could be controlled through masking techniques, allowing for selective deposition or creation of specific patterns that could enhance the transistor's performance or enable various device architectures.

[0114] Act 710 generates plasma from diatomic oxygen using an oxygen source. This act involves the creation of oxygen plasma, which is a state of matter where oxygen gas is ionized and becomes electrically conductive. The generation of plasma from diatomic oxygen typically occurs in a plasma chamber or reactor designed for this purpose. The oxygen source used in this act may be pure oxygen gas or a gas mixture containing oxygen, such as air or a custom blend with an inert carrier gas. The plasma generation process usually involves applying energy to the oxygen molecules, causing them to dissociate and ionize into a mixture of oxygen atoms, ions, and free electrons.

[0115] The generation of oxygen plasma in Act 710 interacts closely with other elements of the method described in FIG. 7. It follows the formation of the thin-film oxide layer in Act 708 and directly precedes the application of the plasma to anneal the thin-film oxide layer in Act 712. The properties of the generated plasma, such as its density, temperature, and ion energy, can

[0116] influence the effectiveness of the subsequent annealing process. Additionally, the plasma generation process may be optimized based on the specific characteristics of the thin-film oxide layer formed in Act 708, such as its composition and thickness, to ensure optimal annealing results.

[0117] The plasma generation described in Act 710 may be performed by components illustrated in FIG. 6, particularly within the second stage 604 where the annealing process occurs. While not explicitly shown in FIG. 6, the plasma generationAttorney Docket No. P24-189-SEC-WO01 would likely take place in a plasma chamber that houses the transistor structure during the annealing process. This chamber would be equipped sufficient hardware to introduce the oxygen source, apply energy for plasma generation, and control the plasma parameters. The oxygen source and plasma generation system would work in conjunction with the temperature control mechanisms implied in the annealing process depicted in stage 604 of FIG. 6.

[0118] There are several possible variations and alternative embodiments for the plasma generation described in Act 710. The oxygen source could vary from pure oxygen to various oxygen-containing gas mixtures, with concentrations ranging from 20% to 100% oxygen. The method of energy application for plasma generation could include radio frequency (RF) power, microwave energy, or electron cyclotron resonance (ECR). The plasma could be generated using a remote plasma source, where the plasma is created separately and then introduced to the process chamber, or using a direct plasma source within the same chamber as the substrate. The power applied for plasma generation could range from about 500 to 1,000 watts, with some embodiments using approximately 800 watts. The pressure in the plasma generation chamber could also be varied to optimize plasma characteristics. These variations allow for fine-tuning of the plasma properties to best suit the specific requirements of the thin-film oxide layer annealing process.

[0119] Act 712 involves applying the plasma of diatomic oxygen to the thin- film oxide layer to anneal the thin-film oxide layer. This step in the transistor formation process utilizes the reactive oxygen species generated in the plasma to modify and improve the properties of the thin-film oxide layer. The plasma, consisting of ionized oxygen molecules and atoms, interacts with the surface and bulk of the oxide layer, promoting structural reorganization, densification, and potentially introducing beneficial defects or dopants. This plasma annealing process can alter the electrical, physical, and chemical characteristics of the oxide layer, potentially enhancing its dielectric properties, reducing defects, and improving the interface quality with adjacent layers.

[0120] The plasma annealing step in Act 712 interacts with other elements and acts within the transistor formation method. It can follow the plasma generation in Act 710, utilizing the diatomic oxygen plasma created from the oxygen source. Act 712 depends on the quality and characteristics of the plasma generated in the previous step.Attorney Docket No. P24-189-SEC-WO01Furthermore, this annealing process may act upon the thin-film oxide layer formed in Act 708, transforming its properties and structure.

[0121] The plasma annealing process in Act 712 may be performed using the plasma chamber mentioned herein and could be used to contain and control the annealing environment. The remote or direct plasma source discussed may be employed to generate and deliver the oxygen plasma to the thin-film oxide layer. The radio frequency energy application described herein, potentially ranging from 500 to 1,000 watts, may be used to sustain the plasma during the annealing process. Additionally, the temperature control mentioned (e.g., setting the chamber to 200 C or within a range of 100 C to 500 C) may be used for regulating the annealing conditions and influencing the resulting oxide layer properties.

[0122] Act 712 can have several variations and alternative embodiments. The duration of plasma application may vary, potentially ranging from 1 to 30 minutes, with some embodiments using approximately 5 minutes. The plasma composition could be adjusted by varying the oxygen concentration in the gas mixture, with some embodiments using a 20% oxygen / gas mixture as specified. The power of the radio frequency energy used to generate and sustain the plasma could be varied within the 500 to 1,000 watt range to optimize the annealing process. Alternative plasma sources or generation methods not explicitly mentioned herein as known by one of ordinary skill in the art could also be employed. Furthermore, the annealing process could potentially be performed in multiple steps or cycles, or combined with other treatment methods to achieve specific oxide layer properties tailored for different transistor designs or applications.

[0123] Act 713 forms a channel layer on the thin-film oxide layer. Act 713 involves forming a channel layer on the thin-film oxide layer that was annealed in Act 712. This channel layer serves as a semiconductor region where charge carriers can move, enabling the transistor to control electrical cun-ent between the source and drain regions. The formation of the channel layer is achieved by depositing a semiconductor material directly onto the annealed thin-film oxide layer. This process establishes an interface between the channel layer and the thin-film oxide layer, which acts as the gate dielectric in the transistor structure.

[0124] The semiconductor material used for the channel layer can vary depending on the desired electrical properties of the transistor. In some embodiments, the channel layer may be composed of materials such as amorphous silicon,Attorney Docket No. P24-189-SEC-WO01 polycrystalline silicon, or metal oxide semiconductors like indium gallium zinc oxide (IGZO). The choice of material influences characteristics such as carrier mobility, threshold voltage, and overall device performance. Deposition techniques for forming the channel layer may include chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD), each offering precise control over layer thickness and composition.

[0125] During the deposition process, parameters such as temperature, pressure, gas flow rates, and deposition time are carefully controlled to achieve a uniform and high-quality channel layer. The thickness of the channel layer is selected based on the specific requirements of the transistor design, typically ranging from a few nanometers to several tens of nanometers. A thinner channel layer may provide better control over short-channel effects, while a thicker layer might enhance current-driving capability.

[0126] The formation of the channel layer directly on the annealed thin-film oxide layer can help facilitate an interface with minimal, or none, defects for targeted transistor performance. This interface allows the gate electrode, provided in Act 706, to effectively modulate the conductivity of the channel layer through the thin-film oxide layer when a voltage is applied. The electric field induced by the gate voltage influences the charge carriers within the channel layer, enabling the transistor to switch between conductive (on) and non-conductive (off) states.

[0127] Following the deposition of the channel layer, additional treatments may be applied to enhance its properties. These treatments can include thermal annealing to improve crystallinity and reduce defects, or doping processes to introduce impurities that adjust the electrical conductivity and earner concentration. The doping of the channel layer can be accomplished through ion implantation or in-situ doping during the deposition process. The level and type of dopants introduced are selected to achieve the desired balance between device performance and stability.

[0128] The formation of the channel layer in Act 713 is closely related to the subsequent formation of the source and drain regions in Act 714. The channel layer provides the semiconductor material into which the source and drain regions are formed, typically by introducing dopants of opposite type to the channel layer. This creates p-n junctions at the interfaces, allowing for controlled injection and collection of charge carriers during transistor operation. The precise alignment and doping profilesAttorney Docket No. P24-189-SEC-WO01 of the source and drain regions relative to the channel layer are adjusted for achieving high-performance devices with low leakage currents and fast switching speeds.

[0129] In the context of the transistor structure depicted in FIG. 6, the formation of the channel layer corresponds to the addition of the channel layer 618 in the third stage 606. This layer is shown directly above the annealed thin-film oxide layer 616 and beneath the source region 620 and drain region 622. The channel layer 618 interacts with the gate electrode 612 through the thin-film oxide layer, allowing the gate voltage to control the flow of charge earners in the channel.

[0130] Variations in the formation of the channel layer can lead to different transistor characteristics. For example, using a metal oxide semiconductor material for the channel layer can result in a device with higher electron mobility compared to traditional silicon-based materials. Additionally, adjusting the stoichiometry or introducing alloying elements into the channel material can fine-tune properties such as bandgap and carrier concentration. The deposition process can also be modified to create multilayer channel structures or introduce strain into the channel layer, further enhancing device performance.

[0131] The formation of the channel layer on the annealed thin-film oxide layer completes the active region of the transistor, enabling it to function effectively in controlling electrical current. This act builds upon the previous steps of providing the substrate, silicon dioxide layer, gate electrode, and annealed thin-film oxide layer, integrating them into a cohesive structure. The quality and properties of the channel layer are adjusted in determining the overall performance, reliability, and applicability of the transistor in various electronic devices and circuits. By controlling the material properties and deposition parameters during Act 713, the resulting channel layer contributes to the efficiency and effectiveness of the final transistor product.

[0132] Act 714 forms a source region and a drain region on the channel layer. This act creates the components that facilitate current flow through the transistor. The source region acts as the origin of charge carriers, while the drain region serves as their destination. These regions are typically heavily doped areas of the channel layer, with the type of dopant (n-type or p-type) depending on whether an NMOS or PMOS transistor is being fabricated. The formation process may involve ion implantation, where dopant ions are accelerated and embedded into the channel layer, or diffusion, where dopant atoms are introduced and allowed to spread through the channel layer at high temperatures.Attorney Docket No. P24-189-SEC-WO01

[0133] In Act 714, the placement of the source and drain regions is determined by the position of the gate electrode formed in earlier steps. These regions are formed on the channel layer adjacent to the gate electrode. The formation of these regions on the channel layer allows for controlled current flow in the transistor. Additionally, the depth and lateral spread of the source and drain regions can be controlled to maintain the desired channel length under the gate electrode.

[0134] The formation of the source and drain regions in Act 714 may be performed by components described in FIG. 6. For example, the ion implantation process could be carried out using an ion implanter, which accelerates dopant ions and directs them towards specific areas of the channel layer. The transistor structure may be placed on a stage within the implanter, allowing control over the implantation angle and energy. If a diffusion process is used instead, a high-temperature furnace could be employed to drive the dopant atoms into the channel layer. Photolithography equipment may also be used to define the areas where the source and drain regions will be formed, using photoresist patterns to protect other areas of the channel layer during implantation or diffusion.

[0135] There are several variations and alternative embodiments for forming the source and drain regions in Act 714. One common variation is the creation of lightly doped drain (LDD) structures, where a lighter doping concentration is used near the channel region to reduce hot carrier effects. Another alternative is the formation of raised source and drain regions, where additional semiconductor material is grown on top of the original channel layer to reduce parasitic resistances. In some embodiments, the source and drain regions may be formed using epitaxially grown materials that differ from the channel layer, such as silicon-germanium, to induce strain in the channel and vary the carrier mobility. The doping profile of the source and drain regions can also be varied, with options including retrograde profiles or halo implants to fine-tune the transistor's electrical characteristics. These variations allow for customization of the transistor performance to meet specific application requirements.

[0136] FIG. 8 shows experiment data that presents a detailed comparison of the effects of thermal annealing and plasma annealing on the electrical characteristics of FETs, specifically focusing on the threshold voltage (Vth) and subthreshold swing (SS). The figure is divided into three distinct experimental setups, labeled as experiments 802, 804, and 806. Each experiment examines Fets with varying channel widths of 5Attorney Docket No. P24-189-SEC-WO01 pm, 10 pm, 20 pm, and 50 pm, and a consistent gate electrode length of 3 pm with a 2 pm overlap.

[0137] Experiment 802: Control Group

[0138] In the first set of graphs, labeled as experiment 802, the FETs were subjected to no annealing treatment, serving as the control group. The graphs plot the drain current (Id) and gate current (Ig) against the gate voltage (Vg). For the control devices, the Id and 1g curves exhibit clockwise hysteresis which is a sign of a Vt shift due to traps in the device stack. The control group serves as a baseline for comparing the effects of the subsequent annealing processes.

[0139] In experiment 802, which serves as the control group, the FETs were not subjected to any annealing treatment. The Id-Vg and Ig-Vg curves exhibit a pronounced clockwise hysteresis loop, indicating significant charge trapping within the device stack. This trapping is primarily due to defects and impurities in the gate oxide and at the interfaces, which capture and release charge earners as the gate voltage is cycled. The presence of these traps leads to a threshold voltage (Vth) shift, adversely affecting the transistor's switching performance and reliability. The hysteresis observed across various channel widths suggests a consistent issue with charge retention and release, highlighting the need for effective annealing processes to mitigate these effects and improve device stability.Experiment 804: Plasma Annealing

[0140] The second set of graphs, labeled as experiment 804, depicts the impact of plasma annealing on the FETs. Plasma annealing was done on the gate oxide layer before putting down the channel layer. It was conducted using an oxygen plasma generated from a 20% oxygen / gas mixture, with radio frequency energy applied at approximately 800 watts. The Id and Ig curves for the plasma-annealed FETs reveal a significant improvement in terms of the trapping hysteresis from the control group. The threshold voltage (Vth) has moved to negative and ON current has improved significantly. The absence of the clockwise hysteresis loop , indicating that 02 plasma anneal was able to mitigate effect of the traps on the electrical characteristics of the FET devices. The plasma annealing process effectively modifies the thin-film oxide layer, improving its dielectric properties and the overall interface quality with the channel layer. This enhancement is observed consistently across different channel widths, demonstrating the efficacy of plasma annealing in optimizing FET performance.Attorney Docket No. P24-189-SEC-WO01

[0141] Experiment 804 demonstrates the impact of plasma-02 annealing on the FETs, showing a marked improvement in device performance. The plasma annealing process significantly reduces the hysteresis loop observed in the Id-Vg and Ig-Vg curves, indicating a substantial decrease in trap densities. This treatment enhances the dielectric properties of the gate oxide and improves the interface quality between the oxide and the channel layer. As a result, the threshold voltage shifts to more favorable levels, and the ON current is enhanced, leading to improved device stability and reliability. The consistent reduction in hysteresis across different channel widths underscores the effectiveness of plasma-02 annealing in addressing charge trapping issues and optimizing FET performance.Experiment 806: Thermal Annealing

[0142] The third set of graphs, labeled as experiment 806, illustrates the results of thermal annealing on the FETs. The Id and Ig curves for the thermally annealed FETs doesn’t show any significant improvement in terms of the trapping hysteresis from the control group. The threshold voltage (Vth) and subthreshold swing (SS) values remain largely unchanged. The presence of the clockwise hysteresis loop, indicating that thermal annealing does not significantly impact the electrical characteristics of the FETs. This observation is consistent across all channel widths tested, suggesting that thermal annealing alone is insufficient to enhance the FET performance.

[0143] The threshold voltage and subthreshold swing remain largely unchanged, suggesting that the thermal-Ch process does not significantly alter the electrical characteristics of the FETs. This lack of improvement highlights the limitations of thermal annealing in mitigating charge trapping effects.

[0144] Various alternatives and modifications can be devised by those skilled in the art without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications and variances. Additionally, while several embodiments of the present disclosure have been shown in the drawings and / or discussed herein, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. And, those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto. Other elements, steps, methods and techniques that areAttorney Docket No. P24-189-SEC-WO01 insubstantially different from those described above and / or in the appended claims are also intended to be within the scope of the disclosure.

[0145] The embodiments shown in the drawings are presented only to demonstrate certain examples of the disclosure. And, the drawings described are only illustrative and are non-limiting. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to a particular scale. Additionally, elements shown within the drawings that have the same numbers may be identical elements or may be similar elements, depending on the context.

[0146] Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g., "a," "an," or "the,” this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term "comprising" should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression "a device comprising items A and B" should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B.

[0147] Furthermore, the terms "first," "second," "third," and the like, whether used in the description or in the claims, are provided for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances (unless clearly disclosed otherwise) and that the embodiments of the disclosure described herein are capable of operation in other sequences and / or arrangements than are described or illustrated herein.

Claims

1. Attorney Docket No. P24-189-SEC-WO01What is claimed is:

1. A method of forming a transistor, comprising: providing a substrate; providing a silicon dioxide layer disposed on the substrate; providing a gate electrode disposed on the silicon dioxide layer; forming a thin-film oxide layer on the gate electrode and the silicon dioxide layer; generating plasma from diatomic oxygen using an oxygen source; and applying the plasma of the diatomic oxygen to the thin-film oxide layer to anneal the thin-film oxide layer.

2. The method according to claim 1 , wherein the transistor is selected from the group consisting of a thin-film transistor and an AOS.

3. The method according to claim 1 , wherein the substrate is a silicon substrate.

4. The method according to claim 1 , where in the oxygen source comprises a 20% oxygen / gas mixture.

5. The method according to claim 1 , wherein the plasma is generated in a plasma chamber.

6. The method according to claim 1, wherein the plasma is generated using a remote plasma source.

7. The method according to claim 1, wherein the plasma is generated using a direct plasma source.

8. The method according to claim 1, the method further comprising applying a radio frequency energy to the diatomic oxygen to strike the diatomic oxygen to the plasma.Attorney Docket No. P24-189-SEC-WO019. The method according to claims 8, wherein the radio frequency energy is applied at 800 watts of power.

10. The method according to claims 8, wherein the radio frequency energy is applied at about 500 to 800 watts of power.

11. The method according to claims 8, wherein the radio frequency energy is applied at about 500 to 1,000 watts of power.

12. The method according to claim 1, wherein the applying act is performed for about 5 minutes.

13. The method according to claim 1, wherein the applying act is performed from 1 to 30 minutes.

14. The method according to claim 1 , further comprising placing the transistor in a chamber and setting a temperature to 200°C during annealing.

15. The method according to claim 1, further comprising placing the transistor in a chamber and setting a temperature from 100°C to 500°C during annealing.

16. The method according to claim 1 , wherein the transistor has a gate electrode length of about 3 micrometers.

17. The method according to claim 1 , wherein the transistor has a length of about 3 micrometers.

18. The method according to claim 1, wherein the transistor has a channel width selected from the group consisting of 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers.

19. The method according to claim 1, wherein the transistor has a channel width less than 50 micrometers.Attorney Docket No. P24-189-SEC-WO0120. The method according to claim 1, wherein the transistor has a width selected from the group consisting of 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers.

21. The method according to claim 1 , wherein the transistor has a width of less than 50 micrometers.

22. The method according to claim 1, further comprising forming a source region and a drain region adjacent to the gate electrode on the substrate.

23. The method according to claim 22, wherein the transistor has an overlap between the gate electrode and the source region of about 2 micrometers.

24. The method according to claim 22, wherein the transistor has an overlap between the gate electrode and the source region of less than 5 micrometers.

25. The method according to claim 22, wherein the transistor has an overlap between the gate electrode and the drain region of about 2 micrometers.

26. The method according to claim 22, wherein the transistor has an overlap between the gate electrode and the drain region of less than 5 micrometers.

27. The method according to claim 1, wherein the thin-film oxide layer is a high-k dielectric material.

28. The method according to claim 1, wherein the thin-film oxide layer is a ferroelectric oxide.

29. The method according to claim 1 , wherein the transistor is configured as a fieldeffect transistor.Attorney Docket No. P24-189-SEC-WO0130. The method according to claim 29, wherein the transistor is configured as a switch, the method further comprising switching the transistor between at least two states.

31. The method according to claim 29, wherein the transistor is configured as an amplifier, the method further comprising applying a signal to the transistor to amplify the signal.

32. The method according to claim 29, wherein the transistor is configured as a memory device, the method further comprising reading a state of the transistor and corresponding the state to a memory value.33 The method according to claim 29, wherein the field-effect transistor is a ferroelectric field-effect transistor.

34. The method according to claim 1, wherein the gate electrode includes at least one of a metal, tungsten (W), titanium nitride (TiN), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), mthenium (Ru), hafnium (Hf), chromium (Cr), a polysilicon, a metal silicide, a nickel silicide, a cobalt silicide, a titanium silicide, a metal nitrides, and a metal alloy.

35. The method according to claim 1, wherein the gate electrode comprises tungsten.Attorney Docket No. P24-189-SEC-WO0136. The method according to claim 1, wherein the transistor has a gate electrode length from a nanometer to tens of micrometers.

37. The method according to claim 1, wherein the transistor has a gate electrode length from a nanometer to 30 micrometers.

38. A transistor, comprising: a substrate; a silicon dioxide layer disposed on the substrate: a gate electrode disposed on the silicon dioxide layer; and a thin-film oxide layer formed on the gate electrode and the silicon dioxide layer, wherein the thin-film oxide layer has been plasma annealed by exposure to a plasma of diatomic oxygen generated from an oxygen source.

39. The transistor according to claim 38, wherein the transistor is selected from the group consisting of a thin-film transistor and an amorphous oxide semiconductor (AOS).

40. The transistor according to claim 38, wherein the substrate is a silicon substrate.The transistor according to claim 34, wherein the oxygen source comprises a 20% oxygen / gas mixture.

41. The transistor according to claim 38, wherein the plasma is generated in a plasma chamber.

42. The transistor according to claim 38, wherein the plasma is generated using a remote plasma source.Attorney Docket No. P24-189-SEC-WO0143. The transistor according to claim 38, wherein the plasma is generated using a direct plasma source.

44. The transistor according to claim 38, wherein the plasma is generated by applying radio frequency energy to the diatomic oxygen to create the plasma.

45. The transistor according to claim 44, wherein the radio frequency energy is applied at 800 watts of power.

46. The transistor according to claim 44, wherein the radio frequency energy is applied at about 500 to 800 watts of power.

47. The transistor according to claim 44, wherein the radio frequency energy is applied at about 500 to 1,000 watts of power.

48. The transistor according to claim 38, wherein the thin-film oxide layer is annealed for about 5 minutes.

49. The transistor according to claim 38, wherein the thin-film oxide layer is annealed for a duration from 1 to 30 minutes.

50. The transistor according to claim 38, wherein the thin-film oxide layer is annealed at a temperature of 200°C.

51. The transistor according to claim 38, wherein the thin-film oxide layer is annealed at a temperature ranging from 100°C to 500°C.

52. The transistor according to claim 38, wherein the gate electrode has a length of about 3 micrometers.

53. The transistor according to claim 38, wherein the transistor has a length of about 3 micrometers.Attorney Docket No. P24-189-SEC-WO0154. The transistor according to claim 38, wherein the transistor has a channel width selected from the group consisting of 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers.

55. The transistor according to claim 38, wherein the transistor has a channel width less than 50 micrometers.

56. The transistor according to claim 38, wherein the transistor has a width selected from the group consisting of 5 micrometers, 10 micrometers, 20 micrometers, and 50 micrometers.

57. The transistor according to claim 38, wherein the transistor has a width of less than 50 micrometers.

58. The transistor according to claim 38, further comprising a source region and a drain region adjacent to the gate electrode on the substrate.

59. The transistor according to claim 58, wherein there is an overlap between the gate electrode and the source region of about 2 micrometers.

60. The transistor according to claim 58, wherein there is an overlap between the gate electrode and the source region of less than 5 micrometers.

61. The transistor according to claim 58, wherein there is an overlap between the gate electrode and the drain region of about 2 micrometers.

62. The transistor according to claim 58, wherein there is an overlap between the gate electrode and the drain region of less than 5 micrometers.

63. The transistor according to claim 38, wherein the thin-film oxide layer is a high-k dielectric material.

64. The transistor according to claim 38, wherein the thin-film oxide layer is a ferroelectric oxide.Attorney Docket No. P24-189-SEC-WO0165. The transistor according to claim 38, wherein the transistor is configured as a field-effect transistor.

66. The transistor according to claim 65, wherein the transistor is configured to operate as a switch, capable of switching between at least two states.

67. The transistor according to claim 65, wherein the transistor is configured to function as an amplifier, capable of amplifying an input signal.

68. The transistor according to claim 65, wherein the transistor is configured as a memory device, capable of storing and representing a memory state corresponding to a state of the transistor.

69. The transistor according to claim 65, wherein the field-effect transistor is a ferroelectric field-effect transistor.

70. The transistor according to claim 38, wherein the gate electrode includes at least one of a metal, tungsten (W), titanium nitride (TiN), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), platinum (Pt), palladium (Pd), ruthenium (Ru), hafnium (Hf), chromium (Cr), a polysilicon, a metal silicide, a nickel silicide, a cobalt silicide, a titanium silicide, a metal nitrides, and a metal alloy.

71. The transistor according to claim 38, wherein the gate electrode comprises tungsten.

72. The transistor according to claim 38, wherein the transistor has a gate electrode length from a nanometer to tens of micrometers.Attorney Docket No. P24-189-SEC-WO0173. The transistor according to claim 38, wherein the transistor has a gate electrode length from a nanometer to 30 micrometers.

Images