Systems and methods for laser annealing semiconductor junctions

Abstract

Described is a method for laser annealing a semiconductor junction in a stack. The method includes providing a substrate layer; depositing a semiconductor junction layer over the substrate layer; and annealing the semiconductor junction layer by directing a laser beam at an outer surface of the semiconductor junction layer, wherein the laser beam has a wavelength longer than the near infrared range; wherein the substrate layer absorbs more laser energy from the laser beam than the semiconductor junction layer.

Description

1 ,005,602,092SYSTEMS AND METHODS FOR LASER ANNEALING SEMICONDUCTOR JUNCTIONSFIELD OF THE INVENTION

[0001] The present disclosure relates to manufacturing semiconductors. In particular, the present invention relates to laser annealing semiconductor junctions in the manufacturing of semiconductors such as solar cells and optoelectronics.BACKGROUND OF THE INVENTION

[0002] Semiconductor devices, such as solar cells and optoelectronics, are formed from a stack of multiple layers including a substrate layer, a semiconductor junction layer and electrode layers. The semiconductor junction layer may include an active layer or absorber layer between hole and electron transport layers. Semiconductor devices may be either single junction or multijunction devices, that is, they may include multiple semiconductor junction layers. In the manufacturing of semiconductor devices, layers may be annealed to heat treat the layers, facilitating crystallisation, improving electrical characteristics and / or stabilising the material structure. In the case of thin film semiconductors, including organic and hybrid semiconductor junctions such as perovskite and organic photovoltaics, heat treatment is important in the absorber crystallisation process.

[0003] Various heat treatment or annealing techniques exist. Heat treatment or thermal annealing is commonly performed through heating plates. Traditional thermal annealing typically relies on physical contact between the heat source and the semiconductor device and thus, is a thermal conduction method providing full area heating and high substrate temperatures. Photonic annealing with lamps, intense pulsed lights, lasers and the like may provide non-contact annealing, targeted to the absorber with less adverse thermal effects on adjacent functional layers and the substrate. This is beneficial for heat-sensitive substrates. Existing laser photonic annealing techniques have focused on short-wavelength lasers ranging from 355 to 1064 nanometres (nm), such as ultraviolet (UV), visible, and near infrared (NIR) lasers, for example, for laser annealing during solar cell fabrication. However, such short wavelength lasers have high energy that can be detrimental to the chemical bonds of the absorber and / or other layers. Furthermore,1 ,005,602,092 short wavelength laser beams generally have smaller penetration depth into the active layer.

[0004] Accordingly, the inventors of the present invention have identified that there remains a need for improved systems and methods for laser annealing semiconductor junctions. In particular, the inventors have developed techniques for laser annealing semiconductor junctions utilising lasers with wavelengths longer than the near infrared range.

[0005] Background information described in this specification is background information known to the inventors. Reference to this information as background information is not an acknowledgment or suggestion that this background information is prior art or is common general knowledge to a person of ordinary skill in the art.SUMMARY OF THE INVENTION

[0006] According to a first aspect of the invention, there is provided a method for laser annealing a semiconductor junction in a stack, the method including: providing a substrate layer; depositing a semiconductor junction layer over the substrate layer; and annealing the semiconductor junction layer by directing a laser beam at an outer surface of the semiconductor junction layer, wherein the laser beam has a wavelength longer than the near infrared range; wherein the substrate layer absorbs more laser energy from the laser beam than the semiconductor junction layer.

[0007] According to a second aspect of the invention, there is provided a system for laser annealing a semiconductor junction according to the method of the first aspect.

[0008] According to a third aspect of the invention, there is provided a semiconductor device including a semiconductor junction layer laser annealed by the system of the second aspect, according to the method of the first aspect.

[0009] In some embodiments, the semiconductor junction layer is more transparent to the laser beam than the substrate layer. In some embodiments, the laser beam primarily heats the substrate layer, and the substrate layer conveys heat to the semiconductor junction layer thereby annealing the semiconductor layer.1 ,005,602,092

[0010] In some embodiments, the laser beam has a wavelength in the mid infrared range or the far infrared range. In some embodiments, the laser beam has a wavelength between approximately 2.5 micrometres (pm) and approximately 25 pm. In some embodiments, the laser beam has a wavelength between approximately 2.5 pm and approximately 10.6 pm. In some embodiments, the laser beam has a wavelength between approximately 9.3 pm and approximately 10.6 pm. In some embodiments, the substrate layer, the semiconductor junction layer and the wavelength of the laser beam are selected such that the substrate has relatively high absorption of light at the wavelength and the semiconductor junction has relatively low absorption of light at the wavelength.

[0011] In some embodiments, the method further includes depositing a laser modulating layer in the stack, wherein the laser modulating layer is configured to cause the absorption of laser energy, from the laser beam, by the substrate. In some embodiments, the laser modulating layer is one or more of an anti -refraction type layer; an intermittent reflection type layer, a coupling down type layer, a total internal reflection type layer, and a photothermal type layer. In some embodiments, the laser modulating layer is provided: adjacent to the semiconductor junction layer or the substrate layer; between the semiconductor junction layer and the substrate layer; beneath the substrate layer; or on top of the semiconductor junction layer. In some embodiments, the stack includes one or more intermediary layers between the laser modulating layer and the semiconductor junction layer or substrate layer. In some embodiments, the method further includes depositing one or more additional modulating layers in the stack.

[0012] In some embodiments, the laser beam is directed at the outer surface of the semiconductor junction layer with a power density configured to facilitate a phase transition of the semiconductor junction layer and to minimise the occurrence of defects in the semiconductor junction layer. In some embodiments, the laser beam is directed at the outer surface of the semiconductor junction layer with a power density of between approximately 1 .4 kilowatts a square centre metre (kW / cm2) and approximately 2.3 kW / cm2. In some embodiments, the laser beam is directed at the outer surface of the semiconductor junction layer with a power density of between approximately 1 .5 kW / cm2 and approximately 1 .9 kW / cm2. In some embodiments,1 ,005,602,092 the laser beam is directed at the outer surface of the semiconductor junction layer with a power density of approximately 1 .7 kW / cm2.

[0013] In some embodiments, the semiconductor junction layer includes one or more of: an active absorber layer; an organic semiconductor; an inorganic semiconductor; a hybrid semiconductor; perovskite; and formamidinium lead iodide (FAPbh). In some embodiments, the semiconductor junction layer is a perovskite semiconductor junction.

[0014] In some embodiments, the substrate layer includes one or more of: rigid glass, flexible glass, ultrathin glass, borosilicate glass, sapphire, quartz glass, flexible Polyethylene Terephthalate (PET), metal sheet, flexible Poly(dimethylsiloxane) (PMDS) sheet, a silicon junction, a rigid silicon bottom cell, flexible ultra-thin silicon cell, and a copper indium gallium (di)selenide (CIGS) cell.

[0015] In some embodiments, the method includes depositing a bottom electrode layer over the substrate layer; depositing a hole transport layer over the bottom electrode layer, wherein the semiconductor junction layer is deposited over the hole transport layer; depositing an electron transport layer over the semiconductor junction layer; and depositing a top electrode layer over the semiconductor junction layer.

[0016] In some embodiments, the bottom electrode and the top electrode each respectively include one or more of: a transparent conductive oxide (TCO), indium tin oxide (ITO), fluorine-doped tin oxide (FTO), silver (Ag), gold (Au), copper (Cu), aluminium (Al), and chrome (Cr).

[0017] In some embodiments, the hole transport layer includes one or more of a self-assembled molecule, 2-(9H-carbazol-9-yl)ethyl)phosphonic acid (2PACz), (2- (3,6-Diphenyl-9H-carbazol-9-yl)ethyl)phosphonic acid (Ph-2PACz), (2-(3,6- Dimethoxy-9H-carbazol-9-yl)ethyl)phosphonic acid (MeO-2PACz), (4-(3,6- Dimethoxy-9H-carbazol-9-yl)butyl)phosphonic acid (MeO-4PACz), [4-(3,6-Dimethyl- 9H-carbazol-9-yl)butyl]phosphonic Acid (Me-4PACz), Poly[bis(4-phenyl)(2,4,6- trimethylphenyl)amine (PTAA), water-based (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) PEDOTPSS, water-free PEDOT:complex, Nickel oxide (NiOx), Copper(l) thiocyanate (CuSCN), Spiro-based material, WOx, and Culx.1 ,005,602,092

[0018] In some embodiments, the electron transport layer includes one or more of: a metal oxide, a fullerene, an organic polymer, [6, 6]-phenyl-C61 -butyric acid methyl ester (PCBM), buckminsterfullerenes (C60), bathocuproine (BCP), tin oxide (SnO2), zinc oxide (ZnO), and lithium floride (LiF).

[0019] Reference throughout this specification to “some embodiments” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “some embodiments” or “various embodiments” throughout this specification are not necessarily all referring to the same embodiments, but may. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art. For example, in the following description and claims, any of the features of any one the embodiments may be used in any combination.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Preferred embodiments of the invention will be described, by way of example only, with reference to the accompanying drawings in which:

[0021] Figure 1 is an exemplary structure of a semiconductor device stack according to embodiments of the present disclosure.

[0022] Figure 2 is a block diagram of a system for laser annealing a semiconductor device according to embodiments of the present disclosure.

[0023] Figure 3 is an exemplary structure of a perovskite solar cell semiconductor device according to embodiments of the present disclosure.

[0024] Figure 4 is a graph of power conversion efficiency vs annealing laser wavelength for perovskite solar cells laser annealed according to existing methods.

[0025] Figure 5 is a flowchart depicting an example method for manufacturing a semiconductor including laser annealing a semiconductor junction according to embodiments of the present disclosure.1 ,005,602,092

[0026] Figure 6(a) is a scanning electron microscopy (SEM) images of a perovskite thin film of cell annealed by an existing method, with Figures 6(b) to 6(f) showing SEM images of respective perovskite thin films of cells laser annealed according to embodiments of the present disclosure.

[0027] Figures 7(a) to 7(f) are graphs comparing the performance of a perovskite solar cell annealed by an existing method versus perovskite solar cells laser annealed according to embodiments of the present disclosure.

[0028] Figure 8(a) is an exemplary structure of a semiconductor device stack including laser absorption modulating layers, while Figure 8(b) depicts an exemplary structure of a multijunction semiconductor device stack including laser absorption modulating layers.

[0029] Figures 9(a) and 9(b) are graphs comparing the substrate temperature, during laser annealing, of cells with and without a laser absorption modulating layer.

[0030] For ease of reference in the figures and throughout the description, corresponding features have been given corresponding reference numerals. For clarity, not all instances of each feature and not all features in each figure are referenced.DETAILED DESCRIPTION

[0031] Particular embodiments of the invention will now be described, including with reference to manufacturing perovskite solar cells. As will be understood, the invention is also applicable to manufacturing of other semiconductor devices, for example other devices including organic and hybrid thin film semiconductor junctions such as memory devices, LEDs, transistors, photodetectors, lasers and the like.

[0032] Referring generally to the figures, embodiments of the present invention are directed to laser annealing semiconductor junction layers in the manufacture of semiconductor devices, for example, perovskite solar cells. Embodiments of the invention relate to laser annealing semiconductor junctions utilising relatively long wavelength, relatively low photon energy, lasers to induce localised substrate heating for causing annealing of a semiconductor junction layer deposited on the substrate. Particular embodiments of the invention are directed to laser annealing1 ,005,602,092 techniques utilising lasers with wavelengths longer than the near infrared range, for example mid infrared or far infrared wavelength lasers. As used herein, near infrared (NIR) refers to light with a wavelength in the range of 0.7 to less than 2.5 micrometres (pm); mid infrared (MIR) refers to light with a wavelength in the range of 2.5 to 25 pm; and far infrared (FIR) refers to light with a wavelength in the range of greater than 25 pm. Additionally, laser absorption modulating layers may be included in the semiconductor device stack to direct laser energy into the substrate for causing annealing of the semiconductor junction.

[0033] Semiconductor devices may include one or more semiconductor junctions as layers between electrodes on a substrate. Referring to FIGURE 1 , there is illustrated an exemplary semiconductor device 100 structure including a stack 102 of layers. The stack 102 may include a semiconductor junction layer 104, between a hole transport layer 106 and an electron transport layer 108, between electrode layers 110 and 112, on a substrate layer 114. Whilst figure 1 depicts a single junction 104, multilayer semiconductor device 100, in alternative embodiments alternative semiconductor structures are possible, for example p-n junction semiconductors and other semiconductor devices of alternative structures. As part of manufacturing semiconductor devices, the layers may be annealed to improve adhesion and bonding, modify material properties of the layers, reduce defects in the layers, modify electrical characteristics of the layers, control for crystallisation in the layers and / or activate dopants in the layers.

[0034] As discussed above, various heat treatment or annealing techniques exist, such as hot-plate thermal annealing, microwave annealing and laser annealing. Whilst thermal annealing with hot-plates is widely used, laser annealing using continuous wave (CW) or pulsed laser beams has the advantage of providing noncontact annealing. Referring to FIGURE 2, there is illustrated a system 200 for laser annealing semiconductor devices 100. Figure 2 depicts a multijunction semiconductor device 202, including multiple laser absorption modulating layers 204, undergoing laser annealing. In particular, an nth semiconductor junction 206 may be laser annealed following the annealing of a first semiconductor junction, a second semiconductor junction and an n- / th semiconductor junction, and so on for n semiconductor junctions. Such multijunction devices 202 and modulating layers 2041 ,005,602,092 will be described in further detail below. The system 200 is also applicable for laser annealing single junction devices 208 (with or without modulating layers). Laser annealing may be performed after deposition of each respective one or more layers or may be performed to anneal multiple layers at once.

[0035] Broadly speaking, in laser annealing for semiconductor device fabrication, the layers are deposited upon a substrate 114 and annealed by the laser. A laser 210 may operate to emit either a continuous beam or a pulsed beam. The collimated laser beam 212 is emitted by the laser at a laser head 214 including a mirror 216 and a lens 218. The beam 212 is reflected by the mirror 216 and focussed by the lens 218, creating a focused beam 220. To direct the focused beam 220 at a desired spot size upon the semiconductor device for processing, the beam may be positively defocussed by a defocusing depth 222. The beam scans across the semiconductor device 202, across the nth semiconductor junction 206 outer surface 224, synchronising the laser head 214 motion in an in x-direction and y- direction at a desired speed, and operating with a desired pulse per inch. Generally, the laser is directed at the top surface of the semiconductor junction 206. In some embodiments, the laser may be directed at a bottom or underside outer surface, or other surface, of the semiconductor junction 206. For example, the laser may be directed at the underside of the semiconductor junction, through the substrate. The laser beam property parameters (defocusing length, pulse width, pulse energy, pulse repetition rate, pulse per inch, laser power ratio) and scanning motion parameters (scanning trajectory, pulse overlap ratio, scanning speed, delay times for beam emission on / off and axis transition (i.e. , jump delay, on / off delay)) are configured according to the properties of the semiconductor device being processed.

[0036] As one example of semiconductor devices 100, perovskite solar cells utilise a perovskite thin-film photoactive absorber layer between the hole transport layer and the electron transport layer of the semiconductor. Referring to FIGURE 3, there is illustrated an exemplary perovskite solar cell structure as an example of a semiconducting device 300. In particular, the example shown in Figure 3 is a stack 302 including glass / indium tin oxide (ITO) / 2-(3,6-Dimethoxy-9H-carbazol-9- yl)ethyl)phosphonic acid (MeO-2PACz) / formamidinium lead iodide (FAPbh) / buckminsterfullerene (C60) / bathocuproine (BCP) / copper (Cu) as a solar cell1 ,005,602,092 structure. In such semiconductor devices 300, the substrate 314 provides a relatively transparent (to UV and visible light) support structure for the remaining layers in the device; the bottom electrode 310 may be relatively transparent (to UV and visible light) and provides electrical conductivity and acts as a first contact for connecting the device 300 to a circuit; the hole transport layer 306 facilitates extraction and transport of holes from the active layer 304 to the bottom electrode 310, the active layer 304 generates electron-hole pairs upon (visible and / or UV) light absorption; the electron transport layer 308 facilitates extraction and transport of electrons, and may block holes, from the active layer 304 to the top electrode 312; the top electrode 312 provides electrical conductivity and acts as a second contact for connecting the device 300 to the circuit. In alternative embodiments, alternative materials and combinations of materials are also possible. For example, the techniques disclosed herein may be applied to various thin film devices, memory devices, LEDs, transistors, photodetectors, lasers, including such devices having perovskite materials in their structures.

[0037] For example, the substrate 114 may be a rigid or flexible substrate, with or without coatings. Substrate materials may be or include rigid glass, flexible glass, ultrathin glass, borosilicate glass, sapphire, quartz glass, flexible Polyethylene Terephthalate (PET) and / or metal sheet, flexible Poly(dimethylsiloxane) (PMDS) sheet or another suitable substrate material. In the case of a multijunction or multilayer semiconductor device, the substrate may be a silicon junction, a rigid silicon bottom cell, flexible ultra-thin silicon cell, a copper indium gallium (di)selenide (CIGS) cell or the like. In the example of figure 3, the substrate 314 is a glass substrate.

[0038] The electrode layers 110 and 112 may be or include a transparent conductive oxide (TCO) layer, such as indium tin oxide (ITO) or fluorine-doped tin oxide (FTO), or a metal layer such as silver (Ag), gold (Au), copper (Cu), aluminium (Al), or chrome (Cr). The electrode layers may be made of the same material or may each be a different material. In the example of figure 3, the bottom electrode 310 is an ITO electrode and the top electrode 312 is a copper (Cu) contact.

[0039] The hole transport layer (HTL) 106 may be or include self-assembled molecules (SAM) such as 2-(9H-carbazol-9-yl)ethyl)phosphonic acid (2PACz), (2-1 ,005,602,092(3,6-Diphenyl-9H-carbazol-9-yl)ethyl)phosphonic acid (Ph-2PACz), (2-(3,6- Dimethoxy-9H-carbazol-9-yl)ethyl)phosphonic acid (MeO-2PACz), (4-(3,6- Dimethoxy-9H-carbazol-9-yl)butyl)phosphonic acid (MeO-4PACz), [4-(3,6-Dimethyl- 9H-carbazol-9-yl)butyl]phosphonic Acid (Me-4PACz), Poly[bis(4-phenyl)(2,4,6- trimethylphenyl)amine (PTAA), water-based (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) PEDOTPSS and water-free PEDOT:complex, Nickel oxide (NiOx), Copper(l) thiocyanate (CuSCN), Spiro-based material, WOx, Culx and the like. In the particular example of Figure 3, the HTL layer 306 is MeO-2PACz.

[0040] The semiconductor junction layer 104 may be an active absorber layer. The absorber layer may be or include organic and hybrid organic-inorganic layers, for example, perovskite materials. In the particular example of Figure 3, the semiconductor junction layer 304 is formamidinium lead iodide (FAPbh).

[0041] The electron transport layer (ETL) 108 may be or include [6,6]-phenyl-C61 - butyric acid methyl ester (PCBM), buckminsterfullerenes (C60), bathocuproine (BCP), tin oxide (SnO2), zinc oxide (ZnO), lithium floride (LiF), or other suitable materials such as suitable metal oxides, fullerenes, and / or organic polymers. In the example of figure 3, the ETL 308 includes buckminsterfullerenes (C60) and bathocuproine (BCP).

[0042] In the manufacturing of such semiconductor devices, the layers are respectively deposited atop the substrate, and each other, in a deposition process. The deposition processes may include solution processes, spin-coating, slot die coating, inkjet printing, doctor blade coating, physical deposition processes, thermal evaporation, or sputtering. Different layers may be deposited by the same or different deposition processes. Annealing processes, such as laser annealing, may be applied after deposition of the active perovskite layer and / or after deposition of other layers.

[0043] Perovskite solar cells, such as those with a structure of Figure 3B, represent a viable alternative to their counterpart of traditional silicon cells. However, there remains room for improvement in the power conversion efficiency and general effectiveness of perovskite solar cells. Controlling the crystallinity of the perovskite photoactive layer is one avenue for improving the efficiency of perovskite1 ,005,602,092 solar cells. Crystallinity of the perovskite layer is important as high-quality, uniform crystallinity with larger grains, fewer defects and grain boundaries can facilitate improved charge transport, improved light absorption, improved interfacing between layers and overall improved efficiency, stability and durability. Numerous efforts including composition exploration, device structure optimisation, process improvement, as well as passivation strategies, have been attempted to enhance the crystallinity of the perovskite layer and thus improve device performance.

[0044] Heat treatment is an important factor in the perovskite crystallisation process, which provides activation energy for phase transition. Whilst various heat treatment techniques exist, laser annealing has been explored as an advantageous non-contact annealing process. Existing laser annealing techniques have focussed on short-wavelength lasers ranging from 355 to 1064 nanometres (nm), such as ultraviolet (UV), visible, and near infrared (NIR) lasers. Such short-wavelength laser annealing techniques were found to provide targeted heating to the active absorber layer which was beneficial for heat-sensitive substrates. However, such short wavelength lasers also have relatively high energy, 5.0 to 1 .2 electron volts (eV), that can be detrimental to the chemical bonds of the absorber and / or other layers.Further, short wavelength laser beams generally have smaller penetration depth into the active layer. Furthermore, the penetration depth becomes even shorter as heating occurs, considering the enhanced absorption resulting from the heat-induced crystallization or phase transition. The shrinkage in penetration depth may eventually lead to over-heating at the top surface while under heating at the bottom. Such top-down conventional heating processes with short wavelengths are also more likely to induce undesirable reactions (i.e., oxidation) between the film surface and surrounding atmosphere at the top surface. Such short wavelength laser annealing techniques also generally use short pulse widths which can be damaging to the charge transport layers, adjacent to the active perovskite absorber layer.

[0045] Referring to FIGURE 4, there is illustrated a graph 400 concerning various perovskite solar cells which have been laser annealed, showing power conversion efficiency (PCE) percentage (%) versus the laser wavelength by which they were annealed. These results were compiled from a literature study of publications in respect of laser annealed perovskite solar cells ranging from 2016 to 2023, utilising1 ,005,602,092 laser wavelengths between 248 to 1064 nanometres (nm) - i.e., laser annealing with lasers having wavelengths between 0.248 to 1 .064 m, which ranges from the ultraviolet spectrum through the visible spectrum to the low NIR range. Amongst these results, the PCE of the perovskite solar cells laser annealed by such wavelengths varied from 12.1% to 20.8% with the highest PCE 402 (of 20.8%) being achieved, in a publication in 2020, by a perovskite solar cell laser annealed by a laser with a wavelength of 450 nm (0.45 pm).

[0046] Of note in the results of Figure 4 is that, in a publication in 2020, perovskite solar cells laser annealed by a laser with a wavelength of 800 nm (0.8 pm) achieved a PCE 404 of 18.6%. Additionally, in publications in 2016 and 2020, perovskite solar cells laser annealed by a laser with a wavelength of 1064 nm (1 .064 pm) achieved a PCE 406 of 12.1% and 12.5%, respectively. That is, laser annealing with lasers with a wavelength in the NIR range (0.8 and 1 .064 pm) was not as effective, in terms of PCE of the perovskite solar cells, compared to shorter wavelength laser annealing. Moreover, the lowest PCEs 406 were achieved by laser annealing with the longest wavelength NIR, amongst the results, in 2016 and 2020. The results of Figure 4 would thus suggest that, according to conventional laser annealing techniques, laser annealing is most effective with a laser having a wavelength in the area of 450 nm and that longer wavelength lasers were less effective for annealing perovskite solar cells.

[0047] The inventors of the present invention identified that, surprisingly, laser annealing with lasers having a wavelength of longer than the NIR range, for example in the MIR or FIR range could result in particularly efficient perovskite solar cells having PCE as high as 21 .8% without requiring bulk passivation additives or additional surface passivating layers. In initial experiments, involving laser annealing with a carbon dioxide (CO2) laser with a 10.6 pm MIR laser wavelength, it was noticed that higher than expected laser power density was required to anneal the perovskite active layer. It was identified that the laser energy was not substantially interacting directly with the semiconductor junction layer and that, instead, the laser energy was heating the substrate layer which was in turn heating, and annealing, the semiconductor junction layer.1 ,005,602,092

[0048] This was understood by the inventors to be a new and different mechanism for laser annealing the semiconductor junction. Existing techniques focused on higher photon energy lasers with shorter wavelength (e.g., NIR / red / green / UV) to directly heat the semiconductor junction in a direct laser material interaction, where the relatively high laser energy could cause material damage to the semiconductor junction, that is for example, break bonds in perovskite. Advantageously, with the techniques of the present disclosure, perovskite semiconductor junctions were relatively transparent to lasers with longer wavelengths (e.g., MIR and FIR) and thus, the heating was conveyed via the substrate, primarily utilising laser absorption by the substrate not by the semiconductor junction itself. That is, the substrate is substantially less transparent to and has substantially more absorption of MIR and FIR wavelengths, compared to the semiconductor junction. The absorption of various layers will be affected by their respective material composition and properties, as well as their thickness and may be further configured by absorptive coatings. In general, in the present techniques, the substrate is more absorptive than the semiconductor junction for wavelengths in the MIR to FIR range. In one example, a glass substrate layer may be more absorptive than a FAPbh semiconductor junction layer, for a 10.6 pm laser light, suitably at an absorbance ratio of approximately 0.95 : 0.11 , or greater. Although, in alternative examples, alternative absorbance ratios (e.g., 2:1 , 4:1 , 10:1 , etc.) are also feasible, balancing the properties of the substrate and semiconductor junction layers with the advantageous effects of longer wavelength laser annealing as described herein. Thus, the semiconductor junction may be annealed according to various configurations of laser wavelength, power density, and material properties including relative thicknesses and modulating layers.

[0049] That is, when annealing semiconductor junction layers with lasers having wavelengths to which the semiconductor junction layers are relatively transparent, the heating is instead conveyed via the substrate which is heated by the laser. Thus, the laser energy may be absorbed by the substrate (and / or other layers beneath or adjacent the semiconductor junction) and the substrate (and / or the other layers beneath or adjacent the semiconductor junction) may then convey the heating to the semiconductor junction. For example, the electrode and / or HTL layer may absorb laser energy and convey heat to the semiconductor junction. Generally, the1 ,005,602,092 semiconductor junction may be 0.5-1 pm thick, the electrode may be between 100- 200 nm thick, and the HTL may be less than 10 nm thick, whereas the substrate may be hundreds to thousands of microns thick, for example, a thickness in the range 250 pm-2.2 mm. As such, the substrate is substantially more absorptive to the MIR and FIR light than the other layers and thus, the substrate is primarily responsible for the laser-matter interactions (heat generation) and converting heat to the semiconductor junction. For perovskite solar cells, this was found to provide advantages in relation to improved crystallisation, improved phase transition and grain growth, and improved solar cell efficiency.

[0050] The wavelength of the laser for annealing is configured in consideration of the materials and properties of the semiconductor junction layer and the substrate layer, as well as the desired properties of the ultimate semiconductor device. The wavelength may be selected as a wavelength that the substrate has relatively high absorption of, and that the semiconductor junction has relatively low absorption of. The wavelength may be selected from a range of suitable wavelengths based on the properties of the semiconductor junction layer and the substrate layer. The laser annealing wavelength may be selected as a wavelength to which the semiconductor junction is relatively transparent. The laser annealing wavelength, semiconductor junction and substrate may be selected and configured in conjunction. For example, the materials and configuration of the substrate layer may be selected based on a selected wavelength that a selected semiconductor junction is relatively transparent to, such that the substrate has a strong absorption of the selected laser annealing wavelength.

[0051] Semiconductor junctions may have absorption peaks at particular wavelengths in the infrared range, with relatively high transmittance at wavelengths between the peaks, which provides flexibility in selection of the laser wavelength and the substrate. The semiconductor junction may be, for example, a perovskite semiconductor junction layer, another crystalline material or another semiconductor material. For example, perovskites show absorption peaks at 3.3 pm, 6.7 pm and 12.5 pm, with the perovskites being relatively transparent to (having high transmittance of) wavelengths between those absorption peaks. Accordingly, the laser annealing wavelength may be selected as a wavelength between such1 ,005,602,092 absorption peaks. For example, perovskites are particularly transparent to wavelengths between 3.3-6.7 pm, wavelengths between 9.3-10.6 pm, and wavelengths greater than 12.5 pm. Alternatively, depending on the properties of the semiconductor junction and the desired properties of the semiconductor device, wavelengths at such peaks may still be suitable, albeit with greater absorption by the semiconductor junction, provided that the substrate is overall still relatively more absorptive.

[0052] Based on a selected semiconductor junction and laser annealing wavelength, the substrate may be selected and configured to absorb the laser wavelength. For example, a substrate material may have relatively high absorption at laser wavelength ranges at which the semiconductor junction has relatively high transmittance. The substrate layer is also selected in consideration of its rigidity or flexibility and may include coatings to enhance its absorption of the wavelength. In some embodiments, the substrate layer may have an absorption peak between absorption peaks of the semiconductor junction material at the laser annealing wavelength.

[0053] Additionally, the relative thickness of the semiconductor junction layer compared to the substrate layer may also be configured such that the substrate layer absorbs substantially more of the laser energy. This may be particularly advantageous for wavelengths to which the semiconductor junction is only semitransparent. For example, semiconductor junction layer may have a thickness of between 0.5-1 pm whereas the substrate layer may have a thickness of between 100-2,200 pm or thicker. The thickness of substrate relative to the semiconductor junction may be configured to facilitate laser annealing. Moreover, as longer wavelengths can generally penetrate further into materials, the relatively long wavelengths of MIR and FIR are able to travel deeper into semiconductor structures enabling arriving at and primarily interacting with the substrate layer. Thus, the substantial difference in thickness between the layers provides that the substrate will absorb more laser annealing energy, particularly at longer wavelengths.

[0054] Whilst wavelengths of between 9.3-10.6 pm were found to be particularly suitable for laser annealing perovskite thin film semiconductor layers on glass, alternative MIR and FIR wavelengths are also suitable according to respective1 ,005,602,092 semiconductor device structures. For example, laser annealing may be performed at various MIR and FIR laser wavelengths according to the relative absorption of such wavelengths by the substrate and the semiconductor junction, such that the substrate layer absorbs more laser energy than the semiconductor junction layer. In general, the semiconductor junction layer (and potentially intermediary layers) is relatively transparent to an incident laser beam; and the substrate layer is highly absorptive of the incident beam. Both layers can also be relatively thermally non- conductive. Additionally, thermal diffusion length (of / by the layers), determined by pulse width of laser beam and thermal diffusivity of material, is a factor to the local and selective heating via the laser. The layers may thus be selected, and configured, with low thermal conductivity and diffusivity of both layers (in addition to consideration of their absorptance ratio) to contribute to improved heat confinement, improving the overall photothermal process of the laser annealing. Such MIR and FIR laser annealing may provide advantages in laser annealing semiconductor junctions with targeted conveying of heating to the junction or active layer without damaging the active layer. This MIR and FIR laser annealing may also reduce the reactivity between a top surface of the device and the surrounding ambient atmosphere. That is, oxidation is likely to occur when annealing in ambient, however, the (bottom) substrate layer is embedded in (or below) the junction layer, thereby mitigating (or avoiding) the atmosphere influence amid the photo-thermal laser annealing process. This effect - the long wavelength laser annealing not substantially directly interacting with the semiconductor junction layer, and rather heating via laser material interaction with adjacent layers (e.g., the substrate and / or other adjacent layers) - also enables the use of laser absorption modulating layers to further control and enhance the laser material interaction with layers adjacent the semiconductor junction layer. Such modulating layers are discussed in detail further below.

[0055] Referring to FIGURE 5, a method 500 of laser annealing a semiconductor junction 104 in the manufacture of a semiconductor device 100 will now be described. The laser annealing may be performed, for example, using the system 200 of Figure 2. The operations of the method 500 are described, by way of example, in relation to the fabrication of a semiconductor junction device 100 having a stack 102 of multiple layers. The semiconductor device 100 may be a perovskite1 ,005,602,092 solar cell semiconductor device 300, for example a glass / ITO / MeO- 2PACz / FAPbl3 / C60 / BCP / Cu solar cell having the structure of Figure 3. However, in alternative embodiments, alternative systems, configurations, semiconductor structure and materials may be implemented according to the techniques disclosed herein.

[0056] The method 500 begins at step 502 of providing a substrate 114, for example a glass sheet 314 as a support structure for the remaining layers in the stack. At step 504 an electrode layer 110 is deposited onto the substrate layer 114. The electrode layer 110 may be an ITO 310 which is deposited on the glass substrate 314 by a sputtering process. At step 506, a hole transport layer (HTL) 106 is deposited onto the electrode layer 310. The HTL 106 may be deposited in a solution process such as spin-coating, slot die coating, or the like., or an alternative physical deposition such as thermal evaporation. The HTL 106 may be a selfassembled molecule such as MeO-2PACz 306. At step 508, a semiconductor junction layer 104 is deposited onto the HTL 106 in a spin-coating process. The semiconductor junction layer 104 may be a photoactive absorber layer including hybrid organic-inorganic photovoltaics. The semiconduction junction layer 104 may be a perovskite active layer 304, for example, FAPbh.

[0057] In particular, taking FAPbh perovskite as an example, the semiconductor junction layer 304 may be deposited on the HTL by spin-coating the HTL with a precursor solution. The precursor solution may be prepared, for example, by mixing formamidinium iodide (FAI) (258 mg), lead iodide (Pbl2) (692 mg) with dimethylformamide (DMF) (900 pL): N-Methyl-2-pyrrolidone (NMP) (100 pL) binary solvent. The corresponding concentration may be approximately 1 .5M and stirred at room temperature for 30 minutes before use. To deposit the layer, 80 pL of the FAPbh precursor solution may then spin-coated onto the HTL with an acceleration of rate of 400 rpm / s to a spin rate of 4000 rpm for 50 seconds. At 15 seconds into the spin coating, nitrogen (N2) gas quenching (at a pressure of approximately 100 psi) may be applied until the end of spin-coating duration. In alternative embodiments, alternative precursor solutions and spin-coating and deposition processes may be used.1 ,005,602,092

[0058] At step 510, the semiconductor junction layer 104 is laser annealed. The laser annealing may include directing a continuous wave (CW) or pulsed beam 212 of laser light at an outer surface 224 of the semiconductor junction layer 104, for example, the top surface. The laser 210 may have an emission wavelength longer than the NIR range, for example, the laser 210 may have an emission wavelength between 2.5 and 25 pm. The laser 210 may suitably have an emission wavelength between 2.5 and 10.6 pm. In one embodiment, the laser 210 may be a CO2 laser suitably having an emission wavelength of about 10.6 pm. The semiconductor junction 104 may be annealed by laser beam 212 in ambient. The semiconductor junction 104 may be annealed by directing the laser beam 212 at the surface 224 of the semiconductor junction layer 104 and scanning the laser across the surface 224 at a predetermined speed, for example, approximately 254-256 mm / s. The annealing may be performed in a single pass, one-time annealing, or multiple passes / anneals. The laser power density may range from about 1 .4 to about 2.3 kilowatts a square centre metre (kW / cm2). For a 10 by 20 millimetre area of the semiconductor junction layer surface, the overall processing time of the laser annealing may be approximately 60 seconds. The speed of laser scanning and laser power may be configured according to the properties of the material being annealed and the desired properties of the resultant semiconductor junction. For example, the laser power and scanning speeds may be configured to suitably anneal the semiconductor junction 104 balancing thermal effects such as phase transition and crystallisation improvements against thermal defects. X-ray Diffraction (XRD), photoluminescence spectra, transient photoluminescence spectra as well photoluminescence quantum yield (PLQY) analysis of the annealed semiconductor device may be used to determine the annealing effects and revise annealing configurations.

[0059] Continuing the example of the FAPbh active layer of the perovskite solar cell 300, the semiconductor junction layer 304 may be annealed by annealing the deposited FAPbh precursor solution with a laser 210 having an emission wavelength longer than the NIR range. In particular, the FAPbh precursor solution may be annealed in a laser annealing process using a CO2 laser 210 having an emission wavelength of about 9.3 to 10.6 pm. The junction 304 may be annealed by the CO2 laser 210 in a pulsed laser annealing process or a quasi-CW with pulse widths of 60-1 ,005,602,092100 ps. In some embodiments, CW modes may be particularly suitable considering their stronger heat effects induced due to the relatively long pulse durations. For annealing semiconductor junctions 104 and crystallization of perovskites or other crystalline materials having phase transition properties, ultrashort-pulsed lasers are also possible as an alternative laser annealing mode. CW lasers are primarily used for heating, while ultrafast pulsed lasers take advantage of their ultra-high peak power density at ultra-short duration. Advantageously, such MIR lasers 210 are less damaging to semiconductor junctions 104, such as perovskite active layers 304, as they have much longer wavelengths (and thus have lower photon energy) compared to NIR, visible and UV lasers.

[0060] The laser 210 may emit laser light 212 at a mirror 21 that is reflected and focussed by a lens 218, for example a Zinc Selenide (ZnSe) lens, creating a focused beam 220. The focussed beam 220 may be positively defocused by positioning the surface 224 of the semiconductor stack, with the deposited precursor film, below the lens, at a defocussing length 222 of 12.5mm in order to obtain a spot size of emitted laser light of approximately 1 mm in diameter on the surface 224 for processing. The defocused laser beam 220 may then scan across the surface 224 at a rate of 254 mm / s, with a power density in the range of 1 .4 to 2.3 kW / cm2, suitably about 1 .7 kW / cm2, thereby laser annealing the FAPbh semiconductor junction layer 304. In alternative examples, the laser emission wavelength, spot size and power density may be suitably varied according to the material properties of the perovskite layer and the desired properties of the solar cell.

[0061] At step 512, an electron transport layer (ETL) 108 is then deposited on top of the semiconductor junction layer. The ETL 108 may be deposited in a solution process such as spin-coating or a physical deposition such as thermal evaporation. The layer 108 may be (or include) buckminsterfullerenes C60. Additionally, or alternatively, the ETL 108 may be (or include) bathocuproine (BCP). The C60 may be deposited on the semiconductor junction layer 104, for example the perovskite active layer 304, in a thermal evaporation process. The C60 may be deposited on the BCP layer in a further thermal evaporation process. At step 514, a top electrode layer 112 is deposited onto the ETL 104. The top electrode layer 112 may be deposited in a thermal evaporation or sputtering process. The top electrode layer1 ,005,602,092112 may be a copper (Cu) layer 312. The manufacture of the semiconductor device 100 stack 102 is then complete and method 500 ends.

[0062] Whilst method 500 is described above with reference to particular deposition processes for particular layers of particular materials, it will be understood that in alternative embodiments, alternative deposition processes and / or alternative materials may be used for the various layers in the stack. For example, the bottom electrode 110 may be an FTO instead of an ITO. Additionally, or alternatively, for example, the semiconductor junction layer 104 may be deposited in a slot die coating, inkjet printing, doctor blade coating, thermal evaporation, or sputtering process instead of a spin-coating process. In alternative embodiments, semiconductor devices 100 other than perovskite solar cells 300 may be manufactured and the semiconductor junction laser annealed according to the method 500. For various devices 100, the semiconductor junction layer 104, substrate layer 114 material and laser annealing wavelength may selected such that the substrate 114 has relatively high absorption of light at the wavelength and the semiconductor junction 104 has relatively low absorption of light at the wavelength. Many alternatives and combinations of alternatives are possible.

[0063] The method 500 focuses, in particular, on the laser annealing of the semiconductor junction layer 104. Whilst not specifically illustrated in Figure 5 with reference to the steps of method 500, additional pre-processing, processing and post-processing steps of various layers and the stack 102 may also be performed. Additional pre-processing, processing and / or post-processing steps may be performed or omitted depending on the properties and requirements of the semiconductor device and the speed and scale of the manufacturing process. Additional pre-processing, processing and post-processing steps may include additional annealing steps. Additional annealing steps may include laser annealing and / or alternative thermal annealing processes.

[0064] In some embodiments, for example, one or more of the bottom electrode 110, HTL 106, ETL 108, and / or top electrode 112 may be annealed before the deposition of subsequent layers, and / or as part of an aggregated annealing stage in addition to the steps 502 to 514 of method 500. In some embodiments the bottom electrode layer 110, for example an ITO layer 310, may be annealed before1 ,005,602,092 depositing the HTL layer 106. In some embodiments the HTL layer 106 may be annealed before depositing the semiconductor junction layer 104. In some embodiments the ETL layer 108 may be annealed before depositing the top electrode layer 112. In some embodiments the semiconductor junction layer 104 may undergo an additional annealing process after depositing the ETL 108. In some embodiments, the top electrode layer 112 and / or completed stack 102 may undergo a further annealing or thermal postprocessing step. In some embodiments one or more, or all, additional annealing may be foregone depending on the properties of the semiconductor device 100 and its layers. For example, where a layer is deposited in a thermal evaporation process, such as when the C60 and BCP layers 308 are deposited as the ETL 108 in a thermal evaporation process, the deposition process may involve sufficient thermal treatment and thus, specific annealing of the layer may be foregone.

[0065] Additionally, whilst method 500 is described with reference to the laser annealing of a single semiconductor junction layer 104, the techniques may also be applicable to multijunction semiconductor devices 202. For example, the step 502 of providing a substrate 114 may include providing a different semiconductor junction (e.g., a silicon bottom cell) as the substrate for supporting a stack 102 including a further semiconductor junction layer 104. In alternative embodiments, for example, steps 506 to 512, of depositing the HTL 106, depositing and annealing the semiconductor junction layer 104, and depositing the ETL 108 may be repeated in one or more loops to manufacturer a multijunction semiconductor device 202 including multiple semiconductor junctions 104. Furthermore, additional steps of providing and / or depositing one or more laser modulating layers 204 in the stack 104, for example beneath the substrate 114, between the substrate 114 and the semiconductor junction layer 104, and / or above the semiconductor junction layer 104 may also be included between the steps 502-510.

[0066] Referring now to FIGURES 6(a) to 6(f) and FIGURES 7(a) to 7(f), the performance of perovskite solar cells annealed by conventional thermal annealing is compared to the performance of MIR laser annealed perovskite solar cells. In particular, six categories of glass / ITO / MeO-2PACz / FAPbl3 / C60 / BCP / Cu single junction perovskite solar cells were tested, ambient thermal annealed (ATA) cells1 ,005,602,092 and five categories of ambient laser annealed (ALA) cells, annealed with a MIR (~10.6pm) laser at various power densities: ~1.4; ~1 .5; ~1.7; ~1.9; and ~2.3 kW / cm2.

[0067] Figures 6(a) to 6(f) are scanning electron microscopy (SEM) images of the respective perovskite thin films of cells annealed by (a) ATA and (b-f) ALA using MIR laser power densities (b) 1 .4 kW / cm2, (c)1 .5 kW / cm2, (d) 1 .7 kW / cm2, (e) 1 .9 kW / cm2, and (f) 2.3 kW / cm2. The scale bar, in the bottom right corner of each image, is 300 nm. In Figure 6(a), for the ATA cell, grain growth self-limits as neighbouring grains begin to impinge on each other. In Figures 6(b) to 6(f), for the ALA cells, grain growth extends to regions that are not yet irradiated. This is indicative of the new and different mechanism of laser with wavelengths longer than NIR primarily interacting with the substrate which then conveys heat to the perovskite active layer. Across Figures 6(b) to 6(f), the increasing laser power leads to increased grain size. Although film decomposition occurs at very high laser power, evident in cracks, pinholes and increased roughness (circled in broken lines) in Figure 6(f). The increase in laser power facilitates 5- to a-phase transition and grain growth in the perovskite. However, increasing laser power also drives out volatile organic component increasing the presence of Pbl2 and related defects.

[0068] Figures 7(a) to 7(f) are graphs of results collected from multiple respective measurements of the categories of cells, that is cells annealed by ATA and ALA at various power densities. Figure 7(a) shows short circuit current density (Jsc) in mA / cm2on the y-axis versus ATA and ALA power density (kW / cm2) along the x-axis. Figure 7(b) shows open circuit voltage (Voc) in mV on the y-axis versus ATA and ALA power density (kW / cm2) along the x-axis. Figure 7(c) shows fill factor (FF) as a percentage on the y-axis versus ATA and ALA power density (kW / cm2) along the x- axis. Figure 7(d) shows power conversion efficiency (PCE) as a percentage on the y-axis versus ATA and ALA power density (kW / cm2) along the x-axis. In Figures 7(a) to 7(d), respective measurements are provided as scatter points above the respective annealing category of the cell, along with box and whisker plots and a distribution curve showing the distribution of the respective points. Figure 7(e) shows curves of current density in mA / cm2on the y-axis versus voltage in volts (V) along the x-axis, measured for a respective champion cell in each category. The curves of Figure 7(e), originating from the y-axis, from top to bottom respectively1 ,005,602,092 correspond to the champion cells for ALA 1 .7 kW / cm2; ATA; ALA 1 .9 kW / cm2; ALA 1 .5 kW / cm2; ALA2.3 kW / cm2; and ALA 1 .4 kW / cm2. Figure 7(f) shows curves of external quantum efficiency (EQE) as a percentage on the y-axis versus the wavelength of incident in nanometres (nm) along the x-axis, measured for a respective champion cell in each category. The curves of Figure 7(f), from top to bottom, respectively correspond to the champion cells for ALA 1 .9 kW / cm2; ALA 1 .7 kW / cm2; ATA; ALA 1 .5 kW / cm2; ALA 2.3 kW / cm2; and ALA 1 .4 kW / cm2.

[0069] Table 1 , below, summarises the photovoltaic performance of the champion perovskite solar cells in each of the categories of devices measured.Table 1 performance of ATA and ALA perovskite solar cells

[0070] The highest efficiency was achieved with the cell laser annealed with 1 .7 kW / cm2power density, reaching 21 .8% PCE which is higher than 17.6% thermal annealed device in ambient (ATA). Thus, laser annealing with a relatively long wavelength (MIR) laser provided an efficient cell, moreover, this was achieved in ambient; without bulk passivation additives or additional surface passivating layers; with relatively short processing time (-60S); and at a relatively low substrate temperature (~24-38°C).

[0071] Across the ALA cells, as mentioned above, increasing laser power aided phase transition, improving crystallisation and the performance of the solar cells. Short circuit current density (sc) increases with increasing laser power, due to the improved phase transitioning. Although, at very high laser power (~2.3 kW / cm2), declines due to film decomposition and defects. Open circuit voltage (Voc) decreases with increasing laser power due to the gradual precipitation of Pbh which leads to defects. Recombination was also found to increase with laser power, with increasing laser power increasing (n) due to higher trap-assisted Shockley-Read-Hall1 ,005,602,092 recombination; and decreasing activation energy (Ea) for recombination as recombination is more surface dominated due to the increasing the presence of Pbh related defects. Therefore, the optimal laser power is determined based on balancing the competing effects that increasing the laser power density has on the efficiency, phase transition, film decomposition, defect generation, and recombination according to the material and electrical properties of the semiconductor junction.

[0072] Referring to FIGURES 8(a) and 8(b), laser absorption modulating layers 204 (modulating layers for short) will now be described. Broadly speaking, modulating layers 204 may be incorporated into the stack 102 of a semiconductor device 100 to modulate laser absorption for desirable thermal effects at various layers during manufacturing and laser annealing processes. The modulating layers 204 are configured in consideration of the different laser absorption behaviours and properties of and between different materials, for example, their refractive index and photothermal absorption properties. In general, the modulating layers 204 are used to facilitate converting laser energy into heat at a desired layer and to convey the heat to the same or a different desired layer in a desired manner to cause annealing. For example, modulating layers 204 may be introduced into a semiconductor device 100 stack 102 to facilitate annealing of the semiconductor junction layer 104 by modulating the laser absorption and heat generation of the semiconductor junction 104 and adjacent layers.

[0073] One or more modulating layers 204 may be introduced into a semiconductor device 100 stack 102 at various locations within the stack. For example, referring to Figure 8(a), the stack 802 may include a modulating layer 204 between the semiconductor junction 104 and the substrate 114, above the semiconductor junction 104, and / or below the substrate 114. Figure 8(a) also symbolically shows, for reference, transmitted laser light 804 directed from the top of the stack 802 towards the bottom of the stack, generally passing through the semiconductor junction 104 and then the substrate 114. Transmitted laser light 802 may also pass through the substrate 114 and reflected light 806 reflected back into the substrate 114 by the bottom most modulating layer 204. Furthermore, figure 8(a) symbolically shows the heat 808 from laser material interaction in the respective1 ,005,602,092 modulating layers 204 or substrate 114 being conveyed to the semiconductor junction 104. The laser material interaction and heat generation may primarily occur in the substrate 114. Additionally, or alternatively, heat generation may occur in the modulating layers 204 and the interface between the modulating layer(s) 204 and the substrate 114 and / or the semiconductor junction 104. Semiconductor device 100 stacks 102 may include multiple modulating layers 204. Each modulating layer 204 may be directly adjacent to the semiconductor junction 104 or the substrate 114, or there may be intermediate layers between a respective modulating layer 204 and the semiconductor junction 104 and / or the substrate 114. In a multijunction semiconductor device stack 810 (such as that shown in Figure 8(b)), one or more modulating layers 204 may correspond to (and be positioned adjacent to) respective semiconductor junctions 104.

[0074] Types of modulating layers 204 may include anti-refraction type layers, intermittent reflection type layers, coupling down type layers, total internal reflection type layers, and / or photothermal type layers. In some embodiments, a respective modulating layer 204 may comprise (and include the properties of) more than one type of modulating layer. The modulating layers 204 may be or include silica materials, metals, polymer materials and other suitable materials having a suitable refractive index, reflectivity, absorptivity and / or photothermal absorption properties for the respective modulating type. Respective modulating layers 204 may be deposited using a spin coating process, a dip-coating process, a thermal evaporation process, or another suitable process, at a desired location in the stack 102 during the manufacturing process of the semiconductor device 100.

[0075] An anti-refraction modulating layer 204 may be deposited on top of the semiconductor junction 104 in the stack 102. The anti-refraction modulating layer 204 may be configured with a refractive index which causes laser light energy to be substantially absorbed by the modulating layer 204, or to facilitate laser light energy being absorbed by the substrate 114. An intermittent reflection modulating layer 204 may be deposited below the semiconductor junction 104 in a stack 102. The intermittent reflection modulating 204 layer may be configured to partially and / or intermittently reflect laser light. A coupling down modulating layer 204 may be deposited between the semiconductor junction 104 and the substrate 114 in the1 ,005,602,092 stack 102. The coupling down modulating layer 204 may be configured to couple more laser light energy into the substrate 114. For example, for substrates 114 with a higher refractive index than the semiconductor junction 104, the coupling down modulating layer 204 may be configured to have a refractive index between that of the semiconductor junction 104 and the substrate 114. A total internal reflection layer 24 may be deposited underneath, that is deposited or provided on the bottom surface of, the substrate 114 in the stack 102. The total internal reflection layer 204 may be configured with a refractive index which causes laser light to be reflected back towards the substrate 114. Additionally, or alternatively, a highly reflective layer 204 could be deposited underneath the substrate 114 to reflect the laser light back into the substrate 114. Furthermore, a photothermal modulating layer 204 may be deposited adjacent the semiconductor junction 104 and / or the substrate 114. Regardless of respective refractive indexes, the photothermal modulating layer 204 may include active photothermal materials to enhance the thermal effect at the interface between the modulating layer 204 and the semiconductor junction 104 and / or the substrate 114.

[0076] As shown in Figure 8(b) modulating layers 204 may be deposited between the substrate 114 and the different semiconductor junctions 104 of a multijunction device 810. Each stack 812 and 814 of figure 8(b) may include substantially similar layers to those of figure 1 , with the further inclusion of the modulating layers 204. Each modulating layer 204 may be a silica thin layer, a polymer layer such as PMMA, cellulose, or another material having a suitable refractive index and photothermal properties for modulating the laser absorption in the device 810 stacks and respectively targeting the specific junction(s) 104 in the stack 812 and / or 814.

[0077] Referring initially to the first semiconductor junction stack 812 of Figure 8(b), the stack 812 may have a structure similar to that of the perovskite solar cell stack of Figure 3, additionally including a modulating layer 204 provided between the semiconductor junction 104 and the substrate 114. In particular, in Figure 8(b), a modulating layer 204 is deposited on top of the bottom electrode layer 110 and beneath the HTL 106. In such an example, the modulating layer 204 may be silica nanoparticle (SiC ) layer deposited on a glass substrate 314 and an ITO hole transport layer 306 for improving the thermal effect when laser annealing the1 ,005,602,092 perovskite semiconductor junction layer 304. The modulating layer 204 may also work as an intermittent reflection layer, or may absorb more laser power by itself, or may couple laser power into the substrate 114 to cause annealing of the semiconductor junction 104.

[0078] The silica nanoparticle laser modulating layer 204 may be deposited by a spin coating process, or from the chemical translation from tetraethyl orthosilicate (TEOS), or other vapor deposition processes such as magnetron sputtering, atomic layer deposition. The spin coating deposition may include spin coating the substrate 114 and bottom electrode 110 with a silica nanoparticle precursor with a speed of 4000 rpm, at an acceleration of 2000 rpm / s, and a spinning duration of 16s. This may be followed by an annealing step, of the silica nanoparticle layer, for 10 minutes at 100°C temperature in ambient. After the laser modulating layer 204 has cooled to room temperature, the HTL 106, for example a monolayer of self-assembled molecules (e.g., MeO-2PACz) may be deposited using spin coating. That is, for example, the laser modulating layer 204 may be deposited onto the stack 102 between steps 504 and 506 of method 500. After which the semiconductor junction layer 104 (e.g., FAPbh) may be deposited, for example, by spin coating a precursor solution on top of the HTL 106. The semiconductor junction layer 104 may then be laser annealed (e.g., as at step 510 of method 500) with the stack 102 now including a modulating layer 204 to modulate laser absorption for desirable thermal effects to facilitate active layer crystallisation.

[0079] Additionally, referring now to the subsequent semiconductor junction stack 814 of Figure 8(b), once a first junction 104 has been annealed (and intermediary layers deposited), a second junction 104 and intermediary layers may be deposited onto the stack and annealed. A multijunction semiconductor device 810 of n junctions may thus be formed by iteratively depositing semiconductor junctions 104 (and intermediary layers) on top of the first semiconductor junction and annealing the respective laser. Each semiconductor junction stack 812, 814 in the device 810 stack may include one or more one or more modulating layers 204 to facilitate laser annealing of the respective semiconductor junction layer 104. Whilst the above example is in respect of a silica nanoparticle modulating layer 204, in alternative embodiments additional or alternative modulating layers 204 or alternative materials1 ,005,602,092 and / or types may be included in the stack. Furthermore, the above example is not limited to perovskite solar cells, the techniques and modulating layers 204 are also applicable to alternative semiconductor devices 100 and semiconductor junction stacks 102 including alternative layers and materials. For example, semiconductor junction stacks 102 deposited on silicon substrates 114, including other semiconductor junctions 104 such as a silicon bottom cell, may also include modulating layers 204 and be laser annealed according to the above techniques.

[0080] Referring to FIGURES 9(a) and 9(b), the effect of the inclusion of a modulating layer 204 is demonstrated with the example of laser annealing a semiconductor junction 104 deposition on a substratel 14. Figure 9(a) compares the substrate 114 temperature between a first cell and second cell, during laser annealing of the respective cells. Each cell respectively includes a top semiconductor junction 104 deposited on top of a silicon bottom (silicon / ITO) substrate 114. The first cell includes a laser modulating layer 204, in this example a silica (SiO2) nanoparticle layer deposited on top of the silicon / ITO substrate 114. The modulating layer 204 may be deposited in a process similar to that described above, after which the top semiconductor junction 104 is deposited on top of the modulating layer 204. In this example, the modulating layer 204 acts as a laser absorption modulating layer. For the second cell, the respective top semiconductor junction 104 is deposited onto the substrate 114 without a modulating layer between. The respective top semiconductor junctions 104 of the first and second cell are then laser and annealed and Figure 9(a) shows the temperature of the silicon bottom cell substrate 114 of each cell during the laser annealing. The temperature of the first cell substrate 114, having the modulating layer 204, is shown by the line 901 with square points; and the temperature of the second cell substrate 114, not having a modulating layer is shown by the line with circular points 902. The measurement for substrate temperature of the first cell is approximately 12% higher than the second cell, demonstrating the stronger thermal effect via the silica modulating layer 204 atop the silicon / ITO.

[0081] Figure 9(b) compares the substrate temperature between a third cell and fourth cell, during laser annealing of the respective cells. Each cell respectively includes a top semiconductor junction 104 deposited on top of a silicon bottom cell1 ,005,602,092(Si) substrate 114. The third cell includes a laser modulating layer 204, in this example a polymethyl methacrylate (PMMA) layer, deposited on top of the substrate 114. The modulating layer 204 may be deposited in a suitable process similar to that described above, after which the semiconductor junction 104, in this example a perovskite semiconductor junction layer 304, is deposited on top of the modulating layer 204. In this example, the modulating layer acts as a thermal modulation layer. For the fourth cell, the respective perovskite semiconductor junction 304 is deposited onto the substrate 114 without any modulating layer between. The respective top semiconductor junctions 104 of the third and fourth cell are then laser and annealed and Figure 9(b) shows the temperature of the silicon bottom cell substrate 114 of each cell during the laser annealing. The temperature of the third cell substrate 114, having the modulating layer 204, is shown by the top line 903; and the temperature of the fourth cell substrate 114, not having a modulating layer is shown by the bottom line 904. As will be seen, the substrate temperature of the third cell is approximately 16% higher than the fourth cell, demonstrating the stronger thermal effect via the PPM modulating layer 204 between the substrate 114 and the semiconductor junction 104. Whilst Figures 9(a) and 9(b) show results from cells with a single modulating layer 204 (of silica or PPM), multiple modulating layers 204 and a variety of different materials for modulating layers may be employed.

[0082] Advantageously, the above-described techniques may laser anneal semiconductor junctions 104 with relatively long wavelength, low photon energy lasers 210, providing rapid heating rate, high spatial selectivity, short heating duration, and resultant improved semiconductor device 100 performance. The annealing may provide improved thin film crystallisation and reduced damage to active layers in phase transition for organic and hybrid semiconductor junctions compared to conventional long wavelength laser annealing. Additionally, the laser absorption modulating layers 204 reduce the laser annealing threshold and enable a lower power requirement. Accordingly, embodiments disclosed herein, including the techniques described above, may provide improved systems and methods for laser annealing semiconductor junctions utilising relatively long wavelength, low photon energy, lasers.1 ,005,602,092

[0083] In the above-described structures and techniques, where a first layer is deposited or provided above, on top of, beneath, underneath, or adjacent to a second layer, this includes doing so directly and also envisions including intermediary layers. That is, the first layer may be in direct contact with the second layer or one or more intermediary layers may exist between the layers in a stack. For example, where a semiconductor junction is deposited on top of a substrate, the semiconductor junction may be deposited directly on top of the substrate or there may be one or more intermediary layers (e.g., electrode, modulating layer(s), HTL, etc.) between the semiconductor junction layer and the substrate.

[0084] Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that the invention may be embodied in many other forms. For example, the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text or drawings. All of these different combinations constitute various alternative aspects of the invention.

[0085] The flowcharts illustrated in the figures and described above define operations in particular orders to explain various features. In some cases, the operations described and illustrated may be able to be performed in a different order to that shown / described, one or more operations may be combined into a single operation, a single operation may be divided into multiple separate operations, and / or the function(s) achieved by one or more of the described / illustrated operations may be achieved by one or more alternative operations. Still further, the functionality / processing of a given flowchart operation could potentially be performed by (or in conjunction with) different applications running on the same or different computer processing systems.

[0086] In certain instances where the present disclosure uses the terms “first,” “second,” etc. to describe various elements. Unless stated otherwise, these terms are used only to distinguish elements from one another and not in an ordinal sense. For example, a first element or feature could be termed a second element or feature or vice versa without departing from the scope of the described examples.1 ,005,602,092

[0087] As used herein, except where the context requires otherwise, the terms “include” and “comprise” (and variations thereof such as “including”, “includes”, “comprising”, “comprises”, “comprised” and the like) are used inclusively and do not exclude further features, components, integers, steps, or elements.

Claims

1 ,005,602,092CLAIMS1 . A method for laser annealing a semiconductor junction in a stack, the method including: providing a substrate layer; depositing a semiconductor junction layer over the substrate layer; and annealing the semiconductor junction layer by directing a laser beam at an outer surface of the semiconductor junction layer, wherein the laser beam has a wavelength longer than the near infrared range; wherein the substrate layer absorbs more laser energy from the laser beam than the semiconductor junction layer.

2. The method of claim 1 , wherein the semiconductor junction layer is more transparent to the laser beam than the substrate layer.

3. The method of any one of the preceding claims, wherein the laser beam primarily heats the substrate layer, and the substrate layer conveys heat to the semiconductor junction layer thereby annealing the semiconductor layer.

4. The method of any one of the preceding claims, wherein the laser beam has a wavelength in the mid infrared range or the far infrared range.

5. The method of any one of the preceding claims, wherein the laser beam has a wavelength of: between approximately 2.5 micrometres (pm) and approximately 25 pm; between approximately 2.5 pm and approximately 10.6 pm; or between approximately 9.3 pm and approximately 10.6 pm.

6. The method of any one of the preceding claims, wherein the substrate layer, the semiconductor junction layer and the wavelength of the laser beam are selected such that the substrate has relatively high absorption of light at the wavelength and the semiconductor junction has relatively low absorption of light at the wavelength.

7. The method of any one of the preceding claims, further including the step of depositing a laser modulating layer in the stack, wherein the laser modulating layer is configured to cause the absorption of laser energy, from the laser beam, by the substrate.1 ,005,602,0928. The method of claim 7, wherein the laser modulating layer is one or more of an anti-refraction type layer; an intermittent reflection type layer, a coupling down type layer, a total internal reflection type layer, and a photothermal type layer.

9. The method of claim 7 or claim 8, wherein the laser modulating layer is provided: adjacent to the semiconductor junction layer or the substrate layer; between the semiconductor junction layer and the substrate layer; beneath the substrate layer; or on top of the semiconductor junction layer.

10. The method of claim 10, wherein the stack includes one or more intermediary layers between the laser modulating layer and the semiconductor junction layer or substrate layer.11 . The method of any one of claims 7 to 10, further including the step of depositing one or more additional modulating layers in the stack.

12. The method of any one of the preceding claims, wherein the laser beam is directed at the outer surface of the semiconductor junction layer with a power density configured to facilitate a phase transition of the semiconductor junction layer and to minimise the occurrence of defects in the semiconductor junction layer.

13. The method of claim 12, wherein the laser beam is directed at the outer surface of the semiconductor junction layer with a power density of: between approximately 1 .4 kilowatts a square centre metre (kW / cm2) and approximately 2.3 kW / cm2; between approximately 1 .5 kW / cm2and approximately 1 .9 kW / cm2; or approximately 1 .7 kW / cm2.

14. The method of any one of the preceding claims, wherein the semiconductor junction layer includes one or more of: an active absorber layer; an organic semiconductor; an inorganic semiconductor; a hybrid semiconductor; perovskite; and formamidinium lead iodide (FAPbh).

15. The method of any one of the preceding claims, wherein the semiconductor junction layer is a perovskite semiconductor junction.1 ,005,602,09216. The method of any one of the preceding claims, wherein the substrate layer includes one or more of: rigid glass, flexible glass, ultrathin glass, borosilicate glass, sapphire, quartz glass, flexible Polyethylene Terephthalate (PET), metal sheet, flexible Poly(dimethylsiloxane) (PMDS) sheet, a silicon junction, a rigid silicon bottom cell, flexible ultra-thin silicon cell, and a copper indium gallium (di)selenide (CIGS) cell.

17. The method of any one of the preceding claims, further including: depositing a bottom electrode layer over the substrate layer; depositing a hole transport layer over the bottom electrode layer, wherein the semiconductor junction layer is deposited over the hole transport layer; depositing an electron transport layer over the semiconductor junction layer; and depositing a top electrode layer over the semiconductor junction layer.

18. The method of claim 17, wherein the bottom electrode and the top electrode each respectively include one or more of: a transparent conductive oxide (TCO), indium tin oxide (ITO), fluorine-doped tin oxide (FTO), silver (Ag), gold (Au), copper (Cu), aluminium (Al), and chrome (Cr).

19. The method of claim 17 or 18, wherein the hole transport layer includes one or more of a self-assembled molecule, 2-(9H-carbazol-9-yl)ethyl)phosphonic acid (2PACz), (2-(3,6-Diphenyl-9H-carbazol-9-yl)ethyl)phosphonic acid (Ph-2PACz), (2- (3,6-Dimethoxy-9H-carbazol-9-yl)ethyl)phosphonic acid (MeO-2PACz), (4-(3,6- Dimethoxy-9H-carbazol-9-yl)butyl)phosphonic acid (MeO-4PACz), [4-(3,6-Dimethyl- 9H-carbazol-9-yl)butyl]phosphonic Acid (Me-4PACz), Poly[bis(4-phenyl)(2,4,6- trimethylphenyl)amine (PTAA), water-based (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) PEDOTPSS, water-free PEDOT:complex, Nickel oxide (NiOx), Copper(l) thiocyanate (CuSCN), Spiro-based material, WOx, and Culx.

20. The method of any one of claims 17 to 19, wherein the electron transport layer includes one or more of: a metal oxide, a fullerene, an organic polymer, [6,6]-phenyl- C61 -butyric acid methyl ester (PCBM), buckminsterfullerenes (C60), bathocuproine (BCP), tin oxide (SnO2), zinc oxide (ZnO), and lithium floride (LiF).

Images