Integrated circuit and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronic devices, and provide an integrated circuit and an electronic device. The integrated circuit comprises a chip, a plurality of first connecting members, a first conductive group, and a second conductive group. The chip is provided with a plurality of first through holes arranged at intervals, and the first through holes run through the chip. The first connecting members are arranged in the corresponding first through holes. The first conductive group and the second conductive group are respectively arranged on two sides of the chip. The first conductive group is electrically connected to one end of each of the plurality of first connecting members, and the second conductive group is electrically connected to the other end of each of the plurality of first connecting members. The first conductive group and / or the second conductive group comprise(s) a plurality of conductive layers, a plurality of contact portions are provided between two adjacent conductive layers, and the two adjacent conductive layers are electrically connected by means of the plurality of contact portions. In the embodiments of the present application, a transmission path having a large current-carrying capacity can be obtained without additionally adding a manufacturing step for the integrated circuit, thereby achieving signal transmission having good performance between a front surface and a back surface of the chip.

Description

Integrated circuits and electronic devices

[0001] This application claims priority to Chinese patent application No. 202411577819.4, filed on November 5, 2024, entitled "Integrated Circuits and Electronic Devices", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic equipment technology, and more particularly to an integrated circuit and an electronic device. Background Technology

[0003] Moore's Law predicted an exponential increase in transistor density, and with the evolution of technology, the most advanced devices have now reached the nanoscale. However, the miniaturization of device size forces a simultaneous reduction in metal linewidth, significantly increasing the resistance on the wires. This results in a marked increase in signal transmission delay and voltage drop, limiting improvements in chip utilization and power consumption reduction, and diminishing the gains in power consumption, performance, and area of ​​advanced nodes.

[0004] Backside power delivery (BSPDN) technology offers an effective solution to this problem by adding metal interconnects to the back of the chip and connecting them to devices on the front of the chip via nanovias (nTSVs). This allows the power network to be constructed on the back metal, while the front metal is used entirely for signal routing. On one hand, the thicker metal network on the back significantly reduces voltage drop (IR Drop); on the other hand, the freed-up routing resources on the front alleviate routing stress, improving chip utilization or limiting frequencies.

[0005] However, in BSPDN technology, after the signal is generated and propagated on the front side of the chip, in order to facilitate subsequent packaging, the signal network on the front side of the chip still needs to be packaged with the packaging structure through a substrate set on the back side of the chip. Some signals (such as input and output signals) have large current amplitudes. In the process of these signals being transmitted from the front side of the chip to the substrate on the back side of the chip, a transmission path with high current carrying capacity is required to ensure good signal transmission. Summary of the Invention

[0006] This application provides an integrated circuit and an electronic device, the purpose of which is to obtain a transmission path with high current carrying capacity without adding extra integrated circuit fabrication steps or increasing fabrication difficulty, and to achieve high-performance signal transmission between the front and back of the chip.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, an integrated circuit is provided, which includes a chip, a plurality of first connectors, a first conductive group, and a second conductive group.

[0009] The chip has multiple first through holes spaced apart and penetrating the chip. First connectors are disposed within the first through holes. First conductive groups and second conductive groups are disposed on opposite sides of the chip, with the first conductive group electrically connected to one end of each of the first connectors and the second conductive group electrically connected to the other end of each of the first connectors.

[0010] The first conductive group and / or the second conductive group include multiple conductive layers, which are stacked and spaced apart along a third direction, which is perpendicular to the chip; multiple contact portions are provided between adjacent conductive layers, which are spaced apart along a direction parallel to the chip, and adjacent conductive layers are electrically connected through the multiple contact portions.

[0011] In the integrated circuit provided in this application embodiment, by connecting multiple first connectors in parallel and connecting multiple conductive layers in the first conductive group and / or the second conductive group connected by the first connectors in parallel, the overall resistance of the connection assembly formed by the first conductive group, the second conductive group, and the multiple first connectors interconnecting the two is reduced, resulting in a transmission path with high current carrying capacity (for signal transmission with large current amplitude). Therefore, it is not necessary to reduce the resistance by increasing the size of the first via where the first connector is located. That is, the size of the first via can be the same as the size of the nano-through-hole (nTSV). Thus, in the process of integrated circuit fabrication, the first via for signal transmission with large current amplitude and the nano-through-hole (nTSV) for conventional signal transmission can be fabricated simultaneously without the need for additional design of a transmission path with high current carrying capacity, reducing the fabrication steps of the integrated circuit and lowering its fabrication difficulty.

[0012] In one possible implementation of the first aspect, at least one pair of contacts located on the side surface of different conductive layers near the chip and disposed adjacent to each other are stacked upwards on the third side.

[0013] That is, at least two contacts are aligned upwards in the third direction, thereby achieving parallel connection between the different conductive layers while avoiding excessively long current transmission paths in the direction parallel to the substrate, thereby further reducing the resistance of the first conductive group or the second conductive group, reducing the overall resistance of the connection component, and further optimizing the transmission performance of signals with large current amplitudes in the integrated circuit.

[0014] In one possible implementation of the first aspect, the contact portion and the first connector are stacked in the third direction upward, thereby further reducing the current transmission path in the direction parallel to the substrate, thereby further reducing the overall resistance of the connection component, and further optimizing the transmission performance of signals with large current amplitude in the integrated circuit.

[0015] In one possible implementation of the first aspect, the number of multiple contacts located between two adjacent conductive layers is greater than the number of multiple first connectors; wherein at least one contact is offset from the first connector in a third direction, thereby increasing the number of parallel connection positions between the upper and lower conductive layers electrically connected to the contact and reducing the resistance of the second conductive group.

[0016] In one possible implementation of the first aspect, the chip includes a substrate and a transistor. The substrate includes a first surface and a second surface facing each other in a third-direction orientation, and the transistor is disposed on the first surface. A first via penetrates the substrate. The integrated circuit also includes a dielectric layer and a plurality of second connectors. The dielectric layer is disposed on the first surface and surrounds the transistor. The plurality of second connectors are embedded in the dielectric layer, and the second connectors and the first connectors are stacked in a third-direction orientation. A first conductive group is electrically connected to the plurality of first connectors through the plurality of second connectors, thereby achieving electrical connection between the first conductive group and the plurality of first connectors when the conductive layer and some metal layers and traces of the transistor are disposed on the same layer, through the plurality of second connectors, which are spaced apart.

[0017] In one possible implementation of the first aspect, the chip includes a substrate and transistors, and the integrated circuit further includes a dielectric layer and multiple second interconnects. The first and second interconnects, stacked along a third direction, are integrally disposed to facilitate the simultaneous fabrication of the first and second interconnects, thereby improving the fabrication efficiency of the integrated circuit.

[0018] In one possible implementation of the first aspect, the integrated circuit further includes a transition layer disposed on the side of the second conductive group away from the chip and electrically connected to the second conductive group; the thickness of the transition layer is greater than the thickness of the conductive layer, and / or the width of the transition layer is greater than the width of the conductive layer.

[0019] The transition layer is used to connect to pads at the micrometer level. Therefore, the size of the transition layer can be larger than that of the conductive layer. While realizing the external connection of the connecting components, it can reduce the resistance when transitioning to the pads and optimize the overall electrical performance of the integrated circuit.

[0020] In one possible implementation of the first aspect, the chip includes a substrate and transistors, the transistors including input / output transistors, the signal network of the input / output transistors being disposed on the side of the chip away from the second conductive group, and the first conductive group being electrically connected to the signal network of the input / output transistors.

[0021] The signal (input signal and output signal) transmitted by the signal network of the input / output transistor has a large current amplitude. By electrically connecting the aforementioned connection component to the input / output transistor, the signal transmitted by the signal network can be transmitted to the back of the chip in a transmission path with high current capacity (i.e., connection component with low resistance), thus meeting the signal transmission requirements between the input / output transistor and the pads on the back of the chip.

[0022] In one possible implementation of the first aspect, the power supply network for the input / output transistors is located on the side of the chip away from the first conductive group. The chip also has a second via, through which the input / output transistors are electrically connected to the power supply network. The dimensions of the first via and the second via are the same.

[0023] That is, in the integrated circuit provided by this application, the fabrication processes of the first through hole and the second through hole can be the same, for example, they can be fabricated simultaneously without the need to design a separate fabrication step for the first through hole, thus reducing the fabrication difficulty of the integrated circuit.

[0024] In one possible implementation of the first aspect, the signal network of the input / output transistor includes multiple signal layers; in the multiple conductive layers of the first conductive group, one conductive layer is disposed on the same layer as the signal layer furthest from the chip in the multiple signal layers, and the thickness of the conductive layer is greater than the thickness of the conductive layers of other layers in the multiple conductive layers.

[0025] By increasing the thickness of this conductive layer (relative to other conductive layers), the resistance of the first conductive group and even the entire connection assembly can be further reduced, thereby further improving the electrical performance of the integrated circuit.

[0026] In one possible implementation of the first aspect, the chip includes a substrate and transistors, the transistors including storage transistors, and the power supply network of the storage transistors is disposed on the side of the chip away from the second conductive group. The first conductive group is electrically connected to the power supply network of the storage transistors, thereby facilitating the transmission of power signals provided by the power supply pads on the back of the chip to the storage transistors via the second conductive group, the first connector, the first conductive group and the power supply network, thereby enabling power supply to the storage transistors.

[0027] In one possible implementation of the first aspect, the chip includes multiple storage transistors. A first conductive group electrically connected to the storage transistors, and corresponding multiple first connectors and second conductive groups, are disposed on at least one side of the multiple storage transistors along a direction parallel to the chip, thereby avoiding crowding out the design space of the storage transistors T and ensuring that the integrated circuit has a high storage density.

[0028] In one possible implementation of the first aspect, the chip includes a hotspot region, which is the area where the chip experiences high temperatures during operation. A first via is formed in the hotspot region of the chip, and the first and second conductive groups corresponding to the hotspot region are in a floating state.

[0029] This application embodiment, by setting a floating connection component in the hot spot area, can conduct heat in the hot spot area to the first conductive group and the second conductive group (see the arrows in the figure) through multiple first connectors. The thermal conductivity of the first conductive group and the second conductive group (mostly made of metal) is higher than that of the chip (silicon), which has better heat dissipation capability and can dissipate heat, thereby reducing the damage caused by heat accumulation to the chip, optimizing the electrical performance of the integrated circuit, and extending its service life.

[0030] In a second aspect, an electronic device is provided, the electronic device comprising a circuit board and an integrated circuit provided in any embodiment of the first aspect.

[0031] The technical effects of the electronic devices in the second aspect can be seen in the technical effects of the integrated circuit design method in the first aspect, and will not be repeated here. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0033] Figure 2 is a perspective view of an integrated circuit provided in an embodiment of this application;

[0034] Figure 3 is a top view of an integrated circuit provided in an embodiment of this application;

[0035] Figure 4 is a cross-sectional view of an integrated circuit provided in an embodiment of this application;

[0036] Figure 5 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0037] Figure 6 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0038] Figure 7 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0039] Figure 8 is another top view of the integrated circuit provided in an embodiment of this application;

[0040] Figure 9 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0041] Figure 10 is another top view of the integrated circuit provided in an embodiment of this application;

[0042] Figure 11 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0043] Figure 12 is another cross-sectional view of the integrated circuit provided in an embodiment of this application;

[0044] Figure 13 is another perspective view of the integrated circuit provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0046] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0049] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0050] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0051] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0053] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0055] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0056] Figure 1 is a schematic diagram of the structure of an electronic device provided by an embodiment of this application. As shown in Figure 1, the electronic device 1000 includes an integrated circuit 100 and a circuit board 200, and the integrated circuit 100 can be disposed on the circuit board 200.

[0057] For example, circuit board 200 may be a printed circuit board (PCB).

[0058] It is understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1, or may combine some of the components shown in FIG1, or may have a different arrangement of components than those shown in FIG1.

[0059] This application also provides an integrated circuit 100.

[0060] For example, as shown in FIG1, the integrated circuit 100 may include logic circuit 101, analog circuit 102, storage circuit 103, and input / output circuit 104, etc.

[0061] It should be understood that the integrated circuit 100 includes, but is not limited to, logic circuit 101, analog circuit 102, storage circuit 103 and input / output circuit 104. For example, in addition to the four types of circuits mentioned above, the integrated circuit 100 may also include other types or functions of circuits, or power distribution devices.

[0062] In addition, integrated circuit 100 may include one or more of logic circuit 101, analog circuit 102, storage circuit 103 and input / output circuit 104.

[0063] Based on this, the number of logic circuits 101, analog circuits 102, storage circuits 103, and input / output circuits 104 included in integrated circuit 100 can be set as needed. Integrated circuit 100 may include one or more logic circuits 101. Integrated circuit 100 may also include one or more analog circuits 102. Integrated circuit 100 may also include one or more storage circuits 103. Integrated circuit 100 may also include one or more input / output circuits 104.

[0064] For example, integrated circuit 100 may include semiconductor devices and some electronic devices. The electronic devices are electrically connected to the semiconductor devices to perform corresponding functions.

[0065] For example, semiconductor devices and electronic devices can be integrated into logic circuit 101. The semiconductor devices and electronic devices in logic circuit 101 cooperate with each other to realize the "AND", "OR", and "NOT" functions in logic circuit 101. Alternatively, semiconductor devices and electronic devices can also be disposed in other circuits, such as storage circuit 103. This application does not impose specific limitations on this.

[0066] For example, the electronic device can be a resistor, capacitor, controller, or other electronic device.

[0067] For example, the semiconductor device can be a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAAFET), or a vertical transistor (VFET).

[0068] Alternatively, the semiconductor device may also be a memory containing the aforementioned transistors, such as a dynamic random access memory (DRAM), for example, a 1T1C architecture DRAM, or a static random-access memory (SRAM), etc. The embodiments of this application do not limit the device type of the semiconductor device included in the integrated circuit 100.

[0069] Figure 2 is a perspective view of the integrated circuit 100 provided in an embodiment of this application; Figure 3 is a top view of the integrated circuit 100 provided in an embodiment of this application; and Figure 4 is a cross-sectional view of the integrated circuit 100 provided in an embodiment of this application.

[0070] As shown in Figure 2, the integrated circuit 100 may include a chip 1, a plurality of first connectors 21, a first conductive group 31, and a second conductive group 32.

[0071] For example, referring to FIG4, the chip 1 may include a substrate 11 and a transistor T disposed on the substrate 11.

[0072] Referring to Figure 4, the substrate 11 includes a first surface 1a and a second surface 1b that are opposite each other in the third direction Z, where the third direction Z is the thickness direction of the substrate 11.

[0073] Referring to Figure 4, transistor T can be disposed on the first surface 1a of substrate 11.

[0074] For example, a plurality of transistors T may be disposed on the substrate 11, which are used to implement at least one function. For example, the transistors T may be one or more of input / output transistors T1, storage transistors T2 and logic transistors T3, thereby enabling one or more of the following functions: storage function, input / output signal control function, and logic "yes" and "no" functions. It is understood that this embodiment is merely exemplary and does not limit the type of transistors T and their corresponding functions.

[0075] For example, referring to FIG3, an input / output transistor T1, a storage transistor T2, and a logic transistor T3 can be disposed on the substrate 11. These transistors T are interconnected with corresponding electrical network wiring (see FIG4) to form a module capable of realizing a specific function. For example, referring to FIG3, a logic circuit 101, a storage circuit 103, and an input / output circuit 104 can be formed accordingly.

[0076] Referring to Figures 2 and 4, the chip 1 has a plurality of first through holes H1 spaced apart, and the first through holes H1 penetrate the chip 1.

[0077] For example, referring to Figures 2 and 4, the plurality of first through holes H1 can be spaced apart along the first direction X.

[0078] Alternatively, as an example, the plurality of first through holes H1 may also be spaced apart along the second direction Y. This application embodiment does not limit the arrangement direction of the plurality of first through holes H1.

[0079] The first direction X and the second direction Y are both parallel to the substrate 11 and intersect each other. For example, the first direction X and the second direction Y are perpendicular to each other. For example, the first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0080] For example, referring to FIG4, the first through-hole H1 penetrates the substrate 11 of the chip 1.

[0081] Both sides of chip 1 (e.g., the side where the first surface 1a is located and the side where the second surface 1b is located) are provided with various electrical networks. Through holes (e.g., the first through hole H1) through chip 1 can facilitate the interconnection between electrical networks on both sides of chip 1.

[0082] For example, the first through hole H1 can be integrally formed with other through holes (such as the second through hole H2 in FIG4) that penetrate the chip 1.

[0083] For example, the first through-hole H1 can be a nano-through-hole (nTSV).

[0084] For example, the shape of the first through hole H1 can be cylindrical, elliptical cylindrical, frustum-shaped, rectangular (as shown in Figure 2), etc., and the embodiments of this application do not limit this.

[0085] Referring to Figures 2 and 4, the first connector 21 is disposed in the first through hole H1.

[0086] For example, referring to Figures 2 and 4, a plurality of first connectors 21 are disposed in a plurality of first through holes H1 in a one-to-one correspondence, that is, a first connector 21 is disposed in each first through hole H1.

[0087] For example, the material of the first connector 21 is a conductive material, such as a metal, alloy or other conductive material.

[0088] Referring to Figure 4, one end of the first connector 21 facing the first surface 1a of the substrate 11 is used to electrically connect with the conductive structure located on the side of the first surface 1a, and the other end of the first connector 21 facing the second surface 1b of the substrate 11 is used to electrically connect with the conductive structure located on the side of the second surface 1b, thereby realizing the electrical connection between the conductive structures on both sides of the chip 1.

[0089] Referring to Figures 2 and 4, the first conductive group 31 and the second conductive group 32 are respectively located on both sides of the chip 1.

[0090] For example, referring to Figures 2 and 4, the first conductive group 31 can be disposed on the side where the first surface 1a of the substrate 11 is located, and the second conductive group 32 can be disposed on the side where the second surface 1b of the substrate 11 is located.

[0091] Referring to Figures 2 and 4, the first conductive group 31 is electrically connected to one end of a plurality of first connectors 21, and the second conductive group 32 is electrically connected to the other end of a plurality of first connectors 21. That is, the first conductive group 31 and the second conductive group 32 are electrically connected through the plurality of first connectors 21, and each first connector 21 is electrically connected to the first conductive group 31 and the second conductive group 32 respectively. This not only realizes the electrical connection between the first conductive group 31 and the second conductive group 32, but also realizes the parallel connection between the two, thereby reducing the overall resistance of the connection component W (refer to Figure 4) formed after the first conductive group 31 and the second conductive group 32 are connected.

[0092] The first conductive group 31 and / or the second conductive group 32 include multiple conductive layers M. For example, referring to FIG2, multiple conductive layers M can be provided in the first conductive group 31, and only one conductive layer M can be provided in the second conductive group 32. Or, for example, only one conductive layer M can be provided in the first conductive group 31, and multiple conductive layers M can be provided in the second conductive group 32. Or, for example, referring to FIG4, both the first conductive group 31 and the second conductive group 32 are provided with multiple conductive layers M.

[0093] Referring to Figures 2 and 4, multiple conductive layers M are stacked and spaced apart along the third direction Z. Multiple contact portions M' are provided between two adjacent conductive layers M. The multiple contact portions M' are spaced apart along a direction parallel to the chip 1. Two adjacent conductive layers M are electrically connected through the multiple contact portions M'.

[0094] Referring to Figure 4, adjacent conductive layers M are electrically connected through multiple contact portions M', that is, there are multiple connection positions spaced apart between adjacent conductive layers M, thereby realizing the parallel connection between the adjacent conductive layers M, reducing the resistance of the first conductive group 31 or the second conductive group 32 itself, and further reducing the overall resistance of the connection component W formed after the first conductive group 31 and the second conductive group 32 are connected.

[0095] For example, referring to Figure 4, the conductive layer M can be disposed on the same layer as conventional metal layers (such as metal layers and traces in the power supply network) in the integrated circuit 100 and integrally formed, without the need to add an additional film layer and preparation steps for the conductive layer M, thus avoiding increasing the preparation difficulty of the integrated circuit 100.

[0096] The aforementioned first conductive group 31, second conductive group 32, and multiple first connectors 21 interconnected between them together form a connection component W (see Figures 3 and 4). This connection component W is used to realize the transmission between electrical signals on the side where the first surface 1a of the chip 1 is located and electrical signals on the side where the second surface 1b is located.

[0097] For example, referring to Figures 3 and 4, the integrated circuit 100 may include at least one of the connection components W. The connection component W can be set at any location on the chip 1 where interconnection between the two sides is required. For example, referring to Figure 3, the connection component W can be set in the logic circuit 101.

[0098] In some other embodiments, with the development of electronic device technology, conventional signals on both sides of the chip are usually transmitted through nanovias (nTSVs), while signals with larger current amplitudes are transmitted through ordinary vias (TSVs). The size (e.g., diameter) of an ordinary via is larger than that of a nanovia (nTSV), and therefore has lower resistance, allowing signals with larger current amplitudes to pass through.

[0099] However, in this embodiment, due to the size difference, different fabrication steps need to be designed for the through-hole TSV and the nano-through-hole nTSV, or additional steps need to be added to achieve the size difference between the two types of through holes. It may even be necessary to design different pad areas or other structures for the through-hole TSV and the nano-through-hole nTSV, which increases the fabrication difficulty of integrated circuits and reduces the production efficiency of integrated circuits.

[0100] In the integrated circuit 100 provided in this application embodiment, by connecting multiple first connectors 21 in parallel and connecting multiple conductive layers in the first conductive group 31 and / or the second conductive group 32 connected to the first connectors 21 in parallel, the overall resistance of the connection component W formed by the first conductive group 31, the second conductive group 32 and the multiple first connectors 21 interconnected between them is reduced, thereby obtaining a transmission path with high current carrying capacity (for signal transmission with large current amplitude). Therefore, it is not necessary to reduce the resistance by increasing the size of the first via H1 where the first connector 21 is located. That is, the size of the first via H1 can be the same as the size of the nano-via nTSV. Thus, in the fabrication process of the integrated circuit 100, the first via H1 used for signal transmission with large current amplitude and the nano-via nTSV used for conventional signal transmission can be fabricated simultaneously without the need to design an additional transmission path with high current carrying capacity, reducing the fabrication steps of the integrated circuit 100 and reducing its fabrication difficulty.

[0101] Meanwhile, in the transmission path (i.e., connection component W) with high current carrying capacity provided in the embodiments of this application, the multilayer conductive layer M can also be set on the same layer as conventional signal traces, metal layers, etc., and can also be prepared synchronously. That is, the transmission path does not add any additional structures that need to be designed independently, and will not add any additional preparation steps.

[0102] Furthermore, since the size of the first via H1 is the same as the size of the nano-via nTSV, other structures corresponding to both, such as pads, do not need to be designed independently and can also be fabricated simultaneously, further reducing the fabrication difficulty of the integrated circuit 100.

[0103] Furthermore, in embodiments where the size of the via TSV is further increased to transmit signals with larger current amplitudes, the area occupied by the via TSV in the direction parallel to chip 1 gradually increases, which is not conducive to the miniaturization design of integrated circuit 100. However, in the transmission path (i.e., connection component W) provided in this application embodiment, the resistance can be further reduced simply by increasing the number of parallel conductive layers M in the third direction Z. That is, the transmission path provided in this application embodiment can achieve flexible control of resistance without increasing the horizontal (parallel to chip 1) design space occupied by the transmission path, which is conducive to the miniaturization design of integrated circuit 100. Moreover, the connection component W can be flexibly applied in signal transmission processes with different resistance value requirements.

[0104] In the aforementioned connection component W provided in the embodiments of this application, the resistance of the connection component W as a whole can be adjusted by different parallel connection methods among the various structures. The following embodiments illustrate some parallel connection methods.

[0105] In some embodiments, referring to FIG4, at least a pair of contacts M' located on the side surface of different conductive layers M near the chip 1 and disposed adjacent to each other are stacked in the third direction Z.

[0106] That is, at least two contact portions M' are aligned in the third direction Z, thereby achieving parallel connection between the different conductive layers M, while avoiding excessively long current transmission paths in the direction parallel to the substrate 11, thereby further reducing the resistance of the first conductive group 31 or the second conductive group 32, reducing the overall resistance of the connection component W, and further optimizing the transmission performance of signals with large current amplitudes in the integrated circuit 100.

[0107] For example, referring to FIG4, multiple contact portions M' are stacked and aligned in a string on the third direction Z ("string" refers to multiple portions stacked on the third direction Z).

[0108] For example, referring to FIG4, multiple strings of contact portions M' stacked in the third direction Z can be provided along the first direction X, and the same applies to the second direction Y.

[0109] For example, referring to FIG4, the number of multiple contacts M' provided on the side surface of each conductive layer M near the chip 1 is the same, and in the third direction Z, the contacts M' of adjacent layers are aligned one-to-one.

[0110] In some embodiments, referring to FIG4, the contact portion M' may also be stacked with the first connector 21 on the third direction Z.

[0111] For example, in the multilayer conductive layers M, the contact portion M' between the conductive layer M closest to the chip 1 and the first connector 21 is aligned with the first connector 21. Alternatively, as shown in Figure 4, each contact portion M' is stacked on top of the first connector 21 to be aligned with the first connector 21, thereby further reducing the current transmission path in the direction parallel to the substrate 11, thereby further reducing the overall resistance of the connection component W, and further optimizing the transmission performance of signals with large current amplitudes in the integrated circuit 100.

[0112] The aforementioned "alignment along the third direction Z" can be understood as different components being roughly on the same reference line extending along the third direction Z.

[0113] For example, referring to FIG4, each first connector 21 can be provided with a series of contact portions M' (i.e., multiple contact portions M' stacked upwards on the third side), and multiple first connectors 21 are provided with multiple series of contact portions M'.

[0114] In some embodiments, referring to FIG4, the number of multiple contacts M' located between two adjacent conductive layers M can be the same as the number of multiple first connectors 21.

[0115] Alternatively, in some embodiments, referring to Figures 9 and 11 below, the number of multiple contacts M' located between two adjacent conductive layers M may be different from the number of multiple first connectors 21, so as to adjust the number of parallel positions of conductive layers M in the first conductive group 31 or the second conductive group 32, thereby realizing the adjustment of the resistance of the connecting component W.

[0116] For example, referring to FIG9, the number of multiple contacts M' located between two adjacent conductive layers M can be greater than the number of multiple first connectors 21, wherein at least one contact M' is offset from the first connector 21 in the third direction Z.

[0117] For example, in the second conductive group 32 of Figure 9, the number of contact portions M' closest to the chip 1 can be greater than the number of multiple first connectors 21, thereby increasing the number of parallel connection positions between the upper and lower conductive layers M that are electrically connected to the contact portion M', and reducing the resistance of the second conductive group 32.

[0118] Alternatively, referring to the second conductive group 32 in FIG11, the number of multiple contact portions M' located between two adjacent conductive layers M can be less than the number of multiple first connectors 21, thereby appropriately reducing the distribution density of contact portions M' and reducing the difficulty of drilling while satisfying the overall resistance of the connection assembly W.

[0119] It is understandable that, referring to Figures 9 and 11, the number of contact portions M' on the surface of the conductive layer M near the chip 1 can also be different, which can also achieve the adjustment of the overall resistance of the connection component W.

[0120] In addition to the various parallel connection methods between different conductive layers M and between conductive layer M and first connector 21 provided in the foregoing embodiments affecting the overall performance of the connection component W, the connection method between the first conductive group 31 and the second conductive group 32 can also affect the signal transmission performance, as detailed in the following various embodiments.

[0121] Figure 5 is another cross-sectional view of the integrated circuit 100 provided in the embodiment of this application, Figure 6 is another cross-sectional view of the integrated circuit 100 provided in the embodiment of this application, and Figure 7 is another cross-sectional view of the integrated circuit 100 provided in the embodiment of this application.

[0122] In some embodiments, referring to Figures 4 to 7, the integrated circuit 100 further includes a dielectric layer 4 disposed on the first surface 1a and surrounding the transistor T, so as to protect the transistor T and prevent unexpected electrical connections between the transistor T and other conductive structures.

[0123] It is understood that, referring to Figures 4 to 7, the metal layer and traces corresponding to transistor T (e.g., the signal network A1 of input / output transistor T in Figure 4) can be embedded in the dielectric layer 4 so that the metal layer or traces can be electrically insulated from other conductive structures and electrically connected only to the preset location of transistor T (e.g., gate, word line, bit line, etc.).

[0124] Referring to Figures 4 to 7, when the conductive layer M and the aforementioned metal layer and wiring of the transistor T are disposed on the same layer to facilitate synchronous fabrication, the conductive layer M is also embedded in the dielectric layer 4, and the conductive layer M closest to the first connector 21 is spaced apart from the substrate 11, that is, the conductive layer M and the first connector 21 are spaced apart by a certain distance.

[0125] Referring to Figure 5, the integrated circuit 100 may include a plurality of second connectors 22, which are embedded in the dielectric layer 4. The second connectors 22 and the first connectors 21 are stacked in the third direction Z. The first conductive group 31, which is set at a certain distance, is electrically connected to the plurality of first connectors 21 through the plurality of second connectors 22.

[0126] Among them, multiple first connectors 21 and multiple second connectors 22 are electrically connected in a one-to-one correspondence.

[0127] For example, referring to FIG5, the second connector 22 can be disposed on the side where the first surface 1a of the chip 1 is located, or the second connector 22 can also be disposed on the side where the second surface 1b of the chip 1 is located. That is, the first connector 21 and the first conductive group 31 can be electrically connected through the second connector 22, and the first connector 21 and the second conductive group 32 can also be electrically connected through the second connector 22.

[0128] For example, the first connector 21 and the second connector 22 can be configured in steps. For instance, the first connector 21 can be formed through the substrate 11 first, and then the second connector 22 can be formed on the first connector 21 through a portion of the dielectric layer 4. This allows the fabrication of the first connector 21 and the second connector 22 to be achieved by forming two vias with a small depth-to-width ratio, thus realizing the electrical connection between the first conductive group 31 and the second conductive group 32 that are far apart. This avoids the problem of increasing the fabrication difficulty of the integrated circuit 100 by forming vias with a large depth-to-width ratio that simultaneously penetrate the dielectric layer 4 and the substrate 11 in one step.

[0129] Alternatively, by way of example, the first connector 21 and the second connector 22 stacked on the third direction Z can be integrally disposed. For example, the substrate 11 can be thinned first (see Figures 6 and 7) to reduce the distance between the first conductive group 31 and the second conductive group 32, thereby reducing the aspect ratio of the via that simultaneously penetrates the substrate 11 and the dielectric layer 4, so as to realize the synchronous fabrication of the first connector 21 and the second connector 22 and improve the fabrication efficiency of the integrated circuit 100.

[0130] For example, the second connector 22 can be integrally formed with the conductive layer M. For instance, the conductive layer M closest to the substrate 11 can be fabricated simultaneously with the second connector 22. This can also reduce the steps of fabricating the second connector 22 separately while avoiding the fabrication of vias with large depth-to-width ratios, thereby improving the fabrication efficiency of the integrated circuit 100.

[0131] For example, referring to FIG4, the second connector 22 can be the same structure as the power contact structure (PCT, a power rail for supplying power to chip 1). For example, the second connector 22 can be fabricated simultaneously with the power contact structure.

[0132] For example, referring to FIG5, the second connector 22 can be the same structure as the buried power rail (BPR, which is also a power rail used to power chip 1). For example, referring to FIG5, the second connector 22 can include a portion embedded in the substrate 11 and a portion embedded in the dielectric layer 4, i.e., a BPR+VBPR (vertical BPR) structure.

[0133] For example, referring to FIG6, when the thickness of the substrate 11 is reduced, the second connector 22 can be fabricated simultaneously with the contact structure of the transistor T (not shown in the figure, the contact structure that realizes the external connection of the gate or source and drain, referred to as CT).

[0134] For example, referring to FIG6, the first via H1 can be a via similar to the back power supply via. For example, referring to FIG6, the first connector 21 can penetrate the substrate 11 and protrude from the second surface 1b so as to be electrically connected to the second conductive group 32 (e.g., disposed in the same layer as the back power supply network).

[0135] For example, referring to FIG7, when the substrate 11 is thinned to a very thin thickness that allows current to pass through smoothly, the first through hole H1 and the first connector 21 can be replaced by a conductive channel. For example, referring to FIG7, the substrate 11 is thin, and contact structures (CTs) are provided on both the first surface 1a and the second surface 1b of the substrate 11. The upper and lower contact structures can be electrically connected through the thin substrate 11. In this case, the part of the substrate 11 sandwiched between the two contact structures (i.e., the second connector 22) can play the same role as the first connector 21.

[0136] Figure 8 is another top view of the integrated circuit 100 provided in the embodiment of this application; Figure 9 is a cross-sectional view of the integrated circuit 100 in Figure 8; Figure 10 is another top view of the integrated circuit 100 provided in the embodiment of this application; Figure 11 is a cross-sectional view of the integrated circuit 100 in Figure 10; Figure 12 is another cross-sectional view of the integrated circuit 100 provided in the embodiment of this application; and Figure 13 is another perspective view of the integrated circuit 100 provided in the embodiment of this application.

[0137] In some embodiments, referring to Figures 9, 11 and 12, the integrated circuit 100 may further include a transition layer 5.

[0138] Referring to Figures 9, 11 and 12, the transition layer 5 is disposed on the side of the second conductive group 32 away from the chip 1 (i.e., disposed on the back side of the chip 1).

[0139] For example, referring to Figures 9, 11 and 12, the transition layer 5 may be provided with power pads P and signal pads P. The power network and / or signal network of the transistor T in the chip 1 can be connected to these pads P. In some embodiments, the interconnection between the chip 1 and the package structure can be achieved through the pads P on the transition layer 5.

[0140] For example, referring to Figures 9, 11 and 12, the transition layer 5 can be electrically connected to the second conductive group 32 so that the electrical signals on the front side of the chip 1 can be transmitted to the back side of the chip 1 via the first conductive group 31, the second conductive group 32 and the transition layer 5, and finally interconnected with the package structure through the pads P on the transition layer 5.

[0141] The transition layer 5 can transmit signals from the smaller second conductive group 32 (the spacing between adjacent first vias H1 is on the nanometer scale) to the corresponding pads P (the spacing between adjacent pads P is on the micrometer scale).

[0142] For example, the thickness of the transition layer 5 is greater than the thickness of the conductive layer M (see Figures 9, 11 and 12), and / or the width of the transition layer 5 is greater than the width of the conductive layer M. The transition layer 5 is used to connect to the micron-sized pad P. Therefore, the size of the transition layer 5 can be greater than the size of the conductive layer M. While realizing the external connection of the connection component W, the resistance when connecting to the pad P can be reduced, and the overall electrical performance of the integrated circuit 100 can be optimized.

[0143] By setting the transition layer 5, the interconnection between the connection component W and the pad P is realized. Therefore, there is no need to design a special pad to match the connection component W, which further reduces the fabrication difficulty of the integrated circuit 100.

[0144] For example, the material of the transition layer 5 may include aluminum, that is, the transition layer 5 may be an aluminum pad (ALPA).

[0145] In some embodiments, referring to Figures 8 and 9, transistor T includes input / output transistor T1, and the aforementioned connection component W can be electrically connected to input / output transistor T1 to enable external connection of input / output transistor T1.

[0146] For example, referring to Figures 4 and 9, the signal network A1 of the input / output transistor T1 is disposed on the side of the chip 1 away from the second conductive group 32, that is, on the front side of the chip 1 (the side where the first surface 1a is located). The first conductive group 31 is electrically connected to the signal network A1 of the input / output transistor T1, thereby transmitting the signal of the input / output transistor T1 from the first surface 1a of the chip 1 to the second surface 1b (i.e., the back side) of the chip 1 through the connection component W.

[0147] The signal (input signal and output signal) transmitted by the signal network A1 of the input / output transistor T1 has a large current amplitude. By electrically connecting the aforementioned connection component W to the input / output transistor, the signal transmitted by the signal network A1 can be transmitted to the back of the chip 1 in a transmission path with high current carrying capacity (i.e., a connection component with low resistance), thus meeting the signal transmission requirements between the input / output transistor T1 and the pad P on the back of the chip 1 (see the arrow in Figure 9 for the transmission path).

[0148] In some embodiments, referring to Figures 4 and 9, the input / output transistor T further includes a power supply network B1, which is disposed on the side of the chip 1 away from the first conductive group 31, that is, on the back side of the chip 1 (the side where the second surface 1b is located).

[0149] Referring to Figures 4 and 9, chip 1 also has a second through-hole H2. Input / output transistor T1 passes through the second through-hole H2 and is electrically connected to power supply network B1. The power signal current amplitude transmitted by power supply network B1 of input / output transistor T1 is relatively small (for example, smaller than that of signal network A1), so there is no need to use a transmission path with a large current carrying capacity for transmission. As shown in Figure 4, it can be directly electrically connected to the power supply network B1 on the back through the second through-hole H2 through chip 1.

[0150] Wherein, the size of the first through hole H1 is the same as the size of the second through hole H2. That is, in the integrated circuit 100 provided in this application, the fabrication process of the first through hole H1 and the second through hole H2 can be the same. For example, they can be fabricated simultaneously without designing a separate fabrication step for the first through hole H1, thus reducing the fabrication difficulty of the integrated circuit 100.

[0151] In some embodiments, referring to Figures 4 and 9, the signal network A1 of the input / output transistor T1 includes multiple signal layers A1', which are electrically connected to each other to form the signal network A1 of the input / output transistor T1.

[0152] Referring to Figures 4 and 9, in the multilayer conductive layers M of the first conductive group 31, one conductive layer M is co-located with the signal layer A1' that is furthest from the chip 1 in the multilayer signal layers A1'. For example, taking the orientation in Figure 9 as an example, the uppermost conductive layer M in the multilayer conductive layers M is co-located with the uppermost signal layer A1' in the multilayer signal layers A1'. Or, for example, the multilayer conductive layers M and the multilayer signal layers A1' are co-located in a one-to-one correspondence, that is, each conductive layer M is co-located with one signal layer A1', which facilitates the synchronous fabrication of the conductive layer M and the signal layer A1', and further reduces the fabrication difficulty of the integrated circuit 100.

[0153] Referring to Figures 4 and 9, the thickness of the conductive layer M is greater than the thickness of the conductive layers M in the multilayer conductive layers M. The size (e.g., thickness) of the signal layer A1' farthest from chip 1 in the multilayer signal layers A1' can be flexibly adjusted (because it is located on the top layer, even if the thickness is increased, it will not affect the fabrication of other signal layers A1'). By setting a conductive layer M in the same layer as the signal layer A1' with adjustable thickness, the thickness of the conductive layer M can also be flexibly adjusted. By increasing the thickness of the conductive layer M (relative to the conductive layers M in the other layers), the resistance of the first conductive group 31 and even the entire connection component W can be further reduced, thereby further improving the electrical performance of the integrated circuit 100.

[0154] In some embodiments, referring to Figures 10 and 11, transistor T may further include storage transistor T2 (e.g., forming SRAM), and the aforementioned connection component W may be electrically connected to storage transistor T2 to enable the transmission of signals from storage transistor T2 to the back side of chip 1.

[0155] For example, referring to Figures 4 and 11, the power supply network B2 of the storage transistor T2 is disposed on the side of the chip 1 away from the second conductive group 32, that is, on the side where the first surface 1a of the substrate 11 is located, that is, the power supply network B2 of the storage transistor T2 is disposed on the front side of the chip 1.

[0156] With the development of semiconductor technology, the distribution density of storage transistors T2 in memory has gradually increased. There is no longer enough design space between adjacent storage transistors T2 to design a structure for connecting the power supply network B2 (such as a structure similar to the aforementioned second via H2). In this embodiment, the power supply network B2 of the storage transistor T2 is set on the front side of the chip 1 so that the power supply network B2 can be set in the peripheral circuit of the storage transistor T2, thus avoiding the power supply network B2 from occupying the design space of the storage transistor T2.

[0157] Referring to Figures 4 and 11, the first conductive group 31 is electrically connected to the power supply network B2 of the storage transistor T2, so that the power signal can be transmitted from the back of the chip 1 to the power supply network B2 provided on the front of the chip 1 through the connection component W, thereby completing the power supply to the storage transistor T2 (see the arrow in Figure 11 for the power supply path).

[0158] In some embodiments, referring to Figures 10 and 11, chip 1 includes a plurality of storage transistors T2, a first conductive group 31 electrically connected to the storage transistors T2, and a plurality of corresponding first connectors 21 and second conductive groups 32 (i.e., the entire connection assembly W), disposed on at least one side of the plurality of storage transistors T2 along a direction parallel to chip 1.

[0159] For example, referring to Figure 10(a), the components can be arranged on the left and right sides of the multiple storage transistors T2, or, for example, referring to Figure 10(b), they can be arranged around the multiple storage transistors T2 (which can reduce voltage drop), thereby avoiding the connection components W from crowding the design space of the storage transistors T2 and ensuring that the integrated circuit 100 has a high storage density.

[0160] In some embodiments, referring to Figures 3 and 4, chip 1 includes a hot spot region Q, which is a region of chip 1 with a high temperature during operation.

[0161] Referring to Figures 3, 4 and 12, the first via H1 can be opened in the hot spot area Q of chip 1, and the first conductive group 31 and the second conductive group 32 corresponding to the hot spot area Q are in a floating state (i.e., do not participate in current transmission).

[0162] With the development of semiconductor technology, chip 1 (e.g., chip substrate 11) can be thinned. For example, the thickness of conventional chip 1 substrate 11 can be about 750 μm, while the thickness of the thinned substrate 11 can be about 500 nm. As the substrate 11 is thinned, the heat dissipation capability of chip 1 in the lateral direction (parallel to the substrate 11, i.e. the plane containing the first direction X and the second direction Y) is greatly reduced, which can easily cause local hot spots (i.e., hot spot regions Q). The presence of local hot spots will affect the electrical performance and lifespan of integrated circuit 100.

[0163] In this embodiment, by setting a floating connection component W in the hot spot area Q, heat in the hot spot area Q can be conducted to the first conductive group 31 and the second conductive group 32 (refer to the arrows in Figures 12 and 13) through multiple first connectors 21. The thermal conductivity of the first conductive group 31 and the second conductive group 32 (mostly made of metal) is higher than that of the chip 1 (silicon material), which has better heat dissipation capability and can dissipate heat, thereby reducing the damage caused by heat accumulation to the chip 1, optimizing the electrical performance of the integrated circuit 100, and extending its service life.

[0164] In some embodiments, the distribution density of the first via H1 is greater than the distribution density of the second via H2. The second via H2 refers to a via that penetrates the chip 1 other than the first via H1, such as a second via H2 located in the region where the input / output transistor T1 is located, or a via located in the region where the logic transistor is located.

[0165] The aforementioned connection component W can be located in a passive region. For example, referring to Figure 4, the connection component W can be located on one side of the input / output transistor T1, or for example, it can be located on the periphery of the storage transistor T2. Therefore, the connection component W is not limited by the location of the core device (e.g., transistor T). Thus, the distribution density of the first via H1 in the connection component W can be further increased, thereby further reducing the resistance or thermal resistance and optimizing the electrical performance of the integrated circuit 100.

[0166] For example, the distribution density of the contact portion M' in the connection component W can also be greater than the distribution density of the via (used to realize the interconnection between two adjacent metal layers) between the metal layers in the region where the core device (e.g., transistor T) is located, thereby further reducing the resistance or thermal resistance and optimizing the electrical performance of the integrated circuit 100.

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated circuit, characterized in that, include: The chip has a plurality of first through holes spaced apart, and the first through holes penetrate the chip; Multiple first connectors, each first connector being disposed in the first through hole; The first conductive group and the second conductive group are respectively disposed on both sides of the chip, and the first conductive group is electrically connected to one end of the plurality of first connectors, and the second conductive group is electrically connected to the other end of the plurality of first connectors. The first conductive group and / or the second conductive group include multiple conductive layers, which are stacked and spaced apart along a third direction, which is perpendicular to the chip; multiple contact portions are provided between adjacent conductive layers, which are spaced apart along a direction parallel to the chip, and adjacent conductive layers are electrically connected through the multiple contact portions.

2. The integrated circuit according to claim 1, characterized in that, At least one pair of contacts located on the side surface of different conductive layers near the chip and arranged adjacent to each other are stacked upwards on the third layer.

3. The integrated circuit according to claim 1 or 2, characterized in that, The contact portion and the first connector are stacked upwards on the third side.

4. The integrated circuit according to claim 1 or 2, characterized in that, The number of the plurality of contacts located between two adjacent conductive layers is greater than the number of the plurality of first connectors; wherein at least one contact is offset from the first connector in the third direction.

5. The integrated circuit according to any one of claims 1 to 4, characterized in that, The chip includes a substrate and transistors, the substrate including a first surface and a second surface facing upwards on the third surface, and the transistors are disposed on the first surface; The first through-hole penetrates the substrate; The integrated circuit also includes: A dielectric layer is disposed on the first surface and surrounds the transistor; Multiple second connectors are embedded in the dielectric layer, and the second connectors and the first connectors are stacked on the third side. The first conductive group is electrically connected to the multiple first connectors through the multiple second connectors.

6. The integrated circuit according to any one of claims 1 to 4, characterized in that, The chip includes a substrate and transistors, and the integrated circuit further includes a dielectric layer and a plurality of second interconnects; The first connector and the second connector are integrally formed and stacked along the third direction.

7. The integrated circuit according to any one of claims 1 to 6, characterized in that, Also includes: An adapter layer is disposed on the side of the second conductive group away from the chip and is electrically connected to the second conductive group; The thickness of the transition layer is greater than the thickness of the conductive layer, and / or the width of the transition layer is greater than the width of the conductive layer.

8. The integrated circuit according to any one of claims 1 to 7, characterized in that, The chip includes a substrate and transistors, the transistors including input / output transistors, and the signal network of the input / output transistors is disposed on the side of the chip away from the second conductive group, the first conductive group being electrically connected to the signal network of the input / output transistors.

9. The integrated circuit according to claim 8, characterized in that, The input / output transistor power supply network is located on the side of the chip away from the first conductive group; The chip also has a second through-hole, through which the input / output transistor passes and is electrically connected to the power supply network; The size of the first through hole is the same as the size of the second through hole.

10. The integrated circuit according to claim 8 or 9, characterized in that, The signal network of the input / output transistor includes multiple signal layers; in the multiple conductive layers of the first conductive group, one conductive layer is disposed on the same layer as the signal layer furthest from the chip in the multiple signal layers, and the thickness of the conductive layer is greater than the thickness of the conductive layers of the other layers in the multiple conductive layers.

11. The integrated circuit according to any one of claims 1 to 10, characterized in that, The chip includes a substrate and transistors, the transistors including storage transistors, and a power supply network for the storage transistors is disposed on the side of the chip away from the second conductive group, the first conductive group being electrically connected to the power supply network for the storage transistors.

12. The integrated circuit according to claim 11, characterized in that, The chip includes multiple storage transistors; A first conductive group electrically connected to the storage transistor, and a plurality of corresponding first connectors and second conductive groups, are disposed on at least one side of the plurality of storage transistors along a direction parallel to the chip.

13. The integrated circuit according to any one of claims 1 to 12, characterized in that, The chip includes a hot spot area, which is the area where the chip has a high temperature when it is working; The first via is formed in the hot spot area of ​​the chip, and the first conductive group and the second conductive group corresponding to the hot spot area are in a floating state.

14. An electronic device, characterized in that, include: Integrated circuit as described in any one of claims 1 to 13; A circuit board, on which the integrated circuit is disposed.

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