Global shutter pixel and image sensor

Abstract

A global shutter pixel and an image sensor, relating to the technical field of image sensors. The global shutter pixel comprises a photosensitive unit, a transmission unit, a reset unit, a storage unit, and a differential unit; the photosensitive unit is used for generating electric charges in response to light; the transmission unit is used, when turned on, for transmitting the electric charges to a floating diffusion node; the reset unit is used, when turned on, for resetting the global shutter pixel; the storage unit is used for storing a voltage at the floating diffusion node, the voltage at the floating diffusion node comprising a reset voltage and a signal voltage; and the differential unit is used for outputting a difference between the reset voltage and the signal voltage. The global shutter pixel can reduce the power consumption of the image sensor, and increase the frame rate of the image sensor.

Description

A global shutter pixel and image sensor

[0001] This application claims priority to Chinese Patent Application No. 202411580889.5, filed on November 7, 2024, entitled "A Global Shutter Pixel and Image Sensor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of image sensor technology, and in particular to a global shutter pixel and image sensor. Background Technology

[0003] High-speed, high-frame-rate imaging is typically achieved using global shutter cameras. These cameras simultaneously expose and terminate the entire pixel array, storing the reset and signal voltages. These voltages are then transmitted row-by-row or column-by-column to external circuitry. The external circuitry uses an analog-to-digital converter (ADC) to convert the analog signals into digital signals for output, and finally, the actual signal value is calculated. Currently, most image sensors employ SSADC (single-slope analog-to-digital converter) quantization. However, the mainstream approach currently uses column ADC quantization, where each column of pixels shares a single ADC. To further improve the frame rate, multiple ADCs are used for simultaneous multi-row quantization, but this approach offers limited frame rate improvement and is accompanied by an exponential increase in power consumption, chip area, and cost. Therefore, reducing the power consumption and improving the frame rate of image sensors has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a global shutter pixel and image sensor that can reduce the power consumption of the image sensor and increase the frame rate of the image sensor.

[0005] To address the aforementioned technical problems, this application provides a global shutter pixel, comprising:

[0006] Photosensitive unit, transmission unit, reset unit, storage unit, differential unit;

[0007] The photosensitive unit is used to generate charge by sensing light;

[0008] The transmission unit is used to transmit the charge to the floating diffusion node when the transmission unit is turned on.

[0009] The reset unit is used to reset the global shutter pixels when the reset unit is turned on.

[0010] The storage unit is used to store the voltage at the floating diffusion node, wherein the voltage at the floating diffusion node includes a reset voltage and a signal voltage;

[0011] The differential unit is used to output the difference between the reset voltage and the signal voltage.

[0012] In some embodiments, the storage unit includes:

[0013] A first storage unit and a second storage unit; the first storage unit is used to store one of a reset voltage and a signal voltage, and the second storage unit is used to store the other of a reset voltage and a signal voltage.

[0014] In some embodiments, the first storage unit is connected to the input terminal of the second storage unit and serves as the input terminal of the storage unit, the output terminal of the first storage unit is connected to one input terminal of the differential unit, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit.

[0015] In some embodiments, the input terminal of the first storage unit serves as the input terminal of the storage unit, the output terminal of the first storage unit is connected to the input terminal of the second storage unit and one input terminal of the differential unit, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit.

[0016] In some embodiments, the differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on, connecting the power supply of the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the input terminal of the first storage unit.

[0017] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, and fourth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third and fourth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth control signal is a first-level signal; during the signal voltage storage phase, the first, third, and fourth control signals are second-level signals, and the second control signal is a first-level signal; during the output phase, the first control signal is a first-level signal, and the second, third, and fourth control signals are second-level signals.

[0018] In some embodiments, it also includes:

[0019] An amplification unit is used to amplify the voltage at the floating diffusion node and output it to the input terminal of the storage unit.

[0020] In some embodiments, the differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on, connecting the power supply of the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the floating diffusion node. The second storage unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the second capacitor of the second storage unit is connected to the input terminal of the second storage unit. The amplification unit is controlled by a sixth control signal. When the sixth control signal is a first level signal, the amplification unit amplifies the voltage at the floating diffusion node and outputs it to the input terminal of the storage unit.

[0021] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, fourth, fifth, and sixth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third, fourth, fifth, and sixth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth, fifth, and sixth control signals are first-level signals; during the signal voltage storage phase, the first, third, and fourth control signals are second-level signals, and the second, fifth, and sixth control signals are first-level signals; during the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

[0022] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, fourth, fifth, and sixth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third, fourth, fifth, and sixth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth, fifth, and sixth control signals are first-level signals; during the signal voltage storage phase, the first, third, and fifth control signals are second-level signals, and the second, fourth, and sixth control signals are first-level signals; during the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

[0023] In some embodiments, the differential unit includes:

[0024] The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor;

[0025] The first terminal of the first transistor serves as one input terminal of the differential unit. The second terminal of the first transistor is connected to the third terminal of the second transistor and the third terminal of the third transistor. The third terminal of the first transistor is connected to the third terminal of the fourth transistor. The first terminal of the second transistor serves as another input terminal of the differential unit. The second terminal of the second transistor is connected to the third terminal of the fifth transistor and serves as the output terminal of the differential unit. The first terminal of the third transistor is connected to the first control signal. The second terminal of the third transistor is grounded. The first terminal of the fourth transistor is connected to the third terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the power supply. The second terminal of the fifth transistor is connected to the power supply.

[0026] In some embodiments, the photosensitive unit includes:

[0027] A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

[0028] In some embodiments, the transmission unit includes:

[0029] A sixth transistor; the first terminal of the sixth transistor is connected to the second control signal, the second terminal of the sixth transistor is connected to the photosensitive unit, and the third terminal of the sixth transistor is connected to the floating diffusion node.

[0030] In some embodiments, the reset unit includes:

[0031] The seventh transistor; the first terminal of the seventh transistor is connected to the third control signal, the second terminal of the seventh transistor is connected to the floating diffusion node, and the third terminal of the seventh transistor is connected to the power supply.

[0032] In some embodiments, the first storage unit includes:

[0033] The eighth transistor and the first capacitor; the first terminal of the eighth transistor is connected to the fourth control signal, the second terminal of the eighth transistor serves as the input terminal of the first memory cell, the third terminal of the eighth transistor is connected to the first terminal of the first capacitor and serves as the output terminal of the first memory cell, and the other terminal of the first capacitor is grounded.

[0034] In some embodiments, the second storage unit includes:

[0035] The second capacitor; the first terminal of the second capacitor is connected to the first storage unit and the differential unit, and the second terminal of the second capacitor is grounded.

[0036] In some embodiments, the second storage unit further includes:

[0037] The ninth transistor; the first terminal of the ninth transistor is connected to the fifth control signal, the second terminal of the ninth transistor is connected to the first terminal of the second capacitor and serves as the output terminal of the second memory cell, and the third terminal of the ninth transistor serves as the input terminal of the second memory cell.

[0038] In some embodiments, the amplification unit includes:

[0039] The tenth and eleventh transistors;

[0040] The first terminal of the tenth transistor is connected to the floating diffusion node, the second terminal of the tenth transistor is connected to the third terminal of the eleventh transistor and serves as the output terminal of the amplification unit, the third terminal of the tenth transistor is connected to the power supply, the first terminal of the eleventh transistor is connected to the sixth control signal, and the second terminal of the eleventh transistor is grounded.

[0041] To address the aforementioned technical problems, this application also provides an image sensor, which includes the global shutter pixels described above.

[0042] In some embodiments, a preset number of global shutter pixels share a differential unit in the image sensor.

[0043] In some embodiments, the image sensor has a preset number of global shutter pixels sharing storage units.

[0044] The global shutter pixel provided in this application includes a photosensitive unit, a transmission unit, a reset unit, a storage unit, and a differential unit; the photosensitive unit is used to generate charge by photosensitive sensing; the transmission unit is used to transmit the charge to a floating diffusion node when the transmission unit is turned on; the reset unit is used to reset the global shutter pixel when the reset unit is turned on; the storage unit is used to store the voltage at the floating diffusion node, the voltage at the floating diffusion node including a reset voltage and a signal voltage; the differential unit is used to output the difference between the reset voltage and the signal voltage.

[0045] As can be seen, the global shutter pixel provided in this application calculates the difference between the reset voltage and the signal voltage through the differential unit. The global shutter pixel outputs the difference between the reset voltage and the signal voltage. In this way, the global shutter pixel only needs to output a signal to the analog-to-digital converter once, reducing the number of signal outputs. This reduces the data processing load of the analog-to-digital converter, lowers the power consumption of the image sensor, and improves the frame rate of the image sensor.

[0046] The image sensor provided in this application also has the aforementioned technical effects. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 is a schematic diagram of the overall architecture of a CIS provided in an embodiment of this application;

[0049] Figure 2 is a schematic diagram of a single-slope analog-to-digital converter provided in an embodiment of this application;

[0050] Figure 3 is a schematic diagram of the first type of global shutter pixel provided in the embodiments of this application;

[0051] Figure 4 is a schematic diagram of the second type of global shutter pixel provided in the embodiments of this application;

[0052] Figure 5 is a first timing diagram provided in the embodiments of this application;

[0053] Figure 6 is a schematic diagram of the third type of global shutter pixel provided in the embodiments of this application;

[0054] Figure 7 is a schematic diagram of the fourth type of global shutter pixel provided in the embodiments of this application;

[0055] Figure 8 is a schematic diagram of the fifth type of global shutter pixel provided in the embodiments of this application;

[0056] Figure 9 is a second timing diagram provided in an embodiment of this application;

[0057] Figure 10 is a third timing diagram provided in the embodiments of this application;

[0058] Figure 11 is a schematic diagram of a first specific global shutter pixel provided in the embodiment of this application;

[0059] Figure 12 is a cross-sectional view of the first type of global shutter pixel provided in the embodiment of this application;

[0060] Figure 13 is a schematic diagram of a copper-to-copper bonding process provided in an embodiment of this application;

[0061] Figure 14 is a schematic diagram of a second specific global shutter pixel provided in the embodiments of this application;

[0062] Figure 15 is a cross-sectional view of the second type of global shutter pixel provided in the embodiment of this application;

[0063] Figure 16 is a schematic diagram of a third specific global shutter pixel provided in the embodiments of this application;

[0064] Figure 17 is a cross-sectional view of the second type of global shutter pixel provided in the embodiment of this application;

[0065] Figure 18 is a schematic diagram of the first type of pixel-shared differential unit provided in the embodiments of this application;

[0066] Figure 19 is a schematic diagram of the second type of pixel-shared differential unit provided in the embodiments of this application;

[0067] Figure 20 is a schematic diagram of the third type of pixel-shared differential unit provided in the embodiments of this application;

[0068] Figure 21 is a schematic diagram of the first type of pixel shared storage unit and differential unit provided in the embodiments of this application;

[0069] Figure 22 is a schematic diagram of the second type of pixel shared storage unit and differential unit provided in the embodiments of this application;

[0070] Figure 23 is a schematic diagram of the first pixel sharing reset unit, amplification unit, storage unit and differential unit provided in the embodiments of this application;

[0071] Figure 24 is a schematic diagram of a pixel shared reset unit, a storage unit, and a differential unit provided in an embodiment of this application;

[0072] Figure 25 is a schematic diagram of the second type of pixel sharing reset unit, amplification unit, storage unit and differential unit provided in the embodiments of this application. Detailed Implementation

[0073] The core of this application is to provide a global shutter pixel and image sensor that can reduce the power consumption of the image sensor and improve the frame rate of the image sensor.

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0075] As shown in Figure 1, the complete circuit consists of the following parts:

[0076] Pixel array unit: It is a pixel unit with r rows × c columns. Its core function is to convert light signals into photoelectrons, then convert the photoelectrons into electrical signals, and finally output the reset voltage and signal voltage to the input terminal (Vin terminal) of the analog-to-digital converter connected in parallel to each column of pixels.

[0077] Analog-to-digital converters (ADCs): Currently, single-slope ADCs (SS-ADCs) are mainly used. As shown in Figure 2, the voltage of the floating diffusion node (FD) is connected to the input terminal (Vin terminal) of the operational amplifier (COMP) through a source follower. It is then compared with the step voltage (Vramp) generated by the ramp generator. When the voltage input to the operational amplifier equals the step voltage, the operational amplifier reverses, and the counter stops counting. Correlated double sampling (CDS) first samples the Vrst voltage (reset voltage), and then samples Vrst voltage + Vsig voltage (i.e., the signal voltage). One upsampling yields the rst count, and one downsampling yields the sig + rst count. The difference between the two counter counts is the actual output value sig count of the pixel. Upsampling refers to increasing the sampling rate or resolution of a signal or image, while downsampling refers to decreasing the sampling rate or resolution of a signal or image.

[0078] Readout logic: Its main components include adders or subtractors, multipliers, inverting logic, and storage units. The readout logic reassembles the digital signals output from the analog-to-digital converter into new digital signals. This includes noise suppression, fitting signals with different gains, adding a synchronization signal to adjust the lens aperture, and finally completing the image signal.

[0079] Parallel-to-serial conversion circuit: This part is currently mainly implemented using a sense amplifier (SA), but it can also be implemented using other circuits. The parallel-to-serial circuit primarily converts the digital output on the column into a serial digital output through a decoder on the column, transmitting the constituent data and character code elements in the read logic bit by bit in sequence. Parallel data transmission transmits a fixed number of bits (usually 8 or 12 bits, etc.) of data and character code elements simultaneously to the receiving end, which is the grayscale value of the output image.

[0080] The current mainstream solution adopts column ADC quantization mode, that is, each column of pixels shares one ADC. For example, as shown in Figure 1, the pixels in the first column of the pixel array use the first ADC (ADC(1)) to process data, and the pixels in the Cth column use the Cth ADC (ADC(C)) to process data. One ADC can only process the data of one pixel at a time. In order to improve the quantization speed, multiple ADCs are currently deployed to achieve simultaneous quantization of multiple rows, thereby improving the frame rate, but this will lead to increased power consumption, larger chip area and higher overall cost. In order to solve the above technical defects, this application provides a global shutter pixel.

[0081] Please refer to Figure 3, which is a schematic diagram of a global shutter pixel provided in an embodiment of this application. As shown in Figure 3, the global shutter pixel includes:

[0082] Photosensitive unit 10, transmission unit 20, reset unit 30, storage unit 40, differential unit 50;

[0083] The photosensitive unit 10 is used to generate charge by sensing light;

[0084] The transmission unit 20 is used to transmit the charge to the floating diffusion node when the transmission unit 20 is turned on.

[0085] The reset unit 30 is used to reset the global shutter pixels when the reset unit 30 is turned on.

[0086] The storage unit 40 is used to store the voltage at the floating diffusion node, the voltage at the floating diffusion node including a reset voltage and a signal voltage;

[0087] The differential unit 50 is used to output the difference between the reset voltage and the signal voltage.

[0088] The photosensitive unit 10 is connected to the transmission unit 20. The transmission unit 20, the reset unit 30, and the storage unit 40 are all connected to the floating diffusion node (FD shown in Figure 3). The storage unit 40 is also connected to the differential unit 50. The reset voltage and signal voltage stored in the storage unit 40 are input to the differential unit 50, and the differential unit 50 outputs the difference between the reset voltage and the signal voltage. In this way, the differential unit 50 calculates the reset voltage and signal voltage within the global shutter pixel, and only needs to output the difference between the reset voltage and the signal voltage once to the analog-to-digital converter.

[0089] In some embodiments, the storage unit 40 includes:

[0090] A first storage unit and a second storage unit; the first storage unit is used to store one of a reset voltage and a signal voltage, and the second storage unit is used to store the other of a reset voltage and a signal voltage.

[0091] The first storage unit and the second storage unit store voltages of different types. The first storage unit stores a reset voltage, and the second storage unit stores a signal voltage. Alternatively, the first storage unit stores a signal voltage, and the second storage unit stores a reset voltage.

[0092] In some embodiments, the first storage unit is connected to the input terminal of the second storage unit and serves as the input terminal of the storage unit 40, the output terminal of the first storage unit is connected to one input terminal of the differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit 50.

[0093] In this embodiment, the first storage unit and the second storage unit are connected in a parallel manner. The input terminal of the first storage unit is connected to the input terminal of the second storage unit, the output terminal of the first storage unit is connected to one input terminal of the differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit 50. For example, as shown in FIG4, both the input terminals of the first storage unit and the second storage unit are connected to floating diffusion nodes, the output terminal of the first storage unit is connected to one input terminal of the differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit 50.

[0094] In some embodiments, the input terminal of the first storage unit serves as the input terminal of the storage unit 40, the output terminal of the first storage unit is connected to the input terminal of the second storage unit and one input terminal of the differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit 50.

[0095] In this embodiment, the first storage unit and the second storage unit are connected in series. The input terminal of the first storage unit serves as the input terminal of the storage unit 40, the output terminal of the first storage unit is connected to the input terminal of the second storage unit and one input terminal of the differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit 50.

[0096] In some embodiments, the differential unit 50 is controlled by a first control signal. When the first control signal is a first level signal, the differential unit 50 outputs the difference between the reset voltage and the signal voltage. The transmission unit 20 is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a third control signal. When the third control signal is a first level signal, the reset unit 30 is turned on, connecting the power supply of the floating diffusion node to the reset unit 30. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor C1 of the first storage unit is connected to the input terminal of the first storage unit.

[0097] The first control signal can be high. When the first control signal is high, the differential unit 50 outputs the difference between the reset voltage and the signal voltage; when the second control signal is high, the transmission unit 20 is turned on; when the third control signal is high, the reset unit 30 is turned on, connecting the power supply of the floating diffusion node to the reset unit 30; when the fourth control signal is high, the first capacitor C1 of the first storage unit is connected to the input terminal of the first storage unit.

[0098] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, and fourth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third and fourth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth control signal is a first-level signal; during the signal voltage storage phase, the first, third, and fourth control signals are second-level signals, and the second control signal is a first-level signal; during the output phase, the first control signal is a first-level signal, and the second, third, and fourth control signals are second-level signals.

[0099] Referring to Figure 5, when the first control signal is high and the second control signal is low, the working principle of the global shutter pixel shown in Figure 4 is as follows:

[0100] In Figure 5, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, and S1 represents the fourth control signal.

[0101] At time t0, the system enters the reset phase. During the reset phase, the first control signal is low (e.g., -1V to 0V), and the second, third, and fourth control signals are all high (e.g., 2.5V to 3.5V). At this time, the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are reset. The original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state so that during subsequent exposures, the charges induced by global shutter pixels at different locations are entirely due to illumination.

[0102] The reset state is maintained until time t1, at which point the exposure stage begins. During the exposure stage, the second control signal is low (e.g., -1V to 0V), and the photosensitive unit 10 begins to accumulate photogenerated electrons. At this time, the third and fourth control signals are maintained high to remove photogenerated electrons at the floating diffusion node, the first storage unit, and the second storage unit, reducing signal noise and eliminating the need for light-shielding structures at these locations. Under strong light, the photosensitive unit 10 becomes fully charged, as shown by the dashed line in Figure 5. The closing negative voltage of the transmission unit 20 (typically the negative voltage of the solid line (around -1V)) can be increased to (e.g., -0.5V to 0.5V), causing some electrons to overflow to the floating diffusion node. This enhances the signal crosstalk capability of the global exposure pixels and improves image quality.

[0103] The exposure phase continues until time t2, after which the reset voltage storage phase begins. During this phase, the third control signal is low, and the reset voltage of the floating diffusion node is stored in the first and second memory cells. Since the first and second memory cells are directly connected to the floating diffusion node, a proportional charge transfer is achieved, increasing the actual output swing. At time t3, the fourth control signal goes low, latching the reset voltage into the first memory cell.

[0104] At time t3, the signal voltage storage stage begins. During this stage, the second control signal is high, the transmission unit 20 is turned on, photogenerated electrons in the photosensitive unit 10 flow into the floating diffusion node, the voltage of the floating diffusion node drops, and the signal voltage at the floating diffusion node is directly stored in the second storage unit.

[0105] At time t4, the output stage begins, where signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to a single-slope analog-to-digital converter for processing. The first control signal in the output stage is high, at which point the differential unit 50 starts operating, and its output terminal Vout outputs the value of the reset voltage minus the signal voltage.

[0106] Next, the single-slope analog-to-digital converter outside the pixel array is activated, and the output signal Vout of the global shutter pixel is input to the Vin port of the comparator COMP. It is compared with the gradually increasing Vramp voltage, and the counter counts to represent the gray value corresponding to the output signal. When Vin and Vramp are equal, the comparator COMP reverses, and the counter stops counting. The count is the actual gray value of the pixel. Then, the gray value of the global shutter pixel in that row (or column) is passed to the storage unit of the next level readout logic. The global shutter pixel in that row (or column) enters the reset standby state at time t6, and the operation of the global shutter pixel in the next row (or next column) begins from time t4 to time t6.

[0107] Finally, the data from all rows (or all columns) are combined in a parallel-to-serial converter to perform image synthesis calculations and output a high frame rate image.

[0108] Referring to Figure 6, in some embodiments, the global shutter pixel further includes:

[0109] Amplification unit 60 is used to amplify the voltage at the floating diffusion node and output it to the input terminal of storage unit 40.

[0110] Photosensitive unit 10 is connected to transmission unit 20. Transmission unit 20 and reset unit 30 are connected to a floating diffusion node. The input terminal of amplification unit 60 serves as the floating diffusion node. The input terminal of storage unit 40 is connected to the output terminal of amplification unit 60. Storage unit 40 is also connected to differential unit 50. As shown in Figure 7, the input terminals of the first and second storage units are both connected to the output terminals of amplification unit 60. The output terminal of the first storage unit is connected to one input terminal of differential unit 50, and the output terminal of the second storage unit is connected to the other input terminal of differential unit 50. Alternatively, as shown in Figure 8, the input terminal of the first storage unit is connected to the output terminal of amplification unit 60. The output terminal of the first storage unit is connected to one input terminal of differential unit 50 and the input terminal of the second storage unit. The output terminal of the second storage unit is connected to the other input terminal of differential unit 50. Amplification unit 60 amplifies the voltage at the floating diffusion node and outputs it to storage unit 40. The reset voltage and signal voltage stored in storage unit 40 are input to differential unit 50, and differential unit 50 outputs the difference between the reset voltage and the signal voltage.

[0111] In some embodiments, the differential unit 50 is controlled by a first control signal. When the first control signal is a first level signal, the differential unit 50 outputs the difference between the reset voltage and the signal voltage. The transmission unit 20 is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a third control signal. When the third control signal is a first level signal, the reset unit 30 is turned on, connecting the power supply of the floating diffusion node to the reset unit 30. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor C1 of the first storage unit is connected to the floating diffusion node. The second storage unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the second capacitor C2 of the second storage unit is connected to the input terminal of the second storage unit. The amplification unit 60 is controlled by a sixth control signal. When the sixth control signal is a first level signal, the amplification unit 60 amplifies the voltage at the floating diffusion node and outputs it to the input terminal of the storage unit 40.

[0112] The first control signal can be high level. When the first control signal is high level, the differential unit 50 outputs the difference between the reset voltage and the signal voltage. When the second control signal is high level, the transmission unit 20 is turned on. When the third control signal is high level, the reset unit 30 is turned on, connecting the power supply of the floating diffusion node to the reset unit 30. When the fourth control signal is high level, the first capacitor C1 of the first storage unit is connected to the floating diffusion node. When the fifth control signal is high level, the second capacitor C2 of the second storage unit is connected to the input terminal of the second storage unit. When the sixth control signal is high level, the amplification unit 60 amplifies the voltage at the floating diffusion node and outputs it to the input terminal of the storage unit 40.

[0113] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, fourth, fifth, and sixth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third, fourth, fifth, and sixth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth, fifth, and sixth control signals are first-level signals; during the signal voltage storage phase, the first, third, and fourth control signals are second-level signals, and the second, fifth, and sixth control signals are first-level signals; during the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

[0114] Referring to Figure 9, when the first control signal is high and the second control signal is low, the working principle of the global shutter pixel shown in Figure 7 is as follows:

[0115] In Figure 9, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, and PC represents the sixth control signal.

[0116] At time t0, the reset phase begins. The first control signal is low (e.g., -1V to 0V), while the second, third, fourth, fifth, and sixth control signals are high (e.g., 2.5V to 3.5V). During this phase, the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are reset. The original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state. This ensures that during subsequent exposures, the charges induced by pixels at different locations are entirely due to illumination.

[0117] The system remains in the reset state until time t1, at which point it enters the exposure phase. During the exposure phase, the second control signal is low (e.g., -1V to 0V), and the photosensitive unit 10 begins to accumulate photogenerated electrons. The third, fourth, fifth, and sixth control signals are maintained at high levels to remove photogenerated electrons from the floating diffusion node, the first storage unit, and the second storage unit, reducing signal noise and eliminating the need for the light-shielding structures of the floating diffusion node, the first storage unit, and the second storage unit. Under strong light, when the charge storage in the photosensitive unit 10 is full, the closing negative voltage of the transmission unit 20 can be increased to (e.g., -0.5V to 0.5V), causing some electrons to overflow to the floating diffusion node, thereby enhancing the signal crosstalk capability of the pixel and improving image quality.

[0118] The exposure phase continues until time t2, after which the reset voltage storage phase begins. During this phase, the second control signal is low, while the fourth and fifth control signals are high. The potential of the floating diffusion node is the reset voltage, which is transmitted to the first and second memory cells via amplification unit 60. Then, at time t3, the fourth control signal goes low, latching the reset voltage into the first memory cell.

[0119] During the signal voltage storage phase, the second control signal is at a high level. During this phase, photogenerated electrons flow into the floating diffusion node in the photosensitive unit 10, causing the voltage of the floating diffusion node to drop. Similarly, the amplification unit 60 converts the photogenerated signal into a signal voltage and stores it in the second storage unit. At time t4, the fifth control signal goes low, latching the signal voltage into the second storage unit.

[0120] At time t4, the output stage begins, where signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to a single-slope analog-to-digital converter for processing. The first control signal in the output stage is high, at which point the differential unit 50 starts operating, and its output terminal Vout outputs the value of the reset voltage minus the signal voltage.

[0121] Next, the single-slope analog-to-digital converter outside the pixel array is activated, and the output signal Vout of the global shutter pixel is input to the Vin port of the comparator COMP. It is compared with the gradually increasing Vramp voltage, and the counter counts to represent the gray value corresponding to the output signal. When Vin and Vramp are equal, the comparator COMP reverses, and the counter stops counting. The count is the actual gray value of the pixel. Then, the gray value of the global shutter pixel in that row (or column) is passed to the storage unit of the next level readout logic. The global shutter pixel in that row (or column) enters the reset standby state at time t6, and the operation of the global shutter pixel in the next row (or next column) begins from time t4 to time t6.

[0122] Finally, the data from all rows (or all columns) are combined in a parallel-to-serial converter to perform image synthesis calculations and output a high frame rate image.

[0123] In some embodiments, during the reset phase, the first control signal is a second-level signal, and the second, third, fourth, fifth, and sixth control signals are first-level signals; during the exposure phase, the first and second control signals are second-level signals, and the third, fourth, fifth, and sixth control signals are first-level signals; during the reset voltage storage phase, the first, second, and third control signals are second-level signals, and the fourth, fifth, and sixth control signals are first-level signals; during the signal voltage storage phase, the first, third, and fifth control signals are second-level signals, and the second, fourth, and sixth control signals are first-level signals; during the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

[0124] Referring to Figure 10, when the first control signal is high and the second control signal is low, the working principle of the global shutter pixel shown in Figure 8 is as follows:

[0125] In Figure 10, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, and PC represents the sixth control signal.

[0126] At time t0, the reset phase begins. The first control signal is low (e.g., -1V to 0V), while the second, third, fourth, fifth, and sixth control signals are high (e.g., 2.5V to 3.5V). During this phase, the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are reset. The original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit, and the second storage unit are cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state. This ensures that during subsequent exposures, the charges induced by pixels at different locations are entirely due to illumination.

[0127] The system remains in the reset state until time t1, at which point it enters the exposure phase. During the exposure phase, the second control signal is low (e.g., -1V to 0V), and the photosensitive unit 10 begins to accumulate photogenerated electrons. The third, fourth, fifth, and sixth control signals are maintained at high levels to remove photogenerated electrons from the floating diffusion node, the first storage unit, and the second storage unit, reducing signal noise and eliminating the need for the light-shielding structures of the floating diffusion node, the first storage unit, and the second storage unit. Under strong light, when the charge storage in the photosensitive unit 10 is full, the closing negative voltage of the transmission unit 20 can be increased to (e.g., -0.5V to 0.5V), causing some electrons to overflow to the floating diffusion node, thereby enhancing the signal crosstalk capability of the pixel and improving image quality.

[0128] The exposure phase continues until time t2, after which the reset voltage storage phase begins. During this phase, the second control signal is low, while the fourth and fifth control signals are high. The potential of the floating diffusion node is the reset voltage, which is transmitted to the first and second memory cells via amplification unit 60. Then, at time t3, the fifth control signal goes low, latching the reset voltage into the second memory cell.

[0129] During the signal voltage storage phase, the second control signal is at a high level. During this phase, photogenerated electrons flow into the floating diffusion node in the photosensitive unit 10, causing the voltage of the floating diffusion node to drop. Similarly, the amplification unit 60 converts the photogenerated signal into a signal voltage and stores it in the first storage unit. At time t4, the fourth control signal goes low, latching the signal voltage into the first storage unit.

[0130] At time t4, the output stage begins, where signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to a single-slope analog-to-digital converter for processing. The first control signal in the output stage is high, at which point the differential unit 50 starts operating, and its output terminal Vout outputs the value of the reset voltage minus the signal voltage.

[0131] Next, the single-slope analog-to-digital converter outside the pixel array is activated, and the output signal Vout of the global shutter pixel is input to the Vin port of the comparator COMP. It is compared with the gradually increasing Vramp voltage, and the counter counts to represent the gray value corresponding to the output signal. When Vin and Vramp are equal, the comparator COMP reverses, and the counter stops counting. The count is the actual gray value of the pixel. Then, the gray value of the global shutter pixel in that row (or column) is passed to the storage unit of the next level readout logic. The global shutter pixel in that row (or column) enters the reset standby state at time t6, and the operation of the global shutter pixel in the next row (or next column) begins from time t4 to time t6.

[0132] Finally, the data from all rows (or all columns) are combined in a parallel-to-serial converter to perform image synthesis calculations and output a high frame rate image.

[0133] In some embodiments, the differential unit 50 includes:

[0134] The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5;

[0135] The first terminal of the first transistor M1 serves as one input terminal of the differential unit 50. The second terminal of the first transistor M1 is connected to the third terminal of the second transistor M2 and the third terminal of the third transistor M3. The third terminal of the first transistor M1 is connected to the third terminal of the fourth transistor M4. The first terminal of the second transistor M2 serves as the other input terminal of the differential unit 50. The second terminal of the second transistor M2 is connected to the third terminal of the fifth transistor M5 and serves as the output terminal of the differential unit 50. The first terminal of the third transistor M3 is connected to the first control signal, and the second terminal of the third transistor M3 is grounded. The first terminal of the fourth transistor M4 is connected to the third terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5. The second terminal of the fourth transistor M4 is connected to the power supply, and the second terminal of the fifth transistor M5 is connected to the power supply.

[0136] In some embodiments, the photosensitive unit 10 includes:

[0137] A photodiode PD; the anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the transmission unit 20.

[0138] In some embodiments, the transmission unit 20 includes:

[0139] The sixth transistor M6; the first terminal of the sixth transistor M6 is connected to the second control signal, the second terminal of the sixth transistor M6 is connected to the photosensitive unit 10, and the third terminal of the sixth transistor M6 is connected to the floating diffusion node.

[0140] In some embodiments, the reset unit 30 includes:

[0141] The seventh transistor M7; the first terminal of the seventh transistor M7 is connected to the third control signal, the second terminal of the seventh transistor M7 is connected to the floating diffusion node, and the third terminal of the seventh transistor M7 is connected to the power supply.

[0142] In some embodiments, the first storage unit includes:

[0143] The eighth transistor M8 is connected to the first capacitor C1; the first terminal of the eighth transistor M8 is connected to the fourth control signal, the second terminal of the eighth transistor M8 serves as the input terminal of the first memory cell, the third terminal of the eighth transistor M8 is connected to the first terminal of the first capacitor C1 and serves as the output terminal of the first memory cell, and the other terminal of the first capacitor C1 is grounded.

[0144] In some embodiments, the second storage unit includes:

[0145] The second capacitor C2; the first end of the second capacitor C2 is connected to the first storage unit and the differential unit, and the second end of the second capacitor C2 is grounded.

[0146] As shown in Figure 11, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the eighth transistor M8 can be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 can be PMOS transistors.

[0147] The global shutter pixel can be stacked, dividing it into a photosensitive readout pixel layer and a differential circuit logic layer to improve the fill factor (FF) of the photodiode (PD) area. The differential circuit logic layer can use the same or different process as the photosensitive readout pixel layer to reduce the development difficulty of the PMOS process. The first capacitor C1, the second capacitor C2, and the eighth transistor belong to the readout pixel layer, while the transistors in the differential unit 50 belong to the differential circuit logic layer. Figure 11 shows a cross-sectional view of the global shutter pixel, which is illustrated in Figure 12. This cross-sectional view is a general schematic diagram of the first capacitor C1, the second capacitor C2, the transistors in the differential unit 50, the eighth transistor M8, and their metal interconnections. The interface between the photosensitive readout pixel layer and the differential circuit logic layer is called the hybrid bond interface, typically using pixel-level copper-to-copper bonding (Cu-Cu hybrid bond). The process flow is shown in Figure 13. A dielectric layer of uniform thickness is formed on the entire silicon surface using Chemical Vapor Deposition (PVD), followed by the fabrication of trenches and vias as part of the Back End of Line (BEOL) process. Copper seed crystals are formed in the trenches using Physical Vapor Deposition (PVD). Subsequently, the trenches are filled with copper using Electrochemical Deposition (ECD), excess copper is removed, and a very low dielectric roughness is achieved through Chemical Mechanical Polishing (CMP). During CMP, the copper is expected to be recessed to a certain extent, allowing the wafers of the photosensitive readout pixel layer and the differential circuit logic layer to bond face-to-face, and the dielectrics to bond instantaneously. After chemical mechanical polishing, annealing is performed at a temperature of 150°C to 300°C. Since the coefficient of thermal expansion (CTE) of the metal is higher than that of the oxide, the metal expands to fill the gaps between them. As a result of the above steps, due to the dielectric bonding between the upper and lower wafers, and the copper-to-copper bonding process providing physical and electrical connections, the normal operation of the photosensitive readout pixel layer and the differential circuit logic layer is achieved.

[0148] In some embodiments, the second storage unit further includes:

[0149] The ninth transistor M9; the first terminal of the ninth transistor M9 is connected to the fifth control signal, the second terminal of the ninth transistor M9 is connected to the first terminal of the second capacitor C2 and serves as the output terminal of the second memory cell, and the third terminal of the ninth transistor M9 serves as the input terminal of the second memory cell.

[0150] As shown in Figure 14 or Figure 16, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the ninth transistor M9 can be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 can be PMOS transistors.

[0151] When using a stacking process, the cross-sectional view of the global shutter pixel shown in Figure 14 can be referred to as Figure 15, and the cross-sectional view of the global shutter pixel shown in Figure 16 can be referred to as Figure 17.

[0152] In some embodiments, the amplification unit 60 includes:

[0153] Tenth transistor M10 and eleventh transistor M11;

[0154] The first terminal of the tenth transistor M10 is connected to the floating diffusion node, the second terminal of the tenth transistor M10 is connected to the third terminal of the eleventh transistor M11 and serves as the output terminal of the amplification unit 60, the third terminal of the tenth transistor M10 is connected to the power supply, the first terminal of the eleventh transistor M11 is connected to the sixth control signal, and the second terminal of the eleventh transistor M11 is grounded.

[0155] As shown in Figure 14 or Figure 16, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the eleventh transistor M11 can be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 can be PMOS transistors.

[0156] In summary, the global shutter pixel provided in this application calculates the difference between the reset voltage and the signal voltage through a differential unit. The global shutter pixel outputs the difference between the reset voltage and the signal voltage. In this way, the global shutter pixel only needs to output a signal to the analog-to-digital converter once, reducing the number of signal outputs. This reduces the data processing load of the analog-to-digital converter, lowers the power consumption of the image sensor, and increases the frame rate of the image sensor.

[0157] This application also provides an image sensor that includes the global shutter pixel as described in the above embodiments.

[0158] In some embodiments, a preset number of global shutter pixels in the image sensor share a differential unit. For example, as shown in Figures 18, 19, and 20, two global shutter pixels share a differential unit. Specifically, selection transistors Share_S1_L, Share_S2_L and Share_S1_R, Share_S2_R are added to the capacitors of the two global shutter pixels to increase the readout capability of transistors DN1 and DN2. The two global shutter pixels sharing the differential unit can be divided into a left global shutter pixel and a right global shutter pixel. When reading the output value of the left global shutter pixel, Share_S1_L and Share_S2_L are turned on, while Share_S1_R and Share_S2_R are turned off. The voltage of capacitor C1_L is applied to transistor DN1, and the voltage of capacitor C2_L is applied to transistor DN2. At this time, the differential unit outputs the difference between the reset voltage and the signal voltage of the left global shutter pixel. When reading the output value of the right global shutter pixel, Share_S1_R and Share_S2_R are turned on, while Share_S1_L and Share_S2_L are turned off. The voltage of capacitor C1_R is applied to transistor DN1, and the voltage of capacitor C2_R is applied to transistor DN2. At this time, the differential unit outputs the difference between the reset voltage and the signal voltage of the right global shutter pixel.

[0159] Global shutter pixels share a differential unit, which reduces the number of components, increases the fill factor of global shutter pixels, reduces costs, and improves the quantum efficiency of the camera.

[0160] In some embodiments, a predetermined number of global shutter pixels share a storage unit in the image sensor. For example, as shown in Figures 21 and 22, two global shutter pixels share a storage unit. After exposure, the difference between the reset voltage and the signal voltage of the odd-numbered global shutter pixels can be calculated first, and then the difference between the reset voltage and the signal voltage of the even-numbered global shutter pixels can be calculated.

[0161] The global shutter pixels share a storage unit, which can reduce the number of components, improve the fill factor of the global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0162] In this system, global shutter pixels can share both differential units and storage units, which can further reduce the number of devices, improve the fill factor of global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0163] In some embodiments, a predetermined number of global shutter pixels in the image sensor share a reset unit, an amplification unit, a storage unit, and a differential unit. For example, as shown in Figures 23 and 25. In some embodiments, a predetermined number of global shutter pixels in the image sensor share a reset unit, a storage unit, and a differential unit. For example, as shown in Figure 24. The above embodiments can be applied to the readout of combinations of different photodiodes, or different photodiodes can be designed under a single photosensitive lens for autofocus and distance measurement.

[0164] Global shutter pixels share differential units, shared memory units, reset units, and / or amplification units, which can further reduce the number of components, improve the fill factor of global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0165] Due to the complexity of the situation, it is impossible to list and elaborate on them all. Those skilled in the art should realize that there can be multiple examples based on the basic principles of the embodiments provided in this application and in combination with actual situations. Without sufficient creative effort, all of them should be within the scope of this application.

[0166] The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0167] The global shutter pixel and image sensor provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0168] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A global shutter pixel, characterized in that, include: Photosensitive unit, transmission unit, reset unit, storage unit, differential unit; The photosensitive unit is used to generate charge by sensing light; The transmission unit is used to transmit the charge to the floating diffusion node when the transmission unit is turned on. The reset unit is used to reset the global shutter pixels when the reset unit is turned on. The storage unit is used to store the voltage at the floating diffusion node, wherein the voltage at the floating diffusion node includes a reset voltage and a signal voltage; The differential unit is used to output the difference between the reset voltage and the signal voltage.

2. The global shutter pixel according to claim 1, characterized in that, The storage unit includes: A first storage unit and a second storage unit; the first storage unit is used to store one of a reset voltage and a signal voltage, and the second storage unit is used to store the other of a reset voltage and a signal voltage.

3. The global shutter pixel according to claim 2, characterized in that, The first storage unit is connected to the input terminal of the second storage unit and serves as the input terminal of the storage unit. The output terminal of the first storage unit is connected to one input terminal of the differential unit, and the output terminal of the second storage unit is connected to the other input terminal of the differential unit.

4. The global shutter pixel according to claim 2, characterized in that, The input terminal of the first storage unit serves as the input terminal of the storage unit. The output terminal of the first storage unit is connected to the input terminal of the second storage unit and one input terminal of the differential unit. The output terminal of the second storage unit is connected to the other input terminal of the differential unit.

5. The global shutter pixel according to claim 3, characterized in that, The differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on, connecting the power supply of the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the input terminal of the first storage unit.

6. The global shutter pixel according to claim 5, characterized in that, During the reset phase, the first control signal is a second-level signal, and the second control signal, the third control signal, and the fourth control signal are first-level signals. During the exposure stage, the first control signal and the second control signal are second-level signals, and the third control signal and the fourth control signal are first-level signals; During the reset voltage storage phase, the first control signal, the second control signal, and the third control signal are second-level signals, and the fourth control signal is a first-level signal; During the signal voltage storage stage, the first control signal, the third control signal, and the fourth control signal are second-level signals, and the second control signal is a first-level signal; During the output phase, the first control signal is a first-level signal, and the second, third, and fourth control signals are second-level signals.

7. The global shutter pixel according to claim 1, characterized in that, Also includes: An amplification unit is used to amplify the voltage at the floating diffusion node and output it to the input terminal of the storage unit.

8. The global shutter pixel according to claim 7, characterized in that, The differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on, connecting the power supply between the floating diffusion node and the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the floating diffusion node. The second storage unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the second capacitor of the second storage unit is connected to the input terminal of the second storage unit. The amplification unit is controlled by a sixth control signal. When the sixth control signal is a first level signal, the amplification unit amplifies the voltage at the floating diffusion node and outputs it to the input terminal of the storage unit.

9. The global shutter pixel according to claim 8, characterized in that, During the reset phase, the first control signal is a second-level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals. During the exposure stage, the first control signal and the second control signal are second-level signals, and the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals. During the reset voltage storage phase, the first control signal, the second control signal, and the third control signal are second-level signals, and the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals; during the signal voltage storage phase, the first control signal, the third control signal, and the fourth control signal are second-level signals, and the second control signal, the fifth control signal, and the sixth control signal are first-level signals. During the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

10. The global shutter pixel according to claim 8, characterized in that, During the reset phase, the first control signal is a second-level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals. During the exposure stage, the first control signal and the second control signal are second-level signals, and the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals. During the reset voltage storage phase, the first control signal, the second control signal, and the third control signal are second-level signals, and the fourth control signal, the fifth control signal, and the sixth control signal are first-level signals; during the signal voltage storage phase, the first control signal, the third control signal, and the fifth control signal are second-level signals, and the second control signal, the fourth control signal, and the sixth control signal are first-level signals. During the output phase, the first control signal is a first-level signal, and the second, third, fourth, fifth, and sixth control signals are second-level signals.

11. The global shutter pixel according to any one of claims 1 to 10, characterized in that, The differential unit includes: The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor; The first terminal of the first transistor serves as one input terminal of the differential unit. The second terminal of the first transistor is connected to the third terminal of the second transistor and the third terminal of the third transistor. The third terminal of the first transistor is connected to the third terminal of the fourth transistor. The first terminal of the second transistor serves as another input terminal of the differential unit. The second terminal of the second transistor is connected to the third terminal of the fifth transistor and serves as the output terminal of the differential unit. The first terminal of the third transistor is connected to the first control signal. The second terminal of the third transistor is grounded. The first terminal of the fourth transistor is connected to the third terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the power supply. The second terminal of the fifth transistor is connected to the power supply.

12. The global shutter pixel according to claim 1, characterized in that, The photosensitive unit includes: A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

13. The global shutter pixel according to claim 1, characterized in that, The transmission unit includes: A sixth transistor; the first terminal of the sixth transistor is connected to the second control signal, the second terminal of the sixth transistor is connected to the photosensitive unit, and the third terminal of the sixth transistor is connected to the floating diffusion node.

14. The global shutter pixel according to claim 1, characterized in that, The reset unit includes: The seventh transistor; the first terminal of the seventh transistor is connected to the third control signal, the second terminal of the seventh transistor is connected to the floating diffusion node, and the third terminal of the seventh transistor is connected to the power supply.

15. The global shutter pixel according to claim 2, characterized in that, The first storage unit includes: The eighth transistor and the first capacitor; the first terminal of the eighth transistor is connected to the fourth control signal, the second terminal of the eighth transistor serves as the input terminal of the first memory cell, the third terminal of the eighth transistor is connected to the first terminal of the first capacitor and serves as the output terminal of the first memory cell, and the other terminal of the first capacitor is grounded.

16. The global shutter pixel according to claim 2, characterized in that, The second storage unit includes: The second capacitor; the first terminal of the second capacitor is connected to the first storage unit and the differential unit, and the second terminal of the second capacitor is grounded.

17. The global shutter pixel according to claim 2, characterized in that, The second storage unit further includes: The ninth transistor; the first terminal of the ninth transistor is connected to the fifth control signal, the second terminal of the ninth transistor is connected to the first terminal of the second capacitor and serves as the output terminal of the second memory cell, and the third terminal of the ninth transistor serves as the input terminal of the second memory cell.

18. The global shutter pixel according to claim 7, characterized in that, The amplification unit includes: The tenth and eleventh transistors; The first terminal of the tenth transistor is connected to the floating diffusion node, the second terminal of the tenth transistor is connected to the third terminal of the eleventh transistor and serves as the output terminal of the amplification unit, the third terminal of the tenth transistor is connected to the power supply, the first terminal of the eleventh transistor is connected to the sixth control signal, and the second terminal of the eleventh transistor is grounded.

19. An image sensor, characterized in that, The image sensor includes a global shutter pixel as described in any one of claims 1 to 18.

20. The image sensor according to claim 19, characterized in that, The image sensor contains a preset number of global shutter pixel-sharing differential units.

21. The image sensor according to claim 19, characterized in that, The image sensor contains a preset number of global shutter pixel shared storage units.

Images