Compound hall integrated chip and preparation method therefor
By forming grooves and depositing dielectric layers on the wafer surface of a silicon-based signal conditioning chip, the compound Hall element and the silicon-based signal conditioning circuit are heterogeneously integrated, solving the problem that the compound Hall chip and the silicon-based signal conditioning circuit cannot be integrated. This achieves higher integration, accuracy and reliability, and improves performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NINGBO CRRC TIMES TRANSDUCER TECH CO LTD
- Filing Date
- 2025-08-08
- Publication Date
- 2026-05-15
AI Technical Summary
In the existing technology, compound Hall chips and silicon-based signal conditioning circuits cannot be heterogeneously integrated, resulting in large package size, difficulty in alignment accuracy, long signal transmission path and poor package reliability.
By forming grooves on the wafer surface of a silicon-based signal conditioning chip, depositing dielectric films and organic adhesives, assembling compound Hall elements into the grooves, filling them with dielectric layers, and finally connecting the compound Hall elements to the silicon-based signal conditioning circuit via CONTACT and interconnects, a separate compound Hall integrated chip is formed.
It achieves high integration, precision and reliability of compound Hall effect sensors and silicon-based signal conditioning circuits, overcomes the shortcomings of traditional dual-chip co-packaging, and improves sensitivity and temperature drift characteristics.
Smart Images
Figure CN2025113454_15052026_PF_FP_ABST
Abstract
Description
A compound Hall integrated chip and its fabrication method Technical Field
[0001] This invention relates to the field of Hall effect chip technology, and in particular to a compound Hall effect integrated chip and its preparation method. Background Technology
[0002] Hall effect chips convert external input magnetic fields into output electrical signals, detecting changes in the magnetic field through these signals. A Hall effect chip mainly consists of two parts: a signal conditioning circuit and a Hall element. The signal conditioning circuit is typically fabricated on a silicon substrate using standard integrated circuit technology and mainly includes functional modules such as amplification, filtering, oscillation, clocking, and storage. Hall elements can be classified into silicon-based and compound-based (GaAs / InSb / InAs, etc.) depending on the substrate. Due to the material advantages of compound substrates, such as carrier concentration and carrier mobility, compound-based Hall elements exhibit higher sensitivity and better temperature characteristics than silicon-based Hall elements.
[0003] Currently, Hall effect chips in the industry are divided into two types. The first type is a pure silicon-based Hall effect chip integrated with a silicon-based signal conditioning circuit. This type of chip is limited by the silicon material itself and suffers from problems such as low sensitivity and temperature drift. The second type integrates a compound Hall effect chip and a silicon-based signal conditioning circuit chip into the same package through die bonding, wire bonding, and molding. Package-level integration generally refers to bonding the compound Hall effect chip and the silicon-based signal conditioning circuit chip separately during die bonding, then interconnecting them through wire bonding, and finally molding them together into the package to achieve integration. This type of chip benefits from the advantages of compound materials and has significantly better Hall effect electrical performance than the first type of pure silicon-based Hall effect chip. However, this encapsulation method has disadvantages such as large package size, difficulty in achieving alignment accuracy, long signal transmission path, and poor package reliability. Currently, there is no method in the industry to obtain a single chip integrating a compound Hall effect chip and a silicon-based signal conditioning circuit through heterogeneous integration.
[0004] A complete wafer fabrication process can be divided into three parts from front to back: device manufacturing process, control manufacturing process, and interconnect manufacturing process. The device manufacturing process mainly includes active region definition, ion implantation, and functional definition of oxide isolation devices. The control manufacturing process connects functional devices to interconnects through via structures. The interconnect manufacturing process mainly includes signal lines such as vias, metal interconnects, metal pads, dielectric layers, and passivation layers.
[0005] To address the shortcomings of existing technologies, this solution provides a compound Hall effect integrated chip and its fabrication method, thereby solving the problem of heterogeneous integration of existing compound Hall effect chips and silicon-based signal conditioning circuits. Summary of the Invention
[0006] The significance of this invention lies in solving the problem of heterogeneous integration of compound Hall effect sensors and silicon-based signal conditioning circuits, and providing a method for fabricating a compound Hall effect integrated chip. This method is the first to propose integrating a compound Hall effect element and a silicon-based signal conditioning chip together to form a single compound Hall effect integrated chip through heterogeneous integration. It overcomes the current approach of only achieving dual-chip co-packaging of the compound Hall effect chip and the silicon-based signal conditioning chip at the packaging level. The resulting compound Hall effect integrated chip features higher integration density, higher precision, superior performance, and higher reliability.
[0007] The above-mentioned objectives of the present invention are achieved through the following technical measures:
[0008] A compound Hall effect integrated chip structure and its fabrication method are provided. After the device manufacturing process is completed, a groove is formed on the wafer surface of the silicon-based signal conditioning chip by photolithography and etching. A dielectric film is deposited and an organic adhesive is coated in the groove. Then, the compound Hall element is assembled into the groove. The groove is then filled with a dielectric layer. Finally, the signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip is realized by CONTACT, VIA and interconnects, and the compound Hall effect integrated chip is finally obtained.
[0009] The method for preparing the compound Hall integrated chip of the present invention comprises the following steps:
[0010] S1. Perform device manufacturing processes on the wafer to obtain a silicon-based signal conditioning chip;
[0011] S2. Grooves are formed on the wafer surface of the silicon-based signal conditioning chip obtained in S1 by photolithography and etching, and a dielectric film is deposited and an organic adhesive is coated in the grooves.
[0012] S3. Assemble the compound Hall element into the groove obtained in S2, and proceed to S4;
[0013] S4. Deposit a dielectric layer on the wafer surface to fill the gap between the groove and the compound Hall element, thereby completing the chip surface planarization operation and proceeding to S5.
[0014] S5. Perform the CONTACT manufacturing process, followed by the interconnect manufacturing process. The interconnect manufacturing process includes the fabrication of VIA structure, METAL structure, output signal pad PAD and passivation layer structure to realize the signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.
[0015] Preferably, S2 is performed by the following steps:
[0016] S2.1. Perform photolithography and etching on the S1 silicon-based signal conditioning chip to obtain the first groove structure;
[0017] S2.2. Deposit a dielectric thin film on the inner surface of the first groove structure obtained in S2.1 to obtain the second groove structure;
[0018] S2.3. Apply organic adhesive to the bottom of the second groove structure obtained in S2.2 to obtain the groove.
[0019] Preferably, the width of the first groove structure increases sequentially from the bottom to the opening direction, and the cross-sectional shape of the first groove structure is an inverted trapezoid.
[0020] Preferably, S2.3 specifically involves spin-coating an organic adhesive onto the inner surface wafer of the second groove structure obtained in S2.2, and then using exposure and development to retain only the organic adhesive at the bottom of the second groove structure, thereby obtaining the groove.
[0021] Preferably, the bottom width of the first groove structure is greater than the maximum length of the compound Hall element.
[0022] Preferably, the bottom width of the first groove structure is 100μm to 250μm.
[0023] Preferably, the opening width of the first groove structure is 150μm to 300μm.
[0024] Preferably, the depth of the first groove structure is 1μm to 10μm.
[0025] Preferably, the thickness of the dielectric film is 1 nm to 5 nm.
[0026] Preferably, the thickness of the above-mentioned organic adhesive is 1 nm to 5 nm.
[0027] Preferably, the silicon-based signal conditioning chip is provided with a substrate and functional module elements constituting a silicon-based signal conditioning circuit.
[0028] Another objective of this invention is to overcome the shortcomings of existing technologies and provide a compound Hall effect integrated chip. This compound Hall effect integrated chip features higher integration density, higher precision, and higher reliability.
[0029] The above-mentioned objectives of the present invention are achieved through the following technical measures:
[0030] A compound Hall effect integrated chip is provided, which is prepared using the above-described method for preparing a compound Hall effect integrated chip.
[0031] This invention discloses a compound Hall effect integrated chip and its fabrication method. The fabrication method involves forming grooves on the wafer surface of a silicon-based signal conditioning chip after the device manufacturing process is completed, using photolithography and etching. A dielectric thin film is deposited and an organic adhesive is coated within the grooves. A compound Hall element is then assembled into the groove, and the groove is filled with a dielectric layer. Finally, signal connections between the compound Hall element and the functional modules of the silicon-based signal conditioning chip are achieved using CONTACT, VIA, and interconnects, ultimately resulting in the compound Hall effect integrated chip. This invention integrates a compound Hall element and a silicon-based signal conditioning chip into a single compound Hall effect integrated chip through heterogeneous integration, offering performance advantages such as sensitivity and temperature drift characteristics compared to a single-chip silicon-based Hall effect chip. Furthermore, compared to the existing dual-chip encapsulation method using a compound Hall element and a silicon-based signal conditioning circuit, this invention offers higher integration, higher precision, and higher reliability. By forming grooves in the silicon-based signal conditioning chip, this invention provides wafer integration space for the compound Hall element, enabling wafer integration of the compound Hall element and the silicon-based signal conditioning circuit. Attached Figure Description
[0032] The invention will be further described with reference to the accompanying drawings, but the contents of the drawings do not constitute any limitation on the invention.
[0033] Figure 1 is a schematic diagram of the compound Hall integrated chip of the present invention.
[0034] Figure 2 is a cross-sectional view of the "A-A" direction in Figure 1.
[0035] Figure 3 is a schematic diagram of the structure of a silicon-based signal conditioning chip.
[0036] Figure 4 is a schematic diagram of the silicon-based signal conditioning chip after processing in S2.1.
[0037] Figure 5 is a schematic diagram of the silicon-based signal conditioning chip after processing by S2.2.
[0038] Figure 6 is a top view of Figure 5.
[0039] Figure 7 is a schematic diagram of the silicon-based signal conditioning chip after processing in S2.3.
[0040] Figure 8 is a partially enlarged schematic diagram of the groove in Figure 7.
[0041] Figure 9 is a schematic diagram of the compound Hall element assembled into the groove in S3.
[0042] Figure 10 is a schematic diagram after the deposition of the medium layer in S4.
[0043] Figures 1 to 10 include:
[0044] Silicon-based signal conditioning chip 100
[0045] First groove structure 200, dielectric film 210, organic adhesive 220
[0046] Dielectric layer 300, compound Hall element 400, CONTACT structure 500, VIA / METAL structure 600, output signal pad PAD 700, substrate 800, functional module element 900. Detailed Implementation
[0047] The technical solution of the present invention will be further described in conjunction with the following embodiments. Example 1
[0048] A method for fabricating a compound Hall integrated chip involves forming grooves on the wafer surface of a silicon-based signal conditioning chip 100 after the device manufacturing process is completed by photolithography and etching. A dielectric thin film 210 and an organic adhesive 220 are deposited in the grooves. Then, a compound Hall element 400 is assembled into the grooves and filled with a dielectric layer 300. Finally, the signal connection between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100 is achieved using CONTACT, VIA, and interconnects, resulting in a compound Hall integrated chip, as shown in Figures 1 and 2.
[0049] It should be noted that the conventional silicon-based Hall chip wafer fabrication process consists of three main parts from front to back: device fabrication, CONTACT fabrication, and interconnect fabrication. This invention innovatively introduces a structure and process method between the device fabrication and CONTACT fabrication processes to achieve chip-level integration of compound Hall elements and silicon-based signal conditioning circuits, solving the current challenge of heterogeneous integration of compound Hall elements and silicon-based conditioning circuits on the same wafer. Specifically, on the wafer surface after the device fabrication process, grooves are formed by photolithography and etching. An adhesive layer is coated within the grooves, and the compound Hall element 400 is assembled within the grooves. The dielectric layer 300 is then filled and planarized, completing the new structure and process. Subsequently, the CONTACT and interconnect fabrication processes are performed according to standard procedures to finally obtain the compound Hall integrated chip.
[0050] It is evident that the method for fabricating the compound Hall integrated chip of the present invention overcomes the current approach of only being able to achieve dual-chip packaging of compound Hall chips and silicon-based signal conditioning chips 100 at the packaging level. The compound Hall integrated chip prepared has the characteristics of higher integration, higher precision, better performance, and higher reliability.
[0051] The silicon-based signal conditioning chip 100 of this invention is obtained through device manufacturing processes in the prior art, prior to the CONTACT manufacturing process. The specific structure of the silicon-based signal conditioning chip 100 is not the focus of this invention. The silicon-based signal conditioning chip 100 includes a substrate 800 and functional module elements 900 constituting a silicon-based signal conditioning circuit. These functional module elements 900 can be amplification, filtering, oscillation, clocking, storage, etc., and these functional module elements 900 together form the conditioning circuit of the silicon-based signal conditioning chip 100. Furthermore, the device manufacturing process, the CONTACT manufacturing process, and the interconnect manufacturing process are all conventional integrated circuit technologies, and those skilled in the art should be familiar with the specific operating procedures.
[0052] The method for preparing the compound Hall integrated chip of the present invention comprises the following steps:
[0053] S1. Perform device manufacturing process on the wafer to obtain silicon-based signal conditioning chip 100, as shown in Figure 3. The silicon-based signal conditioning chip 100 has not undergone CONTACT process.
[0054] S2. Grooves are formed on the wafer surface of the silicon-based signal conditioning chip 100 obtained in S1 by photolithography and etching, and a dielectric thin film 210 is deposited and an organic adhesive 220 is coated in the grooves. Specifically, S2 is performed by the following steps:
[0055] S2.1. The silicon-based signal conditioning chip 100 in S1 is subjected to photolithography and etching to obtain a first groove structure 200, as shown in Figure 4. The width of the first groove structure 200 increases sequentially from the bottom to the opening direction, and the cross-sectional shape of the first groove structure 200 is an inverted trapezoid. The bottom width of the first groove structure 200 is greater than the maximum length of the compound Hall element 400. The bottom width of the first groove structure 200 is 100μm to 250μm, the opening width of the first groove structure 200 is 150μm to 300μm, and the depth of the first groove structure 200 is 1μm to 10μm.
[0056] S2.2. A dielectric film 210 is deposited on the inner surface of the first groove structure 200 obtained in S2.1 to obtain a second groove structure, as shown in Figures 5 and 6, wherein the thickness of the dielectric film 210 is 1 nm to 5 nm.
[0057] S2.3. Apply organic adhesive 220 to the bottom of the second groove structure obtained in S2.2 to obtain the groove, as shown in Figures 7 and 8, wherein the thickness of organic adhesive 220 is 1nm to 5nm;
[0058] S3. Assemble the compound Hall element 400 into the groove obtained in S2, and proceed to S4, as shown in Figure 9.
[0059] S4. Deposit a dielectric layer 300 on the wafer surface to fill the gap between the groove and the compound Hall element 400, thereby completing the chip surface planarization operation and proceeding to S5, as shown in Figure 10, where the dielectric layer 300 is SiO2.
[0060] S5. Perform the CONTACT manufacturing process, followed by the interconnect manufacturing process. The interconnect manufacturing process includes the fabrication of VIA structure 600, METAL structure 600, output signal pad PAD 700, and passivation layer structure to realize the signal connection between the compound Hall element 400 and the conditioning circuit of the silicon-based signal conditioning chip 100, and finally obtain the compound Hall integrated chip.
[0061] It should be noted that the organic adhesive 220 serves to temporarily fix the compound Hall element 400. By depositing the dielectric layer 300 on the wafer surface via S4, the compound Hall element 400 can be completely fixed to the wafer, forming an integral structure with the silicon-based signal conditioning chip 100. The width of the first groove structure 200 increases sequentially from the bottom to the opening direction, meaning that the cross-sectional shape of the first groove structure 200 is an inverted trapezoid, and the entire first groove structure is inverted trapezoidal in shape. The advantage of this structure is that it facilitates the uniform deposition of the dielectric layer 300. The compound substrate 800 of the compound Hall element 400 can be made of materials such as GaAs, InSb, or InAs.
[0062] The compound Hall element 400 of the present invention is prepared by pre-preparing a Hall chip wafer (including Hall functional area and interconnects) of a compound substrate 800 and completing thinning and cutting, so that each compound Hall element 400 is separated from each other, and then the individual compound Hall element 400 is picked up and assembled into the groove.
[0063] In S4 of this invention, a dielectric layer 300 is deposited to fill the gap between the groove and the compound Hall element 400, and then deposition continues to form a planarized structure surface on the surface of the first integrated chip.
[0064] S2.3 Specifically, an organic adhesive 220 is spin-coated onto the inner surface wafer of the second groove structure obtained in S2.2, and then the organic adhesive 220 at the bottom of the second groove structure is retained by exposure and development to obtain the groove.
[0065] It should be noted that the METAL structure 600 is a circuit trace structure in the X / Y direction, and the VIA structure 600 is a pillar connection structure in the Z direction. Both the METAL structure 600 and VIA structure 600 comply with IC circuit design specifications. The METAL structure 600 and VIA structure 600 are internal interconnections between Hall element pads and signal conditioning pads. The fabrication methods of the METAL structure 600 and VIA structure 600 are common knowledge in the art and should be known to those skilled in the art, so they will not be described in detail here. The output signal pad PAD700 is an externally exposed dielectric layer 300. The output signal pad PAD700 is used for subsequent package leads, and the fabrication method of the output signal pad PAD700 is common knowledge in the art and should be known to those skilled in the art, so it will not be described in detail here.
[0066] The compound Hall effect integrated chip obtained by this invention can be used in subsequent packaging processes after thinning and dicing. The thickness after thinning is generally 150μm~300μm. Substrate thinning at 800 is also common knowledge in the art and should be known by those skilled in the art, so it will not be described in detail here.
[0067] This method for fabricating a compound Hall effect integrated chip innovatively introduces a structure and process between the device manufacturing process and the control manufacturing process, achieving chip-level integration of the compound Hall effect sensor and silicon-based signal conditioning circuitry, thus solving the current challenge of heterogeneous integration of compound Hall effect sensors and silicon-based conditioning circuitry on the same wafer. This method integrates the compound Hall effect sensor 400 and the silicon-based signal conditioning chip 100 together to form a single compound Hall effect integrated chip, offering performance advantages such as sensitivity and temperature drift characteristics compared to single-chip silicon-based Hall effect sensors. Furthermore, compared to the existing dual-chip packaging method involving the compound Hall effect sensor 400 and the silicon-based signal conditioning circuitry, this invention offers higher integration, higher precision, and higher reliability. This invention provides wafer integration space for the compound Hall effect sensor by forming a recess in the silicon-based signal conditioning chip 100, enabling wafer integration of the compound Hall effect sensor and the silicon-based signal conditioning circuitry. Example 2
[0068] A method for fabricating a compound Hall effect integrated chip, with other features the same as in Example 1, except that: both the dielectric thin film 210 and the dielectric layer 300 are SiO2. The dielectric thin film 210 has a thickness of 2 nm, and the organic adhesive 220 has a thickness of 2 nm. The bottom width of the first groove structure 200 is 150 μm, the opening width of the first groove structure 200 is 250 μm, and the depth of the first groove structure 200 is 6 μm.
[0069] The dimensions of the first groove structure 200 in this embodiment can facilitate the compound Hall element 400 while reducing the gap between the groove and the compound Hall element 400. Example 3
[0070] A compound Hall integrated chip is prepared using the preparation method of the compound Hall integrated chip in Example 1 or 2.
[0071] This compound Hall effect integrated chip combines a compound Hall element 400 and a silicon-based signal conditioning chip 100 into a single compound Hall effect integrated chip, offering performance advantages such as sensitivity and temperature characteristics compared to a single-chip silicon-based Hall effect chip. Furthermore, compared to the existing dual-chip packaging method involving the compound Hall element 400 and the silicon-based signal conditioning circuit, this invention offers higher integration, higher precision, and higher reliability. This invention achieves wafer integration of the compound Hall effect chip and the silicon-based signal conditioning circuit by forming a recess in the silicon-based signal conditioning chip 100, providing wafer space for the compound Hall effect chip.
[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a compound Hall effect integrated chip, characterized in that: After the device manufacturing process is completed, the wafer surface of the silicon-based signal conditioning chip is formed with photolithography and etching to form grooves. Dielectric thin films are deposited and organic adhesives are coated in the grooves. Then, the compound Hall element is assembled into the inside of the groove. The groove is then filled with a dielectric layer. Finally, the signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip is realized by using CONTACT, VIA and interconnects, and finally the compound Hall integrated chip is obtained. The process is as follows: S1. Perform device manufacturing processes on the wafer to obtain a silicon-based signal conditioning chip; S2. Grooves are formed on the wafer surface of the silicon-based signal conditioning chip obtained in S1 by photolithography and etching, and a dielectric layer is deposited and an organic adhesive is coated in the grooves. S3. Assemble the compound Hall element into the groove obtained in S2, and proceed to S4; S4. Deposit a dielectric layer on the wafer surface to fill the gap between the groove and the compound Hall element, thereby completing the chip surface planarization operation and proceeding to S5. S5. Perform the CONTACT manufacturing process, followed by the interconnect manufacturing process. The interconnect manufacturing process includes the fabrication of VIA structure, METAL structure, output signal pad PAD and passivation layer structure to realize the signal connection between the compound Hall element and the conditioning circuit of the silicon-based signal conditioning chip, and finally obtain the compound Hall integrated chip.
2. The method for fabricating a compound Hall integrated chip according to claim 1, characterized in that, S2 is performed by the following steps: S2.
1. Perform photolithography and etching on the S1 silicon-based signal conditioning chip to obtain the first groove structure; S2.
2. Deposit a dielectric thin film on the inner surface of the first groove structure obtained in S2.1 to obtain the second groove structure; S2.
3. Apply organic adhesive to the bottom of the second groove structure obtained in S2.2 to obtain the groove.
3. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: The width of the first groove structure increases sequentially from the bottom to the opening direction, and the cross-sectional shape of the first groove structure is an inverted trapezoid.
4. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: Specifically, S2.3 involves spin-coating an organic adhesive onto the inner surface wafer of the second groove structure obtained in S2.2, and then using exposure and development to retain only the organic adhesive at the bottom of the second groove structure, thus obtaining the groove.
5. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: The bottom width of the first groove structure is greater than the maximum length of the compound Hall element.
6. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: The bottom width of the first groove structure is 100μm to 250μm; The opening width of the first groove structure is 150μm to 300μm; The depth of the first groove structure is 1μm to 10μm.
7. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: The thickness of the dielectric film is 1 nm to 5 nm.
8. The method for fabricating a compound Hall integrated chip according to claim 2, characterized in that: The thickness of the organic adhesive is 1 nm to 5 nm; The silicon-based signal conditioning chip is provided with a substrate and functional module elements that constitute a silicon-based signal conditioning circuit.
9. A compound Hall effect integrated chip, characterized in that: It was prepared using the method for preparing the compound Hall integrated chip according to any one of claims 1 to 8.