Power on / off control circuit and multi-power supply system

Abstract

The present application relates to the field of power control, and provides a power on / off control circuit and a multi-power supply system. The power on / off control circuit comprises a first control sub-circuit, an input end of the first control sub-circuit being connected to a first power supply, an output end of the first control sub-circuit being connected to an electrical module, and a power supply end of the first control sub-circuit being connected to a second power supply. The first control sub-circuit is turned on to operate when the second power supply is powered on, and the first control sub-circuit is used to, on the basis of an output voltage of the first power supply, control the electrical module to operate. A reset signal is generated by comparing values of first power supplies, and, depending on whether the second power supply is powered on, it is determined whether the reset signal is transmitted to the electrical module. When the electrical module receives the reset signal, a power on / off state of the first power supply can be known, and the electrical module is controlled when the first power supply is first powered off and then powered on.

Description

Power-on / off control circuits and multiple power supply systems

[0001] This application claims priority to Chinese Patent Application No. 202411578067.3, filed on November 6, 2024, entitled "Power-on / off control circuit and multi-power supply system", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of power control, and more particularly to a power-on / off control circuit and a multi-power supply system. Background Technology

[0003] Power-on and power-off sequencing ensures the normal and stable startup and shutdown of a chip, significantly impacting its normal operation, stability, and lifespan. During power-on, each module needs to connect to power and signals in a specific sequence to guarantee the overall stability and normal operation of the chip. Similarly, during power-off, each module needs to shut down in a specific sequence to prevent data loss and system crashes. With the continuous development of electronic hardware systems, multi-power supply systems are increasingly powering various modules of a chip. These systems require a very complex sequencing mechanism to control the power-on and power-off of each power source sequentially. For example, in a chip system with memory and digital modules, the power supplies for the two modules are different, but the normal operation of the digital module requires the cooperation of the memory module. Therefore, to ensure normal chip operation, the memory and digital modules must be powered on and off according to a prescribed sequence. Failure to follow this sequence will result in timing errors in the memory module, causing malfunctions in the digital module and core, and even affecting the overall safety performance of the chip. Summary of the Invention

[0004] This application provides a power-on / off control circuit and a multi-power supply system to solve the power-on / off timing problem.

[0005] In a first aspect, this application provides a power-on / off control circuit, the circuit including a first control sub-circuit (201), the input terminal of the first control sub-circuit (201) is connected to a first power supply (101), the output terminal of the first control sub-circuit (201) is connected to a power module (301), and the power supply terminal of the first control sub-circuit (201) is connected to a second power supply (102).

[0006] The first control sub-circuit (201) is turned on when the second power supply (102) is powered on. The first control sub-circuit (201) is used to control the power module (301) to work based on the output voltage of the first power supply (101).

[0007] In one embodiment, the power management module of the first power supply (101) includes a reset port (103), which is connected to the first power supply (101) through a first resistor (R1). The reset port (103) outputs an external reset signal based on the output voltage of the first power supply (101).

[0008] The input terminal of the first control sub-circuit (201) is connected to the reset port (103). The first control sub-circuit (201) is used to control the power module (301) to work according to the external reset signal.

[0009] In one embodiment, the first control sub-circuit (201) includes a voltage comparison module (2011), the input terminal of which is connected to the reset port (103), and the output terminal of which is connected to the power consumption module (301).

[0010] The voltage comparison module (2011) is turned on when the second power supply (102) is powered on. The voltage comparison module (2011) is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power module (301).

[0011] In one embodiment, the voltage comparison module (2011) includes a trigger.

[0012] In one embodiment, the trigger is a Schmitt trigger.

[0013] In one embodiment, the first control sub-circuit (201) further includes an isolation module (2012), the input terminal of which is connected to the reset port (103), and the output terminal of which is connected to the input terminal of the voltage comparison module (2011).

[0014] The isolation module (2012) is used to isolate the reset port (103) and the power supply module (301).

[0015] In one embodiment, the isolation module (2012) includes a second resistor (R2).

[0016] In one embodiment, the first control sub-circuit (201) further includes a voltage processing module (2013), the input terminal of which is connected to the output terminal of the voltage comparison module (2011), and the output terminal of which is connected to the power consumption module (301).

[0017] The voltage processing module (2013) is used to process the reference reset signal output by the voltage comparison module (2011) and output the target reset signal to drive the power module (301).

[0018] In one embodiment, the voltage processing module (2013) includes a voltage conversion unit (1301), the input terminal of which is connected to the output terminal of the voltage comparison module (2011), and the output terminal of which is connected to the power consumption module (301).

[0019] The voltage conversion unit (1201) is used to convert the power domain of the reference reset signal from the first power domain to the second power domain and output the first target reset signal to drive the power module (301).

[0020] In one embodiment, the voltage processing module (2013) further includes a drive processing unit (1302), the input terminal of which is connected to the output terminal of the voltage conversion unit (1301), and the output terminal of which is connected to the power consumption module (301).

[0021] The drive processing unit (1302) is used to amplify the first target reset signal output by the voltage conversion unit (1301) and output the second target reset signal to drive the power module (301).

[0022] In one embodiment, the drive processing unit (1302) includes a buffer amplifier.

[0023] In one embodiment, the drive processing unit (1302) further includes a filter subunit, the input of which is connected to the output of the buffer amplifier, and the output of which is connected to the power module (301).

[0024] In one embodiment, the filtering subunit includes a low-pass filter (1001) and at least one flip-flop (1002); the low-pass filter (1001) and at least one flip-flop (1002) are connected in sequence; the output terminal of the low-pass filter (1001) and the output terminal of the at least one flip-flop (1002) are connected to the power module (301).

[0025] In one embodiment, the trigger is a D trigger.

[0026] In one embodiment, the power-on / off control circuit further includes a second control sub-circuit (202), the input terminal of the second control sub-circuit (202) is connected to the first power supply (101), the output terminal of the second control sub-circuit (202) is connected to the power module (301), and the power supply terminal of the second control sub-circuit (202) is connected to the first power supply (101).

[0027] The second control sub-circuit (202) is used to control the operation of the power module (301) based on the output voltage of the first power supply (101).

[0028] In one embodiment, the second control sub-circuit (202) includes a power-on reset module (2021), the input terminal and power supply terminal of the power-on reset module (2021) are connected to the first power supply (101), and the output terminal of the power-on reset module (2021) is connected to the power consumption module (301).

[0029] The power-on reset module (2021) is used to send a power-on reset signal to the power consumption module (301) based on the boost process of the first power supply (101).

[0030] In one embodiment, the second control sub-circuit (202) further includes a power-down reset module (2022), the input terminal and power supply terminal of the power-down reset module (2022) are connected to the first power supply (101), and the output terminal of the power-down reset module (2022) is connected to the power consumption module (301);

[0031] The power-down reset module (2022) is used to send an undervoltage reset signal to the power consumption module (301) based on the step-down process of the first power supply (101).

[0032] In one embodiment, the second control sub-circuit (202) is further configured to trigger the power-on reset signal or the undervoltage reset signal after a preset time period after detecting that the voltage of the first power supply (101) meets the triggering conditions of the power-on reset signal or the undervoltage reset signal.

[0033] Secondly, this application provides a multi-power supply system, which includes a first power supply (101), a second power supply (102), and a power management module (103). The power management module includes the power-on / off control circuit as described in the first aspect embodiment.

[0034] This application provides a power-on / off control circuit and a multi-power supply system. The circuit includes a first control sub-circuit, whose input terminal is connected to a first power supply, output terminal is connected to a power-consuming module, and power supply terminal is connected to a second power supply. The first control sub-circuit operates when the second power supply is powered on. The first control sub-circuit controls the operation of the power-consuming module based on the output voltage of the first power supply. A reset signal is generated based on the magnitude of the first power supply voltage. Whether the second power supply is powered on determines whether the reset signal can be transmitted to the power-consuming module. When the power-consuming module receives the reset signal, it can know the power-on / off state of the first power supply, thus enabling control of the power-consuming module when the first power supply is powered on or off. Attached Figure Description

[0035] Figure 1 is a structural diagram of a multi-power supply system provided in one embodiment;

[0036] Figure 2 is a schematic diagram of the power-on / off control timing provided in one embodiment;

[0037] Figure 3 is a schematic diagram of the power-on / off control circuit provided in one embodiment;

[0038] Figure 4 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0039] Figure 5 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0040] Figure 6 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0041] Figure 7 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0042] Figure 8 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0043] Figure 9 is a schematic diagram of the structure of the first control sub-circuit provided in one embodiment;

[0044] Figure 10 is a schematic diagram of the structure of a filter subunit provided in one embodiment;

[0045] Figure 11 is a schematic diagram of the power-on / off control circuit provided in one embodiment;

[0046] Figure 12 is a schematic diagram of the power-on / off control circuit provided in one embodiment;

[0047] Figure 13 is a schematic diagram of the power-on / off control circuit provided in one embodiment;

[0048] Figure 14 is a circuit diagram of a first control sub-circuit provided in one embodiment;

[0049] Figure 15 is a circuit diagram of a filter subunit provided in one embodiment;

[0050] Figure 16 is a schematic diagram of the power-on / off control timing provided in one embodiment.

[0051] Reference numerals: 101: First power supply; 102: Second power supply; 103: Reset port; 201: First control sub-circuit; 2011: Voltage comparison module; 2012: Isolation module; 2013: Voltage processing module; 1301: Voltage conversion unit; 1302: Drive processing unit; 1001: Low-pass filter; 1002: Trigger; 202: Second control sub-circuit; 2021: Power-on reset module; 2022: Power-off reset module; 301: Power consumption module. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish first information from another type of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0054] First, let me explain the terms used in this application:

[0055] VCC: First power supply unit; AVCC: Analog module power supply voltage; IOVCC: Port module power supply voltage; VD11: Second power supply unit; VD33: Third power supply unit; SARADC: Successive approximation analog-to-digital converter; DSADC: Δ-Σ analog-to-digital converter; CMP: Comparator; PORT: Port; LDO: Low-dropout regulator; POR: Power-On Reset; BOR: Brown-out Reset; POR_N: POR reset pin; BOR_N: BOR reset pin; RST_N: External reset pin; ESD: Electrostatic discharge; MOS: Metal-Oxide-Semiconductor Field-Effect Transistor; Latch up: Latch-up effect.

[0056] Power-on and power-off sequences ensure the normal and stable startup and shutdown of a chip, significantly impacting its normal operation, stability, and lifespan. During power-on, each module needs to be connected to power and signals in a specific order to guarantee the overall stability and normal operation of the chip. Similarly, during power-off, each module needs to be shut down in a specific sequence to prevent data loss and system crashes.

[0057] With the continuous development of electronic hardware systems, multi-power supply systems are increasingly used to power various modules of a chip. These systems require a very complex timing sequence to control the power-on and power-off of each power supply sequentially. As shown in Figure 1, the multi-power supply system powers various functional modules of the chip. The multi-power supply system includes:

[0058] First power supply unit: supplies power to the analog modules (including but not limited to SARADC, DSADC and CMP) and PORT. For ease of explanation, this embodiment is represented by the symbol VCC.

[0059] The third power supply unit is generated by the input from the third power supply unit and the LDO. The LDO outputs the third power supply unit and powers the erase and write functions of the storage module (including but not limited to the flash memory module). In this embodiment, it is represented by the symbol VD33.

[0060] The second power supply unit supplies power to the digital module and the clock module, and supplies power to the digital logic of the storage module (including but not limited to the FLASH module). In this embodiment, it is represented by the symbol VD11.

[0061] In the actual operation of the chip, VCC and VD11 have a timing requirement. During power-up, VCC must be powered on first to VD11. VCC_Min After the minimum operating voltage of VCC is reached, VD11 will start powering on. As shown in the timing diagram in Figure 2: During the VCC power-on process, the power-on reset POR provides a low level to keep the digital module in a reset state until the VCC power-on threshold V is detected. POR_N When the POR reset pin POR_N_VCC goes high, the digital module starts working. During power-down, VD11 drops to V... VD11_Min (The digital module cannot operate below the minimum voltage of analog circuit devices) VCC only starts to lose power when it is below this threshold. Specifically: power is lost when the undervoltage threshold VCC is detected. BOR_N Pulling the BOR reset pin BOR_N_VCC low resets the digital module.

[0062] If the power-on sequence is not followed during the above process, i.e., VD11 is powered on first and VCC is not, the POR reset will be ineffective because the POR circuit only detects the VCC signal. The digital module will then be unable to reset, which may lead to the following risks:

[0063] (1) Timing error in storage module (including but not limited to FLASH module). If the user performs FLASH erase / write operation, VD11 will not be powered on properly due to VCC not being input, which will affect the FLASH data. Therefore, VCC must be powered on first.

[0064] (2) Digital module malfunction. The operation of the digital module requires the normal operation of the storage module. If the storage module malfunctions, it will cause chip program errors. Therefore, VCC must be powered on first.

[0065] (3) If the input voltage is too high, it will damage the chip. The chip's power-on voltage detection requires a reference voltage provided by the bandgap reference. The reference voltage is input from VCC, so VCC must be powered on first.

[0066] Similarly, if the power is not cut off according to the specified timing, i.e., VCC drops off first while VD11 does not, since the BOR circuit only detects the VCC signal, the power will drop to the undervoltage threshold V. BOR_N Previously, BOR reset was ineffective and could not reset the digital module, which posed the following risk: kernel malfunction. The kernel operating voltage is provided by VD11, so VD11 must be powered down first.

[0067] In the above scheme, failure to power on or off according to regulations will lead to timing errors in the storage module, causing abnormal operation of the digital module and core, and even affecting the safety performance of the entire chip.

[0068] To address the technical problems existing in the above solutions, this application provides a power-on / off control circuit, as shown in FIG3. The circuit includes a first control sub-circuit 201, the input terminal of the first control sub-circuit 201 is connected to the first power supply 101, the output terminal of the first control sub-circuit 201 is connected to the power module 301, and the power supply terminal of the first control sub-circuit 201 is connected to the second power supply 102.

[0069] The first control sub-circuit 201 is turned on when the second power supply 102 is powered on. The first control sub-circuit 201 is used to control the operation of the power module 301 based on the output voltage of the first power supply 101.

[0070] The output terminal of the first control sub-circuit 201 is connected to the reset pin of the power module 301. In the circuit provided in this embodiment, the second power supply 102 provides power to the first control sub-circuit 201 so that the first control sub-circuit 201 can work. That is, the first control sub-circuit 201 can only receive the input from the first power supply 101 when the second power supply 102 is powered on, and outputs a reset signal to control the power module 301 according to the output voltage of the first power supply 101.

[0071] The first power supply 101 is connected to the first control sub-circuit 201. When the first power supply 101 has an output, the first control sub-circuit 201 detects and processes the output voltage of the first power supply 101. Based on the magnitude of the output voltage of the first power supply 101, a reset signal is sent to the power consumption module 301 to inform the power consumption module 301 of the power-on and power-off status of the first power supply 101, thereby controlling the working state of the power consumption module 301.

[0072] The power supply terminal of the power module 301 is connected to the second power supply 102. The power module 301 can only receive the reset signal sent by the first control sub-circuit 201 when the second power supply 102 is powered on. When the second power supply 102 is powered on, the operating state of the power module 301 is adjusted according to the reset signal received at the reset pin. For example, if the reset signal sent by the first control sub-circuit 201 is active low, then when the reset signal is low, the power module 301 is in a reset state. At this time, even if the second power supply 102 supplies power to the power module 301, the power module 301 starts but does not begin working.

[0073] Similarly, when the first power supply 101 and the second power supply 102 are powered off, if the first power supply 101 is powered off first, a reset signal will be sent to the power module 301 to control the power module 301 to be in a reset state. Then, when the second power supply is powered off, it will not affect the normal operation of the power module 301.

[0074] Specifically, in one embodiment, the first control sub-circuit 201 has a voltage comparison function. By detecting and judging the voltage output by the first power supply 101, it determines whether the first power supply 101 has reached the power-on threshold or dropped to the undervoltage threshold, thereby outputting a reset signal to control the state of the power module 301. For example, the first control sub-circuit 201 includes a voltage comparator. When it detects that the voltage output by the first power supply 101 is less than the first threshold, it outputs a low level, and the power module 301 is in a reset state. When it detects that the voltage output by the first power supply 101 is not less than the first threshold, it outputs a high level, and the power module 301 operates normally.

[0075] In the circuit provided in the above embodiment, the circuit includes a first control sub-circuit. The input terminal of the first control sub-circuit is connected to a first power supply, the output terminal of the first control sub-circuit is connected to a power-consuming module, and the power supply terminal of the first control sub-circuit is connected to a second power supply. The first control sub-circuit operates when the second power supply is powered on. The first control sub-circuit is used to control the operation of the power-consuming module based on the output voltage of the first power supply. A reset signal is generated based on the magnitude of the first power supply. Whether the second power supply is powered on or off determines whether the reset signal can be transmitted to the power-consuming module. When the power-consuming module receives the reset signal, it can know the power-on / off state of the first power supply, thus realizing the control of the power-consuming module when the first power supply is powered on or off.

[0076] In one embodiment, as shown in FIG4, the power management module of the first power supply 101 includes a reset port 103. The reset port 103 is connected to the first power supply 101 through a first resistor R1. The reset port 103 outputs an external reset signal based on the output voltage of the first power supply 101.

[0077] The input terminal of the first control sub-circuit 201 is connected to the reset port 103. The first control sub-circuit 201 is used to control the power module 301 to work according to the external reset signal.

[0078] The power management module is used to implement power monitoring and management functions. When the power management module detects power instability, it sends a reset signal to the external reset RST pin of the power-consuming module. Reset port 103 refers to the port on the power management module that outputs the reset signal. Under normal circumstances, power-consuming modules 301, such as digital modules, microcontrollers, and processors, all have an RST pin for receiving reset signals. Taking a microcontroller as an example, its RST pin is usually connected to the power management module or a manual reset button. When the power supply voltage is unstable or the user presses the reset button, the RST pin receives a reset signal, thereby resetting the microcontroller. During the reset process, the microcontroller's internal registers and status information are cleared, and the program counter is set to its initial position, ensuring that the microcontroller can start operating from a known and stable state.

[0079] In this embodiment, the reset port 103 is a low-level reset pin, connected to the first power supply 101 via a first resistor R1. This allows the reset port 103 to output an external reset signal to the external reset pin of the power module 301 under the control of the first power supply 101. Specifically, the first resistor R1 can be a pull-up resistor. The initial state of the reset port 103 is low, provided by the first power supply 101. Through the pull-up resistor, the reset port 103 outputs a high / low level depending on the power supply status of the first power supply 101, i.e., whether the first power supply 101 is powered on.

[0080] The value of the first resistor R1 needs to be selected based on the specific requirements of the system. An excessively large resistance may cause the reset signal to rise too slowly, affecting the reset effect; an excessively small resistance may increase power consumption. Typically, the value of the first resistor R1 is chosen to be between several hundred ohms and several thousand ohms.

[0081] In the circuit provided in the above embodiments, the control of the power-consuming module when the second power supply is powered on is realized through the existing reset port without adding external pins and ports.

[0082] In one embodiment, as shown in FIG5, the first control sub-circuit 201 includes a voltage comparison module 2011, the input terminal of the voltage comparison module 2011 is connected to the reset port 103, and the output terminal of the voltage comparison module 2011 is connected to the power consumption module 301.

[0083] The voltage comparison module 2011 is turned on when the second power supply 102 is powered on. The voltage comparison module 2011 is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power module 301.

[0084] It is understood that the reset port 103 is connected to the first power supply 101 through the first resistor R1. The external reset signal output based on the magnitude of the first power supply 101 will fluctuate due to the fluctuation of the first power supply 101. Therefore, the external reset signal directly output by the reset port 103 has a certain degree of fluctuation and the signal waveform is not very regular. This will cause the power module 301 to switch repeatedly between two states in a short period of time, affecting the normal operation and safety of the power module 301.

[0085] The voltage comparator module 2011 filters the external reset signal, outputting high / low levels to handle glitches in the signal by logically determining irregularities. The voltage comparator module 2011 can be a circuit with filtering capabilities, or any circuit or device with voltage comparison functionality. It removes glitches by comparing voltages, such as voltage comparators or flip-flops. The flip-flop can be a Schmitt trigger. A Schmitt trigger can logically determine the initial input signal's glitches using a comparator, outputting stable high or low levels.

[0086] In the circuit provided in the above embodiment, the external reset signal is processed by a voltage comparison module to remove signal glitches and improve the accuracy of the external reset signal.

[0087] In one embodiment, as shown in FIG6, the first control sub-circuit 201 further includes an isolation module 2012, the input terminal of the isolation module 2012 being connected to the reset port 103, and the output terminal of the isolation module 2012 being connected to the input terminal of the voltage comparison module 2011.

[0088] The isolation module 2012 is used to isolate the reset port 103 and the power module 301.

[0089] The isolation module 2012 isolates the first power supply 101 from the circuit components in the first control sub-circuit 201, protecting the safety of the circuit components in the first control sub-circuit 201 and the power-consuming module 301. The isolation module 2012 provides short-circuit protection, overvoltage protection, undervoltage protection, and overcurrent protection. In specific implementation scenarios, a suitable isolation module 2012 is selected based on the actual conditions of the first control sub-circuit 201 and the power-consuming module 301.

[0090] For example, isolation module 2012 includes a second resistor R2. The function of the second resistor R2 is to block ESD current transients and prevent damage to the devices in power module 301.

[0091] In the circuit provided in the above embodiments, the safety of the first control sub-circuit and the power consumption module is protected by an isolation module.

[0092] In one embodiment, as shown in FIG7, the first control sub-circuit 201 further includes a voltage processing module 2013, the input terminal of the voltage processing module 2013 is connected to the output terminal of the voltage comparison module 2011, and the output terminal of the voltage processing module 2013 is connected to the power consumption module 301.

[0093] The voltage processing module 2013 is used to process the reference reset signal output by the voltage comparison module 2011 and output the reference reset signal to drive the power module 301.

[0094] The external reset signal is provided by the reset port 103. The external reset signal provided is a signal within the power domain of the first power supply 101, while the power module 301 operates within the power domain of the second power supply 102. Therefore, the external reset signal cannot directly drive the power module 301. The external reset signal needs to be processed to obtain a reference reset signal that can drive the power module 301.

[0095] The processing of the external reset signal is completed by the voltage processing module 2013. The voltage processing module 2013 performs a series of processing on the external reset signal and then outputs a reference reset signal to drive the power supply module 301. The processing of the external reset signal by the voltage processing module 2013 includes, but is not limited to, processing of the voltage domain, processing of the voltage magnitude, and processing of the driving duration.

[0096] In one embodiment, as shown in FIG8, the voltage processing module 2013 includes a voltage conversion unit 1301, the input terminal of the voltage conversion unit 1301 is connected to the output terminal of the voltage comparison module 2011, and the output terminal of the voltage conversion unit 1301 is connected to the power consumption module 301.

[0097] The voltage conversion unit 1301 is used to convert the power domain of the reference reset signal from the first power domain to the second power domain, and output the first target reset signal to drive the power module 301.

[0098] The first power domain is the power domain corresponding to the first power supply 101, and the second power domain is the power domain corresponding to the second power supply 102. A voltage conversion unit converts the power domain of the reference reset signal from the first power domain to the second power domain, enabling the output first target reset signal to drive the power consumption module 301. The voltage conversion unit 1301 may include a DC-DC converter and an LDO (low dropout linear regulator).

[0099] The voltage conversion unit 1301 only processes the reference reset signal in the power domain of the signal. If the output first target reset signal is to be able to continuously and stably drive the power module 301, the signal driving capability needs to be processed.

[0100] In one embodiment, as shown in FIG9, the voltage processing module 2013 further includes a drive processing unit 1302, the input terminal of the drive processing unit 1302 is connected to the output terminal of the voltage conversion unit 1301, and the output terminal of the drive processing unit 1302 is connected to the power consumption module 301.

[0101] The drive processing unit 1302 is used to amplify the first target signal output by the voltage conversion unit 1301 and output a second target reset signal to drive the power module 301.

[0102] The drive processing unit 1302 includes a buffer amplifier. The buffer amplifier can amplify and output the voltage of the input first target reset signal, thereby improving the driving capability and driving duration of the output second target reset signal, without changing the waveform characteristics of the first target reset signal.

[0103] The drive processing unit 1302 also includes a filter subunit. The input terminal of the filter subunit is connected to the output terminal of the buffer amplifier, and the output terminal of the filter subunit is connected to the power module 301.

[0104] The filtering subunit is used to filter the signal output by the drive processing unit 1302. In one embodiment, as shown in FIG10, the filtering subunit includes a low-pass filter 1001 and at least one trigger 1002; the low-pass filter 1001 and at least one trigger 1002 are connected in sequence; the output terminal of the low-pass filter 1001 and the output terminal of the at least one trigger 1002 are connected to the power module 301.

[0105] The high-frequency components of the signal are filtered out by a low-pass filter 1001. Then, based on the characteristics of the flip-flops 1002, multiple flip-flops 1002 are connected sequentially, and their outputs are connected to the power module 301 to provide a continuous second target reset signal to the power module 301. For example, as shown in Figure 11, the filtering subunit includes three flip-flops. If one flip-flop can hold the first target reset signal for t, then the three flip-flops can hold the first target reset signal for an additional 3t, and the generated second target reset signal is held for 3t.

[0106] The trigger is a D trigger. The output of the D trigger is also connected to the power module 301 via a frequency converter.

[0107] For example, a filtering subunit is provided, which includes a low-pass filter and three D flip-flops. Specifically, the low-pass filter circuit consists of a MOSFET, a third resistor R3, and a capacitor C. The MOSFET amplifies and controls the signal flow, while the third resistor R3 and capacitor C form an RC low-pass filter to filter out high-frequency signals.

[0108] Each of the three D flip-flops integrates two inverters. This design does not affect the signal phase while enhancing the signal driving capability. The D flip-flops are used for data transmission and delay circuits. On the rising edge of the clock signal, if the input of the D flip-flop is high, the output is also high; if the input of the D flip-flop is low, the output is also low. The signal after low-pass filtering by the MOS transistors is output from the three D flip-flops, passes through a NAND gate and an inverter before being input to the power module 301. This design ensures that a continuous low / high level output is required to enter / release the reset state, preventing direct state switching when there are signal glitches.

[0109] The design of the drive processing unit ensures that a continuous and stable second target reset signal can be provided to the power module 301.

[0110] In one embodiment, as shown in FIG11, the power-on / off control circuit further includes a second control sub-circuit 202. The input terminal of the second control sub-circuit 202 is connected to the first power supply 101, the output terminal of the second control sub-circuit 202 is connected to the power module 301, and the power supply terminal of the second control sub-circuit 202 is connected to the first power supply 101.

[0111] The second control sub-circuit 202 is used to control the operation of the power module 301 based on the output voltage of the first power supply 101.

[0112] In the power-on / off control circuit shown in Figure 3, the reset signal provided by the first control sub-circuit 201 is determined by the magnitudes of the first power supply 101 and the second power supply 102. When the second power supply 102 is powered on, the first power supply 101 is powered on, and the first control sub-circuit 201 provides a high level to enable the power module 301 to operate. When the first power supply 101 is not powered on, the first control sub-circuit 201 provides a low level to enable the power module 301 to remain in a reset state. If the second power supply 102 is not powered on, the first control sub-circuit 201 is in a non-operating state, and the power module 301 has no input signal, making it impossible to control its operating state. The power-off process is similar.

[0113] Therefore, when the first power supply 101 is powered on first and the second power supply 102 is powered on later, or when the second power supply 102 is powered off first, the second control sub-circuit 202 provides a reset signal to the power module 301 to control the working state of the power module 301.

[0114] It should be noted that since the reset signals provided by the first control sub-circuit 201 and the second control sub-circuit 202 are used in different scenarios, and only one of the two scenarios will occur, the reset signals provided by the first control sub-circuit 201 and the second control sub-circuit 202 do not have priority.

[0115] In one embodiment, as shown in FIG12, the second control sub-circuit 202 includes a power-on reset module 2021, the input terminal and power supply terminal of the power-on reset module 2021 being connected to the first power supply 101, and the output terminal of the power-on reset module 2021 being connected to the power consumption module 301.

[0116] The power-on reset module 2021 is used to send a power-on reset signal to the power consumption module 301 based on the boost process of the first power supply 101.

[0117] The power-on reset module 2021 includes a POR circuit, which provides a power-on reset signal to the power-consuming module 301. When the first power supply 101 is powered on, a low-level reset signal is provided to the power-consuming module 301. After the first power supply 101 reaches the power-on threshold, a high-level signal is provided to enable the power-consuming module 301 to start working.

[0118] In one embodiment, as shown in FIG13, the second control sub-circuit 202 further includes a power-down reset module 2022, the input terminal and power supply terminal of the power-down reset module 2022 being connected to the first power supply 101, and the output terminal of the power-down reset module 2022 being connected to the power consumption module 301.

[0119] The power-down reset module 2022 is used to send an undervoltage reset signal to the power consumption module 301 based on the step-down process of the first power supply 101.

[0120] The power-down reset module 2022 includes a BOR circuit for providing an undervoltage reset signal to the power module 301. When the first power supply 101 fails, it provides a low-level reset signal to the power module 301. Upon power-down, the second power supply 102 fails first. After the voltage of the first power supply 101 drops to the threshold voltage, it provides a low-level signal to put the power module 301 into a reset state.

[0121] In the circuit provided in the above embodiments, by adding a second control sub-circuit and combining it with the first control sub-circuit, the working state of the second power module can be controlled during either the power-on or power-off sequence of the first power supply and the second power supply, thereby ensuring the safe operation of the second power module.

[0122] In one embodiment, the second control sub-circuit 202 is further configured to trigger the power-on reset signal or the undervoltage reset signal after a preset time period after detecting that the first power supply 101 meets the triggering conditions for the power-on reset signal or the undervoltage reset signal.

[0123] The triggering condition for the power-on reset signal or undervoltage reset signal is that the voltage of the first power supply 101 meets a preset condition. For example, when the power-on reset signal is triggered, the voltage of the first power supply 101 is not less than the power-on threshold. The preset duration is used to determine when the second power supply 102 reaches its operating voltage. That is, taking the power-on process as an example, the first power supply 101 is powered on first, and the second power supply 102 is powered on later. After the voltage of the first power supply 101 reaches the corresponding power-on threshold, the power-on reset signal is pulled high after a preset duration.

[0124] It should be noted that the preset duration is only a reference value. In actual applications, to ensure the normal operation of the power module 301, the voltage of the second power supply 102 needs to be detected after the preset duration. Only after the voltage of the second power supply 102 reaches the corresponding power-on threshold is the power-on reset signal adjusted.

[0125] Similarly, when the voltage of the first power supply 101 is detected to have reached the corresponding undervoltage threshold, the undervoltage reset signal is adjusted after a preset time. The preset time for the power-down process and the preset time for the power-on process are two different concepts; their values ​​can be the same or different.

[0126] In the circuit provided in the above embodiments, by setting a preset time, the reset signal is adjusted only after ensuring the stability of the first power supply and the successful power-on of the second power supply during the power-on and power-off process. This eliminates the need to adjust the target reset signal immediately when the first power supply reaches the corresponding power-on threshold or undervoltage threshold, thus avoiding miscontrol caused by the instability of the first power supply.

[0127] This application also provides a multi-power supply system, which includes a first power supply 101, a second power supply 102, and a power management module 103. The power management module includes power-on / off control circuits as mentioned in any of the above embodiments.

[0128] To better understand the solutions of the embodiments of this application, this application will be described in conjunction with the application scenario of the multi-power supply system powering the chip in Figure 1.

[0129] In the multi-power supply system shown in Figure 1, due to the relationship between the digital module and the storage module, VCC and VD11 have a strict power-on / off sequence in the power-on timing of the first power supply VCC output from the first power supply unit and the second power supply VD11 output from the second power supply unit. Using the digital module as the power-consuming module 301, and following the approach provided in this embodiment, a first control sub-circuit is added between VCC, VD11 and the digital module to provide a reset signal for the RST_N pin of the digital module.

[0130] The structure and connection relationship of the first control sub-circuit are shown in Figure 14. The isolation module of the first control sub-circuit includes the second resistor R2, the voltage comparison module includes a Schmitt trigger, and the voltage processing module includes a power domain conversion, a buffer BUF, and a filter circuit Filter.

[0131] The RST_N port is connected to the IOVCC via a first resistor R1 (40kΩ in this example). Depending on the power supply of the IOVCC to the RST_N, the RST_N outputs an external reset signal (high / low level). After VD11 reaches the operating voltage, the signal passes through a Schmitt trigger, power domain conversion, and a buffer, and is then filtered for a period of time before being sent to the digital module at a high level.

[0132] The second resistor R2 (500kΩ in this example) is used to prevent ESD current transients and thus protect the chip device.

[0133] The function of a Schmitt trigger is to use a comparator to make a logical judgment on irregular signal waveforms and output high or low levels to handle glitches in the input signal. The Schmitt trigger is powered by VD11.

[0134] In this embodiment, a power domain conversion is implemented based on a MOSFET. The function is to convert the IOVCC power domain (5V in this example) to the VD11 power domain (1.1V in this example), thereby converting the signal ground from IOVSS to VSS11 to prevent immediate damage caused by latch-up.

[0135] The function of a buffer is to amplify the voltage of the input signal and output it without changing its waveform characteristics, thereby enhancing the signal's driving capability and stability.

[0136] The filter circuit is used to ensure that the output is continuously low / high before entering / releasing the reset state, preventing the state from switching directly when there are signal glitches.

[0137] Specifically, a filtering subunit is provided as shown in Figure 15. The filtering subunit includes a MOS low-pass filter and three D flip-flops. The MOS low-pass filter circuit consists of a MOS transistor, a third resistor R3, and a capacitor C (RC = 0.5µs in this example). Among them, the MOS transistor amplifies and controls the signal flow, while the third resistor R3 and capacitor C form an RC low-pass filter to filter out high-frequency signals.

[0138] Each of the three D flip-flops integrates two inverters. This design does not affect the signal phase while enhancing the signal driving capability. The D flip-flops are used for data transmission and delay circuits. On the rising edge of the clock signal, if the D input is high, the output is also high; if the D input is low, the output is also low. The signal, after being low-pass filtered by the MOS transistor, is output from the three D flip-flops, passes through a NAND gate and an inverter before being input to the digital module. This design ensures that a continuous low / high level output is required to initiate / release the reset, preventing direct state switching when there are signal glitches.

[0139] In the above embodiment, the power-on and power-off of power supplies VCC, VD33, and VD11 are achieved through the power-on reset signal POR_N_VCC, the undervoltage reset signal BOR_N_VCC, and the external reset signal RST_N, as shown in Figure 16. Wherein, V... VCC_Typ VCC is the typical operating voltage. VD33_Typ The typical operating voltage of VD33 is V. VD11_Typ This is the typical operating voltage of VD11.

[0140] When VCC powers on first and VD11 powers on later, POR_N_VCC provides the power-on reset signal for the digital module. When VD11 powers on first and VCC powers on later, RST_N provides the power-on reset signal for the digital module. When VD11 powers off first, BOR_N_VCC provides the undervoltage reset signal for the digital module. When VCC powers off first, RST_N provides the undervoltage reset signal for the digital module.

[0141] In this example, the power supply domain of POR_N_VCC is 5V (POR_N_VCC is valid during VCC power-on) and 1.1V (sending the reset signal to the digital module). During VCC power-on, POR_N_VCC keeps the digital module in a reset state until the VCC power-on threshold VPOR_N is detected (1.82V in this example, a typical value), and the timer t is set. POR_Delay(In this example, it is 15.6ms ± 50%. 15.6ms is the typical time for VD11 to reach the operating voltage, and ± 50% is the delay caused by clock skew.) After VD11 voltage reaches 1.1V, POR_N_VCC is pulled high, and the digital module starts to work.

[0142] Similarly, when the undervoltage threshold VBOR_N of VCC is detected (2.41V in this example, the default value, digital module reset state, analog circuit state uncertain), timer t is started. BOR_Delay (In this example, it is 110.9us, excluding VCC output voltage fluctuations), BOR_N_VCC is pulled low.

[0143] The working principle of RST_N is as follows: During power-up (when VD11 has reached its operating voltage but VCC has not yet been powered on), RST_N outputs a low level to reset the digital module. Once VCC and VD11 have both been powered on, RST_N is pulled high, and the digital module begins to operate. The power-down process is similar; RST_N must be pulled low to reset the digital module before VCC and VD11 begin to power down sequentially until VD11 is completely powered down.

[0144] In this invention, RST_N resets / releases the digital module only if VD11 reaches its operating voltage. If VCC is not powered on and VD11 does not reach its operating voltage, the entire chip cannot operate and cannot be reset. RST_N reset is effective only when VD11 reaches its operating voltage.

Claims

1. A power-on / off control circuit, characterized in that, The circuit includes a first control sub-circuit (201), the input terminal of the first control sub-circuit (201) is connected to a first power supply (101), the output terminal of the first control sub-circuit (201) is connected to a power module (301), and the power supply terminal of the first control sub-circuit (201) is connected to a second power supply (102). The first control sub-circuit (201) is turned on when the second power supply (102) is powered on. The first control sub-circuit (201) is used to control the power module (301) to work based on the output voltage of the first power supply (101).

2. The circuit according to claim 1, characterized in that, The power management module of the first power supply (101) includes a reset port (103), which is connected to the first power supply (101) through a first resistor (R1). The reset port (103) outputs an external reset signal based on the output voltage of the first power supply (101). The input terminal of the first control sub-circuit (201) is connected to the reset port (103), and the first control sub-circuit (201) is used to control the power module (301) to work according to the external reset signal.

3. The circuit according to claim 2, characterized in that, The first control sub-circuit (201) includes a voltage comparison module (2011), the input terminal of which is connected to the reset port (103), and the output terminal of which is connected to the power consumption module (301). The voltage comparison module (2011) is turned on when the second power supply (102) is powered on. The voltage comparison module (2011) is used to filter the external reset signal and output a reference reset signal. The reference reset signal is used to control the working state of the power module (301).

4. The circuit according to claim 3, characterized in that, The voltage comparison module (2011) includes a trigger.

5. The circuit according to claim 4, characterized in that, The trigger is a Schmitt trigger.

6. The circuit according to claim 3, characterized in that, The first control sub-circuit (201) further includes an isolation module (2012), the input terminal of which is connected to the reset port (103), and the output terminal of which is connected to the input terminal of the voltage comparison module (2011). The isolation module (2012) is used to isolate the reset port (103) and the power module (301).

7. The circuit according to claim 6, characterized in that, The isolation module (2012) includes a second resistor (R2).

8. The circuit according to claim 6, characterized in that, The first control sub-circuit (201) further includes a voltage processing module (2013), the input terminal of which is connected to the output terminal of the voltage comparison module (2011), and the output terminal of which is connected to the power consumption module (301). The voltage processing module (2013) is used to process the reference reset signal output by the voltage comparison module (2011) and output the target reset signal to drive the power consumption module (301).

9. The circuit according to claim 8, characterized in that, The voltage processing module (2013) includes a voltage conversion unit (1301), the input terminal of which is connected to the output terminal of the voltage comparison module (2011), and the output terminal of which is connected to the power consumption module (301). The voltage conversion unit (1301) is used to convert the power domain of the reference reset signal from the first power domain to the second power domain, and output the first target reset signal to drive the power module (301).

10. The circuit according to claim 9, characterized in that, The voltage processing module (2013) further includes a drive processing unit (1302), the input terminal of which is connected to the output terminal of the voltage conversion unit (1301), and the output terminal of which is connected to the power consumption module (301). The drive processing unit (1302) is used to amplify the first target reset signal output by the voltage conversion unit (1301) and output a second target reset signal to drive the power module (301).

11. The circuit according to claim 10, characterized in that, The drive processing unit (1302) includes a buffer amplifier.

12. The circuit according to claim 11, characterized in that, The drive processing unit (1302) further includes a filter subunit, the input terminal of which is connected to the output terminal of the buffer amplifier, and the output terminal of which is connected to the power module (301).

13. The circuit according to claim 12, characterized in that, The filtering subunit includes a low-pass filter (1001) and at least one trigger (1002); the low-pass filter (1001) and the at least one trigger (1002) are connected in sequence; the output terminal of the low-pass filter (1001) and the output terminal of the at least one trigger (1002) are connected to the power module (301).

14. The circuit according to claim 13, characterized in that, The trigger is a D trigger.

15. The circuit according to claim 1, characterized in that, The power-on / off control circuit further includes a second control sub-circuit (202), the input terminal of the second control sub-circuit (202) is connected to the first power supply (101), the output terminal of the second control sub-circuit (202) is connected to the power module (301), and the power supply terminal of the second control sub-circuit (202) is connected to the first power supply (101). The second control sub-circuit (202) is used to control the operation of the power module (301) based on the output voltage of the first power supply (101).

16. The circuit according to claim 15, characterized in that, The second control sub-circuit (202) includes a power-on reset module (2021), the input terminal and power supply terminal of the power-on reset module (2021) are connected to the first power supply (101), and the output terminal of the power-on reset module (2021) is connected to the power consumption module (301). The power-on reset module (2021) is used to send a power-on reset signal to the power consumption module (301) based on the boost process of the first power supply (101).

17. The circuit according to claim 16, characterized in that, The second control sub-circuit (202) further includes a power-down reset module (2022), the input terminal and power supply terminal of the power-down reset module (2022) are connected to the first power supply (101), and the output terminal of the power-down reset module (2022) is connected to the power consumption module (301); The power-down reset module (2022) is used to send an undervoltage reset signal to the power consumption module (301) based on the voltage reduction process of the first power supply (101).

18. The circuit according to any one of claims 16-17, characterized in that, The second control sub-circuit (202) is also used to trigger the power-on reset signal or the undervoltage reset signal after a preset time period after detecting that the voltage of the first power supply (101) meets the triggering conditions of the power-on reset signal or the undervoltage reset signal.

19. A multi-power supply system, characterized in that, The system includes a first power supply (101), a second power supply (102), and a power management module (103), the power management module including the power-on / off control circuit as described in claims 1-18.

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