ΔΣ ZOOM ADC with hybrid integrator

Abstract

Zoom ADCs combine an ADC with coarse quantization and a delta-sigma ADC with fine quantization. This combination offers high energy efficiency and a high dynamic range at the same time. Besides the additional overhead of a coarse quantizing ADC, which can be an SAR ADC, the delta-sigma ADC must span about three LSBs of the coarse quantizing ADC to avoid overdriving the delta-sigma ADC. This reduces the signal-to-quantization-noise ratio (SQNR). Signal transients with rising edges that are too short can also overdrive the delta-sigma ADC. In the invention, a mixed-signal hybrid integrator is used in the delta-sigma ADC. This hybrid integrator already contains a comparator for parallel digital integration. The comparator signal is digitally filtered and fed to a window comparator, which then controls an up-down counter that represents the zoom offset. This zoom offset is then DA-converted and fed to the analog summation point of the delta-sigma modulator to realize the zoom function. The digital zoom offset is filtered and delayed before being added to the output of the delta-sigma modulator's decimation filter.

Description

[0001] AZ ZOOM ADC WITH HYBRID INTEGRATOR

[0002] DESCRIPTION

[0003] Technical field

[0004] Zoom ADCs (Analog-to-digital converter) combine an ADC with coarse quantization and a deltasigma ADC with fine quantization. This combination offers high energy efficiency and a high dynamic range at the same time. Besides the additional overhead of a coarse quantizing ADC, which can be an SAR ADC, the delta-sigma ADC must span about three LSBs (Least Significant Bit) of the coarse quantizing ADC to avoid overdriving the delta-sigma ADC. This reduces the signal-to-quantization-noise ratio (SQNR). Signal transients with rising edges that are too short can also overdrive the delta-sigma ADC. In the invention, a mixed-signal hybrid integrator is used in the delta-sigma ADC. This hybrid integrator already contains a comparator for parallel digital integration. The comparator signal is digitally filtered and fed to a window comparator, which then controls an up-down counter that represents the zoom offset. This zoom offset is then DA- converted and fed to the analog summation point of the delta-sigma modulator to realize the zoom function. The digital zoom offset is filtered and delayed before being added to the output of the delta-sigma modulator's decimation filter.

[0005] Background and prior art

[0006] Analog-to-digital converters (ADCs) are required to have a high dynamic range (DR), high energy efficiency (figure of merit) and a small chip area. Zoom ADCs are a particularly suitable choice for medium frequency ranges, as is the case for audio applications, for example. An overview of the current state of development of zoom ADCs is given in [1], for example. SAR ADCs (SAR: Successive Approximation Register) are usually cited as ADCs with coarse resolution, but flash ADCs can also be used [2],

[0007] A SAR ADC quantizes the input signal in broad increments. The digital value resulting from this coarse quantization is usually denoted as k. Fine quantization is performed using a sigma-delta modulator. An input signal entering the modulator is processed through a loop filter before being sent to a clocked comparator. The comparator output is computed alongside the coarse quantization value k which is then converted to a digital-analog signal (DAC) and subtracted from the input signal.

[0008] This operation, combining the DAC with the coarse quantization value k, shifts the input to a range suitable for the sigma-delta modulator. To maintain stability in the modulator loop, the magnitude must be less than that of the analog representation of allowing the feedback loop to stabilize the input signal around zero. The comparator output is then processed through a decimation filter to yield a digital output with a n-bit resolution. Sine filters are commonly used for decimation. To derive the final digital value that represents an input variable (any analog value), the value k is added to an output signal of the delta-sigma modulator D OUT.

[0009] In practical zoom ADC implementations, the delay from k to the output needs to be aligned with the delay of both the modulator and the decimation filter, which is not detailed here for simplicity. A significant drawback of the zoom ADC is that the analog representation of a signal which aligns with the DAC reference voltage of the delta-sigma modulator, must exceed one quantization step of the coarse ADC by a factor M, known as the overranging factor. This requirement arises because the SAR ADC takes multiple clock cycles to update its digital value, necessitating that the delta-sigma modulator’s maximum operating range always surpass one quantization step of the SAR ADC. To also address potential non-linearities of the SAR ADC while keeping the oversampling ratio (OSR) manageable with the decimation filter, overranging factors up to 5 are recommended [3], However, this overranging can diminish the signal-to-quantization-noise ratio (SQNR), ultimately impacting the overall system’s resolution-to-power consumption ratio.

[0010] Another significant limitation of the zoom ADC is its susceptibility to interference signals outside the signal band. The SAR ADC needs multiple clock pulses to determine a new value k and subsequently adjusts an input signal the delta-sigma modulator to be less than the reference voltage. Consequently, rapid transients in the input signal can cause the signal to exceed the reference voltage, leading to instability in the modulator’s operation. This issue is particularly evident when the transient crosses the modulator’s reference voltage range quicker than the SAR ADC can complete its conversion. One proposed solution is to increase the SAR ADC’s clock rate, which can be achieved using asynchronous SAR ADCs [4], However, synchronous clocking is preferred in digital and mixed analog-digital systems, as asynchronous components are more prone to interference. Flash ADCs offer an alternative [2] but consume significantly more chip area and power, counteracting the benefits of zoom ADCs.

[0011] The sensitivity of zoom ADCs to external interference is particularly problematic when continuoustime integrators are employed in the delta-sigma modulator. When continuous-time integrators are linked in series within the loop filter, with feedback from the comparator output to the integrator input (Chain of Integrators with Feedback, CIFB), they inherently provide anti-aliasing due to their low-pass filter characteristics, thus eliminating the need for a separate anti-alias filter to satisfy the Nyquist-Shannon criterion. The preceding SAR ADC contradicts this robustness of the continuous-time delta-sigma ADC. Therefore, there is a need in the art to improve the performance for Zoom ADCs.

[0012] Objective of the invention

[0013] The objective of the invention is to provide an ADC with a zoom function that increases robustness against transient interference signals with a reliable functionality.

[0014] General description of the invention

[0015] The object of the invention is solved by the independent claims. Advantageous embodiments of the invention are disclosed in the dependent claims.

[0016] In a first aspect, the invention relates to an Analog-to-digital converter (ADC) comprising a delta-sigma modulator, wherein the modulator is configured to provide an output signal starting from an analogue input signal, which is converted to an analogue output signal and fed back into the modulator for a zoom.

[0017] In a further preferred embodiment, the ADC is characterized in that the ADC comprises a hybrid integrator. In a further preferred embodiment, the ADC is characterized in that the analogue output signal is converted by (or by means of) the hybrid integrator.

[0018] In a further aspect, the invention relates to an Analog-to-digital converter (ADC) comprising a delta-sigma modulator (or sigma-delta modulator) and a hybrid integrator, wherein the delta-sigma modulator is configured to provide an output signal starting from an analogue input signal, which is converted to an analogue output signal by means of the hybrid integrator and a digital signal from the delta-sigma modulator is converted to an analog signal and then subtracted from the analogue input signal for a zoom.

[0019] By employing hybrid integrators with a high dynamic range with a delta-sigma modulator, it becomes feasible to eliminate the SAR ADC entirely, achieving the zoom function solely through digital filtering and signal processing of a comparator output. Particularly, the oversampling technology enables the delta-sigma modulator to achieve high resolution and accuracy in signal processing. Using the hybrid integrator can help to reduce quantization noise improving signal quality. Furthermore, a higher stability is provided than using purely digital or analogue integrators, which is particularly important in applications with varying signals. The combination of the modulator and the hybrid integrator allows flexible implementation in different systems as the hybrid integrator uses both digital and analogue components.

[0020] The delta-sigma modulator according to the invention has advantageously the ability to operate at lower clock rates meaning that hardware requirements can be reduced, resulting in lower costs. A further advantageous is that the architecture minimizes distortion in the output signal, resulting in higher signal quality.

[0021] In the context of ADCs, a modulator preferably refers to a component that processes the analog input signal to facilitate accurate digital conversion. The modulator preferably modifies — or modulates — the signal in a way that enhances certain desirable properties, such as reducing noise or improving resolution. It often employs techniques like oversampling and noise shaping to optimize the performance of the ADC.

[0022] A Delta-Sigma Modulator (or Sigma-Delta Modulator) preferably refers to a specific type of modulator widely used in high-resolution ADCs to achieve superior accuracy and low noise levels. It preferably operates by oversampling the input analog signal at a rate much higher than the Nyquist rate and utilizes a feedback loop to shape and minimize quantization errors.

[0023] Hybrid integrator preferably refers to a continuous-time (CT) integrator enhanced with digital techniques to expand its effective operating range. This preferably means that while it performs analog integration, the inclusion of digital elements allows for adjustments and corrections, effectively increasing the range and precision of its operation. This combination of analog and digital features makes a hybrid integrator particularly useful in applications like a Delta-Sigma ADC, where they can achieve high precision and flexibility over a wide range of input signals.

[0024] Zoom preferably refers to a technique that allows the converter to focus on a specific, narrow range of the input signal, advantageously enhancing resolution within that range. Instead of digitizing the full input range with uniform resolution, a zoom ADC may dynamically adjust its effective range, "zooming in" on smaller signal variations. This may be particularly useful in high- resolution applications, where detailed measurement of small signals is critical. The zoom operation is preferably implemented through methods such as feedback mechanisms, and fine- tuning of the modulator.

[0025] In a further preferred embodiment, the ADC is characterized in that an additive variable quantity is derived from signals of the modulator and does not require a separate analog-to-digital conversion for the input signal.

[0026] Additive variable quantity preferably refers to a value or signal component that is added to another quantity in a system, typically to account for some form of adjustment, error correction, or to extend functionality. In systems like signal processing, control systems, or measurement systems, this quantity often compensates for inherent inaccuracies, noise, or variations introduced during processing.

[0027] For example, in an analog-to-digital conversion context, the additive variable quantity may represent an offset or correction factors applied during signal processing. It is added to the primary signal to adjust the final output and enhance precision, accuracy, or dynamic range. In a zoom ADC the additive variable quantity adjusts the input signal to the dynamic range of the fine ADC, e.g. the Delta-Sigma modulator. The purpose of this addition is to refine the final result by compensating for small discrepancies or to shift the effective operating range of the system.

[0028] Avoiding a separate analog-to-digital conversion for the additive variable quantity preferably leads to simplified system design, lower latency, improved accuracy, reduced power consumption, and more flexibility in calibration and control. This makes the overall system more efficient, especially in applications requiring high precision and quick response times.

[0029] In a further preferred embodiment the ADC is characterized in that a variable additive quantity at an input of the modulator increases a maximum input signal amplitude or dynamic range of the ADC compared to a dynamic range of the individual modulator alone and the variable additive quantity is derived from signals of the modulator, wherein preferably the variable additive quantity does not require a separate analog-to-digital conversion for the input signal (or in other words is not converted analog-to-digital to provide a digital output).

[0030] The important advantage of this simplification according to the preferred embodiments is that the hybrid integrator (see Fig. 3) allows to implement the zoom function without additional analog components. Using the hybrid integrator (Fig. 3) there is no longer a need for a separate ramp integrator to compensate for the continuous-time reset. Only the resolution and the range of a digital-to-analog converter would have to be increased. The simplification reduces the hardware effort. Particularly, the robustness of zoom ADCs is enhanced against transient interference signals.

[0031] Maximum Input Signal Amplitude preferably refers to the largest voltage or current level that can be applied to the input of a system, such as an ADC, without causing distortion or saturation. Beyond this level, the system may not be able to accurately convert or process the signal, leading to clipping or signal degradation. In ADCs, exceeding the maximum input amplitude may typically result in incorrect digital values, as the converter cannot handle signals that exceed its designed input range.

[0032] Dynamic Range preferably refers to the ratio between the smallest detectable signal and the largest signal that can be accurately processed. In the context of an ADC, dynamic range preferably defines how well the system can distinguish between very weak and very strong signals. A high dynamic range preferably means the ADC can handle a wide spectrum of signal amplitudes without losing precision at the low end or distorting signals at the high end.

[0033] In a further preferred embodiment, the ADC is characterized in that the analogue output signal is converted by means of a digital comparator, wherein preferably a Fl R-filter is connected to the delta-sigma modulator. In particular, the Fl R-filter (e. g. FIR-C in Fig. 7) is connected to the bit stream v of the delta sigma modulator. For this to work, the coefficient b1 must be small.

[0034] In a further preferred embodiment, the ADC is characterized in that the additive quantity is derived from the analog output of an integrator by applying the analog value of an integrator to a comparator or window comparator and further processing its digital output to the additive quantity.

[0035] Comparators, especially window comparators, have proven to be advantageous for further signal processing. Comparators can detect small voltage differences, which is important for precise sampling.

[0036] They offer fast switching times, which contributes to a high sampling rate of the modulator. Furthermore, standard comparators are relatively easy to implement and integrate into circuits. Furthermore, comparators are often inexpensive and require few external components. In the context of the invention, they are particularly advantageous in that comparators offer efficient signal conversion. They effectively convert analogue signals into digital signals, which increases the performance of the modulator.

[0037] Window comparators allow the monitoring of signals within a certain voltage range, which increases the flexibility of the ADC. Furthermore, the use of a window comparator can help to suppress noise and unwanted signals by only being active within a defined window.

[0038] Window comparators can reduce power consumption by only being active when the signal is within the defined range. In the context of the invention, window comparators are particularly useful for enabling adaptive signal processing, especially when the signal exhibits variable behavior.

[0039] Comparator preferably refers to an electronic device that compares two input voltages or currents and outputs a digital signal indicating which input is larger. The comparator preferably produces a high or low output depending on whether the first input is greater or less than the second input. When the input signal crosses a predefined reference value, the comparator preferably switches its output, making it useful for fast, simple decision-making in circuits.

[0040] Window comparator, also known as a dual comparator or window detector, preferably compares an input signal to two reference voltages and determines whether the input falls within a specific voltage range (the "window"). If the input is within the set limits, the output indicates a valid signal within the window, and if the input is outside the window, the output indicates that the signal is out of range. Preferably, it is displayed whether the range is exceeded upwards or downwards. In particular, the window comparator displays 0 if the input signal is within a certain range, +1 if the input signal is above an upper threshold and -1 if the input signal is below a lower threshold.

[0041] In a further preferred embodiment, the ADC is characterized in that the additive quantity is derived from an output of a decimation filter after the modulator.

[0042] The decimation filter reduces the sampling rate of the high-frequency modulation output, which reduces the amount of data that needs to be processed or stored. By filtering unwanted high- frequency components, the decimation filter improves the SNR of the output signal.

[0043] The filter compensates for quantization noise, resulting in a more accurate representation of the original signal. By removing frequencies above the Nyquist frequency, the filter can reduce the bandwidth of the signal, which is advantageous for certain applications. The decimation filter helps to improve the overall quality of the output signal by removing noise and artefacts. With a lower sampling rate, the subsequent digital signal processing becomes less computationally intensive.

[0044] Decimation filter preferably refers to a digital filter used in signal processing to reduce the sampling rate of a signal. It preferably works by first filtering the input signal to remove high- frequency components (quantization noise outside of the signal band) and then down-sampling the signal, reducing the number of samples. This process is preferably known as decimation, which involves reducing the sampling rate by a factor (called the decimation factor).

[0045] After the Delta-Sigma modulator generates an oversampled bitstream, the decimation filter may reduce the oversampled data to a lower, more manageable rate, while retaining the essential signal information within the desired bandwidth. This filtering advantageously ensures that high- frequency noise and out-of-band components are removed before down-sampling, allowing for a more accurate digital representation of the original analog signal.

[0046] In a further preferred embodiment, the ADC is characterized in that the additive quantity is added as a digital quantity to the digital input of a digital-to-analog converter for a quantizer feedback at the input of the modulator.

[0047] In the modulator (sigma-delta modulator), the quantized output signal (usually a binary signal) is fed back into the integrator. This feedback helps to reduce noise and improve the accuracy of the modulator. Quantized feedback in a sigma-delta modulator refers to the process by which the output signal of the modulator is fed back to improve the input signal and increase the accuracy of the digital representation.

[0048] In a further preferred embodiment, the ADC is characterized in that the additive quantity is added as a digital quantity to the digital input of a digital-to-analog converter for a quantizer feedback at the input of the modulator.

[0049] The use of quantizer feedback in a Zoom ADC without a coarse ADC stage preferably advantageously enables noise shaping, where the quantization noise is pushed to higher frequencies outside the bandwidth of interest. This preferably improves the signal-to-noise ratio within the desired frequency range, resulting in a cleaner and more precise digital representation of the analog signal. Additionally, by eliminating the need for a separate coarse conversion stage, the ADC's architecture is preferably simplified, reducing complexity and potential sources of error associated with multi-stage designs. This simplification leads to enhanced resolution and linearity within the zoomed-in signal range, as the system can focus on correcting errors in a narrower bandwidth. Also, the streamlined design contributes to greater power efficiency and costeffectiveness, as it reduces the number of required components and associated power consumption. The quantizer feedback may also enhance the ADC's ability to accurately capture small signal variations, making it well suited for high-precision applications where both accuracy and efficiency are important.

[0050] Especially in a Zoom ADC operating without a coarse ADC stage, a quantizer feedback is preferably important for achieving high-resolution conversion within a specific, narrow range of the input signal. Instead of relying on an initial coarse approximation, the ADC preferably employs a high-resolution Delta-Sigma modulator that directly processes the analog input. The quantizer preferably converts the continuous analog signal into discrete digital values, inherently introducing quantization noise due to finite resolution. To mitigate this noise, the system preferably implements quantizer feedback by feeding the digital output back to the input of the modulator through a digital-to-analog converter (DAC). This feedback loop preferably continuously subtracts the quantized value from the incoming signal, effectively generating a residual error signal. The modulator advantageously may focus on this error in subsequent cycles, allowing it to correct quantization errors in real-time and preferably enhance the overall accuracy of the conversion process.

[0051] Quantizer Feedback preferably refers to a mechanism often used in ADCs, especially in Delta- Sigma ADCs. It preferably refers to a feedback loop where the output of the quantizer (which converts the analog signal to discrete digital levels) is fed back into the system to improve the overall accuracy of the conversion process. The purpose of quantizer feedback may be to shape and reduce the effect of quantization noise by continuously comparing the quantized output with the original input signal. This feedback mechanism can advantageously help redistribute and minimize quantization errors over time, effectively enhancing the signal resolution and reducing noise in the final digital output. The technique allows for higher precision and better performance, such as in high-resolution ADCs.

[0052] In a further preferred embodiment, the ADC is characterized in that the output of the comparator is filtered and then fed to a following comparator or window comparator to generate the additive quantity out of it.

[0053] The initial comparator preferably acts as a basic threshold detector, ensuring that only significant signals are processed further. This is important because the output of the modulator may contain a mix of the desired signal and quantization noise. By applying this first threshold, the system preferably filters out weak or irrelevant parts of the signal, helping to reduce unnecessary noise propagation through the system.

[0054] Next, the signal preferably passes through a filter, which contributes to refining the signal by reducing noise and isolating the useful portions of the signal. The additive variable is shaped and redistributed during this stage. The filter ensures that the noise is minimized in the frequency band of interest, effectively cleaning up the signal for more accurate digitization. This step preferably improves the signal-to-noise ratio and makes the signal more manageable for subsequent stages.

[0055] Finally, the filtered signal is passed through a second comparator or a window comparator. This stage is important for performing a more refined check on the signal. If a comparator is used, it may apply a second, more specific threshold to ensure that the signal is within an acceptable range. If a window comparator is used, it checks whether the signal stays within a defined operational range, further validating its integrity. This step preferably ensures that the additive variable quantity, which includes any residual noise from the modulator, does not distort the digitized output.

[0056] Filter preferably refers to a device or process that selectively allows certain components of a signal to pass while attenuating or blocking others, based on specific characteristics such as frequency. Filters may be used in both analog and digital systems for cleaning up signals, isolating desired information, and removing unwanted noise or interference. For example, a low- pass filter allows signals below a certain frequency to pass while blocking higher frequencies, making it useful for removing high-frequency noise. Conversely, a high-pass filter does the opposite, letting higher frequencies through while filtering out lower ones. Other types include band-pass filters, which allow a specific range of frequencies to pass, and notch filters, which block a particular frequency range.

[0057] In a further preferred embodiment, the ADC is characterized in that a counter is used to generate the additive quantity.

[0058] Counter preferably refers to a digital system that increments or decrements its stored value by a fixed amount, typically in response to a clock signal or an event. It may count the number of occurrences of specific events, such as clock pulses, and can be used to track time, generate timing intervals, or count pulses for specific operations. They can operate in different modes such as up-counting, down-counting, or up / down-counting, depending on the design and purpose.

[0059] In particular, the counter is configured to hold the variable additive value k. Preferably, because of the zoom function, k is adjusted in steps when, for example, an input voltage Vjnchanges.

[0060] In a further preferred embodiment, the ADC is characterized in that an increment of the counter output is evaluated in order to avoid an overshoot of the counter.

[0061] Overshoot in a counter may occur when the counter's value exceeds its target value., This can happen when the counter increases too. Overshoot in counters is particularly problematic in digital systems because it can lead to incorrect calculations, system instability, or loss of data. In some cases, overshoot can even result in overflow, causing errors in subsequent operations. Managing overshoot may involve for example using control mechanisms to slow or stop increments as the counter approaches its target value, ensuring stable and accurate operation.

[0062] In particular, the counter has an integrating function. Such functions tend to overshoot. This is avoided by forming the difference between k and kdel and the feedback to the comparator input CMP2 (see Fig. 7). Particularly, an overshoot above the desired target value when calculating k is avoided hereby. When evaluating an increment of the counter output, the system can preferably take steps to ensure that it does not exceed target value or cause unintended results. One way this can help prevent overshoot is by monitoring the rate and magnitude of the increments. If the system detects that the counter is approaching its target value too quickly, it can adjust the increment (such as slowing it down or capping it) to prevent the counter from exceeding its target value.

[0063] Additionally, each increment can be evaluated to ensure it remains within a safe operational range. For example, instead of allowing a constant increment (which could push the counter beyond its desired limit), the system might introduce conditional logic, where the size of the increment reduces as the counter increases continuously.

[0064] In a further preferred embodiment the ADC is characterized in that a signal of the window comparator which is part of the hybrid integrator is used to generate the additive quantity.

[0065] By deriving the variable additive value from the hybrid integrator, preferably the 1stintegrator of the Delta-Sigma modulator, the variable additive value can be adjusted faster to the target value, the zoom function is faster and overload of integrators of the modulator can be reduced.

[0066] In a further preferred embodiment, the ADC is characterized in that the additive quantity is added in digital form to the input of the ADC at an input of an analog part of the hybrid integrator.

[0067] Introducing the additive variable quantity through the hybrid integrator preferably improves the system’s ability to continuously correct and smooth out errors and noise, improving signal quality, enhancing noise shaping, and extending dynamic range.

[0068] In a further preferred embodiment, the ADC is characterized in that the additive quantity is first delayed with a filter before it is added at an output of the decimation filter.

[0069] Delaying the additive variable quantity using a filter before adding it to the decimator’s output preferably allows for smoother, more precise AD conversion of the zoom ADC, prevents phase misalignment, and improves the signal-to-noise ratio by attenuating unwanted noise. This may advantageously result in a cleaner and more stable final signal.

[0070] Figures

[0071] Short description of the figures

[0072] Figure 1 Zoom ADC with SAR-ADC, Delta-Sigma-Modulator, Decimation Filter and Summing of Coarse-Value k and Decimation Filter Output (Prior Art)

[0073] Figure 2 Hybrid integrator with local feedback (Prior Art)

[0074] Figure 3 Simplified hybrid integrator with local feed back

[0075] Figure 4 Principle of Zoom-ADC without Coarse-ADC

[0076] Figure 5 Compensation of Delay of Decimation Filter for Coarse Quantization Signal

[0077] Figure 6 Alternative Processing Scheme for Coarse Quantization Control Signal k

[0078] Figure 7 Tapping 1stintegrator output for generation of coarse quantization signal, using 2ndwindows comparator CMP2 with adjusted threshold TH and quantization step LSB, and using FIR filter stages for window comparator CMP and feedback of k to Zoom-ADC output

[0079] Figure 8 Hybrid integrator with additional coarse quantization input k(t)

[0080] Figure 9 Zoom ADC with 2nd order AZ modulator with hybrid integrators - Matlab - Simulink model

[0081] Figure 10 Signal curves in the Zoom ADC with 2ndorder modulato

[0082] Detailed description of the figures

[0083] Figure 1 shows the block diagram of a zoom ADC with SAR ADC and delta-sigma modulator (also sigma-delta modulator). The SAR ADC quantizes the input signal VIN in coarse steps. The digital value of the coarse quantization is k. The fine quantization is achieved with the sigma-delta modulator. The input signal u to the modulator passes through the loop filter H(s) and is then fed to the clocked comparator. The output of the comparator v is calculated together with the coarsely quantized value k, converted to digital-analog (DAC) and then subtracted from the input signal VIN. With the DAC and the component k of the coarsely quantized input, the input u to the loop filter is shifted to a range that lies within the working range of the sigma-delta modulator. In principle, the magnitude of u must be smaller than the magnitude of the analog representation of v so that the feedback loop can compensate the mean value of u towards 0 and the modulator loop is stable.

[0084] The comparator output v is fed into a decimation filter in order to obtain a digital variable DA OUT with n-bit resolution. Sine filters are often used for decimation. To obtain the digital value DOUT representing IN, k must be added to D OUT. In practical zoom ADCs, the delay time from k to the output DOUT must be compensated with respect to the delay time of the modulator and the decimation filter, which is not shown here for the sake of clarity.

[0085] An exemplary hybrid integrator as used in the Zoom ADC is shown in Figure 2 [5], The actual analog integrator INT 1 , which processes the analog input XA(t), is monitored by the window comparator CMP. If the value of integral 3 is too large, the overflow is stored in register R2. Parallel to this, digital integration takes place with register R1. R1 accumulates the digital input Xo(t) and the instantaneous overflow Xo(n). The digital output is Yo(t), the analog output is YA ). If the window comparator indicates an overflow or underflow and saves it in register R2, the overflow is converted from digital to analog with DAC2 and subtracted at the summation point (SUB) before the input of the analog integrator INT 1 . A continuous-time reset of integrator INT1 is performed.

[0086] As the transfer of the analog integral component to the digital component, which is stored in register R1 , does not actually take place until the end of a clock phase, the continuous-time reset must be compensated for by a positive component provided by integrator INT2. Integrator INT2 is reset at the end of each clock phase. Because the digital component of the integral in register R1 only changes with the clock, but the hybrid integrator must also integrate the digital component continuously over time, the current digital input Xo(t) is converted from digital to analog with the DAC1 and integrated continuously over time with integrator INT3. The current analog component of the integral YA( is therefore made up of three components, the core integrator INT1 , which integrates the analog input and is not periodically reset, an integrator I NT2 , which generates a ramp-shaped signal that compensates for the continuous-time reset, and the integrator I NT3, which converts the current digital component into a ramp-shaped signal.

[0087] In Figure 2, both register R2 and register R1 are fed to a separate DAC and then a ramped signal is generated with the INT2 and INT3 integrators. Figure 3 shows how the functions of the INT2 and INT3 integrators can be combined. The digital input XD(t) and register R2 are added (with SUM) and then fed together to the DAC1 and a common ramp signal is generated with INT3. The important advantage of this simplification is that DAC2 is no longer needed to compensate for the continuous-time reset. With the DAC2 and the subtractor SUB in Figure 3, the DAC and the summation node in Figure 1 can now be realized inside the zoom ADC of this invention. The simplified hybrid integrator shown in Figure 3.

[0088] The simplified hybrid integrator shown in Figure 3 thus makes it possible to implement the zoom function without additional analog components. Only the resolution and the range of the DAC2 would have to be increased. The simplification reduces the hardware effort. Figure 3 shows how the functions of the INT2 and INT3 integrators can be combined. The digital input Xo(t) and register R2 are added (with SUM) and then fed together to the DAC1 and a common ramp signal is generated with INT3. The important advantage of this simplification is that DAC2 is no longer needed to compensate for the continuous-time reset. With the DAC2 and the subtractor SUB in Figure 3, the DAC and the summation node in Figure 1 can now be realized inside the zoom ADC of this invention. The simplified hybrid integrator shown in Figure 3 thus makes it possible to implement the zoom function without additional analog components. Only the resolution and the range of the DAC2 would have to be increased. The simplification reduces the hardware effort.

[0089] The principle of a zoom ADC without a separate coarse quantizing ADC is shown in Figure 4. This is based on a delta-sigma modulator consisting of loop filter H(s), quantizer and DAC. The modulator is shown in Figure 4 in a dashed box. The quantizer output v, i.e. the bit stream of the modulator, is converted into a digital value DAZOUT using a decimation filter. DAZOUT is compared with the references + / -Ref of a window comparator CMP. If the amount of DA OUT is less than the absolute value of the references, the comparator outputs the value 0 and the subsequent counter, represented by register Count and the summation node Sum in front of it, remains at the value 0. If DAZOUT exceeds the references of the window comparator, the counter starts to count up or down. The counter output is k, which is digital-to-analog converted and then subtracted.

[0090] If the input signal VIN is small, i.e. no zoom is required, the amount of the modulator output DAZOUT is small, the window comparator outputs 0, the counter Count remains at k=0. If the input signal VIN increases, the output of the decimation filter DAZOUT increases, but with a delay of the propagation time of the decimation filter. If the mean value of DAZOUT is greater than the value of the references Ref, the counter Count starts to increment the value k. The counter increases the value of k until DAZOUT falls below the threshold Ref of the window comparator.

[0091] If k is changed by the counter, this change is first delayed by the modulator and then by the decimation filter. As a result, the window comparator falls back with a delay and the counter counts too long, the value of k overshoots, so to speak. In Figure 5 this overshoot is avoided by delaying k with the Delay block, subtracting it from k and then adding it to DAZOUT and feeding it to the input of the window comparator. The value of Delay is dimensioned so that it corresponds approximately to the delay and the step response of the decimation filter.

[0092] The blocks CMP, Count and Delay in Figure 5 can be regarded as a special embodiment of the signal processing shown in generalized form in Figure 6 for extracting the coarse quantization k from the decimated modulator signal DAZOUT. The following functions can be used for this purpose:

[0093] • Non-linear transfer function Non-Linear, with a dead zone defined by VR,

[0094] • Filter function G(s), preferably low-pass filtering and moving averaging with FIR filters (Finite Impulse Response),

[0095] • Hysteresis or counter functions with adjustable thresholds and hysteresis functions with adjustable hysteresis widths VH,

[0096] • Filter function L(s) for the negative feedback of k to avoid the overshoot of k.

[0097] The order of the Non-Linear, G(s) and Hysteresis blocks can also be changed.

[0098] If the modulator works with continuous-time integrators, the Laplace transform of the functions is used for H(s) as shown in the figures. If the modulator works with discrete-time switched- capacitor integrators, H(s) is represented by the Z-transform H(z). In signal processing for the extraction of k, the Z-transform of the functions G(s) and L(s) is used in the technical realization.

[0099] Figure 7 shows a detailed technical realization of a zoom ADC with a continuous-time 3rd order modulator, k is extracted from the output of the 1st integrator. This has the advantage of less time delay when setting the coarse quantization k. The 1st integrator supplies an analog value which is fed to the window comparator CMP with adjustable thresholds Ref+ / -. The window comparator provides three values, including 0 if the integrator provides small values. The output of the window comparator is then fed into a filter FIR-C. FIR-C can be a sine filter, as it is often used for the decimation of the bit stream v. However, as no high resolution is required for the calculation of k, FIR-C can, for example, be a sine filter with a lower order and lower down-sampling ratio than is normally used in the decimation filter Decimation. This has the advantage that the delay in the calculation of k is less than if the calculation of k would be derived from D OUT.

[0100] The output of FIR-C then goes to a second window comparator CMP2 with adjustable threshold TH. The digital output is either 0 if k is not to be changed, or + / - 1 LSB if the counter for k is active. The difference between k and the delayed kdel is added to the input of the CMP2 to prevent the counter from overshooting. The coarse quantization k is first delayed with FIR-K before it is added to DA OUT. FIR-K compensates for the delay (group delay) of the decimation filter Decimation. Alternatively, k can be added to v at the input of the decimation filter. This then requires an input at the decimation filter with a larger bit width.

[0101] The simplified hybrid integrator shown in Figure 3 can easily be extended by an input for the coarsely quantized value k, as shown in Figure 8. The input k(t) is fed to the DAC2 via a subtractor SUB2. The DAC2 only requires an extended input range with more output levels. This hybrid integrator is now used in a zoom ADC with a second-order modulator as shown in Figure 9. The hybrid integrator with the additional input for k is the first integrator hint_v21 in Figure 9. In the Simulink sub-model, the input of k is labeled A_in_sub. The second integrator hint_v20 does not need this additional input and is therefore constructed as shown in Figure 2.

[0102] The modulator has a structure as in Figure 7, but the modulator only consists of 2 integrators. The coefficients are b1 =b2=1 , a1=-1 and a2=-2.

[0103] The window comparator, which evaluates the output of the 1st integrator, is already integrated in the hybrid integrator (in Figure 9). The comparator output cmp of h int_v21 is fed into the filter FIR- C via a sample-and-hold element SHcmp. The Comp_Counter block contains the functions CMP2 according to Figure 7, with a threshold value set to 0.5 and an LSB of 0.375, and the up and down counter. The roughly quantized signal k is then available at the output count of this block, k is then fed both to the input A_in_sub of the hybrid integrator hint_v21 and displayed as the 2nd variable in the 3 sub-diagram of the oscilloscope. k is delayed with the block Delay, then k is subtracted from this, weighted with 0.25 and added to the input of Comp_Counter. This avoids the mentioned overshoot of the counter. The coarse quantization k is then delayed again with FIR-K and finally added to the digital value of the modulator at the output of the decimation filter Decimation-sinc.

[0104] Figure 10 shows some examples of important signals in 4 sub-diagrams. The first diagram shows Vin, the input signal to be AD-converted, as a dotted line. ADC_out, the entire AD-converted signal, is shown with a solid line. It is delayed by the delay and the downsampling of the decimation filter. The modulator's contribution the total digital output value is represented by the dashed signal DSM.

[0105] The 2nd diagram in Figure 10 shows the window comparator, which evaluates the 1 st analog integrator. If Vin rises, the window comparator pulses +1 . If Vin falls, pulses with -1 are generated. If the input is stable, the coarse quantization does not need to be changed, the window comparator outputs 0.

[0106] The pulses filtered with FIR-C are the solid line in the 3rd sub-diagram. If the output of FIR-C exceeds the threshold value of 0.5, k increases or decreases in steps of 0.375, as shown by the dashed signal curve.

[0107] The 4th sub-diagram in Figure 10 shows an example of the effect of the hybrid integrator and its significance for the operation of the zoom ADC. A_int1 is shown with a solid line. This is the purely analog component of the hybrid integrator. The dotted line shows the mathematical sum of the analog and digital components AD_int1 . It can be seen how the hybrid integrator prevents a possible overload of the analog parts of the integral by converting analog parts of the integral into digital parts. This can be seen in particular in the time range from time point 500 to 600, when the input signal Vin drops steeply and the delay in setting the coarse quantization has a critical effect on the dynamic range of the analogue part of the integrator.

[0108] The use of a hybrid integrator in the AZ modulator of a zoom ADC enables coarse quantization and thus implementation of the zoom function without the use of an additional ADC. A possible overload of the integrator of the modulator is prevented by the hybrid integrator because it compensates for the overflow of the analog integrator without delay and transfers it to the digital part of the integrator.

[0109] References

[0110] [1] E. Eland, S. Mehrotra, S. Karmakar, R. van Veldhoven, and K. A. A. Makinwa, "The Zoom ADC: An Evolving Architecture," in Biomedical Electronics, Noise Shaping ADCs, and Frequency References, P. Harpe, A. Baschirotto, and K. A. Makinwa, Eds., Cham: Springer International Publishing, 2023, pp. 179-201.

[0111] [2] O. E. Erol and S. Ozev, "Dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator," US 10,541 ,706 B2, Jan 21 ., 2020.

[0112] [3] B. Gonen, S. Karmakar, R. van Veldhoven, and K. A. A. Makinwa, "A Continuous-Time Zoom ADC for Low-Power Audio Applications," IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1023-1031 , 2020, doi: 10.1109 / JSSC.2019.2959480.

[0113] [4] S. Karmakar, B. Gonen, F. Sebastiano, R. van Veldhoven, and K. A. A. Makinwa, "A 280 pW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW," IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3497-3507, 2018, doi:

[0114] 10.1109 / JSSC.2018.2865466.

[0115] [5] D. Killat, B. Ulmann, and S. Koppel, "Hybrid integrators with predictive overload estimation for analog computers and continuous-time AZ modulators," Adv. Radio Sci., vol. 21 , pp. 89-100, 2023, doi: 10.5194 / ars-21-89-2023.

Claims

1. CLAIMS1 . Analog-to-digital converter (ADC) comprising a delta-sigma modulator, wherein the modulator is configured to provide an output signal starting from an analogue input signal, which is converted to an analogue output signal and fed back into the modulator for a zoom.

2. ADC according to claim 1 characterized in that the analogue output signal is converted by means of a hybrid integrator.

3. ADC according to claim 1 characterized in that the analogue output signal is converted by means of a digital comparator, wherein preferably a FIR-filter is connected to the delta-sigma modulator.

4. ADC according to claim 1 characterized in that an additive variable quantity is derived from signals of the modulator and does not require a separate analog-to-digital conversion for the input signal.

5. ADC according to claim 1 characterized in that a variable additive quantity at an input of the modulator increases a maximum input signal amplitude or dynamic range of the ADC compared to a dynamic range of the individual modulator alone and the variable additive quantity is derived from signals of the modulator, wherein preferably the variable additive quantity does not require a separate analog-to- digital conversion for the input signal.

6. ADC according to claim 1 , characterized in that the additive quantity is derived from the analog output of an integrator by applying the analog value of an integrator to a comparator or window comparator and further processing its digital output to the additive quantity.

7. ADC according to any of the previous claims characterized in that the additive quantity is derived from an output of a decimation filter after the modulator.

8. ADC according to any of the previous claims characterized in thatthe additive quantity is added as a digital quantity to the digital input of a digital-to-analog converter for a quantizer feedback at the input of the modulator.

9. ADC according to any of the previous claims characterized in that a output of a comparator is filtered and then fed to a following comparator or window comparator to generate the additive quantity out of it.

10. ADC according to any of the previous claims characterized in that a counter is used to generate the additive quantity.11 . ADC according to claim 10, characterized in that an increment of the counter output is evaluated in order to avoid an overshoot of the counter.

12. ADC according to claim 6 and / or 9 characterized in that a signal of the window comparator which is part of the hybrid integrator is used to generate the additive quantity.

13. ADC according to any of the previous claims characterized in that the additive quantity is added in digital form to the input of the ADC at an input of an analog part of the hybrid integrator.

14. ADC according to any of the previous claims characterized in that the additive quantity is first delayed with a filter before it is added at an output of the decimation filter.

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