Ingan vcsel via lateral epitaxial overgrowth

Abstract

The invention relates to a method for producing an electronic component. The method comprises: forming a first semiconductor layer on or over a substrate, having a second semiconductor layer laterally adjacent to a dielectric structure using a lateral epitaxial overgrowth process such that the first semiconductor layer laterally overgrowths the dielectric structure from the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer include or are formed from a semiconductor material; forming a third semiconductor layer on or over the first semiconductor layer such that the first semiconductor layer and the third semiconductor layer have a common interface, wherein the third semiconductor layer is configured to have a light-generating layer structure of the vertical surface emitter; and removing the substrate and removing at least part of the first semiconductor layer.

Description

[0001] 2024P00593 P96357

[0002] 1

[0003] InGaN-VCSEL via epitactic lateral overgrowth

[0004] Description

[0005] This disclosure refers to vertical

[0006] Surface emitters and methods for their manufacture.

[0007] It is known to grow vertical cavity surface emitting lasers (VCSELs) made of indium gallium nitrad (InGaN) on gallium nitrad (GaN) substrates, for example, 2" GaN wafers. This enables substrates with a low defect density to ensure devices with a long lifetime. However, these substrates are very expensive, and the size limitations of these substrates make it difficult to scale this technology for mass-market applications.

[0008] One objective of this invention is to enable the design of an electronic component that is substrate-independent or compatible with a greater variety of substrates. This allows GaN-based surface emitters to be produced on more cost-effective substrates.

[0009] In one aspect, a method for fabricating an electronic component is provided. The method comprises: forming a first semiconductor layer on or over a substrate having a second semiconductor layer laterally adjacent to a dielectric structure, by means of an epitaxial lateral overgrowth method such that the first semiconductor layer laterally overgrows the dielectric structure from the second semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise or are formed from a semiconductor material.The method further comprises forming a third semiconductor layer on or above the first semiconductor layer such that the first semiconductor layer and the third semiconductor layer have a common interface, wherein the third semiconductor layer is configured to assign a light-generating layer structure of the vertical surface emitter. The method further comprises removing the substrate and removing at least part of the first semiconductor layer.

[0010] In one implementation, the first semiconductor layer is formed by a single, continuous epitaxial lateral overgrowth (ELOG) process that begins at the edges of the underlying second semiconductor layer and extends laterally across the dielectric mask without any changes in growth chemistry, temperature, or V / 111 ratio. In this way, the entire thickness of the "badge" spanning the respective opening exhibits a uniform composition, dopant concentration, and crystal morphology.

[0011] For example, a more cost-effective sapphire substrate can be used instead of a costly GaN substrate.

[0012] In the second region, the dielectric structure is epitaxially overgrown laterally by the first semiconductor layer (epitaxial lateral overgrowth, ELOG).

[0013] The third semiconductor layer can therefore have a lower defect density above the dielectric structure than in the area above the second semiconductor layer.

[0014] The first semiconductor layer enables a high-quality surface, for example with improved or lower surface roughness, for the formation of the third semiconductor layer.

[0015] Alternatively or additionally, the method enables the precise formation of an optical cavity in a surface emitter, where the third semiconductor layer is a 2024P00593 P96357

[0016] Part of the optical cavity is . This is made possible by a low defect density at the position of the optical aperture or the current aperture of the active region in the third semiconductor layer in a surface emitter.

[0017] In another aspect, a vertical surface emitter is provided, comprising: a semiconductor layer with a light-generating structure, wherein the semiconductor layer is arranged between a first mirror structure and a second mirror structure; and a dielectric layer between the light-generating structure and one of the mirror structures, wherein the dielectric layer has one or more lenses.

[0018] In the drawings, the same reference symbols generally refer to the same parts in the different views. The drawings are not necessarily to scale, with the emphasis generally being on illustrating the principles of the invention. The following description details various aspects of the invention with reference to the following drawings, in which:

[0019] FIG. 1A to FIG. 1H schematic cross-sectional views of structures in the process for manufacturing a vertical surface emitter;

[0020] FIG. 2A to FIG. 2F schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0021] FIG. 3 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0022] FIG. 4A to FIG. 4D schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0023] FIG. 5 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter; 2024P00593 P96357

[0024] FIG.6 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0025] FIG.7A and FIG.7B schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0026] FIG.8A to FIG.80 schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0027] FIG.9A and FIG.9B schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0028] FIG.10A to FIG. IOC schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0029] FIG.11 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0030] FIG.12A to FIG.12D schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0031] FIG.13A to FIG.13C schematic cross-sectional views of structures in the process for manufacturing a surface emitter;

[0032] FIG.14 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0033] FIG.15 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0034] FIG.16 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0035] FIG. 17A and FIG. 17B schematic cross-sectional views of

[0036] Structures in the process for manufacturing a surface emitter; 2024P00593 P96357

[0037] FIG. 18 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0038] FIG. 19 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0039] FIG. 20A to FIG. 20C schematic top views of structures in the process for manufacturing a surface emitter;

[0040] FIG. 21 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0041] FIG. 22 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0042] FIG. 23 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter; and

[0043] FIG. 24 shows a schematic cross-sectional view of a structure in the process for manufacturing a surface emitter;

[0044] The following detailed description refers to the accompanying drawings, which illustrate specific details and aspects in which the disclosure can be put into practice. One or more aspects are described in sufficient detail to enable those skilled in the art to put the disclosure into practice. Other aspects may be used, and structural, logical, and electrical modifications may be made without departing from the scope of the disclosure. The various aspects described here are not necessarily mutually exclusive, since some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in the context of methods, and various aspects in the context of devices. However, it is understood that aspects described in the context of methods also apply to 2024P00593 P96357.

[0045] Devices may apply and vice versa. The drawings indicate that identical or similar elements, features, and structures are represented by the same reference numbers. It should be noted that the proportions in the drawings need not be to scale and that the size of features may be emphasized for clarity.

[0046] FIG. 1A to FIG. 1H illustrate schematic cross-sectional views of a structure in a method for manufacturing a vertical surface emitter.

[0047] FIG. 1A illustrates epitaxially grown layers 122 on a substrate support 102 of a substrate 160. The layers or structures on or above the substrate support 102 can be epitaxially grown and form an epitaxial layer stack 122. The epitaxially grown layers 122 have at least a portion 120 of an optical cavity of the vertical surface emitter.

[0048] The process for fabricating the vertical surface emitter involves forming a first semiconductor layer 140 on or over a substrate 160. The substrate 160 has a second semiconductor layer 104, which is laterally adjacent to a dielectric structure 106. The first semiconductor layer 140 is formed by means of an epitactic lateral overgrowth (ELOG) process. In this process, the first semiconductor layer 140 laterally overgrows the dielectric structure 106 from the second semiconductor layer 104. The first semiconductor layer 140 and the second semiconductor layer 104 can be made of or formed from the same semiconductor material.

[0049] The method can further include the (epitaxial) formation of a third semiconductor layer 110 on or above the first semiconductor layer 140 such that the first semiconductor layer 140 and the third semiconductor layer 110 share a common interface. The third semiconductor layer 110 is configured to have a light-emitting layer structure 170 of the vertical surface emitter, for example, that it is formed or can be formed therein. The first semiconductor layer 140 and the third semiconductor layer 110 can have the same semiconductor material or be formed from it. In other words, an electroluminescent structure 170, for example, a multi-quantum well (MQW) structure, can be formed on, above, or in the third semiconductor layer 110.In the coalescing regions (second regions), the light-emitting structure may have an optical aperture and / or a stromal aperture.

[0050] The first semiconductor layer can be formed by a single, continuous epitaxial lateral overgrowth (ELOG) process that begins at the edges of the underlying second semiconductor layer and extends laterally across the dielectric mask without changes in growth chemistry, temperature, or V / 111 ratio. In this way, the entire thickness of the "roof" spanning each vent exhibits a uniform composition, dopant concentration, and crystal morphology. To accelerate coalescence under this continuous growth regime, the dielectric mask can be structured with a dense lattice of vents, for example, with a center-to-center spacing of vents in the range of 1–5 pm.By limiting each lateral span to a very short distance, the first layer quickly seals each opening, while the underlying air inclusions in the cavity (under the roof) remain unchanged.

[0051] In other words, the substrate 160 can have the substrate support 102. A first epitaxial layer 142 can be formed on the substrate support 102. The second semiconductor layer 104 and the dielectric structure 106 2024P00593 P96357 can be formed on the first epitaxial layer 142. The second semiconductor layer 104 and the first epitaxial layer 142 can be epitaxially grown layers. For example, the first epitaxial layer 142 and the second semiconductor layer 104 can have the same semiconductor material or be formed from it. The dielectric structure 106 can be a triethoxysilane (TEOS) or SiO2.

[0052] The first epitaxial layer 142 can be formed from a first material, for example GaN, such as undoped GaN or weakly n-doped GaN. The substrate support 102 can be formed from a second material, for example a sapphire wafer. The second material can be process-specific, for example transparent for a laser lift-off process (see FIG. ID). The second material can be or have an aluminum oxide composition, for example sapphire.

[0053] The dielectric structure 106 can have openings 108 or be structured accordingly. An opening 108 can, for example, be larger than 1 pm and smaller than 20 pm. The dielectric structure 106 can be spaced away from an edge of the substrate support 102, for example, arranged at a distance 112 from it. The distance 112 can, for example, be 1 mm or more.

[0054] The dielectric structure 106 can have a lateral dimension greater than 10 pm, for example in a range of 20 pm to 50 pm .

[0055] The second semiconductor layer 104 can be epitaxially grown or formed on the first epitaxial layer 142. The second semiconductor layer 104 can, for example, be formed from the first material or contain it. The first epitaxial layer 142 can be visualized as a seed layer in the openings 108 of the dielectric structure 106 for the second semiconductor layer.

[0056] 104 act. The first material and the second material can have different material structures. The defect density in the first epitaxial layer can be high.

[0057] The second semiconductor layer 104 can laterally reshape or grow around the dielectric structure 106, for example by means of epitaxial lateral overgrowth (ELOG). This allows a cavity 118 to form (viewed from the substrate support 102) on the back side of the dielectric structure 106 between the second semiconductor layer 104 and the dielectric structure 106, which leads into a coalescence region 116. The second semiconductor layer 104 can laterally enclose the cavity 118 with increasing layer thickness (with increasing distance to the dielectric structure 106).

[0058] The cavity 118 causes defects in the structure of the material of the first semiconductor layer 140 to be compensated for or relaxed. As a result, the region 116 of the first semiconductor layer 140 above the dielectric structure 106 can exhibit a significantly lower defect density in the material structure than the region of the first semiconductor layer in or above the openings 108 of the dielectric structure 106.

[0059] The third semiconductor layer 110 is formed on or above the second semiconductor layer 104. The third semiconductor layer 110 can have a component area 116 above the dielectric structures (illustrated in FIG. 1A by means of the dots 116) with a very low defect density, for example, less than approximately 1% to 10%, than in the area above the openings 108. The component area 116 can be a region for the aperture 126 (see FIG. 1B) of the vertical surface emitter. The diameter of an aperture 126 in a vertical surface emitter can be less than 15 pm, for example, a few pm. The component area in the third semiconductor layer 110 can have a lateral dimension (illustrated in FIG. 1A by means of arrow 132) in a range of 10 pm to 25 pm - for example depending on the lateral width of the 2024P00593 P96357

[0060] 10 dielectric structure 106 between adjacent openings 108 and the layer thickness of the second semiconductor layer 104 .

[0061] The third semiconductor layer 110 can be formed from the first material, have the same material, or have a material with a compatible or comparable lattice structure.

[0062] As illustrated in FIG. 1A, part of the cavity 118 can extend into the third semiconductor layer 110. In this region, the third semiconductor layer 110 can have a high defect density.

[0063] The process can further include the formation of the light-generating layer structure 170 in the third semiconductor layer 110 before the removal of the substrate 160. The light-generating layer structure 170 can also be formed before the removal of the first semiconductor layer 140.

[0064] The dielectric structure 106 can be configured such that a circumferential region of the substrate 160 is essentially free of the dielectric structure 106. The second semiconductor layer 104 essentially covers the substrate 160 in the circumferential region. The second semiconductor layer 104 laterally encapsulates the dielectric structure 106 in the circumferential region.

[0065] FIG. 1B illustrates that a contact layer 128 can be formed on or above the light-generating structure 170, for example an indium tin oxide (ITO) layer, or a p-doped semiconductor layer in the case of an n-doped third semiconductor layer 110.

[0066] The method can further include the formation of a mirror structure 130 on or above the light-generating layer structure 170. For example, a mirror structure 130 can be formed on or above the epitaxial layer stack 122, as illustrated in FIG. 1B. The mirror structure can, for example, be 2024P00593 P96357

[0067] 11 have a Bragg mirror (distributed Bragg mirror, DBR; DBR mirror) 130 and a gold layer 132 on the DBR mirror 130.

[0068] Between the contact layer 128 and the DBR 204, a functional structure 126 can be provided, for example one or more of an optical aperture, an electrical aperture, a current distribution structure and / or a passivation.

[0069] The sidewalls of the openings 136 in the third semiconductor layer 140 above the second semiconductor layer 110 can be passivated by means of a sidewall passivation 124, for example by means of a dielectric material, for example by means of an atomic layer deposition (ALD) process. The openings 136 can be partially or completely filled with one or more materials, for example with a dielectric material, a benzocyclobutene (BCB) polymer or another polymer, or a metal.

[0070] As illustrated in FIG. 1C, a support 150 can be applied to or over the mirror structure, for example by means of an adhesive layer 138 and / or a planarization layer 138. The support 150 can be electrically conductive, for example a Ge wafer, a Si wafer, or a ceramic wafer. An electrical contact structure 152 can be provided on or over the support 150, which is electrically connected to the epitaxial layer stack 122.

[0071] Any bending, for example caused by

[0072] The growth direction of the epitaxial layer stack 122 is determined by applying the support 138. 2024P00593 P96357

[0073] 12

[0074] The process can further involve the removal of the substrate 160 and the removal of at least part of the first semiconductor layer 140.

[0075] For example, by means of a lift-off method, such as a laser lift-off 180 through the substrate support 102, the connection of the first epitaxial layer 142 to the substrate support 102 can be broken, as illustrated in FIG. 1D. This allows the substrate support 102 to be detached from the first epitaxial layer 142, as illustrated in FIG. 1E.

[0076] The first epitaxial layer 142 can be removed from its exposed back side or surface, as illustrated in FIG. 1F. The first epitaxial layer 142 can be removed, for example, by polishing, grinding, chemical-mechanical polishing (CMP), etching, or a combination thereof. In the process, a portion of the second semiconductor layer 104 may also be removed, or the second semiconductor layer may subsequently be removed. This exposes a portion of the first semiconductor layer 146, as illustrated in FIG. IG.

[0077] Furthermore, the dielectric structure can be removed. This exposes a surface 126 of the first semiconductor layer 140, as illustrated in FIG. 1H. The layer structure illustrated in FIG. 1H can serve as the basis for different embodiments of the vertical surface emitter, which are described in more detail below.

[0078] The method for fabricating a vertical surface emitter according to one aspect is illustrated in FIG. 2A to FIG. 2G. Following the process stage in FIG. 1H, the first semiconductor layer 140 is removed. The first semiconductor layer 140 can be removed such that the 2024P00593 P96357

[0079] 13 previous interface (between the first semiconductor layer and the third semiconductor layer) is free of first semiconductor layer 140 .

[0080] The first semiconductor layer can be removed, for example, by means of an etching and / or polishing process, such as CMP, reactive ion etching (RIE), ion beam etching, polishing, or similar.

[0081] In the case of a long optical cavity, for example larger than 10 pm, for example larger than 15 pm, a precise thickness of the optical cavity may be of secondary importance, for example because the free spectral range may be much smaller than 10 nm.

[0082] The method can further include the formation of one or more lenses on or above the common interface. The one or more lenses can be formed by an etching process. For example, a suitably structured photoresist 148 can be formed on the third semiconductor layer 110 above the mirror structure 130, as illustrated in FIG. 2B. Subsequently, the third semiconductor layer 110 can be structured by an etching process such that a third semiconductor layer 110 with one or more lenses 154 is formed, as illustrated in FIG. 2C.

[0083] After substrate removal and exposure of the common interface, the remaining semiconductor layer, or alternatively the dielectric layer 202, can be structured using a dry etching process to form one or more microlenses directly within the semiconductor layer (see FIG. 2C) or the dielectric layer 202 (see FIG. 4G). Since these lenses are defined in situ by etching a layer that has already determined the ELOG step, they are integrally aligned with the underlying optical resonator and do not require any subsequent connection of separate

[0084] Lens plates . 2024P00593 P96357

[0085] The method can further include forming a mirror structure 156 on or above the third semiconductor layer 110, for example on or above one or more of the lenses 154, as illustrated in FIG. 2D. The mirror structure 156 can, for example, be or comprise a DBR mirror.

[0086] The method can further include the formation of a contact structure 162 on or above the third semiconductor layer 110, for example, laterally adjacent to one or more of the lenses 154, as illustrated in FIG. 2E. The contact structure 162 can also be located deeper in the third semiconductor layer 110 than the one or more lenses 154. In other words, it is not necessary for the application to require that the contact structure and lens(es) be arranged in a common plane.

[0087] The formed structures can then be tested and separated, for example along the former openings, as illustrated in FIG. 2F by means of lines 158.

[0088] Depending on the application, the area of ​​lateral overgrowth can be small. This can enable vertical surface emitters with small lateral dimensions. The vertical surface emitter 100 can have two or more ELOG areas in various embodiments, as illustrated in FIG. 3. This simplifies the handling of the vertical surface emitter 100 during manufacturing. The vertical surface emitter 100 can have several ELOG areas (for example, separated areas with or above the first semiconductor layer). However, this does not require a mirror structure 130 and / or an aperture over every ELOG area (see FIG. 3). 2024P00593 P96357

[0089] 15

[0090] The method for producing a vertical surface emitter according to a further aspect is illustrated in FIGS. 4A to 4D. Following the process stage in FIG. 2A, the method includes the formation of a dielectric layer 202 on or above the common interface, as illustrated in FIG. 4A. The dielectric layer 202 may, for example, comprise or be formed from Nb₂O₅ or TiO₂.

[0091] The dielectric layer 202 can be deposited, for example, by ion-assisted sputtering. This allows the dielectric layer 202 to be formed with a low surface roughness, for example, less than 1 nm. The dielectric layer 202 can have at least part of the optical cavity of the vertical surface emitter. The difference between the refractive index of the first semiconductor material and the refractive index of the dielectric layer 202 can be less than 0.05, for example, a dielectric layer 202 made of Nb₂O₅ on a third semiconductor layer 110 made of GaN.

[0092] The method can further include the formation of one or more lenses on or above the common interface. The one or more lenses can be formed by an etching process. For example, a suitably structured photoresist 148 can be formed on the dielectric layer 202 above the mirror structure 130, as illustrated in FIG. 4B. Subsequently, the dielectric layer 202 can be structured by an etching process such that a dielectric layer 202 with one or more lenses 154 is formed, as illustrated in FIG. 4C.

[0093] The subsequent procedural steps can be carried out analogously to the procedure described above.

[0094] For example, the method can form a mirror structure 156 on or above the dielectric layer 2024P00593 P96357

[0095] 16

[0096] 202, for example, on or above one or more of the lenses 154. The mirror structure 156 can, for example, be or have a DBR mirror.

[0097] The method can further include the formation of a contact structure 162 on or above the dielectric layer 202, for example, laterally adjacent to one or more of the lenses 154, as illustrated in FIG. 4D. The contact structure 162 can also be arranged deeper in the dielectric layer 202 than the one or more lenses 154. In other words, it is not necessary, depending on the application, for the contact structure and lens(es) to be arranged in a common plane.

[0098] The formed structures can then be tested and separated, for example along the former openings.

[0099] The method for fabricating a vertical surface emitter according to a further aspect is shown in FIG. 5. Following the process shown in FIG. 1H, the first semiconductor layer 140 is removed such that a fourth semiconductor layer 502 has a remaining portion of the first semiconductor layer 140 on or above the interface, and the fourth semiconductor layer 502 forms part of the optical cavity of the vertical surface emitter. The fourth semiconductor layer 502 may, for example, have a thickness of less than 2 pm. Alternatively, the fourth semiconductor layer 502 may have a thickness in the range of approximately 10 pm to approximately 25 pm.

[0100] The first semiconductor layer can be partially removed, for example, by an etching and / or polishing process, such as CMP, reactive ion etching (RIE), ion beam etching, polishing, or similar. 2024P00593 P96357

[0101] 17

[0102] In the case of a long optical cavity, for example larger than 10 pm, for example larger than 15 pm, a precise thickness of the optical cavity may be of secondary importance, for example because the free spectral range may be much smaller than 10 nm.

[0103] The method can further include the formation of one or more lenses on or above the common interface. The one or more lenses can be formed by an etching process. For example, a suitably structured photoresist can be formed on the fourth semiconductor layer 502 above the mirror structure 130. Subsequently, the fourth semiconductor layer 502 can be structured by an etching process such that a fourth semiconductor layer 502 with one or more lenses 154 is formed, as illustrated in FIG. 5.

[0104] The subsequent procedural steps can be carried out analogously to the procedure described above.

[0105] For example, the method can involve forming a mirror structure 156 on or above the fourth semiconductor layer 502, for example on or above one or more of the lenses 154. The mirror structure 156 can, for example, be a DBR mirror.

[0106] The method can further include the formation of a contact structure on or above the fourth semiconductor layer 502, for example, laterally adjacent to one or more of the lenses 154. The contact structure can also be located deeper in the fourth semiconductor layer than the one or more lenses 154. In other words, it is not necessary for the application to require that the contact structure and lens(es) be arranged in a common plane.

[0107] The formed structures can then be tested and separated, for example along the former openings. 2024P00593 P96357

[0108] The method for producing a vertical surface emitter according to a further aspect is illustrated in FIG. 6. Following the process stage in FIG. 1H, the method involves forming a dielectric layer 202 on or above the first semiconductor layer 140. The dielectric layer 202 can, for example, comprise or be formed from Nb₂O₅ or TiO₂.

[0109] The dielectric layer 202 can be deposited, for example, by ion-assisted sputtering. This allows the dielectric layer 202 to be formed with a low surface roughness, for example, less than 1 nm. The dielectric layer 202 can have at least part of the optical cavity of the vertical surface emitter. The difference between the refractive index of the first semiconductor material and the refractive index of the dielectric layer 202 can be less than 0.05, for example, a dielectric layer 202 made of Nb₂O₅ on a first semiconductor layer 140 made of GaN.

[0110] The method can further include forming one or more lenses 154 on or above the common interface. The one or more lenses can be formed by an etching process. For example, a suitably structured photoresist can be formed on the dielectric layer 202 above the mirror structure 130. Subsequently, the dielectric layer 202 can be structured by an etching process such that a dielectric layer 202 with one or more lenses 154 is formed, as illustrated in FIG. 6.

[0111] The subsequent procedural steps can be carried out analogously to the procedure described above.

[0112] For example, the method can form a mirror structure 156 on or above the dielectric layer 202, for example on or above one or more of the 2024P00593 P96357

[0113] 19

[0114] Lenses 154, exhibit . The mirror structure 156 can, for example, be or exhibit a DBR mirror .

[0115] The method can further include the formation of a contact structure on or above the dielectric layer 202, for example, laterally adjacent to one or more of the lenses 154. The contact structure can also be located deeper in the fourth semiconductor layer than the one or more lenses 154. In other words, it is not necessary for the application to require that the contact structure and lens(es) be arranged in a common plane.

[0116] The formed structures can then be tested and separated, for example along the former openings.

[0117] The method for fabricating a vertical surface emitter according to a further aspect is illustrated in FIG. 7A to FIG. 7B. Following the process state in FIG. 2A, the method involves removing part of the third semiconductor layer 110. The remaining third semiconductor layer 702 may, for example, have a thickness of less than 2 pm.

[0118] The method further includes the formation of a mirror structure 156 on or above the remaining third semiconductor layer 702, as illustrated in FIG. 7A. The mirror structure 156 can, for example, be a DBR mirror or have other features.

[0119] The method can further include the formation of a contact structure 208 on or above the remaining third semiconductor layer 702, for example, laterally adjacent to one or more of the mirror structures 156, as illustrated in FIG. 7B. The contact structure 208 can also be located deeper in the fourth semiconductor layer than the one or more mirror structures 156. (See also 2024P00593 P96357.)

[0120] 20

[0121] In other words, it is not necessary for the application to require that the contact structure 208 and the mirror structure ( en) 156 are arranged in a common plane.

[0122] The formed structures can then be tested and separated, for example along the former openings.

[0123] The method for fabricating a vertical surface emitter according to a further aspect is illustrated in FIG. 8A to FIG. 80. Following the process state in FIG. 2A, the method involves removing part of the third semiconductor layer 110. The remaining third semiconductor layer 702 may, for example, have a thickness of less than 2 pm.

[0124] The process further involves the formation of a dielectric layer 202 on or above the remaining third semiconductor layer 702. The dielectric layer 202 can, for example, consist of or be formed from Nb₂O₅ or TiO₂.

[0125] The dielectric layer 202 can be deposited, for example, by ion-assisted sputtering. This allows the dielectric layer 202 to be formed with a low surface roughness, for example, less than 1 nm. The dielectric layer 202 can have at least part of the optical cavity of the vertical surface emitter. The difference between the refractive index of the first semiconductor material and the refractive index of the dielectric layer 202 can be less than 0.05, for example, a dielectric layer 202 made of Nb₂O₅ on a remaining third semiconductor layer 702 made of GaN.

[0126] The dielectric layer 202 can be configured to set a predetermined optical thickness of the optical cavity. 2024P00593 P96357

[0127] 21

[0128] The method can further include the formation of a mirror structure 156 on or above the dielectric layer 202, as illustrated in FIG. 8B. The mirror structure 156 can, for example, be a DBR mirror or have other features.

[0129] The method can further include the formation of a contact structure 208 on or above the dielectric layer 202, for example, laterally adjacent to one or more of the mirror structures 156, as illustrated in FIG. 8C. The contact structure 208 can also be located deeper in the fourth semiconductor layer than the one or more mirror structures 156. In other words, it is not necessary for the application to require that the contact structure 208 and the mirror structure(s) 156 be arranged in a common plane. The dielectric layer 202 can be structured such that the contact structure 208 is in direct contact with the third semiconductor layer 110.

[0130] The formed structures can then be tested and separated, for example along the former openings.

[0131] The method for producing a vertical surface emitter according to another aspect is illustrated in FIG. 9A to FIG. 9B, for the case that the third semiconductor layer 110 has a thickness less than approximately 2 pm with the first semiconductor layer.

[0132] The method can further include the formation of a mirror structure 156 on or above the first semiconductor layer 140, as illustrated in FIG. 9A. The mirror structure 156 can, for example, be a DBR mirror or have other features.

[0133] The procedure can further form a contact structure 208 on or above the third 2024P00593 P96357

[0134] 22

[0135] The contact structure 208 can be arranged, for example, laterally adjacent to one or more of the mirror structures 156 in the fourth semiconductor layer 110, as illustrated in FIG. 9B. The contact structure 208 can also be arranged deeper in the fourth semiconductor layer than the one or more mirror structures 156. In other words, it is not necessary for the application to require that the contact structure 208 and the mirror structure(s) 156 are arranged in a common plane. The first semiconductor layer 140 can be structured such that the contact structure 208 is in direct contact with the third semiconductor layer 110.

[0136] The formed structures can then be tested and separated, for example along the former openings.

[0137] The method for producing a vertical surface emitter according to another aspect is illustrated in FIG. 9A to FIG. 9B, for the case that the third semiconductor layer 110 has a thickness less than approximately 2 pm with the first semiconductor layer.

[0138] The method can further include the formation of a mirror structure 156 on or above the first semiconductor layer 140, as illustrated in FIG. 9A. The mirror structure 156 can, for example, be a DBR mirror or have other features.

[0139] The method can further include the formation of a contact structure 208 on or above the third semiconductor layer 110, for example, laterally adjacent to one or more of the mirror structures 156, as illustrated in FIG. 9B. The contact structure 208 can also be arranged deeper in the fourth semiconductor layer than the one or more mirror structures 156. In other words, it is not necessary, depending on the application, for the contact structure 208 and the mirror structure(s) 156 to be arranged in a common plane. The first 2024P00593 P96357

[0140] 23

[0141] Semiconductor layer 140 can be structured such that the contact structure 208 is in direct contact with the third semiconductor layer 110.

[0142] The formed structures can then be tested and separated, for example along the former openings.

[0143] The method for producing a vertical surface emitter according to another aspect is illustrated in FIG. 10A to FIG. 10C, for the case that the third semiconductor layer 110 has a thickness less than approximately 2 pm with the first semiconductor layer.

[0144] The process further involves the formation of a dielectric layer 202 on or above the first semiconductor layer 110, as illustrated in FIG. 10A. The dielectric layer 202 may, for example, comprise or be formed from Nb₂O₅ or TiO₂.

[0145] The dielectric layer 202 can be deposited, for example, by ion-assisted sputtering. This allows the dielectric layer 202 to be formed with a low surface roughness, for example, less than 1 nm. The dielectric layer 202 can have at least part of the optical cavity of the vertical surface emitter. The difference between the refractive index of the first semiconductor material and the refractive index of the dielectric layer 202 can be less than 0.05, for example, a dielectric layer 202 made of Nb₂O₅ on a first semiconductor layer 110 made of GaN.

[0146] The dielectric layer 202 can be formed to adjust a predetermined optical thickness of the optical cavity.

[0147] The procedure can still involve training a

[0148] Mirror structure 156 on or above the dielectric layer

[0149] exhibit 202, as illustrated in FIG. 10B. The 2024P00593 P96357

[0150] 24

[0151] Mirror structure 156 can, for example, be or have a DBR mirror.

[0152] The method can further include the formation of a contact structure 208 on or above the dielectric layer 202, for example laterally adjacent to one or more of the mirror structures 156, as illustrated in FIG. 1 OC. The contact structure 208 can be arranged directly on the third semiconductor layer 110.

[0153] The formed structures can then be tested and separated, for example along the former openings.

[0154] The method for producing a vertical surface emitter according to a further aspect is illustrated in FIG. 11. Following the process stage in FIG. 2A, the method involves the deposition of a dielectric spacer 1002 on the exposed third semiconductor layer 110. The dielectric spacer 1002 can be used to form a lens-like curvature of the surface of the third semiconductor layer. If the curvature is already formed in the GaN semiconductor material, it can be reshaped by a dielectric layer with a similar refractive index to the semiconductor material, e.g., Nb₂O₅, without changing the radius of curvature. A thick layer of Nb₂O₅ on a rough GaN surface has no effect on the scattering of light.The deposition of Nb2O5 on a rough surface, supported by ion sputtering, allows for a smooth surface on the Nb2O5 surface by using a specific thickness.

[0155] The process can further include the formation of a stop structure 1202, 1302 for polishing, etching, or chemical-mechanical polishing, as illustrated in FIG. 12A to FIG. 13C. The third semiconductor layer 110 can be formed from a first semiconductor material, and the 2024P00593 P96357

[0156] 25

[0157] The stop structure can be formed from a different semiconductor material that differs from the first semiconductor material. Alternatively, the stop structure can be application-specific and formed from a dielectric material or a metal. The stop structure can be formed in the third semiconductor layer 110, leaving the first semiconductor layer 140 free of the stop structure, as described in more detail below.

[0158] In various embodiments of the described aspects, the method can involve the formation of one or more support structures 1202 in the third semiconductor layer 110, as illustrated in FIGS. 12A to FIGS. 12D. The support structure(s) 1202 can be arranged in a region laterally adjacent to the mirror structure 130 and / or the aperture. For example, in the ELOG method, the support structure 1202 can be configured using the dielectric structure 106, such that the support structure 1202 has different mechanical properties than the third semiconductor layer 110. These different mechanical properties can be based, for example, on a different crystal structure and / or orientation. Alternatively, or additionally, the support structure 1202 can be formed from a dielectric material, for example TEOS or SiO₂; or from a metal.Optionally, the support structure 1202 can fill the openings in the third semiconductor layer 110 above that of the former second semiconductor layer.

[0159] Optionally, the support structure 1202 can extend to the common interface, as illustrated in FIG. 12A. For example, the support structure can serve as a stop structure, for instance in a method for removing the first semiconductor layer 140, for example as a stop for a polishing process, for example as a stop for a CMP process; as illustrated in FIG. 12B.

[0160] The CMP or polishing stops, slows down, or changes its properties after the support structure 1202 2024P00593 P96357

[0161] 26 was achieved because the support structure has different mechanical properties compared to the material of the first semiconductor layer, for example, GaN. This can lead to a very flat and homogeneous surface with low roughness of the third semiconductor layer after removal of the first semiconductor layer. The thickness of the optical cavity of the vertical surface emitter can thus be well defined.

[0162] The support structure 1202 can, for example, be configured as a chip grid, post or column.

[0163] The mirror structure 156 on or above the side of the common interface can be formed laterally next to the support structure 1202, as illustrated in FIG. 12C.

[0164] The contact structure 152 on or above the side of the common interface can be formed laterally next to the support structure 1202 and / or the mirror structure 156, as illustrated in FIG. 12D.

[0165] In various embodiments of the described aspects, the method can include the formation of one or more stop structures 1302 in the third semiconductor layer 110, as illustrated in FIG. 13A to FIG. 13C. The stop structures 1302 can be configured as one or more layers embedded in the third semiconductor layer. The stop structures 1302 can, for example, have a different semiconductor material, such as ALN or AlGaN, than the semiconductor material of the third semiconductor layer 110, such as GaN.

[0166] With multiple layers of the stop structure 1302, the layers can have different thicknesses, as illustrated in FIG. 13A. This allows the layers to be distinguished from one another during etching or polishing. 2024P00593 P96357

[0167] 27

[0168] Figures 13A and 13B illustrate that a sacrificial structure 1302 can be provided between the third semiconductor layer 110 and the first semiconductor layer 140, depending on the application. The sacrificial structure 1302 can have one or more layers. The sacrificial structure 1302 can have a material structure (e.g., a lattice structure) corresponding to the first semiconductor layer 140 and / or the third semiconductor layer 110. The sacrificial structure 1302 can be formed from one or more semiconductor materials. The material of the sacrificial structure 1302 can, for example, have a higher chemical etch rate with respect to a chemical etching medium than the first material. The sacrificial structure 1302 can be formed epitaxially on the first semiconductor layer 140. The sacrificial structure 1302 can, for example, be configured as at least one AlGaN layer in the epitaxial GaN layer stack 122.The sacrificial structure can consist of a material from the following group: AlN, AlInN, AlGaN, or a combination thereof. The Al content of the AlGaN layer can be greater than 6%. In the case of two or more AlGaN layers, a first AlGaN layer can, for example, be thicker than the subsequent AlGaN layers. The layers of sacrificial structure 1302 can serve as sequential etch stop layers. The layers of sacrificial structure 1302 can serve to homogenize the surface roughness. The layers of sacrificial structure 1302 can serve to compensate for inhomogeneities in surface roughness.

[0169] The etching process can be carried out from the side of the common interface, as illustrated by the arrow in FIG. 13B.

[0170] The etching process can be carried out using different etching media. With a stop structure 1302 made of AlGaN or AIN and a third semiconductor layer made of GaN, the etching medium can be non-selective or selective with respect to these layers, for example, exhibiting higher etch rates with respect to GaN. 2024P00593 P96357

[0171] 28

[0172] The etching process ends, for example, after the illustrated second AlGaN layer of the stop structure 1302. The original roughness of the surface of the third semiconductor layer 110 is now reduced, and the process stops at a predetermined thickness of the third semiconductor layer 110. This allows the surface of the third semiconductor layer to be planarized. Alternatively or additionally, this can compensate for thickness variations in the third semiconductor layer.

[0173] Optionally, one or more further described structures can then be formed on or above the common interface of the third semiconductor layer, for example the dielectric layer, one or more lenses, the mirror structure and the contact structure.

[0174] The method can further include the formation of a test structure 1402. The test structure 1402 can, for example, be formed with a second aperture that is larger than the aperture of the vertical surface emitter, as illustrated in FIG. 14. The second aperture can, for example, be larger than 100 pm in diameter. The second aperture can, for example, have the width of an ELOG stripe (the distance from the edge of the dielectric structure to its center).

[0175] The test structure 1402 enables, for example, mapping of the length of the optical cavity, measurement of material thickness over a wafer during the production of a large number of vertical surface emitters on the wafer.

[0176] A test structure 1402 can be provided for each vertical surface emitter of the plurality of vertical surface emitters on the wafer or for a subset of vertical surface emitters of the plurality of vertical surface emitters.

[0177] Alternatively or additionally, a test structure 1402 can be placed at predefined positions on the wafer between the number 2024P00593 P96357.

[0178] 29 vertical surface emitters may be provided. These predefined positions may also have a mirror structure, as illustrated in FIG. 15.

[0179] Together with a mapping of the optical cavity and a mapping of the photoluminescence (PL) or electroluminescence (EL), it is possible to determine the required individual thickness of, for example, the previously described dielectric layer. This allows the peak gain and the length of the optical cavity to be matched or adjusted to each other.

[0180] For a wavelength of 450 nm of the emitted light from the vertical surface emitter, depending on the required thickness of the optical cavity, it may be sufficient to form, for example, dielectric layers with five discrete thicknesses distributed across the wafer for all vertical surface emitters on the common interface of the third semiconductor layer, as illustrated in FIG. 16.

[0181] FIG. 17A illustrates that the third semiconductor layer can be formed with a Tiit 1702 in the ELOG process. The Tiit 1702 can, for example, be inclined at less than 1°. Even if both surfaces of the third semiconductor layer 110 are (slightly) inclined, the principle of the vertical surface emitter still works because the optical cavity is inclined and both surfaces are parallel or have only a small deviation from each other, for example, much less than 0.1°.

[0182] After the application of the support 150, the inclined surfaces of the third semiconductor layer 110 can also be compressed, thus reducing the Tiit, as illustrated in FIG. 17B.

[0183] In various embodiments, the contact structure 152 can optionally be formed in the cavity (136 - see FIG. 11), as illustrated in FIG. 18. The contact structure 2024P00593 P96357

[0184] 30

[0185] 152 in the cavity, the n-contact layer of the light-generating layer structure can directly contact .

[0186] The third semiconductor layer 110 can be electrically isolated from the contact structure 152 in the cavity by means of the sidewall passivation 124. The sidewall passivation 124 can also be configured as a mesa, for example, projecting beyond the surface of the third semiconductor layer 110.

[0187] In various embodiments, a contact structure 152 extending into the cavity of the third semiconductor layer can be configured for two or more vertical surface emitters. Alternatively or additionally, two or more mirror structures can be configured laterally between two adjacent contact structures 152, each extending into the cavity of the third semiconductor layer. For example, a vertical surface emitter can have two or more ELOG strips as described above, or an array of ELOG strips, as shown in the top views illustrated in FIGS. 20A to 20C.

[0188] In various embodiments, the contact structure 152 can have a pad area 1902, as illustrated in FIG. 19. The pad area 1902 can be a large-area electrically conductive layer, for example on or above the third semiconductor layer 110.

[0189] Alternatively or additionally, the contact structure 152 can be set up in such a way that the ELOG strips or the individual apertures of a vertical surface emitter can be addressed individually, for example by means of pad areas 1902 for individual apertures or groups of apertures.

[0190] FIGS. 20A to FIGS. 20C illustrate schematic top views of exemplary arrays of apertures 128 in ELOG strips 2002 with contact structures 152 formed in cavities 136 in the third semiconductor layer. 2024P00593 P96357

[0191] 31 are. In each ELOG strip, one or more rows of apertures 128 can be provided, depending on the application (see FIG. 20A). The apertures of adjacent ELOG strips can be laterally offset (see FIG. 20B) or opposite each other (see FIG. 20C).

[0192] Since the ELOG strip width can be small, ELOG strips 2002 are well suited for pTransfer printing of the vertical surface emitters 2108. A vertical surface emitter 2108 can have one or more ELOG strips 2108, as illustrated in FIG. 21. For this purpose, a transfer carrier 2104 is applied to the planarization layer 138 using a transfer medium 2106. A transfer support structure 1202 can be embedded in the transfer medium 2106 or arranged on the planarization layer 138, for example, laterally next to or above the mirror structure 130, as illustrated in FIG. 21.

[0193] The transfer carrier 2104 can, for example, be transparent. This can enable laser-induced forward transfer (LIFT) of the transfer carrier 2104 for chip transfer. The transfer medium 2106 can be configured to be only temporarily arranged on the vertical surface emitter and can be removed before the transfer, for example, by etching. The transfer carrier 2104 can be or be made of a dielectric material, for example, a polymer or a polymer composed of one, for example, benzocyclobutene.

[0194] The mirror structure 156 on or above the common interface of the third semiconductor layer can essentially cover the surface of the third semiconductor layer. This simplifies the pick-and-place process for chips with a vertical surface emitter.

[0195] Alternatively or additionally, the transfer support structure 1202 can be configured as a connecting material, for example as 2024P00593 P96357

[0196] 32 planar layer between the transfer medium 2106 and the transfer carrier 2104, as illustrated in FIG.22.

[0197] In various embodiments, the back side of the vertical surface emitter can have a solder layer or a solderable layer. This allows contact pads 2302, 2304 to be implemented on the back side, for example, n-contact pads 2302 and p-contact pads 2304, as illustrated in FIG. 23. The contact pads 2302, 2304 can be square or circular. Each contact pad 2302, 2304 can be subdivided into several electrically interconnected areas. Multiple contact pads 2302, 2304 per chip or per vertical surface emitter can lead to self-alignment during (reflow) soldering. Additional stop structures etched with chip mesa can further enhance self-alignment.

[0198] In various embodiments, several ELOG strips can be electrically connected in parallel and / or in series within the vertical surface emitter. For example, arrays with lower current (higher voltage) can be well suited for realizing efficient drivers. The interconnection within a vertical surface emitter can be within an ELOG strip and / or perpendicular to the strips, as illustrated in FIG. 24. The interconnection of ELOG strips can be combined with any of the previously described embodiments.

[0199] The word "for example" is used here to mean "serving as an example, instance, or illustration." Any example or design described here as "for example" is not necessarily to be understood as preferred or advantageous over other examples or designs.

[0200] The words "multiple" and "several" in the description or claims expressly refer to a quantity greater than one. The terms "group (of)" and the like in the description or claims refer to a 2024P00593 P96357

[0201] 33

[0202] A quantity equal to or greater than one, i.e., one or more. Any concept expressed in terms of plurality that is not explicitly designated as "plural" or "multiple" also refers to a quantity equal to or greater than one.

[0203] The term "connected" can be understood in the sense of a (e.g., mechanical, optical, and / or electrical) connection and / or interaction, whether direct or indirect. For example, several elements can be mechanically connected so that they are physically held together (e.g., a plug connected to a socket), and electrically connected so that they have an electrically conductive path (e.g., signal paths exist along a communication chain).

[0204] In the descriptions and accompanying illustrations above, the components of the optical device are depicted as separate elements. However, those skilled in the art will appreciate the various ways in which discrete optical functions can be combined or integrated into a single element. This can include combining two or more components from a single part. Conversely, those skilled in the art will recognize the possibility of dividing a single element into two or more separate elements, such as splitting a single component into two or more separate components.

[0205] It is assumed that the methods described herein are exemplary and can therefore be implemented in a corresponding device. Likewise, it is assumed that implementations of the devices described herein can be implemented as a corresponding method. It is therefore understood that a device corresponding to a method described herein may contain one or more components configured to perform each aspect of the corresponding method. 2024P00593 P96357

[0206] 34

[0207] The following are some examples that relate to what is described and depicted in the figures.

[0208] Example 1 is a method for fabricating a vertical surface emitter, comprising: forming a first semiconductor layer on or above a substrate having a second semiconductor layer laterally adjacent to a dielectric structure, by means of an epitaxial lateral overgrowth method such that the first semiconductor layer laterally overgrows the dielectric structure from the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer comprise or are formed from a semiconductor material; forming a third semiconductor layer on or above the first semiconductor layer such that the first semiconductor layer and the third semiconductor layer have a common interface, wherein the third semiconductor layer is configured to provide a light-emitting layer structure of the vertical surface emitter;and removal of the substrate and removal of at least part of the first semiconductor layer.

[0209] After removing at least part of the first semiconductor layer, the first layer may be completely removed along the common interface or have a reduced thickness. Intuitively, at least part of the first semiconductor layer may be removed at any point along the common interface.

[0210] Optionally, part of the third semiconductor layer can also be removed.

[0211] In Example 2, the subject of Example 1 may optionally further feature: the formation, prior to substrate removal, of a light-generating layer structure in the third semiconductor layer. 2024P00593 P96357

[0212] In Example 3, the subject of Example 1 or 2 may optionally have the light-generating layer structure formed before the removal of the first semiconductor layer.

[0213] In Example 4, the object may optionally further exhibit, from one of Examples 1 to 3: the formation of a mirror structure on or above the light-generating layer structure.

[0214] In Example 5, the object from one of Examples 1 to 4 may optionally further have the first semiconductor layer removed in such a way that the interface is free of the first semiconductor layer.

[0215] In Example 6, the object of any one of Examples 1 to 4 may optionally further have the first semiconductor layer removed in such a way that a fourth semiconductor layer has a remaining part of the first semiconductor layer on or above the interface and the fourth semiconductor layer forms part of the optical cavity of the vertical surface emitter.

[0216] In Example 7, the object from Example 6 may optionally have the fourth semiconductor layer having a thickness of less than 2 pm.

[0217] In Example 8, the object from Example 6 may optionally have the fourth semiconductor layer having a thickness in the range of approximately 10 pm to approximately 25 pm.

[0218] In Example 9, the object from one of Examples 1 to 8 may optionally, after removal of the first semiconductor layer, further exhibit: the formation of a fifth semiconductor layer on or above the common interface.

[0219] In Example 10, the object from Example 9 may optionally have that the fifth semiconductor layer contains at least one 2024P00593 P96357

[0220] exhibits part of the optical cavity of the vertical surface emitter.

[0221] In Example 11, the object of one of Examples 9 to 10 may optionally further have the third semiconductor layer formed from a first semiconductor material, and the fifth semiconductor layer formed from a second semiconductor material that differs from the first semiconductor material.

[0222] In Example 12, the object of Example 11 may optionally have a difference in the refractive index of the first semiconductor material to the refractive index of the second semiconductor material that is less than 0.05.

[0223] In Example 13, the object from one of Examples 1 to 12 may optionally, after removal of the first semiconductor layer, further exhibit: the formation of a dielectric layer on or above the common interface.

[0224] In Example 14, the object of Example 13 may optionally have that the dielectric layer comprises at least part of the optical cavity of the vertical surface emitter.

[0225] In Example 15, the object of Example 14 may optionally have a difference in the refractive index of the first semiconductor material to the refractive index of the dielectric layer that is less than 0.05.

[0226] In Example 16, the object from any of Examples 1 to 15 may optionally further have the vertical surface emitter configured such that light is emitted through the common interface. 2024P00593 P96357

[0227] 37

[0228] In Example 17, the object may optionally further comprise one of the features of any of Examples 1 to 16, forming one or more lenses on or above the common interface.

[0229] In Example 18, the subject of Example 17 may optionally have one or more lenses formed by means of an etching process.

[0230] In Example 19, the subject of Example 18 may optionally include the etching process involving etching of the fourth semiconductor layer.

[0231] In Example 20, the subject of Example 14 with Example 9 can optionally include the etching process involving etching of the fifth semiconductor layer.

[0232] In Example 21, the object may optionally further exhibit, from any of Examples 1 to 20, the formation of a mirror structure on or above the common interface.

[0233] The mirror structure is vividly formed on the side (back side) of the common interface where the first semiconducting layer is or was located. The mirror structure can be located on any interface of one of the layers located on the back side.

[0234] In Example 22, the object of Example 21 may optionally have a mirror structure that is a DBR structure.

[0235] In Example 23, the object of Example 21 or 22, in conjunction with Example 19, may optionally have the mirror structure formed on or above the one or more lenses.

[0236] In Example 24, the item may optionally further feature one of Examples 1 to 23: Forming an electrical 2024P00593 P96357

[0237] Contact of the vertical surface emitter on or above the common interface.

[0238] The electrical contact is intuitively formed on the side (back side) of the common interface where the first semiconductor layer is or was located. The electrical contact can be located on any interface of one of the layers located on the back side.

[0239] The electrical contact can be located on the remaining portion of the first semiconductor layer. Alternatively, the electrical contact can be located on the third semiconductor layer exposed by removing the first semiconductor layer. Optionally, the electrical contact can be located deeper within the third semiconductor layer than the plane of the common interface, for example, by removing a portion of the third semiconductor layer.

[0240] The electrical contact can, for example, be exposed, or be accessible from the outside.

[0241] The electrical contact can optionally be arranged laterally next to a mirror structure located on the back.

[0242] The light-generating layer structure can optionally include an electroluminescent layer between a first contact layer and a second contact layer. The first contact layer can be, for example, of the p-type and the second contact layer can be, for example, of the n-type. A first electrical contact, connected to the first contact layer, can be provided on the back side, depending on the application. Alternatively, or additionally, a second electrical contact, connected to the second contact layer, can be provided on the back side, depending on the application. 2024P00593 P96357

[0243] 39

[0244] For example, an electrical via may be provided that extends from the first contact layer above the electroluminescent layer, through the electroluminescent layer and the second contact layer to the electrical contact.

[0245] In Example 25, the item may optionally further comprise one of Examples 1 to 24: the formation of a stop structure for chemical-mechanical polishing, wherein the stop structure is formed in the third semiconductor layer, such that the first semiconductor layer is free of stop structure.

[0246] In Example 26, the subject of Example 25 may optionally feature that the third semiconductor layer is formed from a first semiconductor material, and the stop structure is formed from a third semiconductor material that differs from the first semiconductor material.

[0247] In Example 27, the subject of any one of Examples 1 to 26 may optionally further include: the formation of a first aperture on or above the third semiconductor layer, wherein the first aperture is an electrical aperture and / or an optical aperture.

[0248] In Example 28, the subject of Example 27 may optionally feature the formation of a test structure, wherein the test structure is formed with a second aperture that is larger than the first aperture.

[0249] In Example 29, the subject matter of any one of Examples 1 to 28 may optionally further include: determining a thickness of the first semiconductor layer or the fifth semiconductor layer based on an intended optical length of the cavity of the vertical surface emitter; and forming the first semiconductor layer or the fifth semiconductor layer with a thickness based on a predetermined optical length of the optical cavity of the vertical surface emitter and corresponding to the determined thickness of the third semiconductor layer and the predetermined optical length.

[0250] In Example 30, the object may optionally further comprise one of Examples 1 to 29: the formation of a plurality of vertical surface emitters on a common substrate, wherein the thickness of the first semiconductor layer or the fifth semiconductor layer is determined for each vertical surface emitter.

[0251] In Example 31, the item may optionally further feature, from one of Examples 1 to 30: the formation of a via in the third semiconductor layer from the side of the common interface, for example by means of flip-chip contacting.

[0252] In Example 32, the object from any of Examples 1 to 31 may optionally further include: the formation of a mirror structure on or above the light-generating layer structure; and the application of a support on or above the mirror structure by means of a sacrificial structure, wherein the sacrificial structure has one or more support structures that directly connect the mirror structure to the support.

[0253] In Example 33, the object of Example 32 may optionally have the support structure extending through the mirror structure and the third semiconductor layer.

[0254] In Example 34, the subject matter of any one of Examples 1 to 33 may optionally further comprise that the substrate has a support substrate on which a further semiconductor layer is formed, wherein the second semiconductor layer and the dielectric structure are formed on the further semiconductor layer. 2024P00593 P96357

[0255] 41

[0256] In Example 35, the subject of Example 34 may optionally have the second semiconductor layer and the further semiconductor layer being epitaxially grown layers.

[0257] In Example 36, the subject of Example 34 or 35 may optionally have the further semiconductor layer and the second semiconductor layer having the same semiconductor material or being formed from it.

[0258] In Example 37, the object may optionally further include, from any of Examples 1 to 36, the first semiconductor layer and the third semiconductor layer having the same semiconductor material or being formed from it.

[0259] In Example 38, the article of one of Examples 34 to 37 may optionally further comprise that a further semiconductor layer is or comprises gallium nitride, and wherein the support substrate is or comprises an aluminum oxide, in particular a sapphire.

[0260] In Example 39, the object from one of Examples 32 to 38 may optionally further exhibit that the sacrificial structure comprises a material from the group of materials: AIN, Al InN, AlGaN, or a combination thereof.

[0261] In Example 40, the subject matter of any one of Examples 1 to 39 may optionally further have the dielectric structure arranged such that a circumferential region of the substrate is substantially free of dielectric structure, so that the second semiconductor layer substantially covers the substrate in the circumferential region, wherein the second semiconductor layer laterally encapsulates the dielectric structure in the circumferential region.

[0262] In Example 41, the item may optionally further comprise one of Examples 1 to 40: the application of a support on or above the third semiconductor layer. 2024P00593 P96357

[0263] 42

[0264] In Example 42, the subject of any of Examples 1 to 41 may optionally further feature: forming trench structures in the first semiconductor layer and the third semiconductor layer laterally adjacent to the dielectric structure, wherein the trench structures are formed such that the sacrificial structure is laterally exposed in the trench structure.

[0265] In Example 43, the object may optionally further comprise one of Examples 1 to 42: singling out the vertical surface emitter, wherein at least the third semiconductor layer is removed laterally next to the dielectric structure.

[0266] In Example 44, the object from one of Examples 1 to 42 may optionally further have the light-generating layer structure comprising a plurality of light-generating layer structures that are formed laterally next to each other and interconnected, for example in parallel and / or in series.

[0267] Example 45 is a vertical surface emitter comprising: a semiconductor layer with a light-generating layer structure, wherein the semiconductor layer is arranged between a first mirror structure and a second mirror structure; and a dielectric layer between the light-generating layer structure and one of the mirror structures, wherein the dielectric layer comprises one or more lenses.

[0268] In Example 46, the object of Example 45 optionally shows that one of the mirror structures is formed directly on one or more lenses.

[0269] In Example 47, the object of Example 45 or 46 optionally indicates that one of the mirror structures has a DBR mirror or is configured in this way. 2024P00593 P96357

[0270] 43

[0271] The subject matter of one of Examples 45 to 47 may be designed according to one of Examples 1 to 44 and may have corresponding features. All acronyms defined in the above description also apply to all claims contained herein.

[0272] Although the disclosure has been shown and described, particularly with reference to specific embodiments, it should be clear to the person skilled in the art that various changes in form and detail can be made without departing from the spirit and scope of the disclosure as defined by the appended claims. The scope of the disclosure is therefore specified by the appended claims, and all changes that are in the meaning and

[0273] Claims falling within the equivalence range should therefore be included.

[0274] 2024P00593 P96357

[0275] REFERENCE MARK LIST

[0276] 100 Vertical Surface Emitters

[0277] 102 substrate carriers

[0278] 104 second semiconductor layer

[0279] 106 dielectric structure

[0280] 108 Opening

[0281] 110 third semiconductor layer

[0282] 112 lateral distance to the edge

[0283] 114 Area with high defect density

[0284] 116 Low defect density area

[0285] 118 air gap

[0286] 120 epitaxial layers of the optical cavity

[0287] 122 epitaxially grown layers

[0288] 124 Sidewall passivation

[0289] 128 Aperture

[0290] 130 Mirror structure, for example DBR mirror

[0291] 132 metal layer

[0292] 134 electrical contact

[0293] 136 cavity

[0294] 138 Adhesive layer, planarizing layer

[0295] 140 first semiconductor layer

[0296] 142 first epitaxial layer

[0297] 146 exposed first semiconductor layer

[0298] 148 photoresist

[0299] 150 carriers

[0300] 152 Contact Structure

[0301] 154 lens(es)

[0302] 156 Mirror structure, for example DBR mirror

[0303] 158 separation points

[0304] 160 substrate

[0305] 162 Contact Structure

[0306] 170 light-generating layer structure

[0307] 180 Laser lifts

[0308] 202 dielectric layer

[0309] 208 electrical contact

[0310] 502 fourth semiconductor layer

[0311] 702 remaining third semiconductor layer 2024P00593 P96357

[0312] 45

[0313] 1102 Tibs standshall ter

[0314] 1202 Support structure, stop structure

[0315] 1302 Support structure, stop structure

[0316] 1402 Test structure

[0317] 1702 Tilt

[0318] 1902 Pad area

[0319] 2002 ELOG stripes

[0320] 2102 Transfer support structure

[0321] 2104 Transfer carrier

[0322] 2106 Transmission medium

[0323] 2108 micro-trans ferable chip

[0324] 2302 Contact pad

[0325] 2304 Contact pad

Claims

2024P00593 P96357 PATENT CLAIMS 1. Method for producing a vertical Surface emitters, comprising the method: forming a first semiconductor layer on or over a substrate having a second semiconductor layer laterally adjacent to a dielectric structure, by means of a method of epitaxial lateral overgrowth such that the first Semiconductor layer laterally overgrows the dielectric structure from the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer comprise or are formed from a semiconductor material; forming a third semiconductor layer on or above the first semiconductor layer such that the first semiconductor layer and the third semiconductor layer have a common interface, wherein the third semiconductor layer is configured to have a light-generating layer structure of the vertical surface emitter; and removing the substrate and removing at least part of the first semiconductor layer.

2. Method according to claim 1, wherein the first The semiconductor layer is removed in such a way that the The interface is free of the first semiconductor layer.

3. Method according to one of claims 1 or 2, further comprising, after removal of the first semiconductor layer, forming a dielectric layer on or above the common interface.

4. The method according to claim 3 further comprising: a Determining the thickness of the third semiconductor layer; and forming the dielectric layer with a thickness based on a predetermined optical length of the optical cavity of the vertical surface emitter and 2024P00593 P96357 47 corresponding to the determined thickness of the third semiconductor layer and the specified optical length .

5. Method according to claim 1, wherein the first semiconductor layer is removed such that a fourth semiconductor layer has a remaining part of the first semiconductor layer on or above the interface and the fourth semiconductor layer forms part of the optical cavity of the vertical surface emitter.

6. The method of claim 5, wherein the fourth semiconductor layer has a thickness of less than 2 pm; or wherein the fourth semiconductor layer has a thickness in the range of approximately 10 pm to approximately 25 pm.

7. Method according to one of claims 5 or 6, further comprising determining a thickness of the first Semiconductor layer based on an intended optical length of the cavity of the vertical Surface emitters; and Forming the fourth semiconductor layer with a thickness based on a predetermined optical length of the optical cavity of the vertical surface emitter and corresponding to the determined thickness of the third semiconductor layer and the predetermined optical length.

8. Method according to any one of claims 1 to 7, further comprising forming a mirror structure on or above the common interface.

9. Method according to any one of claims 1 to 8, further comprising: Forming one or more lenses on or above the common interface; wherein the one or more lenses are formed by means of an etching process. 2024P00593 P96357 10. Method according to claim 9, further comprising forming a mirror structure on or above the common interface; wherein the mirror structure is formed on or above the one or more lenses.

11. Method according to any one of claims 1 to 10, further comprising forming a stop structure for chemical-mechanical polishing, wherein the stop structure is formed in the third semiconductor layer, such that the first semiconductor layer is free of stop structure.

12. Method according to any one of claims 1 to 11, further comprising: forming a first aperture on or above the third semiconductor layer, wherein the first aperture is an electrical aperture and / or an optical aperture; and forming a test structure, wherein the test structure is formed with a second aperture that is larger than the first aperture.

13. Method according to any one of claims 1 to 12, further comprising: forming a plurality of vertical surface emitters on a common substrate, wherein the thickness of the third semiconductor layer is determined for each vertical surface emitter.

14. Method according to any one of claims 1 to 13, further comprising: forming a via in the third semiconductor layer from the side of the common interface, in particular by means of flip-chip contacting.

15. Method according to any one of claims 1 to 14, further comprising: forming an electrical contact of the vertical surface emitter on or above the common interface, 2024P00593 P96357 49 wherein the electrical contact is arranged on the remaining part of the first semiconductor layer, or wherein the electrical contact is arranged on the third semiconductor layer exposed by removing the first semiconductor layer.

16. Method according to any one of claims 1 to 15, further comprising: wherein the substrate comprises a support substrate on which a further semiconductor layer is formed, wherein the second semiconductor layer and the dielectric structure are formed on the further semiconductor layer, wherein the second semiconductor layer and the further semiconductor layer are epitaxially grown layers.

17. Method according to any one of claims 1 to 16, wherein the light-generating layer structure comprises a plurality of light-generating layer structures which are formed laterally next to each other and are interconnected.

18. A vertical surface emitter comprising: a semiconductor layer with a light-generating layer structure, wherein the semiconductor layer is arranged between a first mirror structure and a second mirror structure; and a dielectric layer between the light-generating layer structure and one of the mirror structures, wherein the dielectric layer comprises one or more lenses, the one or more lenses being formed by an etching process.

19. Vertical surface emitter according to claim 18, wherein one of the mirror structures is formed directly on the one or more lenses. 2024P00593 P96357 50 20. Vertical surface emitter according to claim 18 or 19, wherein one mirror structure comprises a DBR mirror or is configured accordingly.

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