Information processing apparatus and information processing method

Abstract

An information processing apparatus for assisting a user in a circuit design task, wherein the information processing apparatus includes circuitry configured to: receive a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generate, based on the task description, circuit designs; receive, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generate an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapt the circuit design based on the overall reward signal.

Description

[0001] INFORMATION PROCESSING APPARATUS AND INFORMATION

[0002] PROCESSING METHOD

[0003] TECHNICAL FIELD

[0004] The present disclosure generally pertains to an information processing apparatus and an information processing method for assisting a user in a circuit design task.

[0005] TECHNICAL BACKGROUND

[0006] Designing (analog) or synthesizing electronic circuits is a difficult task and typically requires experience to come up with the topology of the circuit as well as choosing the correct sizes of its components.

[0007] Hence, methods to automatically synthesize new circuits using machine learning have been developed that can solve this task.

[0008] Machine learning methods can be seen as optimization methods that optimize a metric. For the analog circuit synthesis problem, this metric should measure how good a (analog) circuit is for an application and, hence, this metric is crucial for the resulting circuit. Typically, this metric is either called “loss” for training algorithms, i.e., a metric to be minimized, or “reward” in the context of reinforcement learning, a metric to be maximized.

[0009] However, existing analog circuit design methods are tailored towards one specific application, e.g., the design of an operational amplifier (“OpAmp”) and only a single reward signal is considered (often called “figure of merit”).

[0010] Although there exist techniques for circuit design, it is generally desirable to improve the existing methods.

[0011] SUMMARY

[0012] According to a first aspect, the disclosure provides an information processing apparatus for assisting a user in a circuit design task, comprising circuitry configured to: receive a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generate, based on the task description, circuit designs; receive, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generate an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapt the circuit design based on the overall reward signal.

[0013] According to a second aspect, the disclosure provides an information processing method for assisting a user in a circuit design task, comprising: receiving a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generating, based on the task description, circuit designs; receiving, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generating an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapting the circuit design based on the overall reward signal.

[0014] Further aspects are set forth in the dependent claims, the drawings and the following description.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments are explained by way of example with respect to the accompanying drawings, in which:

[0017] Fig. 1 schematically illustrates in a block diagram an embodiment of a circuit synthesis system;

[0018] Fig. 2 schematically illustrates a circuit generation process;

[0019] Fig. 3 A schematically illustrates a generated circuit;

[0020] Fig. 3B schematically illustrates a generated circuit;

[0021] Fig. 4 schematically illustrates in a flow diagram an embodiment of an information processing method; and

[0022] Fig. 5 schematically illustrates in a block diagram an embodiment of a multi-purpose computer.

[0023] DETAILED DESCRIPTION OF EMBODIMENTS

[0024] Before a detailed description of the embodiments under reference of Fig. 1 is given, general explanations are made.

[0025] As mentioned in the outset, methods to automatically synthesize new circuits using machine learning have been developed that can solve a circuit design task. In machine learning a metric is optimized, which may be called “loss” or “reward”. In the following, the term “reward” is used for convenience as reinforcement learning is the most often used method for (analog) circuit synthesis.

[0026] As further mentioned in the outset, however, existing analog circuit design methods and frameworks are tailored towards one specific application, e.g., the design of an operational amplifier (“OpAmp”) and only a single reward signal is considered (often called “figure of merit”).

[0027] It has been recognized that a circuit synthesis framework should be provided that can find analog circuits for many different applications. An application of a circuit herein refers to a circuit design type, e.g., a low-power design or a compact design and also to the circuit type, e.g., an OpAmp or a clock multiplier.

[0028] Designing a suitable reward function for a circuit synthesis (design) task may be difficult, since there is not a single reward signal that can be used to judge (analog) circuit designs. Many aspects play a role which depend on the circuit that is to be generated.

[0029] It has been recognized that thus different reward functions should be combined into a single one with an application specific weighting or, generally, an application specific combination function such as a minimum or maximum function such that only the worst or best reward signals are take into account.

[0030] Moreover, it has been recognized that the user should be able to adapt the reward function to provide a circuit synthesis framework for many different applications.

[0031] Hence, it has been recognized that the reward function (overall reward signal) should be computed in a modular way encompassing many different aspects relevant for analog circuits and that the user of the synthesis tool should be able to configure how these individual reward signals are combined into a single overall reward signal that is used for the circuit synthesis.

[0032] Hence, some embodiments pertain to an information processing apparatus for assisting a user in a circuit design task, wherein the information processing apparatus includes circuitry configured to: receive a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generate, based on the task description, circuit designs; receive, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generate an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapt the circuit design based on the overall reward signal.

[0033] The information processing apparatus generally may be or may include a computer or a mobile electronic device (e.g., smartphone, tablet, laptop). The information processing apparatus may also include one or more components in a computer network such as a server component which performs some computations.

[0034] The circuitry generally may correspond to or may include typical electronic components which may be configured to provide the functions of the information processing apparatus as described herein, wherein the electronic components may be configured by hardware or by software or by a combination of hardware and software to provide the described functions.

[0035] For example, the circuitry may include one or more processors such as a Central Processing Unit (“CPU”), an application processor, a Graphical Processing Unit (“GPU”), a Digital Signal Processor (“DSP”), a Field-Programmable Gate Array (“FPGA”) or the like. The circuitry may include digital storage elements for storing and retrieving data.

[0036] The circuitry may include one or more input / output interfaces to provide a data exchange between one or more processors and / or one or more storage elements with, for instance, an electronic visual display, a keyboard, a computer mouse, a microphone, a loudspeaker. The electronic visual display may display text and images. The electronic visual display may be configured as a touch-display. The circuitry may include the hardware components connected to the one or more input / output interfaces.

[0037] The functionality of the information processing apparatus may thus be provided by a combination of hardware and software modules, for example, a user interface is provided which receives user input and which may (visually) display information to the user. Additionally, a circuit generator may be provided which is configured to generate, based on the task description, circuit designs and which receives an overall reward signal to adapt the circuit designs. Moreover, a combination module may be provided which manages communication with the circuit generator and the plurality of evaluation modules, and which generates and combines reward signals for feedback about the generated circuit design to the circuit generator.

[0038] The circuitry may also include a communication interface to provide a data exchange with other computers or servers or the like via a computer network, for example, the evaluation modules may run on a different (remote) computer or server or in the cloud or the like. As mentioned above, the information processing apparatus is generally configured to assist a user in a circuit design task.

[0039] The circuit design task may include an application of a circuit and one or more constraints for designing the circuit, such as inventory to be used for designing the circuit.

[0040] As mentioned above, the information processing apparatus receives a task description of the circuit design task for a circuit generator and a reward signal generation configuration from the user via a user interface.

[0041] The task description includes at least one of the input / output characteristics and allowed components to be used for designing the circuit. The task description may include an identifier for identifying a specific application, for example, circuit generator may have already been trained by reinforcement learning to generate circuits for that specific application. Furthermore, it may also include the application in form of a text prompt which can be used to condition the circuit generator such that knowledge from previous trainings can be exploited.

[0042] The input / output characteristics include input / output net(s) and input / output voltages. Moreover, the input / output characteristics may include supply nets and supply voltages such as the ground net.

[0043] The allowed components include, for example, specific components to be used or an indication of the allowed basic inventory or the allowed technology node (e.g., specified in the form of a process development kit (PDK) describing the available standard cells) or the like.

[0044] In some embodiments, the circuit design task is directed towards synthesizing analog circuits specifically designed for integration as ICs (“Integrated Circuits”), with an emphasis on circuits for analog computing. Analog computing allows circuits to perform arithmetic tasks, such as adding voltages or currents or executing nonlinear functions. Moreover, analog circuits have the potential to implement entire neural networks, which can offer lower latency / less power consumption compared to the digital counterparts (GPUs / CPUs). This may be beneficial in usecases such as real-time control of robots, where fast responses from a policy network, which determines the behavior of the robot, are critical.

[0045] Hence, in some embodiments, the circuit design task is a task for designing an integrated circuit.

[0046] In some embodiments, the integrated circuit is a circuit that is configured to perform analog computing. In some embodiments, the integrated circuit is a circuit that represents a machine learning system. In some embodiments, the integrated circuit is a circuit that represents a neural network, i.e. the machine learning system is or is based on a neural network.

[0047] In some embodiments, the circuitry is configured to use a machine learning dataset to generate a reward signal indicating a performance of the machine learning system with respect to a certain machine learning task, as will also be discussed in more detail under reference of Fig. 1 below.

[0048] The reward signal generation configuration may include at least one of information about evaluation modules to be used for evaluating a circuit design, information about how reward signals are generated based on the evaluation results from the different evaluation modules, information about a weighting and / or a combination function of individual reward signals to generate the overall reward signal and information about predetermined rules and / or analytical models to be used by a heuristic evaluation module.

[0049] To receive a user input the information processing apparatus provides a graphical user interface in some embodiments. The graphical user interface may use, for instance, an API (“Application Programming Interface”) to process the user input and to provide the task description and the reward signal generation configuration, for example, to the combination module which provides the task description to the circuit generator.

[0050] Instead of the user having to provide the task description and the reward signal generation configuration directly via a graphical user interface, the user may provide a text prompt to an Al (“Artificial Intelligence”) agent that provides them based on the text prompt.

[0051] Hence, in some embodiments, a text prompt is received from the user via the user interface, and the circuitry is configured to provide the text prompt to an artificial intelligence agent that is configured to generate, based on the text prompt, the task description and the reward signal generation configuration, as will also be discussed in more detail under reference of Fig. 1 below.

[0052] In response to the provided task description, in some embodiments, the circuit generator starts generating iteratively circuits, for example, in each iteration cycle, the circuit generator adds a component, an internal net, a connection between a component terminal and a net or adjusts parameters of the components (e.g., increasing or decreasing a resistance value of a resistor or changing sizes of the component). Typically, in some embodiments, the circuit generator is trained based on reinforcement learning such that the circuit generator learns in the long run which actions in which situations has led to increasing reward.

[0053] The information processing apparatus thus iteratively generates with the circuit generator circuit designs and provides the circuit designs to the plurality of evaluation modules, for example, based on the reward signal generation configuration or based on a predefined configuration indicating which evaluation modules are to be used.

[0054] As mentioned above, for an (analog) circuit, there does typically not exist a single metric which would sufficiently represent a performance of the circuit for many different applications.

[0055] Hence, a plurality of different evaluations of the circuit design should be performed and taken into account when generating a reward for training the circuit generator to solve the circuit design task.

[0056] As mentioned above, the information processing apparatus receives from each of a plurality of evaluation modules an evaluation result of a circuit design.

[0057] In some embodiments, the plurality of evaluation modules includes a heuristics evaluation module, a simulation evaluation module, and a layout evaluation module, as will also be discussed in more detail under reference of Fig. 1 below.

[0058] In some embodiments, the circuitry is configured to provide the plurality of evaluation modules, and each of the heuristics evaluation module, the simulation evaluation module and the layout evaluation module is implemented as a neural network, as will also be discussed in more detail under reference of Fig. 1 below.

[0059] In some embodiments, the circuitry is configured to receive a process development kit specifying a technology node for circuit fabrication, and to provide information from the process development kit to the simulation evaluation module and the layout evaluation module, as will also be discussed in more detail under reference of Fig. 1 below.

[0060] Each evaluation module performs an evaluation of the circuit design and provides an evaluation result, based on which reward signals are generated as feedback to the circuit generator.

[0061] In some embodiments, the information processing apparatus generates, for each evaluation result and based on the reward signal generation configuration, a reward signal and generates an overall reward signal by combining, based on the reward signal generation configuration, the individual reward signals, as will also be discussed in more detail under reference of Fig. 1 below. The overall reward signal thus includes a plurality of different contributions to the overall reward, which may also be conflicting contributions such that a Pareto-optimal circuit design may be reached.

[0062] However, the user may dynamically adapt the weighting of the individual contributions or the combination function for combining the individual contributions to guide the circuit generator into a specific direction which may be suitable with respect to the application in some characteristics.

[0063] As mentioned above, the information processing apparatus adapts the circuit design based on the overall reward signal.

[0064] Thus, the circuit generator learns in the long run, based on an overall reward signal, whether certain actions (e.g., adding a component) are useful to increase the reward such that the generated circuits may improve over time.

[0065] In some embodiments, the information processing apparatus displays the (current) circuit design and reward signals to the user via the user interface.

[0066] In this way, the user can verify the circuit design and the user receives information about the different individual reward signals such that the user may be able to adapt the reward signal generation configuration to push the circuit generator into a certain direction.

[0067] In some embodiments, the reward signals are displayed in a treemap visualization to the user.

[0068] Such a visualization may allow the user to quickly grasp conflicting reward signals. For example, the distance between the branches is adapted based on whether the reward signals tend in the same direction or not and / or based on how large the influence of the reward signal is on the overall reward signal.

[0069] Generally, the circuitry of the information processing apparatus may also be configured to provide the plurality of evaluations modules and / or the circuit generator.

[0070] Some embodiments pertain to a (corresponding) information processing method for assisting a user in a circuit design task, wherein the information processing method includes: receiving a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generating, based on the task description, circuit designs; receiving, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generating an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapting the circuit design based on the overall reward signal.

[0071] The information processing method may be performed by the information processing apparatus as described herein.

[0072] The methods as described herein are also implemented in some embodiments as a computer program causing a computer and / or a processor to perform the method, when being carried out on the computer and / or processor. In some embodiments, also a non-transitory computer- readable recording medium is provided that stores therein a computer program product, which, when executed by a processor, such as the processor described above, causes the methods described herein to be performed.

[0073] Returning to Fig. 1, which schematically illustrates in a block diagram an embodiment of a circuit synthesis system 1, which is discussed in the following.

[0074] The circuit synthesis system 1 includes a user interface 2, a combination module 3, a circuit generator 4, a heuristics evaluation module 5, a simulation evaluation module 6, a layout evaluation module 7, a DRC and LVS evaluation module 8 and a parasitic extractor evaluation module 9.

[0075] The circuit synthesis system 1 includes one or more information processing apparatus (not shown) to provide the different modules, for example, a first information processing apparatus may provide the user interface 2, the combination module 3 and the circuit generator 4, and a second information processing apparatus may provide the plurality of evaluation modules 5, 6, 7, 8 and 9.

[0076] The circuit synthesis system 1 assists a user 10 in a circuit design task, wherein the user 10 interacts with the circuit synthesis system 1 via the user interface 2.

[0077] The circuit design task is not particularly limited and may be, for example, a sizing of a circuit with fixed topology using a surrogate model to meet testbench requirements after post-layout extraction of parasitics.

[0078] The circuit design task may also correspond to finding a topology of a circuit and components to meet certain input / output requirements, for example, for performing analog computing to perform (complex) math operations, which may reduce latency in high-speed computing and robotics where a lot of computational power is required (e.g., for path planning) but at the same time should be low latency. For example, analog compute-in-memory may be desired (for reducing memory transfer), or the analog circuits may represent a neural network (for speeding- up computations or reducing latency).

[0079] The user 10 then inputs a task description and a reward signal generation configuration via the user interface 2.

[0080] The task description includes the input / output characteristics and allowed components to be used for designing the circuit.

[0081] The reward signal generation configuration includes an indication which evaluation modules to be used, a weighting for reward signals, the reward signal generation functions and one or more rules for the heuristics evaluation module 5.

[0082] Instead of having the user to provide the task description and the configuration for the combination module 3 and the evaluation modules (denoted as “Scheme 1” in Fig. 1), a machine learning system 11 (“Al agent”) can be used that provides the configuration (e.g., controlled with a text prompt received via the user interface 2) - this approach is denoted as “Scheme 2” in Fig. 1 and illustrated by dotted lines. Besides being controlled by a text prompt, the Al agent 11 can also work in an iterative way where the Al agent 11 has as another input the best circuit that was found for the configuration from the previous iteration and where the Al agent 11 can update the configuration in order to obtain the desired results.

[0083] As mentioned also above, there is typically not a single metric and evaluation forjudging a circuit design with respect to a certain application.

[0084] Hence, in this embodiment, five evaluation modules are used for evaluating circuit designs generated by the circuit generator 4, i.e. the heuristics evaluation module 5, the simulation evaluation module 6, the layout evaluation module 7, the DRC and LVS evaluation module 8 and the parasitic extractor evaluation module 9, which will be described in more detail in the following.

[0085] The circuit generator 4 generates a circuit representation of a circuit, for example, a circuit may be represented by a graph which can be converted into a netlist. Then, the circuit generator provides the circuit representation to the combination module 3.

[0086] Based on the reward signal generation configuration, the combination module 3 provides a netlist of the circuit representation to the different evaluation models 5, 6, 7, 8 and 9 to obtain evaluation results of the circuit design to generate reward signals to fuse together information from different evaluation modules. The heuristics module 5 is intended to evaluate basic design rules and simplified sizing rules (“heuristics”) and simple analytical models. Such rules and models may be provided by the user with the reward signal generation configuration and are intended to move the circuit search into “interesting regions”, since the solution could otherwise get stuck at the beginning as the synthesis algorithm may not know how to generate good circuits in the beginning and only receives negative or poor reward for its initial designs.

[0087] Examples for rules to be evaluated may be a rule that “all transistors should be in saturation region” or for the circuit topology that “there are no floating nets”. Analytical models may include, for example, simple equivalent signal models for components (e.g., transistor).

[0088] Moreover, such rules may correspond to consistency checks such as “there are no floating nets”, “all input / output nets are connected”, “there is a path for each input / output net pair” or “there are no independent subgraphs”.

[0089] The heuristics module 5 then uses the netlist to evaluate the rules to provide heuristic scores as an evaluation result to the combination module 3, for example, it counts the number of transistors with the specified property or the number of floating nets.

[0090] The combination module 3 then uses the heuristic scores to generate a first reward signal, for example, the ratio of the heuristic score specifying the number of transistors with a specific property divided by the total number of transistors.

[0091] To receive further evaluation results, the combination module 3 provides the netlist to the simulation evaluation module 6 that is able to run testbench simulations using SPICE to obtain performance metrics as an evaluation result.

[0092] In this embodiment, the user 10 may further provide a PDK (“Process Development Kit”) to the combination module 3 using the user interface 2. The PDK specifies the technology node for circuit fabrication. The PDK provides essential details, such as minimum wire spacings and available standard cells (resistors, capacitors, transistors), which are required for both SPICE simulations and the automated layout needed to pass LVS (“layout vs. schematic checks”) and DRC (“Design Rule Checks”) checks.

[0093] For analog design, besides using heuristics and analytical models (e.g., simplified sizing rules or simple equivalent signal models for transistors), as mentioned above, the circuit synthesis system 1 uses testbenches which evaluate the circuit by specifying inputs and output loads for the circuit and running SPICE (“Simulation Program with Integrated Circuit Emphasis”) simulations. Performance metrics from this evaluation can, e.g., be open-loop gain, step responses, output voltages for various input voltages etc.

[0094] The simulation evaluation module 6 outputs the performance metrics to the combination module 3, wherein the performance metrics are not particularly limited and may encompass various electrical characteristics of the circuit design which may be obtained from testbenches or SPICE simulations.

[0095] For illustration, the above table shows example tasks descriptions and the reward signals for the simulation evaluation module 6. The second reward signal that is generated by the combination module 3 is based on the evaluation result of the simulation evaluation module 6.

[0096] In the table above, the tasks are to design a circuit for voltage division, lowpass filtering, XOR operation and Iris classification.

[0097] The PDK used here is the Skywaterl30 PDK.

[0098] The combination module 3 receives the performance metrics as the evaluation result from the simulation evaluation module 6.

[0099] In addition to the performance metrics, the analog circuit may be tested on known input-output pairs, where its output is compared with a “ground truth” target (e.g., in SPICE simulations). This setup enables designing and refining an analog circuit capable of performing tasks like classification, traditionally handled by digital circuits or GPUs. The reward could then be, for example, accuracy or log-likelihood which is to be maximized.

[0100] For the Iris classification task, the user 10 has provided an additional machine learning dataset via the user interface 2 such that the reward signal can be calculated based on the machine learning dataset. The input feature values for the machine learning system (here: classification system) can be either represented as voltages or currents that are provided at the input. For example, in case of using voltages, we can use 0V to represent a (normalized) feature value of “0” and 1.8 V if we design a circuit with the Sky water PDK to represent a (normalized) feature value of “1” and there are as many input nets as features (here: four input nets as the Iris dataset has four features for each sample). Alternatively, feature values might be expressed using a specific transient waveform, e.g., a pulse-coded modulated voltage waveform which is used to express the feature values of a sample. Furthermore, the output of the circuit can consist of as many output nets as there are classes (here: 3 output nets) where we decide for the class whose output voltage is largest, i.e., we use the circuit as a discriminant function. Alternatively, other representations could be used. For example, the class could be represented by a voltage level of a single output net.

[0101] The combination module 3 generates the second reward signal based on the performance metrics from the simulation evaluation module 6 and may further use the additional machine learning dataset depending on the task. Another evaluation aspect is the layout, i.e., the 3d (“three-dimensional”) realization of the circuit. Using tools for automatic layouting, the combination module 3 can verify how easy it is to layout the proposed circuit.

[0102] Hence, to receive further evaluation results, the combination module 3 provides the netlist to the layout evaluation module 7 that uses an automatic layouter to determine a layout based on which the layout evaluation module 7 provides layout scores as an evaluation result to the combination module 3.

[0103] The layout scores may include, for example, a routability score, a number of wire crossings, a wire length, volume of physical design, number of layers, etc.

[0104] The combination module 3 generates a third reward signal based on the layout scores.

[0105] Furthermore, with the layout, a DRC check and LVS evaluation module 8 performs a DRC and LVS check and provide the check results as an evaluation result to the combination module 3.

[0106] Moreover, with the layout, parasitic capacitances and resistances are extracted to check, by parasitic extractor evaluation module 9, which can be used to check that the circuit behaves as anticipated and that, e.g., there is sufficiently small crosstalk between sensitive nets. Such results are output as parasitic scores as an evaluation result to the combination module 3.

[0107] The combination module 3 generates a fourth and fifth reward signal based on the check results and the parasitic scores, respectively.

[0108] Once the combination module 3 has computed the first reward signal, the second reward signal, the third reward signal, the fourth reward signal and the fifth reward signal, it uses the weighting specified with the reward signal generation configuration for combining the first reward signal, the second reward signal, the third reward signal, the fourth reward signal and the fifth reward signal to generate the overall reward signal and provide it to the circuit generator 4 to adapt the circuit design based on the overall reward signal. Besides using a weighting scheme to combine the reward signals, it is also possible to specify more general combination functions like using the “min” or “max” or “median”. E.g., the “min” combination results in a circuit design taking into account the worst-case reward feedback from one of the reward modules.

[0109] Moreover, the circuit design and first reward signal, the second reward signal, the third reward signal, the fourth reward signal and the fifth reward signal are displayed to the user 10 via the user interface 2.

[0110] This may allow to identify conflicting design requirements. By decomposing the overall reward into multiple components, the system can reveal “negative correlations” where boosting one reward may reduce another. This insight is presented to the user 10 through a treemap visualization, which organizes rewards based on alignment (close for aligned, distant for conflicting), helping users balance trade-offs more effectively. Giving this insight is especially important if hard constraints (DRC, LVS) are not met, and it is not clear which other reward is yielding this undesired behavior.

[0111] This may allow the user also to adapt the weighting for the different reward signals dynamically when the circuit generator 4 generates more and more circuits over time. For example, a high weighting may be used for the reward signal generated based on the heuristic scores to push the circuit generator 4 into a certain useful direction and then this weighting may be lowered over time to improve functionality or layout of the circuit design.

[0112] In general, in the circuit synthesis system 1, each block can be “surrogated”, i.e., replaced by a neural network which learned from input / output pairs to predict the behavior of the block. Furthermore, even the whole combination module 3 together with all evaluation modules 5, 6, 7, 8 and 9 may be surrogated such that a single neural network is obtained that has as input the “circuit” in form of a netlist as well as the “reward signal generation configuration” (configuration for the combination module 3) and returns the overall reward signal.

[0113] As discussed above, the circuit synthesis system 1 has a reward where the user 10 can define the aggregation function according to his needs (e.g., using an API which allows this, e.g., allowing the user to provide a vector of weights that are used to compute the overall reward).

[0114] Moreover, the circuit synthesis system 1 has a GUI (“graphical user interface”) which displays several reward signals and showing the Pareto-optimal designs graphically to the user 10 such that the user 10 can see trade-offs and choose the best circuit for the application.

[0115] In order to implement the configurable reward, for example, an API is exposed to the user which allows the user to give a configuration for the combination module. For example, the user 10 might specify the weight for each reward component through this configuration. This API is exposed to the user 10 and documented.

[0116] Furthermore, the circuit synthesis system 1 has a circuit synthesis framework that might leverage an additional dataset to train a machine learning system, for example, a neural network, optimizing it for a specific machine learning task.

[0117] Additionally, the reward combination module 3 might utilize the PDK to perform automatic layout and SPICE simulation, ensuring designs align with manufacturing constraints. Accordingly, using the proposed configurable reward, the user 10 can adapt the synthesis framework for many different applications and use it to find novel circuits that fit to his needs.

[0118] Fig. 2 schematically illustrates a circuit generation process, which is discussed in the following.

[0119] As discussed herein and in particular under reference of Fig. 1, the circuit generator 4 receives a task description and an overall reward signal and, thus, learns over time to solve the task based on the overall reward signal, e.g., by maximizing the reward signal over time.

[0120] The circuit generator 4 may use a graph sampler that is trained by reinforcement learning based on a policy gradient method.

[0121] The input to the circuit generator 4 is the latest circuit design and the circuit generator 4 computes the probability of the next action, the probability of adding another component and which component, component parameters and a connection probability.

[0122] Finally, the reward signals that are considered might be floating point numbers, e.g., in the range of [-1, 1] where “-1” represents a poor reward and “1” represents the best reward. Alternatively, the reward signal provided by one of the modules or by the combination module 3 itself may be a Boolean to indicate that a certain test or several tests have passed. This might be used to ensure that the circuit is valid and passes all testbenches which were provided in the configuration. The combination function in this case might then, e.g., be the “logical and” or “logical or” operations to obtain an overall reward that is fed back to the Circuit Generator 4. Furthermore, the reward signals might be mixed, i.e., consist of parts that are floating point numbers and parts which correspond to Booleans which are combined in the combination module into a signal reward signal that is fed back to the Circuit Generator 4. As an example for this, consider the following combination function where ' all_testbenches_passed' is Boolean and provided by module 6 whereas 'Layout Reward' is a floating point number provided by 7:

[0123] - 1 if not ' all_testbenches_passed' combined reward =

[0124] Layout Reward if ' all_testbenches_passed'

[0125] As depicted in Fig. 2, the seed graph at t = 0 includes only the input / output nets.

[0126] Then, the circuit generator 4 may randomly, based on the probabilities, add an internal net at t = 1.

[0127] Then, at t = 2, a component and connections may be added.

[0128] After a number of time steps T, the final circuit may be provided. At each step, the circuit design might be evaluated as discussed above and the overall reward signal is provided to the circuit generator 4 to learn over time which actions increase the reward. Alternatively, the reward signal might only be provided at the end of the sampling step such that the combination module 3 only evaluates the final circuit obtained after T steps.

[0129] Fig. 3 A schematically illustrates a generated circuit, which fails to pass consistency checks.

[0130] As discussed above, the heuristics module 3 may be configured with rules for consistency checks to tune the reward signal.

[0131] The consistency checks include “there are no floating nets”, “all input / output nets are connected”, “there is a path for each input / output net pair” or “there are no independent subgraphs”.

[0132] The circuit design depicted in Fig. 3 A only passes the check that there are no floating nets.

[0133] Fig. 3B schematically illustrates a generated circuit, which fails to pass consistency checks.

[0134] The circuit design depicted in Fig. 3B only fails in that there are no independent subgraphs which translates into independent circuits when converting the graph into a circuit.

[0135] Fig. 4 schematically illustrates in a flow diagram an embodiment of an information processing method 100, which is discussed in the following.

[0136] At 101, a task description of a circuit design task and a reward signal generation configuration is received from a user via a user interface, as discussed herein.

[0137] At 102, circuit designs are generated, based on the task description, as discussed herein.

[0138] At 103, an evaluation result of a circuit design is received from each of a plurality of evaluation modules, as discussed herein.

[0139] At 104, an overall reward signal is generated, based on the evaluation results and the reward signal generation configuration, as discussed herein.

[0140] At 105, the circuit design is adapted based on the overall reward signal, as discussed herein.

[0141] At 106, the circuit design and reward signals are displayed to the user, as discussed herein.

[0142] Fig. 5 schematically illustrates in a block diagram and embodiment of a multi-purpose computer 130, which is discussed in the following.

[0143] The computer 130 can be implemented such that it can basically function as any type of information processing apparatus as described herein. The computer has components 131 to 141, which can form a circuitry, such as any one of the circuitries of the information processing apparatus as described herein.

[0144] Embodiments which use software, firmware, programs or the like for performing the methods as described herein can be installed on computer 130, which is then configured to be suitable for the concrete embodiment.

[0145] The computer 130 has a CPU 131 (Central Processing Unit), which can execute various types of procedures and methods as described herein, for example, in accordance with programs stored in a read-only memory (ROM) 132, stored in a storage 137 and loaded into a random-access memory (RAM) 133, stored on a medium 140 which can be inserted in a respective drive 139, etc.

[0146] The CPU 131, the ROM 132 and the RAM 133 are connected with a bus 141, which in turn is connected to an input / output interface 134. The number of CPUs, memories and storages is only exemplary, and the skilled person will appreciate that the computer 130 can be adapted and configured accordingly for meeting specific requirements which arise, when it functions as an information processing apparatus.

[0147] At the input / output interface 134, several components are connected: an input 135, an output 136, the storage 137, a communication interface 138 and the drive 139, into which a medium 140 (compact disc, digital video disc, compact flash memory, or the like) can be inserted.

[0148] The input 135 can be a pointer device (mouse, graphic table, or the like), a keyboard, a microphone, a camera, a touchscreen, etc.

[0149] The output 136 can have a display (liquid crystal display, cathode ray tube display, light emittance diode display, etc.), loudspeakers, etc.

[0150] The storage 137 can have a hard disk, a solid-state drive and the like.

[0151] The communication interface 138 can be adapted to communicate, for example, via a local area network (LAN), wireless local area network (WLAN), mobile telecommunications system 30 (GSM, UMTS, LTE, NR etc.), Bluetooth, infrared, etc.

[0152] It should be noted that the description above only pertains to an example configuration of computer 130. Alternative configurations may be implemented with additional or other sensors, storage devices, interfaces or the like. For example, the communication interface 138 may support other radio access technologies than the mentioned UMTS, LTE and NR. It should be recognized that the embodiments describe methods with an exemplary ordering of method steps. The specific ordering of method steps is however given for illustrative purposes only and should not be construed as binding.

[0153] All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, if not stated otherwise, be implemented by software.

[0154] In so far as the embodiments of the disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be appreciated that a computer program providing such software control and a transmission, storage or other medium by which such a computer program is provided are envisaged as aspects of the present disclosure.

[0155] Note that the present technology can also be configured as described below.

[0156] (1) An information processing apparatus for assisting a user in a circuit design task, wherein the information processing apparatus includes circuitry configured to: receive a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generate, based on the task description, circuit designs; receive, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generate an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapt the circuit design based on the overall reward signal.

[0157] (2) The information processing apparatus of (1), wherein the circuitry is configured to display the circuit design and reward signals to the user via the user interface.

[0158] (3) The information processing apparatus of (1) or (2), wherein the circuit design task is a task for designing an integrated circuit.

[0159] (4) The information processing apparatus of (3), wherein the integrated circuit is a circuit that is configured to perform analog computing.

[0160] (5) The information processing apparatus of (3) or (4), wherein the integrated circuit is a circuit that represents a machine learning system. (6) The information processing apparatus of (5), wherein the circuitry is configured to use a machine learning dataset to generate a reward signal indicating a performance of the machine learning system with respect to a certain machine learning task.

[0161] (7) The information processing apparatus of any one of (1) to (6), wherein the circuitry is configured to receive a process development kit specifying a technology node for circuit fabrication, and to provide information from the process development kit to a simulation evaluation module and a layout evaluation module.

[0162] (8) The information processing apparatus of any one of (2) to (7), wherein reward signals are displayed in a treemap visualization to the user.

[0163] (9) The information processing apparatus of any one of (1) to (8), wherein the plurality of evaluation modules includes a heuristics evaluation module, a simulation evaluation module and a layout evaluation module.

[0164] (10) The information processing apparatus of any one of (1) to (9), wherein the circuitry is configured to provide the plurality of evaluation modules, and wherein each of the heuristics evaluation module, the simulation evaluation module and the layout evaluation module is implemented as a neural network.

[0165] (11) The information processing apparatus of any one of (1) to (10), wherein a text prompt is received from the user via the user interface, and wherein the circuitry is configured to provide the text prompt to an artificial intelligence agent that is configured to generate, based on the text prompt, the task description and the reward signal generation configuration.

[0166] (12) An information processing method for assisting a user in a circuit design task, wherein the information processing method includes: receiving a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generating, based on the task description, circuit designs; receiving, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generating an overall reward signal, based on the evaluation results and the reward signal generation configuration; adapting the circuit design based on the overall reward signal.

[0167] (13) The information processing method of (12), including displaying the circuit design and reward signals to the user via the user interface. (14) The information processing method of (12) or (13), wherein the circuit design task is a task for designing an integrated circuit.

[0168] (15) The information processing method of (14), wherein the integrated circuit is a circuit that is configured to perform analog computing.

[0169] (16) The information processing method of (14) or (15), wherein the integrated circuit is a circuit that represents a machine learning system.

[0170] (17) The information processing method of (16), including using a machine learning dataset to generate a reward signal indicating a performance of the machine learning system with respect to a certain machine learning task.

[0171] (18) The information processing method of any one of (12) to (17), including receiving a process development kit specifying a technology node for circuit fabrication, and to provide information from the process development kit to a simulation evaluation module and a layout evaluation module.

[0172] (19) The information processing method of any one of (13) to (18), wherein reward signals are displayed in a treemap visualization to the user.

[0173] (20) The information processing method of any one of (12) to (19), wherein the plurality of evaluation modules includes a heuristics evaluation module, a simulation evaluation module and a layout evaluation module.

[0174] (21) The information processing method of any one of (12) to (20), including providing the plurality of evaluation modules, and wherein each of the heuristics evaluation module, the simulation evaluation module and the layout evaluation module is implemented as a neural network.

[0175] (22) The information processing method of any one of (12) to (21), wherein a text prompt is received from the user via the user interface, and wherein the information processing method includes providing the text prompt to an artificial intelligence agent that is configured to generate, based on the text prompt, the task description and the reward signal generation configuration.

[0176] (23) A computer program comprising program code causing a computer to perform the method according to anyone of (12) to (22), when being carried out on a computer. (24) A non-transitory computer-readable recording medium that stores therein a computer program product, which, when executed by a processor, causes the information processing method according to anyone of (12) to (22) to be performed.

Claims

CLAIMS1. An information processing apparatus for assisting a user in a circuit design task, comprising circuitry configured to: receive a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generate, based on the task description, circuit designs; receive, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generate an overall reward signal, based on the evaluation results and the reward signal generation configuration; and adapt the circuit design based on the overall reward signal.

2. The information processing apparatus of claim 1, wherein the circuitry is configured to display the circuit design and reward signals to the user via the user interface.

3. The information processing apparatus of claim 1, wherein the circuit design task is a task for designing an integrated circuit.

4. The information processing apparatus of claim 3, wherein the integrated circuit is a circuit that is configured to perform analog computing.

5. The information processing apparatus of claim 3, wherein the integrated circuit is a circuit that represents a machine learning system.

6. The information processing apparatus of claim 5, wherein the circuitry is configured to use a machine learning dataset to generate a reward signal indicating a performance of the machine learning system with respect to a certain machine learning task.

7. The information processing apparatus of claim 1, wherein the circuitry is configured to receive a process development kit specifying a technology node for circuit fabrication, and to provide information from the process development kit to a simulation evaluation module and a layout evaluation module.

8. The information processing apparatus of claim 2, wherein reward signals are displayed in a treemap visualization to the user.

9. The information processing apparatus of claim 1, wherein the plurality of evaluation modules includes a heuristics evaluation module, a simulation evaluation module and a layout evaluation module.

10. The information processing apparatus of claim 1, wherein the circuitry is configured to provide the plurality of evaluation modules, and wherein each of the heuristics evaluation module, the simulation evaluation module and the layout evaluation module is implemented as a neural network.

11. The information processing apparatus of claim 1, wherein a text prompt is received from the user via the user interface, and wherein the circuitry is configured to provide the text prompt to an artificial intelligence agent that is configured to generate, based on the text prompt, the task description and the reward signal generation configuration.

12. An information processing method for assisting a user in a circuit design task, comprising: receiving a task description of the circuit design task and a reward signal generation configuration from the user via a user interface; generating, based on the task description, circuit designs; receiving, from each of a plurality of evaluation modules, an evaluation result of a circuit design; generating an overall reward signa, based on the evaluation results and the reward signal generation configuration; and adapting the circuit design based on the overall reward signal.

13. The information processing method of claim 12, comprising displaying the circuit design and reward signals to the user via the user interface.

14. The information processing method of claim 12, wherein the circuit design task is a task for designing an integrated circuit.

15. The information processing method of claim 14, wherein the integrated circuit is a circuit that is configured to perform analog computing.

16. The information processing method of claim 14, wherein the integrated circuit is a circuit that represents a machine learning system.

17. The information processing method of claim 16, comprising using a machine learning dataset to generate a reward signal indicating a performance of the machine learning system with respect to a certain machine learning task.

18. The information processing method of claim 12, comprising receiving a process development kit specifying a technology node for circuit fabrication, and to provide informationfrom the process development kit to a simulation evaluation module and a layout evaluation module.

19. The information processing method of claim 13, wherein reward signals are displayed in a treemap visualization to the user.

20. The information processing method of claim 12, wherein the plurality of evaluation modules includes a heuristics evaluation module, a simulation evaluation module and a layout evaluation module.

21. The information processing method of claim 12, comprising providing the plurality of evaluation modules, and wherein each of the heuristics evaluation module, the simulation evaluation module and the layout evaluation module is implemented as a neural network.

22. The information processing method of claim 12, wherein a text prompt is received from the user via the user interface, and wherein the information processing method comprises providing the text prompt to an artificial intelligence agent that is configured to generate, based on the text prompt, the task description and the reward signal generation configuration.

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