Power conversion device and switching signal generation method

Abstract

Provided are a compact power conversion device and a switching signal generation method capable of suppressing current imbalance at an output timing of all current values that respective power converters can output (hereinafter referred to as a total current condition). The power conversion device supplies output currents of at least two power converters connected in parallel to an external load. The power conversion device comprises: a storage device that stores a plurality of adjustment times corresponding to the respective values of the output currents; a control device that generates a pulse command on the basis of a command value input from the outside and determines adjustment times corresponding to the values of the output currents among the plurality of adjustment times stored in the storage device; a time adjustment circuit to which the pulse command and the adjustment times are input from the control device and which generates a gate voltage command obtained by delaying the pulse command by the adjustment times; and a gate drive circuit to which the gate voltage command is input from the time adjustment circuit, and which generates a switching signal for each of the power converters on the basis of the gate voltage command and outputs the switching signal to each of the power converters.

Description

Power Conversion Device and Switching Signal Generation Method

[0001] The present invention relates to a power conversion device and a switching signal generation method.

[0002] A power conversion device can convert DC power into AC power or AC power into DC power by the switching (on / off) operation of semiconductor elements, and is widely applied from the field of small power such as home appliances to the fields of medium and large power such as elevators, automobiles, and railways.

[0003] In order to increase the capacity of the power conversion device, for reasons such as the market availability of components, the defect rate of components, and cost reduction, multiple power converters may be connected in parallel to increase the total capacity.

[0004] However, when multiple power converters are connected in parallel without any particular countermeasures, due to factors such as variations in the characteristics of the semiconductor elements constituting each power converter, the switching timing of the semiconductor elements will shift, and a potential difference will occur at the output of each power converter. For example, when two power converters are connected in parallel and the on / off (rise / fall) timing of the voltage at the output of one power converter is Δt earlier than the on / off (rise / fall) timing of the voltage at the output of the other power converter, from when the voltage at the output of one power converter turns on until the voltage at the output of the other power converter turns on, and also from when the voltage at the output of one power converter turns off until the voltage at the output of the other power converter turns off, a difference in output voltage (potential difference) will occur between the outputs of the two power converters during each Δt.

[0005] As described above, when a potential difference occurs at the output of each power converter connected in parallel, current (crosscurrent) flows through the bus connecting each power converter, causing an imbalance in the output current of each power converter (hereinafter referred to as current imbalance). For example, in the above example, although the output current of both power converters is originally the same at 100A, if a crosscurrent of 50A flows from one power converter to the other due to the potential difference at Δt, the output current of one power converter becomes 150A and the output current of the other power converter becomes 50A, resulting in a current imbalance. Therefore, when determining the current capacity of power converters connected in parallel, it is necessary to add the current imbalance to the load current. For example, in the above example, if the load current is 200A, the current capacity of each power converter should be 100A, but as described above, it is necessary to consider the current imbalance and set it to 150A. This causes a deterioration in the power density of the power converter, so suppression of current imbalance is required.

[0006] As a technique for suppressing current imbalance, for example, Patent Document 1 discloses "an output current balancer for power converters that connects multiple power converters in parallel and supplies AC power to a resonant load having an induction heating load and a resonant capacitor, wherein a series connection circuit of an air-core reactor and a reactor for magnetically coupling the outputs of the multiple power converters is connected to the output of each power converter."

[0007] Japanese Patent Publication No. 2010-193582

[0008] As shown in Patent Document 1, current imbalance can be easily suppressed by providing a reactor on the output side of the power converter, but this requires a reactor with a very large inductance, which makes the reactor itself large. There is a high demand for high power density (miniaturization) in power conversion devices, and therefore the power converter, which is a component of such devices, also needs to be miniaturized. However, if a large reactor is provided to suppress current imbalance, the power conversion device as a whole becomes large, which presents a problem.

[0009] On the other hand, gate pulse time adjustment control is effective in suppressing current imbalance without using a reactor. A gate pulse is a switching signal input to the gate of a semiconductor element to switch the semiconductor element on and off. By inputting a gate pulse to a power converter, the internal semiconductor element turns on in response to the rising edge of the gate pulse, and a voltage is output to the output of the power converter. In gate pulse time adjustment control, a time adjustment circuit is used to adjust the timing of the gate pulse input to each power converter (hereinafter referred to as the gate pulse time) so that the time during which a potential difference occurs at the output of each power converter (Δt in the above example) is minimized.

[0010] Conventionally, gate pulse time adjustment control has involved adjusting the gate pulse time to match the switching characteristics (i.e., the timing of when the semiconductor element turns on and off) at the point of maximum current where the semiconductor element temperature is highest. However, because the amount of variation in the characteristics of semiconductor elements differs depending on the magnitude of the current flowing through them, in the current range smaller than the point of maximum current, the switching characteristics do not match with a gate pulse time adjusted based on the point of maximum current, and a potential difference remains at the output of each power converter. This will be explained in detail using Figure 8.

[0011] Figure 8 shows examples of output current waveforms when there is a current imbalance in the output currents of two power converters A and B connected in parallel. In Figure 8, the two solid lines represent the output current waveforms of power converter A and power converter B, as shown in the figure. The dashed line represents the difference in output current between power converter A and power converter B. As shown in Figure 8, a current imbalance occurs between power converter A and power converter B, meaning that the waveforms of their respective output currents are misaligned. When the gate pulse time is adjusted to match the switching characteristics at the maximum current point of each power converter (the area enclosed by the dotted ellipse in Figure 8), the difference between the output current of power converter A and the output current of power converter B, which corresponds to the current imbalance, becomes small (almost disappears) near the peak value of the output current of each power converter, as shown by the dashed waveform. However, for example, near the zero-crossing point of the output current of each power converter (the point at which the output current becomes 0A), the switching characteristics of each power converter do not match with the above gate pulse time because the amount of variation in the characteristics of the semiconductor elements differs depending on the magnitude of the current flowing through the semiconductor elements. As a result, the difference in the output current of each power converter becomes large, as shown by the dashed waveform. Thus, a problem with conventional gate pulse time adjustment control is the decrease in efficiency of the power converter due to the relative increase in current imbalance, particularly near the zero-crossing point of the output current of the power converters and in the light load (small output current) region.

[0012] The object of the present invention is to provide a compact power converter and a switching signal generation method that can suppress current imbalance at all current values ​​that each power converter can output, including not only the maximum current point of each power converter but also near the zero-crossing point (hereinafter referred to as "all current conditions"), in order to solve the above problems.

[0013] The present invention includes several means for solving at least some of the above problems, but one example is as follows: A power conversion device that supplies the output current of at least two power converters connected in parallel to an external load, comprising: a storage device that stores a plurality of adjustment times corresponding to each value of the output current, a control device that generates a pulse command based on a command value input from the outside and determines the adjustment time corresponding to the value of the output current from the plurality of adjustment times stored in the storage device, a time adjustment circuit that receives the pulse command and the adjustment time from the control device and generates a gate voltage command that delays the pulse command by the adjustment time, and a gate drive circuit that receives the gate voltage command from the time adjustment circuit and generates a switching signal for each of the power converters based on the gate voltage command and outputs it to each of the power converters.

[0014] According to the present invention, current imbalance can be suppressed under all current conditions, from the point when the semiconductor element temperature is at its highest and the output current is at its maximum, to the point when the current is low or the current crosses zero. As a result, a reactor is not required, enabling high power density in the power converter and improved efficiency by reducing losses due to current imbalance.

[0015] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments.

[0016] This figure shows an example of the configuration of the power converter according to the first embodiment. This figure shows an example of the processing procedure for pre-preparation for generating switching signals according to the first embodiment. This figure shows an example of the processing procedure for generating switching signals for each power converter by the power converter according to the first embodiment. This figure shows an example of the correspondence between the output current and adjustment time of the power converter according to the first embodiment. This figure shows an example of the configuration of the power converter according to the second embodiment. This figure shows an example of the processing procedure for generating switching signals for each power converter by the power converter according to the second embodiment. This figure shows an example of the correspondence between the output current and adjustment time of the power converter according to the third embodiment. This figure shows an example of the correspondence between the output current and adjustment time of the power converter in a modified example of the third embodiment. This figure shows an example of the waveform of the output current when there is a current imbalance in the output currents of two power converters connected in parallel.

[0017] Embodiments of the present invention will be described below with reference to the drawings. The embodiments are illustrative examples for explaining the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0018] The position, size, shape, and extent of each component shown in the drawings may not represent the actual position, size, shape, and extent in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, and extent disclosed in the drawings. When there are multiple components having the same or similar function, they may be described using the same reference numeral with different subscripts. Furthermore, when it is not necessary to distinguish between these multiple components, the subscripts may be omitted in the description.

[0019] In embodiments, processing performed by executing a program may be described. Here, the computer executes the program using a processor (e.g., CPU, GPU) and performs processing defined by the program using memory resources (e.g., memory) and interface devices (e.g., communication ports). Therefore, the main entity performing the processing by executing the program may be the processor. Similarly, the main entity performing the processing by executing the program may be a controller, device, system, computer, or node having a processor.

[0020] The main component of the processing performed by executing the program can be an arithmetic unit, and may include dedicated circuits for specific processing. Here, dedicated circuits include, for example, FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), and CPLDs (Complex Programmable Logic Devices).

[0021] The program may be installed on the computer from the program source. The program source may be, for example, a program distribution server or a storage medium readable by the computer. If the program source is a program distribution server, the program distribution server includes a processor and storage resources for storing the program to be distributed, and the processor of the program distribution server may distribute the program to other computers. In addition, in some embodiments, two or more programs may be implemented as a single program, or one program may be implemented as two or more programs.

[0022] Figure 1 shows an example of the configuration of a power converter according to the first embodiment. In Figure 1, the power converter 1 includes a power converter A2, a power converter B3, a current sensor 4, a current detection circuit 5, a control device 6, a time adjustment circuit A7, a time adjustment circuit B8, a gate drive circuit A9, and a gate drive circuit B10. Power converters A2 and B3 are connected in parallel. The same battery 11 is connected to the DC section of each power converter. Each power converter outputs a three-phase AC current, and the phase outputs of each power converter (U1 and U2, V1 and V2, W1 and W2) are connected together for each phase to supply power to the load 12.

[0023] In this embodiment, as described above, an example is shown in which two power converters are connected in parallel. However, the embodiment is not limited to this, and the power conversion device 1 may have three or more power converters connected in parallel. In this embodiment, the power converters are assumed to be inverters, but they may also be rectifiers, converters, or DC-DC converters. Also, as described above, an example is shown in which the battery 11 is connected to the DC section of each power converter. However, for example, an AC voltage source may be connected to the DC section via a DC-DC converter or an AC-DC converter. The load 12 is assumed to be a three-phase AC motor such as an induction motor or a synchronous motor, but it may also be an inductive load, and there may be more than one load 12 connected.

[0024] The current sensors 4 are installed on the current supply path (bus) to the load 12 for each phase, and measure the current supplied to the load 12, i.e., the sum of the output currents of the same phase of each power converter, in real time. The current detection circuit 5 transmits the output current detection value for each phase to the control device 6 based on the input measurement values ​​for each phase. In this embodiment, the current sensors 4 are installed for each phase, but current sensors may be installed on the supply paths for only two phases, and the current for the remaining phase may be calculated.

[0025] As described above, the control device 6 receives output current detection values ​​for each phase from the current detection circuit 5, as well as voltage command values ​​from an external device. The external device refers to a higher-level control device that instructs the power converter 1 to control the load 12 in equipment or facilities (such as electric vehicles or industrial equipment) that are equipped with the power converter 1 and the load 12. Note that the input from the external device to the control device 6 is not limited to voltage command values, but may be various command values ​​that change the operation of the load 12 (for example, command values ​​such as rotational speed). The control device 6 also has a memory device (not shown) and, as will be described later, stores adjustment time information corresponding to each value of the output current for each phase of the power converter in the memory device in advance. Based on the input voltage command values, the control device 6 generates pulse commands to supply the necessary power to the load 12. A pulse command is a pulse signal (control signal) that instructs each gate drive circuit on the output timing of the switching signal input to each power converter. Furthermore, as will be described later, the control device 6 determines the adjustment time information for each phase of each power converter in real time based on the input output current detection values ​​for each phase.

[0026] The time adjustment circuit A7 generates a gate voltage command A for each phase based on the pulse command and the adjustment time information A for each phase input from the control device 6. Similarly, the time adjustment circuit B8 generates a gate voltage command B for each phase based on the pulse command and the adjustment time information B for each phase input from the control device 6.

[0027] The gate drive circuit A9 generates the phase-specific switching signals for power converter A based on the phase-specific gate voltage command A. Similarly, the gate drive circuit B10 generates the phase-specific switching signals for power converter B based on the phase-specific gate voltage command B.

[0028] Figure 2 shows an example of the processing procedure for the preliminary steps for generating switching signals in the first embodiment. In the preliminary steps, first, at S21 in Figure 2, a switching evaluation (indicated as SW evaluation in Figure 2) is performed on power converter A and power converter B. In the switching evaluation, pulse commands are input to each power converter to switch each semiconductor element in each phase that constitutes each power converter from off to on and from on to off. The delay time is measured to determine how long the on and off timing of the voltage of each semiconductor element (collector-emitter voltage if the semiconductor element is an insulated gate bipolar transistor (IGBT), and drain-source voltage if the semiconductor element is a metal-oxide-semiconductor field-effect transistor (MOSFET)) lags relative to the pulse command. Such a switching evaluation is performed for each phase of each power converter, not only at the maximum current point where the semiconductor element temperature is highest, but also under all current conditions. In the subsequent S22, the delay time data measured for each phase of each power converter is stored in the memory device of the control device 6 for each phase of the power converter as adjustment time information corresponding to each value of the output current for each phase. Note that the processing procedure shown in Figure 2 is a preliminary preparation before the operation of the power converter 1 (in order to start operation), and is therefore performed using a different device or system than the power converter 1, or manually.

[0029] Figure 4 shows an example of the correspondence between the output current and adjustment time of a power converter. In Figure 4, the solid line shows the correspondence between the output current and adjustment time of the U phase of power converter A, and the dotted line shows the correspondence between the output current and adjustment time of the U phase of power converter B. In the example shown in Figure 4, for the U phase of power converter A, the output current and adjustment time are in a simple inverse proportion relationship. Similarly, for the U phase of power converter B, the output current and adjustment time are also inversely proportional, but the way inverse proportion is determined changes when the output current reaches a specific value. In reality, the adjustment time is measured using the total current conditions for each phase of each power converter, i.e., the delay time corresponding to all current values ​​that each power converter can output for each phase, as determined by the switching evaluation shown in Figure 2. Therefore, the correspondence between the output current and adjustment time for each phase of each power converter is not a neat inverse proportion relationship as shown in Figure 4. However, it is possible to obtain the correspondence between the output current and adjustment time shown in Figure 4 by, for example, obtaining a linear function equation or a function equation of the second order or higher using linear or curve fitting with the least squares method for all measurement data. In Figure 2, step S22 explains that for each phase of the power converter, measurement data of the delay time under all current conditions is stored in the memory device as adjustment time information corresponding to each value of the output current. However, as described above, a function equation corresponding to the measurement data may be obtained for each phase of the power converter, and these function equations for each phase of the power converter may be stored in the memory device.

[0030] Figure 3 is a diagram showing an example of the procedure for generating switching signals for each power converter by the power converter 1 in the first embodiment. First, in S31 in Figure 3, the output current values ​​of each phase measured in real time by the current sensor 4 are input to the current detection circuit 5, and the output current detection values ​​of each phase are input from the current detection circuit 5 to the control device 6.

[0031] In S32, the control device 6 divides the received output current detection value for each phase by the number of parallel power converters (in this embodiment, two power converters are connected in parallel, so the number of parallel power converters is 2) to convert it into the output current value for each phase per power converter. In S33, the control device 6 refers to the adjustment time information corresponding to each output current value for each phase of each power converter stored in the memory device and determines the adjustment time in real time that corresponds to the output current value for each phase of each power converter calculated in S32. Specifically, the memory device stores adjustment time information corresponding to each output current value for the U phase, V phase, and W phase for each power converter, and the control device 6 refers to this adjustment time information to determine the adjustment time corresponding to the respective output current values ​​(values ​​calculated in S32) for the U phase, V phase, and W phase of power converters A and B. Furthermore, if the memory device stores the function formulas for each phase of each power converter, the control device 6 uses each function formula to calculate the adjustment time corresponding to the output current values ​​(values ​​calculated in S32) of the U, V, and W phases of power converters A and B.

[0032] In S34, the control device 6 inputs the determined (or calculated) adjustment time for each of the U, V, and W phases of power converter A as adjustment time information A to the time adjustment circuit A7, and inputs the determined (or calculated) adjustment time for each of the U, V, and W phases of power converter B as adjustment time information B to the time adjustment circuit B8. In S35, the control device 6 generates a pulse command based on the voltage command value input from the external device, and inputs the generated pulse command to the time adjustment circuit A7 and the time adjustment circuit B8.

[0033] In S36, the time adjustment circuit A7 delays the input pulse command by the adjustment time indicated by the input phase-specific adjustment time information A, thereby generating a phase-specific gate voltage command A adjusted to suppress current imbalance in each phase of the corresponding power converter A, and inputs it to the gate drive circuit A9. Similarly, the time adjustment circuit B8 delays the input pulse command by the adjustment time indicated by the input phase-specific adjustment time information B, thereby generating a phase-specific gate voltage command B adjusted to suppress current imbalance in each phase of the corresponding power converter B, and inputs it to the gate drive circuit B10.

[0034] In S37, the gate drive circuit A9 generates a phase-specific switching signal for power converter A based on the phase-specific gate voltage command A, and inputs it to power converter A. Similarly, the gate drive circuit B10 generates a phase-specific switching signal for power converter B based on the phase-specific gate voltage command B, and inputs it to power converter B. Each gate drive circuit generates and outputs a phase-specific switching signal that is approximately identical to the input phase-specific gate voltage command. As a result, each switching signal is adjusted to suppress current imbalance in each phase of the corresponding power converter.

[0035] In each power converter, the on / off state of each semiconductor element is switched according to the phase-specific switching signals input from each gate drive circuit. However, because each switching signal is adjusted as described above, the on / off timing (switching characteristics) of the phase-specific semiconductor elements in each power converter are roughly consistent. As a result, the time during which a potential difference occurs at the output of each power converter is minimized or eliminated, and current imbalance in each phase of each power converter is suppressed. Furthermore, because the power converter 1 constantly performs the above switching signal generation processing procedure, current imbalance in each phase of each power converter is constantly suppressed (the suppressed state is maintained).

[0036] As described above, the power converter in the first embodiment determines adjustment time information corresponding to the output current value of each phase of each power converter in real time based on the output current value of each phase supplied to the load from the power converters connected in parallel, and adjusts the input timing of the switching signal to each power converter for each phase according to the adjustment time information for each phase of each power converter, thereby suppressing current imbalance in each phase of each power converter. Furthermore, the power converter can constantly suppress current imbalance in each phase of each power converter under all current conditions by constantly executing the switching signal generation process that adjusts the input timing to each phase of each power converter, regardless of the magnitude of the output current value of each phase supplied to the load.

[0037] In the first embodiment, an example was shown in which the power converter 1 is equipped with a current sensor 4 and a current detection circuit 5, and the current value supplied to the load 12 is directly measured and detected. However, due to the effects of current detection delay and control delay, the effect of suppressing current imbalance may be insufficient. In such cases, it is effective to estimate the current value supplied to the load 12 rather than to detect it. In the second embodiment, an example of the configuration of such a power converter will be described. Note that in the following description, explanations that overlap with the first embodiment will be omitted, and only the differences will be described.

[0038] Figure 5 shows an example of the configuration of the power converter of the second embodiment, and the same reference numerals are used for components identical to those of the power converter 1 shown in Figure 1. In Figure 5, the power converter 50 includes a power converter A2, a power converter B3, a control device 6, a time adjustment circuit A7, a time adjustment circuit B8, a gate drive circuit A9, and a gate drive circuit B10, similar to the power converter 1 shown in Figure 1. In addition, instead of a current sensor and a current detection circuit, it includes an output current value estimation device 51 that estimates the output current value from the current phase and the output current command value.

[0039] Figure 6 shows an example of the procedure for generating switching signals for each power converter by the power converter 50 in the second embodiment. The processes from S62 to S67 in Figure 6 are the same as the processes from S32 to S37 in the procedure for generating switching signals for each power converter by the power converter 1 shown in Figure 3, with only S61 in Figure 6 being different from S31 in Figure 3.

[0040] In S61 in Figure 6, the output current value estimation device 51 estimates the output current value for each phase supplied to the load 12 from the current phase and the output current command value. The current phase can be calculated from the load power factor, and the output current command value can be calculated from the d and q axis current command values. The output current value estimation device 51 calculates the current phase and output current command value from the load power factor and d and q axis current command values ​​input from an external device, and estimates the output current value for each phase. In this embodiment, as described above, the output current value estimation device 51 estimates the output current value for each phase from the current phase and the output current command value, but it is not limited to this, and the output current value estimation device 51 may estimate the output current value using other methods, such as using information from current sensorless control.

[0041] As explained above, the power conversion device in the second embodiment provides the same effects as the first embodiment, and also makes it possible to sufficiently suppress current imbalance without being affected by current detection delays caused by current sensors or current detection circuits.

[0042] In the first embodiment, an example was shown in which the control device's memory device stores adjustment time information corresponding to each phase output current value under all current conditions for each power converter. In this way, the larger the amount of data (adjustment time corresponding to the output current value) stored in the memory device, the greater the effect of suppressing current imbalance. However, as the output current values ​​are subdivided and the number of power converters connected in parallel increases, the amount of data stored in the memory device becomes enormous, requiring a memory device capable of storing such a large amount of data, i.e., a memory device with a large storage capacity. Therefore, in the third embodiment, an example of a power converter configuration that can reduce the amount of data stored in the memory device will be described. The configuration of the power converter in the third embodiment is the same as that shown in Figure 1 or Figure 5. The procedure for generating switching signals for each power converter by the power converter is also the same as that shown in Figure 3 or Figure 6. In the following description, the explanation of content that overlaps with the first or second embodiment will be omitted, and the differences will be described.

[0043] Figure 7A shows an example of the correspondence between the output current and adjustment time of a power converter in the third embodiment. In Figure 7A, the solid circle indicates the correspondence between the output current and adjustment time of the U phase of power converter A, and the dotted circle indicates the correspondence between the output current and adjustment time of the U phase of power converter B. In the third embodiment, the output current value is divided into two regions based on its magnitude: a high-current region and a specific region where the current value is smaller. For each phase of each power converter, only two correspondences are stored in the memory: the adjustment time corresponding to the output current value included in the high-current region, and the adjustment time corresponding to the output current value included in the specific region. In the first embodiment, as shown in Figure 4, the correspondence between each output current value and the adjustment time was stored in the memory for each phase of each power converter. Compared to that, the amount of data stored in the memory is significantly reduced according to the third embodiment.

[0044] However, according to the third embodiment, since the adjustment of the switching signals for each phase of each power converter is performed only at two adjustment times, there is a possibility that the effect of suppressing current imbalance cannot be sufficiently obtained. Therefore, a modified example that enhances the effect of suppressing current imbalance while reducing the amount of data stored in the storage device will be described using FIG. 7B. FIG. 7B is a diagram showing an example of the correspondence between the output current of the power converter and the adjustment time in a modified example of the third embodiment. Also in FIG. 7B, the solid round marks indicate the correspondence between the output current of the U phase of the power converter A and the adjustment time, and the dotted round marks indicate the correspondence between the output current of the U phase of the power converter B and the adjustment time. Also in this modified example, similar to the example shown in FIG. 7A, the value of the output current is divided into two regions, a large current region and a specific region, and for each phase of each power converter, the adjustment time corresponding to the output current value included in the large current region, and a plurality of adjustment times corresponding to a plurality of output current values included in the specific region, are stored in the storage device as a plurality of correspondence relationships.

[0045] In the examples shown in FIGS. 7A and 7B, the specific region is set as a region where the current value is smaller than the large current region. However, the specific region is selected from, for example, a region where the variation in the switching characteristics of the semiconductor elements constituting each power converter is significant. Thereby, in a region where such variation in the switching characteristics is significant, that is, where the current imbalance is large, the adjustment of the switching signal is finely performed by a plurality of adjustment times corresponding to a plurality of output current values, so that while reducing the amount of data stored in the storage device, it is possible to more effectively suppress the current imbalance in a region where the variation in the switching characteristics is significant. Note that the specific region is not limited to a region where the output current value is small as shown in FIGS. 7A and 7B, and may be a region where the output current value is medium, etc., as long as it is a region where the variation in the switching characteristics of the switching element is significant. In that case, the region may be divided into three or more regions, for example, a small current region, a specific region, and a large current region.

[0046] As described above, according to the power conversion device in the third embodiment and its modified example, in addition to the same effects as in the first and second embodiments, it is possible to significantly reduce the amount of data stored in the storage device provided in the control device.

[0047] The embodiments and modifications of the present invention have been described above, but the present invention is not limited to the examples of embodiments described above, and various modifications are included. For example, the examples of embodiments described above are described in detail for the purpose of making the present invention easy to understand, and the present invention is not limited to having all the configurations described herein. Furthermore, it is possible to replace a part of the configuration of one example of an embodiment with the configuration of another example. Furthermore, it is possible to add a configuration of another example to the configuration of one example of an embodiment. Furthermore, it is possible to add, delete, or replace a part of the configuration of one example of each embodiment with a configuration of another. In addition, some or all of the above configurations, functions, processing units, processing means, etc., may be realized in hardware, for example, by designing them as integrated circuits. Furthermore, the control lines and information lines in the figures are shown only if they are considered necessary for explanation, and do not necessarily show all of them. It can be assumed that almost all of the configurations are interconnected.

[0048] 1, 50... Power converter, 2... Power converter A, 3... Power converter B, 4... Current sensor, 5... Current detection circuit, 6... Control device, 7... Time adjustment circuit A, 8... Time adjustment circuit B, 9... Gate drive circuit A, 10... Gate drive circuit B, 11... Battery, 12... Load, 51... Output current value estimation device

Claims

1. A power conversion device comprising at least two power converters connected in parallel, which supply the output current of the at least two power converters to an external load, the power conversion device comprising: a control device which stores a plurality of adjustment times corresponding to each value of the output current, generates a pulse command based on a command value input from an external source, and determines the adjustment time corresponding to the value of the output current from the plurality of adjustment times stored in the storage device; a time adjustment circuit which receives the pulse command and the adjustment time from the control device and generates a gate voltage command which delays the pulse command by the adjustment time; and a gate drive circuit which receives the gate voltage command from the time adjustment circuit and generates a switching signal for each of the power converters based on the gate voltage command which is output to each of the power converters.

2. A power conversion device according to claim 1, further comprising a current detection circuit for detecting the value of the output current, wherein the control device determines the adjustment time corresponding to the value of the output current detected by the current detection circuit.

3. A power conversion device according to claim 1, further comprising an output current value estimation device for estimating the value of the output current, wherein the control device determines the adjustment time corresponding to the value of the output current estimated by the output current value estimation device.

4. A power conversion device according to claim 2 or claim 3, wherein the storage device stores a plurality of adjustment times corresponding to each value of the output current of each power converter for each power converter, and the control device calculates the value of the output current for each power converter from the detected or estimated value of the output current according to the number of power converters connected in parallel, and determines the adjustment time corresponding to the calculated value of the output current for each power converter.

5. A power converter according to claim 2 or claim 3, wherein each of the power converters outputs a three-phase alternating current, the storage device stores a plurality of adjustment times corresponding to each of the output current values ​​for each phase of each power converter, and the control device calculates the output current value for each phase of each power converter from the detected or estimated output current value for each phase of each power converter according to the number of power converters connected in parallel, and determines the adjustment time corresponding to the calculated output current value for each power converter and each phase.

6. A power converter according to claim 5, wherein each power converter is provided with at least two of the time adjustment circuits and gate drive circuits, each of which generates a gate voltage command for each phase by delaying the pulse command by an adjustment time for each power converter and each phase that has been input, and each of which generates a switching signal based on the gate voltage command for each power converter and each phase that has been input.

7. A power converter according to claim 5, wherein the output current is divided into at least two first current regions and second current regions according to its value, and the storage device stores one adjustment time for each power converter, corresponding to the value of the output current for each phase of the power converter that is included in the first current region, and one or more adjustment times for the value of the output current for each phase that is included in the second current region.

8. A method for generating switching signals in a power converter comprising at least two power converters connected in parallel, which supplies the output currents of the at least two power converters to an external load, the method comprising: storing in advance a plurality of adjustment times corresponding to each value of the output current; generating a pulse command based on a command value input from an external source; determining an adjustment time from the plurality of adjustment times that corresponds to the value of the output current; generating a gate voltage command by delaying the pulse command by the adjustment time; and generating a switching signal for each of the power converters based on the gate voltage command.

9. A switching signal generation method according to claim 8, wherein in the step of determining the adjustment time, the value of the output current is detected, and the adjustment time corresponding to the detected value of the output current is determined.

10. A switching signal generation method according to claim 8, wherein in the step of determining the adjustment time, the value of the output current is estimated, and the adjustment time corresponding to the estimated value of the output current is determined.

11. A switching signal generation method according to claim 9 or claim 10, wherein in the step of storing the adjustment time, a plurality of adjustment times corresponding to each value of the output current of each power converter are stored for each power converter; and in the step of determining the adjustment time, the value of the output current for each power converter is calculated from the detected or estimated value of the output current according to the number of power converters connected in parallel; and the adjustment time corresponding to the calculated value of the output current is determined for each power converter.

12. A switching signal generation method according to claim 9 or claim 10, wherein each of the power converters outputs a three-phase alternating current, in the step of storing the adjustment time, a plurality of adjustment times corresponding to each of the output current values ​​for each phase of each power converter are stored for each power converter, in the step of determining the adjustment time, the value of the output current for each phase is calculated for each power converter according to the number of power converters connected in parallel from the detected or estimated output current values ​​for each phase, and the adjustment time corresponding to the calculated output current value is determined for each power converter and for each phase.

13. A switching signal generation method according to claim 12, wherein in the step of generating a gate voltage command, the gate voltage command for each phase is generated by delaying the pulse command by an adjustment time for each power converter and each phase, and in the step of generating a switching signal, the switching signal is generated based on the gate voltage command for each power converter and each phase.

14. A switching signal generation method according to claim 12, wherein the output current is divided into at least two first current regions and second current regions according to its value, and in the step of storing the adjustment time, for each power converter, one adjustment time is stored for the value of the output current for each phase of the power converter that is included in the first current region, and one or more adjustment times are stored for the value of the output current for each phase that is included in the second current region.

Images