Global shutter pixel and image sensor

Abstract

A global shutter pixel and an image sensor, relating to the technical field of image sensors. The global shutter pixel comprises a photosensitive unit, a transmission unit, a reset unit, an amplifying unit, a storage unit, an output unit, and a port unit; the amplifying unit comprises an amplifier circuit and a filter circuit; a first end of the amplifier circuit serves as an output end of the amplifying unit, a first end of the filter circuit is connected to a second end of the amplifier circuit, and a second end of the filter circuit is connected to the port unit; and the storage unit is connected to the port unit. By means of the output level of the port unit, the voltage outputted by the amplifying unit can be increased, and when a power supply voltage of the pixel is reduced, the voltage outputted by the amplifying unit can be kept unchanged or even increased. By means of the output level of the port unit, the voltage stored in the storage unit can be increased, so that the output of the pixel linearly increases. The filter circuit filters a level signal outputted by the port unit so as to reduce noise and ripple, finally obtaining a high-quality image.

Description

A global shutter pixel and image sensor

[0001] This application claims priority to Chinese Patent Application No. 202411607847.6, filed with the Chinese Patent Office on November 12, 2024, entitled "A Global Shutter Pixel and Image Sensor", and Chinese Patent Application No. 202510136697.3, filed with the Chinese Patent Office on February 7, 2025, entitled "A Global Shutter Pixel and Image Sensor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of image sensor technology, and in particular to a global shutter pixel and image sensor. Background Technology

[0003] As shown in Figure 1, the global shutter pixel structure is an 8T (Transistor) structure. After exposure, the reset signal and photoelectric signal captured during the exposure process cause corresponding voltage changes at the floating diffusion node. These changes are then converted into analog voltage domain signals by the first-stage source follower transistor, stored through two capacitors, and then transmitted to the peripheral circuit using the second-stage source follower transistor. Both stages of the source follower transistor multiply the signal from the previous stage by a coefficient less than 1 before outputting it to the next stage. Therefore, the final signal is significantly smaller than the initial signal, leading to a decrease in image signal-to-noise ratio (SNR). Currently, increasing the pixel voltage is used to increase the output value and improve the SNR. However, increasing the pixel voltage leads to a significant increase in power consumption. To meet the demand for low power consumption, the conventional method is to reduce the pixel power supply voltage, which also leads to a decrease in image SNR. Therefore, how to achieve low power consumption by reducing the pixel power supply voltage while avoiding a decrease in image SNR and ensuring image quality has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a global shutter pixel and image sensor that can reduce power consumption by lowering the pixel power supply voltage while avoiding a decrease in image signal-to-noise ratio and ensuring image quality.

[0005] To address the aforementioned technical problems, this application provides a global shutter pixel, comprising:

[0006] The system comprises a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, an output unit, and a port unit; the amplification unit includes an amplification circuit and a filtering circuit; the first terminal of the amplification circuit serves as the output terminal of the amplification unit, the first terminal of the filtering circuit is connected to the second terminal of the amplification circuit, and the second terminal of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit.

[0007] The photosensitive unit is used to generate charge by sensing light;

[0008] The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node.

[0009] The reset unit is used to reset the pixel;

[0010] The amplification unit is used to amplify the voltage at the floating diffusion node through the amplification circuit and output it to the storage unit, and to filter the level signal output by the port unit through the filtering circuit.

[0011] The storage unit is used to store the reset voltage and the signal voltage;

[0012] The output unit is used to output the signal voltage and the reset voltage;

[0013] The port unit is used to output a level signal to raise the voltage output by the amplification unit during the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored by the storage unit during the preset stage, the read reset voltage stage, and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

[0014] In some embodiments, the port unit includes:

[0015] The first port and the second port; the second end of the filter circuit is connected to the first port; the storage unit is connected to the second port;

[0016] The first port is used to output a first level signal during the storage reset voltage stage and the storage signal voltage stage to increase the voltage output by the amplification unit;

[0017] The second port is used to output a first level signal during the preset phase, the read reset voltage phase, and the read signal voltage phase, so as to increase the voltage stored in the memory cell.

[0018] In some embodiments, the port unit includes:

[0019] The third port; the second terminal of the filter circuit and the storage unit are both connected to the third port; the third port is used to output a first target level signal during the storage reset voltage stage and the storage signal voltage stage to increase the voltage output by the amplification unit; and to output a second target level signal during the preset stage, the read reset voltage stage, and the read signal voltage stage to increase the voltage stored in the storage unit; wherein, the second target level signal output by the third port during the preset stage, the read reset voltage stage, and the read signal voltage stage is higher than the first target level signal output during the storage reset voltage stage and the storage signal voltage stage.

[0020] In some embodiments, the storage unit includes:

[0021] First storage unit and second storage unit;

[0022] The first storage unit is used to store signal voltage;

[0023] The second storage unit is used to store the reset voltage.

[0024] In some embodiments, the transmission unit is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit is turned on; the amplification circuit is controlled by a third control signal, and when the third control signal is a first level signal, the first terminal of the amplification circuit is connected to the second terminal of the amplification circuit; the first storage unit is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the capacitor in the first storage unit is connected to the output terminal of the amplification unit; the second storage unit is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the capacitor in the second storage unit is connected to the first storage unit; the output unit is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the output unit outputs a voltage.

[0025] In some embodiments, during the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal, the signal output from the first port of the port unit, and the signal output from the second port of the port unit are second-level signals; during the exposure phase, the first control signal, the sixth control signal, the signal output from the first port of the port unit, and the signal output from the second port of the port unit are second-level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals; during the reset voltage storage phase, the first control signal, the second control signal, the sixth control signal, and the signal output from the second port of the port unit are second-level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output from the first port of the port unit are first-level signals; during the signal voltage storage phase... The first control signal, the second control signal, the fifth control signal, the sixth control signal, and the signal output from the second port of the port unit are second-level signals, and the third control signal, the fourth control signal, and the signal output from the first port of the port unit are first-level signals. In the preset stage, the first control signal to the sixth control signal and the signal output from the first port of the port unit are second-level signals, and the signal output from the second port of the port unit is a first-level signal. In the read reset voltage stage, the first control signal to the fifth control signal and the signal output from the first port of the port unit are second-level signals, and the signal output from the sixth control signal and the second port of the port unit is a first-level signal. In the read signal voltage stage, the first control signal to the fifth control signal and the signal output from the first port of the port unit are second-level signals, and the signal output from the sixth control signal and the second port of the port unit is a first-level signal.

[0026] In some embodiments, during the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal and the signal output from the third port of the port unit are second-level signals; during the exposure phase, the first control signal, the sixth control signal, and the signal output from the third port of the port unit are second-level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals; during the reset voltage storage phase, the first control signal, the second control signal, and the sixth control signal are second-level signals, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the signal output from the third port of the port unit is a first target level signal; during the signal voltage storage phase, the... The first control signal, the second control signal, the fifth control signal, and the sixth control signal are second-level signals, the third control signal and the fourth control signal are first-level signals, and the signal output from the third port of the port unit is a first target-level signal; in the preset stage, the first control signal to the sixth control signal are second-level signals, and the signal output from the third port of the port unit is a second target-level signal; in the read reset voltage stage, the first control signal to the fifth control signal are second-level signals, the sixth control signal is a first-level signal, and the signal output from the third port of the port unit is a second target-level signal; in the read signal voltage stage, the first control signal to the fifth control signal are second-level signals, the sixth control signal is a first-level signal, and the signal output from the third port of the port unit is a second target-level signal.

[0027] In some embodiments, the filtering circuit includes:

[0028] A resistor and a first capacitor; the first capacitor and the resistor are connected in parallel, the first common terminal of the first capacitor and the resistor serves as the first terminal of the filter circuit, and the second common terminal of the first capacitor and the resistor serves as the second terminal of the filter circuit.

[0029] In some embodiments, the filtering circuit includes:

[0030] A resistor and a first transistor; one end of the resistor is connected to the first terminal of the first transistor and serves as the first terminal of the filter circuit, and the other end of the resistor is connected to the second terminal and / or the third terminal of the first transistor and serves as the second terminal of the filter circuit.

[0031] In some embodiments, the photosensitive unit includes:

[0032] A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

[0033] In some embodiments, the transmission unit includes:

[0034] The second transistor; the second terminal of the second transistor is connected to the photosensitive unit, the third terminal of the second transistor is connected to the input terminal of the amplification unit, and the second transistor is controlled by the first control signal.

[0035] In some embodiments, the reset unit includes:

[0036] The third transistor; the second terminal of the third transistor is connected to the input terminal of the amplification unit, the third terminal of the third transistor is connected to the pixel power supply, and the third transistor is controlled by the second control signal.

[0037] In some embodiments, the amplification circuit includes:

[0038] The fourth transistor and the fifth transistor; the first terminal of the fourth transistor serves as the input terminal of the amplifier circuit, the third terminal of the fourth transistor is connected to the pixel power supply, the second terminal of the fourth transistor is connected to the third terminal of the fifth transistor and serves as the first terminal of the amplifier circuit, the second terminal of the fifth transistor serves as the second terminal of the amplifier circuit, and the fifth transistor is controlled by the third control signal.

[0039] In some embodiments, the first storage unit includes:

[0040] A sixth transistor and a second capacitor; the second terminal of the sixth transistor is connected to the output terminal of the amplification unit, the third terminal of the sixth transistor is connected to the first terminal of the second capacitor and the first terminal of the second storage unit, the sixth transistor is controlled by a fourth control signal, and the second terminal of the second capacitor is connected to the port unit.

[0041] In some embodiments, the second storage unit includes:

[0042] A seventh transistor and a third capacitor; the second terminal of the seventh transistor is connected to the first memory cell as the first terminal of the second memory cell, the third terminal of the seventh transistor is connected to the first terminal of the third capacitor and the input terminal of the output cell, the seventh transistor is controlled by a fifth control signal, and the second terminal of the third capacitor is connected to the port cell.

[0043] In some embodiments, the output unit includes:

[0044] The eighth transistor and the ninth transistor; the first terminal of the eighth transistor serves as the input terminal of the output unit, the third terminal of the eighth transistor is connected to the pixel power supply, the second terminal of the eighth transistor is connected to the third terminal of the ninth transistor, the second terminal of the ninth transistor serves as the output terminal of the output unit, and the ninth transistor is controlled by the sixth control signal.

[0045] To address the aforementioned technical problems, this application also provides an image sensor, including the global shutter pixel as described above.

[0046] The global shutter pixel provided in this application includes: a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, an output unit, and a port unit; the amplification unit includes an amplification circuit and a filtering circuit; the first terminal of the amplification circuit serves as the output terminal of the amplification unit, the first terminal of the filtering circuit is connected to the second terminal of the amplification circuit, and the second terminal of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit; the photosensitive unit is used to generate charge by photosensitive sensing; the transmission unit is used to transmit the charge generated by the photosensitive unit to a floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node; the reset unit is used for... The amplification unit is used to amplify the voltage at the floating diffusion node through the amplification circuit and output it to the storage unit, and to filter the level signal output by the port unit through the filtering circuit; the storage unit is used to store the reset voltage and the signal voltage; the output unit is used to output the signal voltage and the reset voltage; the port unit is used to output a level signal to raise the voltage output by the amplification unit during the reset voltage storage stage and the signal voltage storage stage, and to raise the voltage stored in the storage unit during the preset stage, the reset voltage reading stage, and the signal voltage reading stage; the preset stage is located between the signal voltage storage stage and the reset voltage reading stage.

[0047] As can be seen, the global shutter pixel provided in this application includes an amplification unit comprising an amplification circuit and a filtering circuit. The amplification circuit is connected to the filtering circuit, which in turn is connected to the port unit. The output level of the port unit can increase the output voltage of the amplification unit, allowing the output voltage of the amplification unit to remain constant or even increase when the pixel power supply voltage is reduced. Simultaneously, the storage unit is connected to the port unit, and the output level of the port unit can increase the stored voltage, thus enabling a linear increase in pixel output. Furthermore, filtering the output level signal of the port unit through the filtering circuit can reduce noise and ripple caused by level transitions in the port unit output, ultimately resulting in a high-quality image.

[0048] The image sensor provided in this application also has the aforementioned technical effects. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 is a schematic diagram of a global shutter pixel in an 8T structure;

[0051] Figure 2 is a schematic diagram of a global shutter pixel provided in an embodiment of this application;

[0052] Figure 3 is a schematic diagram of noise and ripple provided in an embodiment of this application;

[0053] Figure 4 is a schematic diagram of another noise and ripple provided in an embodiment of this application;

[0054] Figure 5 is a schematic diagram of a specific global shutter pixel provided in an embodiment of this application;

[0055] Figure 6 is a timing diagram provided in an embodiment of this application;

[0056] Figure 7 is a potential diagram provided in an embodiment of this application;

[0057] Figure 8 is another timing diagram provided by an embodiment of this application;

[0058] Figure 9 is a schematic diagram of another specific global shutter pixel provided in the embodiment of this application;

[0059] Figure 10 is a schematic diagram of another specific global shutter pixel provided in the embodiments of this application;

[0060] Figure 11 is a schematic diagram of another specific global shutter pixel provided in the embodiment of this application. Detailed Implementation

[0061] The core of this application is to provide a global shutter pixel and image sensor that can reduce power consumption by lowering the pixel power supply voltage while avoiding a decrease in image signal-to-noise ratio and ensuring image quality.

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] Please refer to Figure 2, which is a schematic diagram of a global shutter pixel provided in an embodiment of this application. As shown in Figure 2, the global shutter pixel includes:

[0064] The system comprises a photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplification unit 40, a storage unit 50, an output unit 60, and a port unit 70. The amplification unit 40 includes an amplification circuit 401 and a filtering circuit 402. The first terminal of the amplification circuit 401 serves as the output terminal of the amplification unit 40. The first terminal of the filtering circuit 402 is connected to the second terminal of the amplification circuit 401, and the second terminal of the filtering circuit 402 is connected to the port unit 70. The storage unit 50 is connected to the port unit 70.

[0065] The photosensitive unit 10 is used to generate charge by sensing light;

[0066] The transmission unit 20 is used to transmit the charge generated by the photosensitive unit 10 to the floating diffusion node when the transmission unit 20 is turned on; the input terminal of the amplification unit 40 serves as the floating diffusion node.

[0067] The reset unit 30 is used to reset the pixel;

[0068] The amplification unit 40 is used to amplify the voltage at the floating diffusion node through the amplification circuit 401 and output it to the storage unit 50, and to filter the level signal output by the port unit 70 through the filtering circuit 402.

[0069] The storage unit 50 is used to store the reset voltage and the signal voltage;

[0070] The output unit 60 is used to output the signal voltage and the reset voltage;

[0071] The port unit 70 is used to output a level signal to raise the voltage output by the amplification unit 40 during the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored by the storage unit 50 during the preset stage, the read reset voltage stage, and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

[0072] The amplification unit 40 includes an amplification circuit 401 and a filter circuit 402. The amplification circuit 401 amplifies the voltage at the floating diffusion node and outputs it to the storage unit 50. The filter circuit 402 filters the voltage. One end of the filter circuit 402 is connected to the amplification circuit 401, and the other end is connected to the port unit 70. When the pixel power supply voltage is reduced, the voltage output by the amplification unit 40 decreases, the voltage stored in the storage unit 50 decreases, and ultimately the voltage output by the output unit 60 decreases, leading to a decrease in the overall signal-to-noise ratio of the image and affecting image quality. To ensure image quality, in this embodiment, the filter circuit 402 is connected to the port unit 70. By having the port unit 70 output a high level during the reset voltage and signal voltage storage stages, the voltage at the second terminal of the amplification circuit 401 can be raised during these stages, thus increasing the voltage at the first terminal of the amplification circuit 401, i.e., the voltage at the output terminal of the amplification unit 40. Therefore, when the pixel power supply voltage is reduced, the voltage at the output terminal of the amplification unit 40 remains unchanged or even increases.

[0073] As shown in Figure 3, noise and ripple occur during the transition of the output level of port unit 70 from low to high. The noise sources are mainly its own switching noise and the noise caused by the switching current of the devices in the power supply. The noise may appear randomly in time, but it tends to be consistent with the clock in the system. The output level of port unit 70 is obtained by rectifying, filtering, and regulating the external voltage. Due to incomplete filtering, noise signals containing periodic and random components will be attached to the level, thus forming ripple. The noise and ripple of port unit 70 will be recorded at the output of amplifier unit 40, resulting in an increase in the row and column noise of the pixels. To address this, in this embodiment, amplifier unit 40 is equipped with a filter circuit 402 to reduce the noise and ripple caused by voltage jumps in port unit 70, thereby achieving uniform control of the potential at the output of amplifier unit 40. As shown in Figure 4, filtering by filter circuit 402 can effectively reduce noise and ripple.

[0074] When the pixel power supply voltage is reduced, the voltage output by the amplification unit 40 decreases, the voltage stored in the storage unit 50 decreases, and ultimately the voltage output by the output unit 60 decreases, leading to a decrease in the overall signal-to-noise ratio of the image and affecting image quality. To ensure image quality, in this embodiment, the storage unit 50 is connected to the port unit 70. The port unit 70 outputs a high level during the preset phase, the read reset voltage phase, and the read signal voltage phase to increase the voltage stored in the storage unit 50 during these phases. The preset phase is located between the read signal voltage phase and the read reset voltage phase. Thus, when the pixel power supply voltage is reduced, the voltage stored in the storage unit 50 remains unchanged or even increases.

[0075] In some embodiments, the port unit 70 includes:

[0076] The first port and the second port; the second terminal of the filter circuit 402 is connected to the first port; the storage unit 50 is connected to the second port;

[0077] The first port is used to output a first level signal during the storage reset voltage stage and the storage signal voltage stage to boost the voltage output by the amplification unit 40;

[0078] The second port is used to output a first level signal during the preset phase, the read reset voltage phase, and the read signal voltage phase, so as to increase the voltage stored in the storage unit 50.

[0079] In this embodiment, the filter circuit 402 and the storage unit 50 are connected to different ports of the port unit 70. The first port outputs a first-level signal during the reset voltage stage and the signal voltage stage to boost the voltage output by the amplifier unit 40. The second port outputs a first-level signal during the preset stage, the reset voltage stage, and the signal voltage stage to boost the voltage stored in the storage unit 50. The first-level signal is high.

[0080] In some embodiments, the port unit 70 includes:

[0081] The third port; the second terminal of the filter circuit 402 and the storage unit 50 are both connected to the third port; the third port is used to output a first target level signal during the storage reset voltage stage and the storage signal voltage stage to increase the voltage output by the amplification unit 40; and to output a second target level signal during the preset stage, the read reset voltage stage, and the read signal voltage stage to increase the voltage stored in the storage unit 50; wherein, the second target level signal output by the third port during the preset stage, the read reset voltage stage, and the read signal voltage stage is higher than the first target level signal output during the storage reset voltage stage and the storage signal voltage stage.

[0082] In this embodiment, the filter circuit 402 and the storage unit 50 are connected to the same port of the port unit 70, referred to as the third port. During the storage reset voltage stage and the storage signal voltage stage, the third port outputs a first target level signal to boost the voltage output by the amplifier unit 40. During the preset stage, the read reset voltage stage, and the read signal voltage stage, the third port outputs a second target level signal to boost the voltage stored in the storage unit 50. The first and second target level signals are both high-level. The second target level signal output by the third port during the preset stage, the read reset voltage stage, and the read signal voltage stage is higher than the first target level signal output during the storage reset voltage stage and the storage signal voltage stage. Connecting the filter circuit 402 and the storage unit 50 to the same port of the port unit 70 saves pixel layout area and improves integration density.

[0083] Referring to Figure 5, in some embodiments, the storage unit 50 includes:

[0084] First storage unit 501 and second storage unit 502;

[0085] The first storage unit 501 is used to store signal voltage;

[0086] The second storage unit 502 is used to store the reset voltage.

[0087] In this embodiment, the storage unit 50 includes a first storage unit 501 and a second storage unit 502, which are used to store signal voltage and reset voltage, respectively.

[0088] In some embodiments, both the first storage unit 501 and the second storage unit 502 include capacitors.

[0089] In some embodiments, the transmission unit 20 is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit 20 is turned on; the reset unit 30 is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit 30 is turned on; the amplifier circuit 401 is controlled by a third control signal, and when the third control signal is a first level signal, the first terminal of the amplifier circuit 401 is connected to the second terminal of the amplifier circuit 401; the first storage unit 501 is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the capacitor in the first storage unit 501 is connected to the output terminal of the amplifier unit 40; the second storage unit 502 is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the capacitor in the second storage unit 502 is connected to the first storage unit 501; the output unit 60 is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the output unit 60 outputs a voltage.

[0090] The first control signal is high, meaning that when the first control signal is high, the transmission unit 20 is turned on; when the second control signal is high, the reset unit 30 is turned on; when the third control signal is high, the first terminal of the amplifier circuit 401 is connected to the second terminal of the amplifier circuit 401; when the fourth control signal is high, the capacitor in the first storage unit 501 is connected to the output terminal of the amplifier unit 40; when the fifth control signal is high, the capacitor in the second storage unit 502 is connected to the first storage unit 501; and when the sixth control signal is high, the output unit 60 outputs voltage.

[0091] In some embodiments, during the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal, the signal output from the first port of the port unit 70, and the signal output from the second port of the port unit 70 are second-level signals; during the exposure phase, the first control signal, the sixth control signal, the signal output from the first port of the port unit 70, and the signal output from the second port of the port unit 70 are second-level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals; during the reset voltage storage phase, the first control signal, the second control signal, the sixth control signal, and the signal output from the second port of the port unit 70 are second-level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output from the first port of the port unit 70 are first-level signals; during the signal voltage storage phase, the... The first control signal, the second control signal, the fifth control signal, the sixth control signal, and the signal output from the second port of the port unit 70 are second-level signals, and the third control signal, the fourth control signal, and the signal output from the first port of the port unit 70 are first-level signals. In the preset stage, the signals from the first control signal to the sixth control signal and the signal output from the first port of the port unit 70 are second-level signals, and the signal output from the second port of the port unit 70 is a first-level signal. In the read reset voltage stage, the signals from the first control signal to the fifth control signal and the signal output from the first port of the port unit 70 are second-level signals, and the signals output from the sixth control signal and the second port of the port unit 70 are first-level signals. In the read signal voltage stage, the signals from the first control signal to the fifth control signal and the signal output from the first port of the port unit 70 are second-level signals, and the signals output from the sixth control signal and the second port of the port unit 70 are first-level signals.

[0092] The first level signal is high, and the second level signal is low.

[0093] With port unit 70 including a first port and a second port, the second terminal of filter circuit 402 connected to the first port, and storage unit 50 connected to the second port, the timing of each control signal and the signals output from the first and second ports can be referred to Figure 6. Under this timing, the working principle of the global shutter pixel is as follows:

[0094] In Figure 6, TG represents the first control signal, RST represents the second control signal, PC represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, SEL represents the sixth control signal, PCB represents the signal output from the first port, and SDB represents the signal output from the second port.

[0095] From time t0 to t1: The sixth control signal is low (typically -1V to 0V), and output unit 60 is turned off. The first, second, third, fourth, and fifth control signals are high (typically 2.5V to 3.5V), at which time transmission unit 20, reset unit 30, amplification unit 40, first storage unit 501, and second storage unit 502 are turned on, clearing the original charge of photosensitive unit 10, floating diffusion node, output terminal of amplification unit 40, first storage unit 501, and second storage unit 502. The voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. Simultaneously, from time t0 to t1, the signals output from the first and second ports are low (typically -2V to 0V).

[0096] From time t1 to t2: The first control signal is low (e.g., -1V to 0V), at which time the transmission unit 20 is turned off, and the photosensitive unit 10 begins to accumulate charge. The second, third, fourth, and fifth control signals are kept high, and the reset unit 30, amplification unit 40, first storage unit 501, and second storage unit 502 remain on to remove noise at the floating diffusion node, thereby improving image quality.

[0097] From time t2 to t3: The output level of the first port is pulled high (typically 0.1V to 1.5V). The voltage of the floating diffusion node is amplified by the amplification unit 40 and then transmitted to the storage unit 50. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth and fifth control signals are high, and the first storage unit 501 and the second storage unit 502 are in a conducting state. The second storage unit 502 stores the reset voltage. At time t3, the fifth control signal changes from high to low, thereby turning off the second storage unit 502.

[0098] Since a high level is output through the first port between times t2 and t3, the voltage at the output of the amplifier unit 40 rises. By lowering the pixel power supply voltage PIXVDD and simultaneously raising the voltage at the first port, the voltage of the second storage unit 502 can be kept constant or even increased. At the same time, the filter circuit 402 can effectively reduce the noise and ripple caused by the voltage jump at the first port.

[0099] From time t3 to t4: First, the first control signal goes high, and transmission unit 20 is turned on. Due to the potential difference between photosensitive unit 10 and the floating diffusion node, charge is transferred to the floating diffusion node through transmission unit 20. Then, the first control signal goes low, thus turning off transmission unit 20. The floating diffusion node enters a stable state, and the voltage of the floating diffusion node is amplified by amplification unit 40 and transmitted to storage unit 50. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth control signal is high, the fifth control signal is low, the first storage unit 501 is on, and the second storage unit 502 is off. The first storage unit 501 stores the signal voltage. At time t4, the fourth control signal changes from high to low, thus turning off the first storage unit 501.

[0100] Similarly, since the output of the first port remains high from time t3 to t4, by lowering the pixel power supply voltage PIXVDD and raising the level of the first port, the voltage stored in the first storage cell 501 can remain unchanged or even increase.

[0101] From t4 to t5: The output level of the second port is pulled up from low level (generally 0.1V to 2V). Since the fourth and fifth control signals are low level from t4 to t5, the first storage unit 501 and the second storage unit 502 are turned off. Therefore, the first voltage domain storage node (one end of the first storage unit 501) and the second voltage domain storage node (one end of the second storage unit 502) are both in a floating state (the floating state means that there is no leakage path in the storage node and the stored charge of the storage node is conserved). The voltage rise of the first voltage domain storage node and the second voltage domain storage node is increased by the same value through the level rise value of the second port. Therefore, the ΔVout value remains unchanged (as shown in Figure 7). Thus, when the pixel power supply PIXVDD decreases, the actual read reset voltage and signal voltage are maintained or even increased to maintain the low noise and high linearity of the output of the output unit 60.

[0102] Where ΔVout = V1_SD - V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage. SD stands for Storage Diode, meaning voltage domain storage.

[0103] From t5 to t6: The sixth control signal is high, which turns on the output unit 60. The reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V1_PIX_OUT.

[0104] From time t6 to t7, the fifth control signal is high, thus turning on the second storage cell 502. The voltage value after voltage coupling between the first storage cell 501 and the second storage cell 502 is equal to (C2*V2_SD+C3*V1_SD) / (C2+C3). C2 is the capacitor in the first storage cell 501, and C3 is the capacitor in the second storage cell 502.

[0105] From t7 to t8: The fifth control signal is low, thus turning off the second storage unit 502. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V2_PIX_OUT.

[0106] After time t8: Enters reset standby state.

[0107] In some embodiments, during the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal and the signal output from the third port of the port unit 70 are second-level signals; during the exposure phase, the first control signal, the sixth control signal, and the signal output from the third port of the port unit 70 are second-level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals; during the reset voltage storage phase, the first control signal, the second control signal, and the sixth control signal are second-level signals, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the signal output from the third port of the port unit 70 is a first target level signal; during the signal voltage storage phase, the... The first control signal, the second control signal, the fifth control signal, and the sixth control signal are second-level signals, the third control signal and the fourth control signal are first-level signals, and the signal output from the third port of the port unit 70 is a first target-level signal; in the preset stage, the first control signal to the sixth control signal are second-level signals, and the signal output from the third port of the port unit 70 is a second target-level signal; in the read reset voltage stage, the first control signal to the fifth control signal are second-level signals, the sixth control signal is a first-level signal, and the signal output from the third port of the port unit 70 is a second target-level signal; in the read signal voltage stage, the first control signal to the fifth control signal are second-level signals, the sixth control signal is a first-level signal, and the signal output from the third port of the port unit 70 is a second target-level signal.

[0108] The first level signal, the first target level signal, and the second target level signal are all at high levels, while the second level signal is at a low level. The second target level signal is higher than the first target level signal.

[0109] With port unit 70 including a third port, and the second terminal of filter circuit 402 and storage unit 50 both connected to the third port, the timing of each control signal and the signal output from the third port can be referenced in Figure 8. Under this timing, the working principle of the global shutter pixel is as follows:

[0110] In Figure 8, TG represents the first control signal, RST represents the second control signal, PC represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, SEL represents the sixth control signal, and SIG represents the signal output from the third port.

[0111] From time t0 to t1: The sixth control signal is low (typically -1V to 0V), and output unit 60 is turned off. The first, second, third, fourth, and fifth control signals are high (typically 2.5V to 3.5V), at which time transmission unit 20, reset unit 30, amplification unit 40, first storage unit 501, and second storage unit 502 are turned on, clearing the original charge of photosensitive unit 10, floating diffusion node, output terminal of amplification unit 40, first storage unit 501, and second storage unit 502. The voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. Simultaneously, the signal output from the third port is low (typically -2V to 0V) from time t0 to t1.

[0112] From time t1 to t2: The first control signal is low (e.g., -1V to 0V), at which time the transmission unit 20 is turned off, and the photosensitive unit 10 begins to accumulate charge. The second, third, fourth, and fifth control signals are kept high, and the reset unit 30, amplification unit 40, first storage unit 501, and second storage unit 502 remain on to remove noise at the floating diffusion node, thereby improving image quality.

[0113] From time t2 to t3: The output level of the third port is pulled high (typically 0.1V to 1.5V). The voltage of the floating diffusion node is amplified by the amplification unit 40 and then transmitted to the storage unit 50. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth and fifth control signals are high, and the first storage unit 501 and the second storage unit 502 are in a conducting state. The second storage unit 502 stores the reset voltage. At time t3, the fifth control signal changes from high to low, thereby turning off the second storage unit 502.

[0114] Since a high level is output through the third port between times t2 and t3, the voltage at the output of the amplifier unit 40 rises. By lowering the pixel power supply voltage PIXVDD and simultaneously raising the voltage at the third port, the voltage of the second storage unit 502 can be kept constant or even increased. At the same time, the filter circuit 402 can effectively reduce the noise and ripple caused by the voltage jump at the first port.

[0115] From time t3 to t4: First, the first control signal goes high, and transmission unit 20 is turned on. Due to the potential difference between photosensitive unit 10 and the floating diffusion node, charge is transferred to the floating diffusion node through transmission unit 20. Then, the first control signal goes low, thus transmission unit 20 is turned off, and the floating diffusion node enters a stable state. The voltage of the floating diffusion node is amplified by amplification unit 40 and then transferred to storage unit 50. The transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node. Since the fourth control signal is high and the fifth control signal is low from time t3 to t4, the first storage unit 501 is turned on, and the second storage unit 502 is turned off, thus the first storage unit 501 stores the signal voltage.

[0116] Similarly, since the output of the third port remains high from time t3 to t4, by lowering the pixel power supply voltage PIXVDD and raising the level of the third port, the voltage stored in the first storage unit 501 can remain unchanged or even increase.

[0117] From time t4 to t5: The output level of the third port continues to rise (typically from 0.1V to 2V). Since the fourth and fifth control signals are low during time t4 to t5, the first storage unit 501 and the second storage unit 502 are turned off. Therefore, the first voltage domain storage node (one end of the first storage unit 501) and the second voltage domain storage node (one end of the second storage unit 502) are both in a floating state. The voltage rise of the first voltage domain storage node and the second voltage domain storage node is increased by the same value through the level rise value of the third port. Therefore, the ΔVout value remains unchanged, thereby maintaining or even increasing the actual read reset voltage and signal voltage when the pixel power supply PIXVDD decreases, so as to maintain the low noise and high linearity of the output unit 60.

[0118] From t5 to t6: The sixth control signal is high, which turns on the output unit 60. The reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V1_PIX_OUT.

[0119] From time t6 to t7, the fifth control signal is high, thus turning on the second storage cell 502. The voltage value after voltage coupling between the first storage cell 501 and the second storage cell 502 is equal to (C2*V2_SD+C3*V1_SD) / (C2+C3). C2 is the capacitor in the first storage cell 501, and C3 is the capacitor in the second storage cell 502.

[0120] From t7 to t8: The fifth control signal is low, thus turning off the second storage unit 502. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V2_PIX_OUT.

[0121] After time t8: Enters reset standby state.

[0122] Referring to any one of Figures 9 to 11, in some embodiments, the photosensitive unit 10 includes a photodiode PD; the anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the transmission unit 20. The transmission unit 20 includes a second transistor; the second terminal of the second transistor is connected to the photosensitive unit 10, and the third terminal of the second transistor is connected to the input terminal of the amplification unit 40; the second transistor is controlled by the first control signal. The reset unit 30 includes a third transistor; the second terminal of the third transistor is connected to the input terminal of the amplification unit 40, and the third terminal of the third transistor is connected to the pixel power supply; the third transistor is controlled by the second control signal.

[0123] In Figures 9 and 10, PIXVDD represents the pixel power supply, and PIXVSS represents the pixel ground. The second transistor M2 and the third transistor M3 are turned on during the reset phase to clear the initial charge of the photodiode PD and the floating diffusion node FD. During the exposure phase, the photodiode PD generates charge through photosensitive contact, and during this phase, the second transistor M2 remains off, allowing the photodiode PD to accumulate charge. When the first control signal is at the first level, the second transistor M2 is turned on. When the second control signal is at the first level, the third transistor M3 is turned on. PCB represents the signal output from the first port, and SDB represents the signal output from the second port.

[0124] The first terminal of the second transistor M2, the third transistor M3, and the fourth transistor M4 can be the gate, the second terminal of the second transistor M2, the third transistor M3, and the fourth transistor M4 can be the source, and the third terminal of the second transistor M2, the third transistor M3, and the fourth transistor M4 can be the drain.

[0125] Referring to any of Figures 9 to 11, in some embodiments, the amplifier circuit 401 includes:

[0126] The fourth transistor M4 and the fifth transistor M5; the first terminal of the fourth transistor M4 serves as the input terminal of the amplifier circuit 401, the third terminal of the fourth transistor M4 is connected to the pixel power supply, the second terminal of the fourth transistor M4 is connected to the third terminal of the fifth transistor M5 and serves as the first terminal of the amplifier circuit 401, the second terminal of the fifth transistor M5 serves as the second terminal of the amplifier circuit 401, and the fifth transistor M5 is controlled by the third control signal.

[0127] The first terminal of the fourth transistor M4 and the fifth transistor M5 can be the gate, the second terminal of the fourth transistor M4 and the fifth transistor M5 can be the source, and the third terminal of the fourth transistor M4 and the fifth transistor M5 can be the drain.

[0128] The gate of the fourth transistor M4 is the input terminal of the amplifier circuit 401, and the source of the fourth transistor M4 is the output terminal of the amplifier circuit 401. The fourth transistor M4 acts as the source follower transistor of the first stage. When the third control signal is high, the fifth transistor M5 is turned on.

[0129] Referring to Figure 9, in some embodiments, the filter circuit 402 includes:

[0130] A resistor R and a first capacitor C1 are connected in parallel; the first capacitor C1 and the resistor R are connected in parallel; the first common terminal of the first capacitor C1 and the resistor R is used as the first terminal of the filter circuit 402; the second common terminal of the first capacitor C1 and the resistor R is used as the second terminal of the filter circuit 402.

[0131] In this embodiment, the filter circuit 402 includes a resistor R and a first capacitor C1 connected in parallel. The first capacitor C1 can be one or more combinations of metal wire-oxide-metal wire plate capacitor, metal plate-dielectric layer-metal plate capacitor, etc. The resistor R can be one or more combinations of gate silicon resistor, metal resistor, N / P type active silicon resistor.

[0132] Referring to Figure 10, in some embodiments, the filter circuit 402 includes:

[0133] A resistor R is connected to a first transistor M1; one end of the resistor R is connected to the first terminal of the first transistor M1 and serves as the first terminal of the filter circuit 402, and the other end of the resistor R is connected to the second terminal and / or the third terminal of the first transistor M1 and serves as the second terminal of the filter circuit 402.

[0134] The first terminal of the first transistor M1 can be the gate, the second terminal of the first transistor M1 can be the source, and the third terminal of the first transistor M1 can be the drain.

[0135] In this embodiment, the filter circuit 402 includes a resistor R and a first transistor M1. The first transistor M1 serves as a signal feedthrough compensation path. When noise and ripple cause a voltage difference across the resistor R, the resistor R and the first transistor M1 form a filter circuit, which can reduce or even eliminate noise and ripple in a short time.

[0136] Referring to any of Figures 9 to 11, in some embodiments, the first storage unit 501 includes:

[0137] The sixth transistor M6 is connected to the second capacitor C2; the second terminal of the sixth transistor M6 is connected to the output terminal of the amplification unit 40, the third terminal of the sixth transistor M6 is connected to the first terminal of the second capacitor C2 and the first terminal of the second storage unit 502, the sixth transistor M6 is controlled by the fourth control signal, and the second terminal of the second capacitor C2 is connected to the port unit 70.

[0138] The first terminal of the sixth transistor M6 can be the gate, the second terminal can be the source, and the third terminal can be the drain. When the fourth control signal is high, the sixth transistor M6 is turned on.

[0139] Referring to any of Figures 9 to 11, in some embodiments, the second storage unit 502 includes:

[0140] The seventh transistor M7 and the third capacitor C3; the second terminal of the seventh transistor M7 is connected to the first memory unit 501 as the first terminal of the second memory unit 502, the third terminal of the seventh transistor M7 is connected to the first terminal of the third capacitor C3 and the input terminal of the output unit 60, the seventh transistor M7 is controlled by the fifth control signal, and the second terminal of the third capacitor C3 is connected to the port unit 70.

[0141] The first terminal of the seventh transistor M7 can be the gate, the second terminal can be the source, and the third terminal can be the drain. When the fifth control signal is high, the seventh transistor M7 is turned on.

[0142] Referring to any of Figures 9 to 11, in some embodiments, the output unit 60 includes:

[0143] The eighth transistor M8 and the ninth transistor M9; the first terminal of the eighth transistor M8 serves as the input terminal of the output unit 60, the third terminal of the eighth transistor M8 is connected to the pixel power supply, the second terminal of the eighth transistor M8 is connected to the third terminal of the ninth transistor M9, the second terminal of the ninth transistor M9 serves as the output terminal of the output unit 60, and the ninth transistor M9 is controlled by the sixth control signal.

[0144] The first terminal of the eighth transistor M8 and the ninth transistor M9 can be the gate, the second terminal of the eighth transistor M8 and the ninth transistor M9 can be the source, and the third terminal of the eighth transistor M8 and the ninth transistor M9 can be the drain. When the sixth control signal is high, the ninth transistor M9 is turned on. The eighth transistor M8 acts as the second-stage source follower transistor.

[0145] Based on the timing diagram shown in Figure 6, the working principle of the global shutter pixels shown in Figures 9 and 10 is as follows:

[0146] Let the gate of the fourth transistor M4 be the floating diffusion node FD, the drain of the sixth transistor M6 be the first voltage domain storage node, and the drain of the seventh transistor M7 be the second voltage domain storage node. The time intervals t0 to t1 are the reset phase, t1 to t2 are the exposure phase, t2 to t3 are the reset voltage storage phase (i.e., storing V1 as shown in Figure 6), t3 to t4 include the signal voltage storage phase (i.e., storing V2 as shown in Figure 6) and the charge transfer phase (i.e., PD charging FD as shown in Figure 6, gradually becoming V2 voltage), t4 to t5 are the preset phase described above (i.e., raising SD as shown in Figure 6), t5 to t6 are the reset voltage read phase (i.e., reading V1 as shown in Figure 6), t6 to t7 are the voltage coupling phase (i.e., C2 & C3 voltage coupling as shown in Figure 6), and t7 to t8 are the signal voltage read phase (i.e., reading V2 as shown in Figure 6).

[0147] From time t0 to t1: The sixth control signal is low (typically -1V to 0V), and the ninth transistor M9 is off. The first, second, third, fourth, and fifth control signals are high (typically 2.5V to 3.5V), and the second, third, fifth, sixth, and seventh transistors M2, M3, M5, M6, and M7 are on, clearing the original charge at the photodiode PD, the floating diffusion node, the output of the amplification unit 40, the first capacitor C1, the first voltage domain storage node, the second capacitor C2, and the second voltage domain storage node. The voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. Simultaneously, from time t0 to t1, the output levels of the first and second ports are set to low (typically -2V to 0V).

[0148] From time t1 to t2: The first control signal is low (e.g., -1V to 0V), at which time the second transistor M2 is turned off, and the photodiode PD begins to accumulate charge. The second, third, fourth, and fifth control signals are kept high, while the third transistor M3, fifth transistor M5, sixth transistor M6, and seventh transistor M7 remain on to remove noise at the floating diffusion node, the first voltage domain storage node, and the second voltage domain storage node, thereby improving image quality.

[0149] From time t2 to t3: The output level of the first port is pulled high (typically 0.1V to 1.5V). The voltage of the floating diffusion node is transferred to the first and second voltage domain storage nodes through the fourth transistor M4. The transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the seventh transistor M7 is in the on state, and the source and drain voltages of the seventh transistor M7 are equal. At time t3, the fifth control signal changes from high to low, thereby turning off the seventh transistor M7. The third capacitor C3 can be a high-capacitance, low-leakage capacitor, used to store the reset voltage.

[0150] Since a high level is output through the first port between times t2 and t3, the channel resistance of the fifth transistor M5 increases. With the same channel current of the fourth transistor M4, the voltage at the output of the amplifier unit 40 rises. While lowering the pixel power supply voltage PIXVDD, by raising the voltage at the first port, the voltage stored in the third capacitor C3 can be kept constant or even increased. Simultaneously, the filter circuit 402 (as shown in Figure 9, the filter circuit 402 may include a resistor R and the first capacitor C1; as shown in Figure 10, the filter circuit 402 may include a resistor R and the first transistor M1) effectively reduces the noise and ripple caused by the voltage jump at the first port.

[0151] From time t3 to t4: First, the first control signal goes high, and the second transistor M2 turns on. Due to the potential difference between the photodiode PD and the floating diffusion node, charge is transferred to the floating diffusion node through the channel of the second transistor M2. Then, the first control signal goes low, turning off the second transistor M2. The floating diffusion node enters a stable state, and the voltage of the floating diffusion node is transferred to the first voltage domain storage node through the fourth transistor M4. The transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node, and the second capacitor C2 stores the signal voltage. Similarly, since the output of the first port remains high from time t3 to t4, by lowering the pixel power supply voltage PIXVDD and simultaneously raising the level of the first port, the voltage stored in the second capacitor C2 can be kept constant or even increased.

[0152] From time t4 to t5: The output level of the second port is pulled high (typically 0.1V to 2V). Since the sixth transistor M6 and the seventh transistor M7 are turned off during time t4 to t5, both the first voltage domain storage node and the second voltage domain storage node are in a floating state. The voltage rise of the first voltage domain storage node and the second voltage domain storage node is caused by the voltage rise of the second port, so the ΔVout value remains unchanged. This maintains or even increases the actual read reset voltage and signal voltage when the pixel power supply PIXVDD decreases, so as to maintain the low noise and high linearity of the output unit 60.

[0153] Where ΔVout = V1_SD - V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage. SD stands for Storage Diode, meaning voltage domain storage.

[0154] From t5 to t6: The sixth control signal is high, which turns on the ninth transistor M9. The reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V1_PIX_OUT.

[0155] From time t6 to t7, the fifth control signal is at a high level, thereby turning on the seventh transistor M7. The voltage value after voltage coupling of the second capacitor C2 and the third capacitor C3 is equal to (C2*V2_SD+C3*V1_SD) / (C2+C3).

[0156] From t7 to t8: The fifth control signal is low, thus turning off the seventh transistor M7. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V2_PIX_OUT.

[0157] After time t8: Enters reset standby state.

[0158] Based on the timing diagram shown in Figure 8, the working principle of the global shutter pixel shown in Figure 11 is as follows:

[0159] The gate of the fourth transistor M4 is designated as the floating diffusion node, the drain of the sixth transistor M6 is designated as the first voltage domain storage node, and the drain of the seventh transistor M7 is designated as the second voltage domain storage node. The time intervals t0 to t1 are the reset phase, t1 to t2 are the exposure phase, t2 to t3 are the reset voltage storage phase (i.e., storing V1 as shown in Figure 8), t3 to t4 include the signal voltage storage phase (i.e., storing V2 as shown in Figure 8) and the charge transfer phase (i.e., PD charging FD as shown in Figure 8, gradually becoming V2 voltage), t4 to t5 are the preset phase described above (i.e., raising SD as shown in Figure 8), t5 to t6 are the reset voltage read phase (i.e., reading V1 as shown in Figure 8), t6 to t7 are the voltage coupling phase (i.e., C2 & C3 voltage coupling as shown in Figure 8), and t7 to t8 are the signal voltage read phase (i.e., reading V2 as shown in Figure 8).

[0160] From time t0 to t1: The sixth control signal is low (typically -1V to 0V), and the ninth transistor M9 is off. The first, second, third, fourth, and fifth control signals are high (typically 2.5V to 3.5V), and the second, third, fifth, sixth, and seventh transistors M2, M3, M5, M6, and M7 are on, clearing the original charge at the photodiode PD, the floating diffusion node, the output of the amplifier unit 40, the first capacitor C1, the first voltage domain storage node, the second capacitor C2, and the second voltage domain storage node. The voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. Simultaneously, from time t0 to t1, the output level of the third port is set to low (typically -2V to 0V).

[0161] From time t1 to t2: The first control signal is low (e.g., -1V to 0V), at which time the second transistor M2 is turned off, and the photodiode PD begins to accumulate charge. The second, third, fourth, and fifth control signals are kept high, while the third transistor M3, fifth transistor M5, sixth transistor M6, and seventh transistor M7 remain on to remove noise at the floating diffusion node, the first voltage domain storage node, and the second voltage domain storage node, thereby improving image quality.

[0162] From time t2 to t3: The output level of the third port is pulled high for the first time. The voltage of the floating diffusion node is transferred to the first and second voltage domain storage nodes after passing through the fourth transistor M4, and the transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the seventh transistor M7 is in the on state, and the source and drain voltages of the seventh transistor M7 are equal. At time t3, the fifth control signal goes low, thus turning off the seventh transistor M7. The third capacitor C3 can be a high-capacitance, low-leakage capacitor, and is used to store the reset voltage.

[0163] Since a high level is output through the third port between times t2 and t3, the channel resistance of the fifth transistor M5 increases. With the same channel current of the fourth transistor M4, the voltage at the output of the amplifier unit 40 rises. By lowering the pixel power supply voltage PIXVDD and simultaneously raising the voltage at the third port, the voltage stored in the third capacitor C3 can be kept constant or even increased. At the same time, the resistor R and the first capacitor C1 effectively reduce the noise and ripple caused by the voltage jump at the third port.

[0164] From time t3 to t4: First, the first control signal goes high, and the second transistor M2 turns on. Due to the potential difference between the photodiode PD and the floating diffusion node, charge is transferred to the floating diffusion node through the channel of the second transistor M2. Then, the first control signal goes low, thus turning off the second transistor M2. The floating diffusion node enters a stable state, and the voltage of the floating diffusion node is transferred to the first voltage domain storage node through the fourth transistor M4. The transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node, and the second capacitor C2 stores the signal voltage. Similarly, since the output of the third port remains high from time t3 to t4, by lowering the pixel power supply voltage PIXVDD and simultaneously raising the level of the third port, the voltage stored in the second capacitor C2 can be kept constant or even increased.

[0165] From time t4 to t5: The output level of the third port is pulled up a second time after the first pull-up. Since the fourth and fifth control signals are low during time t4 to t5, the sixth transistor M6 and the seventh transistor M7 are turned off. Therefore, both the first and second voltage domain storage nodes are in a floating state. By raising the level of the third port, the first and second voltage domain storage nodes rise by the same voltage. Therefore, the ΔVout value remains unchanged. This maintains or even raises the actual read reset voltage and signal voltage when the pixel power supply PIXVDD decreases, so as to maintain the low noise and high linearity of the output unit 60.

[0166] Where ΔVout = V1_SD - V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage.

[0167] From t5 to t6: The sixth control signal is high, which turns on the ninth transistor M9. The reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V1_PIX_OUT.

[0168] From time t6 to t7, the fifth control signal is at a high level, thereby turning on the seventh transistor M7. The voltage value after voltage coupling of the second capacitor C2 and the third capacitor C3 is equal to (C2*V2_SD+C3*V1_SD) / (C2+C3).

[0169] From t7 to t8: The fifth control signal is low, thus turning off the seventh transistor M7. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V2_PIX_OUT.

[0170] After time t8: Enters reset standby state.

[0171] In summary, the global shutter pixel provided in this application includes an amplification unit comprising an amplification circuit and a filtering circuit. The amplification circuit is connected to the filtering circuit, which in turn is connected to a port unit. The output level of the port unit can increase the output voltage of the amplification unit, allowing the output voltage of the amplification unit to remain constant or even increase when the pixel power supply voltage is reduced. Simultaneously, the storage unit is connected to the port unit, and the output level of the port unit can increase the stored voltage, thus enabling a linear increase in pixel output. Furthermore, filtering by the filtering circuit reduces noise and ripple caused by level transitions in the port unit output, ultimately resulting in a high-quality image.

[0172] This application also provides an image sensor that includes a global shutter pixel as described in the above embodiments. For a description of the image sensor provided in this application, please refer to the above embodiments of the global shutter pixel; further details will not be repeated here.

[0173] Due to the complexity of the situation, it is impossible to list and elaborate on them all. Those skilled in the art should realize that there can be multiple examples based on the basic principles of the embodiments provided in this application and in combination with actual situations. Without sufficient creative effort, all of them should be within the scope of this application.

[0174] The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0175] The global shutter pixel and image sensor provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0176] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A global shutter pixel, characterized by, include: The system comprises a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, an output unit, and a port unit; the amplification unit includes an amplification circuit and a filtering circuit; the first terminal of the amplification circuit serves as the output terminal of the amplification unit, the first terminal of the filtering circuit is connected to the second terminal of the amplification circuit, and the second terminal of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit. The photosensitive unit is used to generate charge by sensing light; The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node. The reset unit is used to reset the pixel; The amplification unit is used to amplify the voltage at the floating diffusion node through the amplification circuit and output it to the storage unit, and to filter the level signal output by the port unit through the filtering circuit. The storage unit is used to store the reset voltage and the signal voltage; The output unit is used to output the signal voltage and the reset voltage; The port unit is used to output a level signal to raise the voltage output by the amplification unit during the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored by the storage unit during the preset stage, the read reset voltage stage, and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

2. The global shutter pixel of claim 1, wherein, The port unit includes: The first port and the second port; the second end of the filter circuit is connected to the first port; the storage unit is connected to the second port; The first port is used to output a first level signal during the storage reset voltage stage and the storage signal voltage stage to increase the voltage output by the amplification unit; The second port is used to output a first level signal during the preset phase, the read reset voltage phase, and the read signal voltage phase, so as to increase the voltage stored in the memory cell.

3. The global shutter pixel of claim 1, wherein, The port unit includes: The third port; the second terminal of the filter circuit and the storage unit are both connected to the third port; the third port is used to output a first target level signal during the storage reset voltage stage and the storage signal voltage stage to increase the voltage output by the amplification unit; and to output a second target level signal during the preset stage, the read reset voltage stage, and the read signal voltage stage to increase the voltage stored in the storage unit; wherein, the second target level signal output by the third port during the preset stage, the read reset voltage stage, and the read signal voltage stage is higher than the first target level signal output during the storage reset voltage stage and the storage signal voltage stage.

4. The global shutter pixel of claim 1, wherein, The storage unit includes: First storage unit and second storage unit; The first storage unit is used to store signal voltage; The second storage unit is used to store the reset voltage.

5. The global shutter pixel of claim 4, wherein, The transmission unit is controlled by a first control signal; when the first control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a second control signal; when the second control signal is a first level signal, the reset unit is turned on. The amplifier circuit is controlled by a third control signal; when the third control signal is a first level signal, the first terminal of the amplifier circuit is connected to the second terminal of the amplifier circuit. The first storage unit is controlled by a fourth control signal; when the fourth control signal is a first level signal, the capacitor in the first storage unit is connected to the output terminal of the amplifier unit. The second storage unit is controlled by a fifth control signal; when the fifth control signal is a first level signal, the capacitor in the second storage unit is connected to the first storage unit. The output unit is controlled by a sixth control signal; when the sixth control signal is a first level signal, the output unit outputs a voltage.

6. The global shutter pixel of claim 5, wherein, During the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal, the signal output from the first port of the port unit, and the signal output from the second port of the port unit are second-level signals. During the exposure stage, the first control signal, the sixth control signal, the signal output from the first port of the port unit, and the signal output from the second port of the port unit are second level signals; The second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals; during the reset voltage storage stage, the first control signal, the second control signal, the sixth control signal, and the signal output from the second port of the port unit are second-level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output from the first port of the port unit are first-level signals; during the signal voltage storage stage, the first control signal, the second control signal, the fifth control signal, the sixth control signal, and the signal output from the second port of the port unit are second-level signals, and the third control signal, the fourth control signal, and the signal output from the first port of the port unit are first-level signals. In the preset stage, the signals from the first control signal to the sixth control signal and the signal output from the first port of the port unit are second-level signals, and the signal output from the second port of the port unit is a first-level signal; During the read reset voltage stage, the signals from the first control signal to the fifth control signal and the signal output from the first port of the port unit are second-level signals, while the signals from the sixth control signal and the signal output from the second port of the port unit are first-level signals. During the signal voltage reading stage, the signals from the first control signal to the fifth control signal and the signal output from the first port of the port unit are second-level signals, while the signals from the sixth control signal and the signal output from the second port of the port unit are first-level signals.

7. The global shutter pixel of claim 5, wherein, During the reset phase, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the sixth control signal and the signal output from the third port of the port unit are second-level signals. During the exposure stage, the first control signal, the sixth control signal, and the signal output from the third port of the port unit are second-level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first-level signals. During the reset voltage storage phase, the first control signal, the second control signal, and the sixth control signal are second-level signals, the third control signal, the fourth control signal, and the fifth control signal are first-level signals, and the signal output from the third port of the port unit is a first target level signal; during the signal voltage storage phase, the first control signal, the second control signal, the fifth control signal, and the sixth control signal are second-level signals, the third control signal and the fourth control signal are first-level signals, and the signal output from the third port of the port unit is a first target level signal. During the preset stage, the first control signal to the sixth control signal are second-level signals, and the signal output from the third port of the port unit is a second target-level signal; During the read reset voltage phase, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output from the third port of the port unit is a second target level signal. During the signal voltage reading stage, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output from the third port of the port unit is a second target level signal.

8. A global shutter pixel according to any one of claims 1 to 7, characterized in that, The filtering circuit includes: A resistor and a first capacitor; the first capacitor and the resistor are connected in parallel, the first common terminal of the first capacitor and the resistor serves as the first terminal of the filter circuit, and the second common terminal of the first capacitor and the resistor serves as the second terminal of the filter circuit.

9. A global shutter pixel according to any one of claims 1 to 7, characterized in that, The filtering circuit includes: A resistor and a first transistor; one end of the resistor is connected to the first terminal of the first transistor and serves as the first terminal of the filter circuit, and the other end of the resistor is connected to the second terminal and / or the third terminal of the first transistor and serves as the second terminal of the filter circuit.

10. The global shutter pixel of claim 1, wherein, The photosensitive unit includes: A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

11. The global shutter pixel of claim 5, wherein, The transmission unit includes: The second transistor; the second terminal of the second transistor is connected to the photosensitive unit, the third terminal of the second transistor is connected to the input terminal of the amplification unit, and the second transistor is controlled by the first control signal.

12. The global shutter pixel of claim 5, wherein, The reset unit includes: The third transistor; the second terminal of the third transistor is connected to the input terminal of the amplification unit, the third terminal of the third transistor is connected to the pixel power supply, and the third transistor is controlled by the second control signal.

13. The global shutter pixel of claim 5, wherein, The amplifier circuit includes: The fourth transistor and the fifth transistor; the first terminal of the fourth transistor serves as the input terminal of the amplifier circuit, the third terminal of the fourth transistor is connected to the pixel power supply, the second terminal of the fourth transistor is connected to the third terminal of the fifth transistor and serves as the first terminal of the amplifier circuit, the second terminal of the fifth transistor serves as the second terminal of the amplifier circuit, and the fifth transistor is controlled by the third control signal.

14. The global shutter pixel of claim 5, wherein, The first storage unit includes: A sixth transistor and a second capacitor; the second terminal of the sixth transistor is connected to the output terminal of the amplification unit, the third terminal of the sixth transistor is connected to the first terminal of the second capacitor and the first terminal of the second storage unit, the sixth transistor is controlled by a fourth control signal, and the second terminal of the second capacitor is connected to the port unit.

15. The global shutter pixel of claim 5, wherein, The second storage unit includes: A seventh transistor and a third capacitor; the second terminal of the seventh transistor is connected to the first memory cell as the first terminal of the second memory cell, the third terminal of the seventh transistor is connected to the first terminal of the third capacitor and the input terminal of the output cell, the seventh transistor is controlled by a fifth control signal, and the second terminal of the third capacitor is connected to the port cell.

16. The global shutter pixel of claim 5, wherein, The output unit includes: The eighth transistor and the ninth transistor; the first terminal of the eighth transistor serves as the input terminal of the output unit, the third terminal of the eighth transistor is connected to the pixel power supply, the second terminal of the eighth transistor is connected to the third terminal of the ninth transistor, the second terminal of the ninth transistor serves as the output terminal of the output unit, and the ninth transistor is controlled by the sixth control signal.

17. An image sensor, comprising: Includes the global shutter pixel as described in any one of claims 1 to 16.

Images