Adaptive communication device

Abstract

A communication device that includes a pair of dies and a die-to-die interconnect that includes first group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes and are associated with first different skew values. The pair is configured to: (a) receive, at the first die transmission lanes, first input data that is arranged at a first defined order; (b) transmit the first data signals over the die-to-die interconnect according to a first programmable virtual mapping between the first die transmission lanes and the second die reception lanes; (c) compensate for the first different skew values; and (d) reorder first data received by the second die reception lanes to provide first output data that is arranged according to the first defined order.

Description

10068-USADAPTIVE COMMUNICATION DEVICE

[0001] Chip-on-Wafer-on-Substrate (CoWoS) is an example of an interposer-based packaging technology. Multiple dies (some of which are located side by side) are bonded through micro-bumps on one side of a silicon interposer forming a chip-on-wafer (CoW). Another side of the CoW is bonded through bumps to a package substrate to form the CoWoS.

[0002] The interposer includes an interconnect that includes multiple signal conductors configured to convey multiple high-frequency signals.

[0003] Figure 1 illustrates an example of pins of a first die (Die_0 10), and pins of a second die (Die_l 20) connected using an advanced UCIe x64 (UCIe xA64) die-to-die connection 9. The receive pins of the first die (RX pins - Die_0 11) are interconnected to the transmit pins of the second die (TX pins -Die_l 22). The transmit pins of the first die (TX pins - Die_0 12) are interconnected to the receive pins of the second die (RX pins -Die_l 21).

[0004] The interconnect has multiple levels of conducting elements connected to vias.

[0005] Figure 2 illustrates interconnects that use a via blocking configuration 18 - see conductive paths 40(1) -40(10) that includes vertical vias that virtually intersect each other -and interconnect the first die transmission unit (Die_0 TX 14) to the second die reception unit (Die_l RX 23). In the via blocking configuration vias that are connected to certain bumps virtually block signal conveying conductors - and requires to use bypassing solutions that increase the size of the interconnect.

[0006] In the via blocking configuration 18 the conductive paths 40(l)-40(10) are of the same length and exhibit the same latency.

[0007] There is a growing need to provide an adaptive high frequency interconnect.SUMMARY

[0008] According to an embodiment there is provided a communication device that includes (i) a pair of dies that includes a first die and a second die; and (ii) a die-to-die interconnect configured to convey first data signals between the first die and the second die. The frequency of the first data signals is not lower than Gigahertz. The die-to-die interconnect includes a first group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes; wherein first different signal conveying conductors of the first group are associated with first different skew values. The pair is configured to: (a) receive, at the first die transmission lanes, first input data that is arranged at a first defined order; (b) transmit the first data signals over the die-to-die10068-USinterconnect according to a first programmable virtual mapping between the first die transmission lanes and the second die reception lanes; the first data signals represent the first input data, (c) compensate for the first different skew values; and (d) reorder first data received by the second die reception lanes to provide first output data that is arranged according to the first defined order.

[0009] According to an embodiment, the pair includes a skew compensation circuit that is configured to measure a skew per signal conveying conductor.

[0010] According to an embodiment, the skew compensation circuit is configured to convey feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.

[0011] According to an embodiment, the communication device includes a first sideband unit configured to convey the feedback.

[0012] According to an embodiment, the feedback is associated with a first die transmission lane identifier, and wherein the first die is configured to send a feedback message associated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier.

[0013] According to an embodiment, the feedback is associated with a first die transmission lane identifier.

[0014] According to an embodiment, the skew compensation circuit includes a clock signals generator for generating multiple clock signals that differ from each other by phase.

[0015] According to an embodiment, the skew compensation circuit is configured to select, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

[0016] According to an embodiment, the skew compensation circuit includes a second die reordering circuit that is downstream to second die physical layer reception circuits.

[0017] According to an embodiment, the first group of signal conveying conductors includes a plurality of first sub-groups of signal conveying conductors; wherein the plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between first die transmitter module and corresponding second die receiver modules; and wherein the pair is configured to transmit the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.10068-US

[0018] According to an embodiment, the die-to-die interconnect includes a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes; wherein different signal conveying conductors of the second group are associated with second different skew values; wherein the pair is configured to: (a) receive, at the second die transmission lanes, second input data that is arranged at a second defined order; (b) transmit the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data, (c) compensate for the second different skew values; and (d) reorder second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.

[0019] According to an embodiment there is provided a method for communication between dies, the method includes (a) receiving, at a first die transmission lanes of a communication device, input data that is arranged at a first defined order; (b) transmitting first data signals over a die-to-die interconnect according to a programmable virtual mapping between the first die transmission lanes and second die reception lanes; the first data signals represent the first input data; the die-to-die interconnect couples a first die of the communication device to a second dies of the communication device; wherein a frequency of the first data signals is not lower than Giga-Hertz; wherein the die-to-die interconnect includes a group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes; wherein different signal conveying conductors of the group are associated with different skew values; (c) compensating for first different skew values; and (b) reordering data received by the second die reception lanes to provide second output data that is arranged according to the second defined order.

[0020] According to an embodiment, the method includes measuring, by a skew compensation circuit, a skew per signal conveying conductor.

[0021] According to an embodiment, the method includes conveying, by the skew compensation circuit, feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.

[0022] According to an embodiment, the method includes using first sideband unit to convey the feedback.

[0023] According to an embodiment, the feedback is associated with a first die transmission lane identifier, and wherein the method includes sending, by the first die, a feedback message10068-USassociated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier.

[0024] According to an embodiment, the feedback is associated with a first die transmission lane identifier.

[0025] According to an embodiment, the method includes generating, by a clock signals generator of the skew compensation circuit, multiple clock signals that differ from each other by phase.

[0026] According to an embodiment, the method includes selecting, by the skew compensation circuit, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

[0027] According to an embodiment, the method includes reordering data units outputted by second die physical reception circuits by second die re-ordering circuit of the skew compensation circuit.

[0028] According to an embodiment, the first group of signal conveying conductors includes a plurality of first sub-groups of signal conveying conductors; wherein the plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between first die transmitter module and corresponding second die receiver modules; and wherein the pair is configured to transmit the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.

[0029] According to an embodiment, the die-to-die interconnect includes a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes; wherein different signal conveying conductors of the second group are associated with second different skew values. The method further includes: (a) receiving, at the second die transmission lanes, second input data that is arranged at a second defined order; (b) transmitting the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data, (c) compensating for the second different skew values; and (d) reordering second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.10068-USBRIEF DESCRIPTION OF THE DRAWINGS

[0030] The subject matter regarding the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

[0031] FIG. 1 illustrates an example of a prior art Advanced UCIe x64 (UCIe xA64) die-to-die connection;

[0032] FIG. 2 illustrates an example of a prior art via blocking configuration;

[0033] FIG. 3 illustrates an example of a via non-blocking configuration;

[0034] FIG. 4 illustrates an example of a first die transmission unit, an interconnect, a second die reception unit, and additional circuits;

[0035] FIG. 5 illustrates an example of a second die transmission unit, an interconnect, a first die reception unit, and additional circuits;

[0036] FIG. 6 illustrates an example of reordering; and

[0037] FIG. 7 illustrates an example of a method.DETAILED DESCRIPTION OF THE DRAWINGS

[0038] There is provided an interconnect for high frequency signals.

[0039] Figure 3 illustrates interconnects that use a via non-blocking configuration 19 - see conductive paths 40(1) -40(10) that includes vertical vias that do not virtually intersect each other - and interconnect the first die transmission unit (Die_0 TX 14) to the second die reception unit (Die_l RX 23). In the via non-blocking configuration there is no need to use bypassing solutions that increase the size of the interconnect.

[0040] In the via non-blocking configuration 19 the conductive paths 40(l)-40(10) are of different lengths and exhibit different latencies.

[0041] There is provided a solution that logically any mapping between transmission lanes of a transmission unit of one die and reception lanes of a reception unit of the other die.

[0042] According to an embodiment, the solution compensates for skews associated with different latencies and also solves out-of-order reception at reception lanes of the other die.

[0043] According to embodiment the solution uses one or more sideband paths which is easy to implements and does not disrupt the interconnect.

[0044] According to an embodiment there is provided a communication device that includes (i) a pair of dies that includes a first die and a second die; and (ii) a die-to-die interconnect10068-USconfigured to convey first data signals between the first die and the second die. The frequency of the first data signals is not lower than Gigahertz. The die-to-die interconnect includes a first group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes; wherein first different signal conveying conductors of the first group are associated with first different skew values. The pair is configured to: (a) receive, at the first die transmission lanes, first input data that is arranged at a first defined order; (b) transmit the first data signals over the die-to-die interconnect according to a first programmable virtual mapping between the first die transmission lanes and the second die reception lanes; the first data signals represent the first input data, (c) compensate for the first different skew values; and (d) reorder first data received by the second die reception lanes to provide first output data that is arranged according to the first defined order.

[0045] According to an embodiment, the pair includes a skew compensation circuit that is configured to measure a skew per signal conveying conductor.

[0046] According to an embodiment, the skew compensation circuit is configured to convey feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.

[0047] According to an embodiment, the communication device includes a first sideband unit configured to convey the feedback.

[0048] According to an embodiment, the feedback is associated with a first die transmission lane identifier, and wherein the first die is configured to send a feedback message associated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier.

[0049] According to an embodiment, the feedback is associated with a first die transmission lane identifier.

[0050] According to an embodiment, the skew compensation circuit includes a clock signals generator for generating multiple clock signals that differ from each other by phase.

[0051] According to an embodiment, the skew compensation circuit is configured to select, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

[0052] According to an embodiment, the skew compensation circuit includes a second die reordering circuit that is downstream to second die physical layer reception circuits.10068-US

[0053] According to an embodiment, the first group of signal conveying conductors includes a plurality of first sub-groups of signal conveying conductors; wherein the plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between first die transmitter module and corresponding second die receiver modules; and wherein the pair is configured to transmit the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.

[0054] According to an embodiment, the die-to-die interconnect includes a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes; wherein different signal conveying conductors of the second group are associated with second different skew values; wherein the pair is configured to: (a) receive, at the second die transmission lanes, second input data that is arranged at a second defined order; (b) transmit the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data, (c) compensate for the second different skew values; and (d) reorder second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.

[0055] Figure 4 is an example of first die 101, second die 102, die-to-die interconnect 103, first die transmission unit 111, second die reception unit 112 and first sideband unit 63.

[0056] The first sideband unit 63 includes first sideband first die portion 63-1 for generating feedback signals, one or more signal conveying conductors 63-2 and first sideband second die portion 63-3 for receiving the feedback signals and providing the feedback signals to the correct transmission lane.

[0057] Figure 4 also illustrates a first clock unit that includes first clock generator 61 and first phases generation unit 62 for providing clock signals to the first die transmission unit 111, second die reception unit 112 - and especially for providing multiple clock signals that differ from each other by phase.

[0058] The first die transmission unit 111 includes four first die transmission modules that include first die logic units 52(0), 52(1), 52(2) and 52(3) and associated transmission lanes.

[0059] The four first die transmission modules distribute data segments between associated transmission lanes.

[0060] First die first logic unit 52(0) is associated with a first die first sub-group of transmission lanes that includes first die first serializers 53 A till 53B, first die first adaptable10068-USde-skew units 55A-55B, and first die first transmitters 54A -54B, which are physically mapped to a first sub-groups of signal conveying conductors UCI_links 71A-71B.

[0061] First die second logic unit 52(1) is associated with a first die second sub-group of transmission lanes that includes first die second serializers 53C till 53D, first die second adaptable de-skew units 55C-55D, and first die second transmitters 54C -54D, which are physically mapped to a second sub-groups of signal conveying conductors UCI_links 71C-71D.

[0062] First die third logic unit 52(2) is associated with a first die third sub-group of transmission lanes that includes first die third serializers 53E till 53F, first die third adaptable de-skew units 55E-55F, and first die third transmitters 54E -54F, which are physically mapped to a third sub-groups of signal conveying conductors UCI_links 71E-71F.

[0063] First die fourth logic unit 52(3) is associated with a first die fourth sub-group of transmission lanes that includes first die fourth serializers 53G till 53H, first die fourth adaptable de-skew units 55G-55H, and first die fourth transmitters 54G-54H, which are physically mapped to a fourth sub-groups of signal conveying conductors UCI_links 71G-71H.

[0064] The first die transmission unit 111 also includes input unit 51 for receiving first input data and distributing it between the four modules. According to an embodiment the input unit is a reception multi module PHY logic (MMPL).

[0065] The second die reception unit 112 includes four second die reception modules that include four second die physical units 58(0), 58(1), 58(2) and 58(3), four second die reorder units 59(0), 59(1), 59(2) and 59(3), and associated reception lanes.

[0066] Second die first physical unit 58(0) is followed by second die first reorder unit 59(0) and is preceded by reception lanes that include second die first receivers 56A-56B, second die first sets of flipflops 57A-57B for selecting one of different clock signals.

[0067] Second die second physical unit 58(1) is followed by second die second reorder unit 59(1) and is preceded by reception lanes that include second die second receivers 56C-56D, second die second sets of flipflops 57C-57D for selecting one of different clock signals.

[0068] Second die third physical unit 58(2) is followed by second die third reorder unit 59(2) and is preceded by reception lanes that include second die third receivers 56E-56F, second die third sets of flipflops 57E-57F for selecting one of different clock signals.

[0069] Second die fourth physical unit 58(3) is followed by second die fourth reorder unit 59(3) and is preceded by reception lanes that include second die fourth receivers 56G-56H, second die fourth sets of flipflops 57G-57H for selecting one of different clock signals.10068-US

[0070] According to an embodiment, the four second die reorder units 59(0), 59(1), 59(2) and 59(3) are followed by an output unit that aggerates the data segments outputted from the four second die reorder segments. According to an embodiment the output unit is an output MMPL.

[0071] Figure 5 is an example of first die 101, second die 102, die-to-die interconnect 103, second die transmission unit 114, a first die reception unit 113, and second sideband unit 66.

[0072] Any reference to the first die transmission unit 111 should be applied mutatis mutandis, to the second die transmission unit 114. Any reference to the second die reception unit 112 should be applied mutatis mutandis, to the first die reception unit 113.

[0073] Any reference to the first sideband unit 63 should be applied mutatis mutandis, to the second sideband unit 66.

[0074] Any reference to the first clock unit should be applied mutatis mutandis to the second clock unit.

[0075] The second sideband unit 66 includes second sideband second die portion 66-1 for generating feedback signals, one or more signal conveying conductors 66-2 and first sideband first die portion 66-3 for receiving the feedback signals and providing the feedback signals to the correct transmission lane.

[0076] Figure 5 also illustrates a second clock unit that includes second clock generator 64 and second phases generation unit 65 for providing clock signals to the second die transmission unit 114, first die reception unit 113 - and especially for providing multiple clock signals that differ from each other by phase.

[0077] The second die transmission unit 114 includes four second die transmission modules that include second die first logic units 82(0), 82(1), 82(2) and 82(3) and associated transmission lanes.

[0078] The four second die transmission modules distribute data segments between associated transmission lanes.

[0079] Second die first logic unit 82(0) is associated with a second die first sub-group of transmission lanes that includes second die first serializers 83A till 83B, second die first adaptable de-skew units 85A-85B, and second die first transmitters 84A -84B, which are physically mapped to a first sub-groups of signal conveying conductors UCI_links 72A-72B.

[0080] Second die second logic unit 82(1) is associated with a second die second sub-group of transmission lanes that includes second die second serializers 83C till 83D, second die second adaptable de-skew units 85C-85D, and second die second transmitters 84C-84D, which are physically mapped to a second sub-groups of signal conveying conductors UCI_links 72C-10068-US

[0081] Second die third logic unit 82(2) is associated with a second die third sub-group of transmission lanes that includes second die third serializers 83E till 83F, second die third adaptable de-skew units 85E-85F, and second die third transmitters 84E -84F, which are physically mapped to a third sub-groups of signal conveying conductors UCI_links 72E-72F.

[0082] Second die fourth logic unit 82(3) is associated with a second die fourth sub-group of transmission lanes that includes second die fourth serializers 83G till 83H, second die fourth adaptable de-skew units 85G-85H, and second die fourth transmitters 84G -84H, which are physically mapped to a fourth sub-groups of signal conveying conductors UCI_links 72G-72H.

[0083] The second die transmission unit 114 also includes input unit 81 for receiving first input data and distributing it between the four modules. According to an embodiment the input unit is a reception MMPL.

[0084] The first die reception unit 113 includes four first die reception modules that include four first die physical units 88(0), 88(1), 88(2) and 88(3), four first die reorder units 89(0), 89(1), 89(2) and 89(3), and associated reception lanes.

[0085] First die first physical unit 88(0) is followed by first die first reorder unit 89(0) and is preceded by reception lanes that include first die first receivers 86A-86B, first die first sets of flipflops 87A-87B for selecting one of different clock signals.

[0086] First die second physical unit 88(1) is followed by first die second reorder unit 89(1) and is preceded by reception lanes that include first die second receivers 86C-86D, first die second sets of flipflops 87C-87D for selecting one of different clock signals.

[0087] First die third physical unit 88(2) is followed by first die third reorder unit 89(2) and is preceded by reception lanes that include first die third receivers 86E-86F, first die third sets of flipflops 87E-87F for selecting one of different clock signals.

[0088] First die fourth physical unit 88(3) is followed by first die fourth reorder unit 89(3), and is preceded by reception lanes that include first die fourth receivers 86G-86H, first die fourth sets of flipflops 87G-87H for selecting one of different clock signals.

[0089] According to an embodiment, the four first die reorder units 89(0), 89(1), 89(2) and 89(3) are followed by an output unit that aggerates the data segments outputted from the four first die reorder segments. According to an embodiment the output unit is an output MMPE.

[0090] Figure 6 illustrates an example of first input data segmented to eight segments S1-S8 701-708, each segment includes sixty four bytes - SI 701 includes D0-D63, S2702 includes D64-D127, S3703 includes D128-D191, S4704 includes D192-D255, S5705 includes10068-USD256-D319, S6706 includes D320-D383, S7707 includes D384-D447 and S8708 includes D448-D551.

[0091] SI and S5 are provided to first die first logic unit 52(0), each data byte is associated with a transmission lane identifier - DO till D63 are associated with the zeroth till sixty third transmission lanes identifiers TL0-ID till TL63-ID. For simplicity of explanation the 0th, 1st, 62ndand the 63rddata bytes and transmission identifiers are shown.

[0092] Due to a different latencies associated with different conductive paths - the second die first physical unit 58(0) received the data units out of order (see for example the 54th, 22nd, 33rdand 44thdata bytes) and provides the out of order data bytes to the second die first reorder unit 59(0) that reorders the data bytes associated to their original order.

[0093] For simplicity of explanation only some of the data units related to S1-S8 were illustrated.

[0094] According to an embodiment, and as illustrated in figures 4 and 5, the lanes are remapped within a module and lanes are not remapped across the modules. According to an embodiment the lane remapping may be applied outside the module borders.

[0095] According to an embodiment, lane remapping routing is done at either an interposer level or at substrate level.

[0096] According to an embodiment, a physical lane remapping information (links between transmission lanes and reception lanes is known.

[0097] According to an embodiment, the physical lane remapping information is configured / programmed in a memory unit or registers in the transmission unit. For example -the zeroth transmission lane is connected to the first reception lane, the 25thtransmission lane is connected to the 30threception lane and so on.

[0098] Using this mapping physical lane remapping information, a feedback message received over a sideband unit is diverted to correct transmission lane to adjust the skew under skew handling point.

[0099] According to an embodiment one or more iteration of skew reduction are executed.

[0100] According to an embodiment the transmission unit performs a sweep of the clock signals phase. On each iteration the transmission unit sends phase calibration messages such as an LFSR pattern, along with a data byte and a clock signal.

[0101] The reception unit analyzes the LFSR pattern and provides the results to the transmission unit at each phase iteration and for each transmission lane.

[0102] The transmission unit uses the physical lane remapping information to divert the sideband messages to correct transmission path.10068-US

[0103] The local transmitter uses the results to find the optimal clock phase that is best synchronized with the received data byte for each reception lane.

[0104] The local transmitter uses the optimal configuration to adjust the skew for each transmission lane.

[0105] The transmission unit performs multiple iteration (one per transmission lane) of a “per lane ID” test pattern, along with a data unit also provided a clock signal.

[0106] According to an embodiment, the reception unit analyzes the test pattern and exchanges messages with the transmission unit, using the side band unit and Tx-to-Rx Lane remapping, to coordinate the reorder function.

[0107] Figure 7 illustrates an example of method 600 for communication between dies.

[0108] According to an embodiment method 600 starts by step 610 of receiving, at a first die transmission lanes of a communication device, input data that is arranged at a first defined order.

[0109] According to an embodiment, step 610 is followed by step 620 of transmitting first data signals over a die-to-die interconnect according to a programmable virtual mapping between the first die transmission lanes and second die reception lanes. The first data signals represent the first input data.

[0110] According to an embodiment, the die-to-die interconnect couples a first die of the communication device to a second dies of the communication device. A frequency of the first data signals is not lower than Gigahertz. The die-to-die interconnect includes a group of signal conveying conductors that implement a first physical mapping between the first die transmission lanes and second die reception lanes. Different signal conveying conductors of the group are associated with different skew values.

[0111] According to an embodiment, step 610 is also followed by step 630 of compensating for first different skew values.

[0112] According to an embodiment, steps 620 and 630 are executed in parallel manner or in serial manner. According to an embodiment, one or more iterations of steps 620 and 630 are performed.

[0113] According to an embodiment multiple iterations of steps 620 and 630 are executed till the skew for each reception lane is determined and once determined step 620 while applying step 630 using the known skew.10068-US

[0114] According to an embodiment, step 620 is also followed by step 640 of reordering data received by the second die reception lanes to provide second output data that is arranged according to the second defined order.

[0115] According to an embodiment, step 640 is a part of step 630.

[0116] According to an embodiment, step 630 includes at least one of:a. Measuring, by a skew compensation circuit, a skew per signal conveying conductor.b. Conveying, by the skew compensation circuit, feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.c. Using the first sideband unit to convey the feedback.d. Sending, by the first die, a feedback message associated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier. This utilizing the association of the feedback with a first die transmission lane identifier.e. Generating, by a clock signals generator of the skew compensation circuit, multiple clock signals that differ from each other by phase.f. Selecting, by the skew compensation circuit, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

[0117] According to an embodiment, step 640 is executed by second die physical reception circuits by second die re-ordering circuit of the skew compensation circuit.

[0118] According to an embodiment the method is applied on a module to module basis. In this case the first group of signal conveying conductors includes a plurality of first sub-groups of signal conveying conductors. The plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between the first die transmitter module and corresponding second die receiver modules. In this case the method includes transmitting the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.

[0119] Any reference to first die transmission lanes and second die reception lanes should be applied mutatis mutandis to second die transmission lanes and first die reception lanes.10068-US

[0120] According to an embodiment, the die-to-die interconnect includes a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes; wherein different signal conveying conductors of the second group are associated with second different skew values.

[0121] In this case method further includes: (a) receiving, at the second die transmission lanes, second input data that is arranged at a second defined order; (b) transmitting the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data, (c) compensating for the second different skew values; and (d) reordering second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.

[0122] In the foregoing detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0123] The subject matter regarding the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.

[0124] It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

[0125] Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.10068-US

[0126] Any reference in the specification to a method should be applied mutatis mutandis to a device or system capable of executing the method.

[0127] Any reference in the specification to a system or device should be applied mutatis mutandis to a method that may be executed by the system,

[0128] Any combination of any module or unit listed in any of the figures, any part of the specification and / or any claims may be provided.

[0129] Any combinations of systems, units, components, processors, sensors, illustrated in the specification and / or drawings may be provided.

[0130] While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above-described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.

[0131] In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0132] Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

[0133] Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

[0134] Furthermore, those skilled in the art will recognize that the boundaries between the above-described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative10068-USembodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0135] Also, for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within the same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

[0136] However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

[0137] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘includes ’ does not exclude the presence of other elements or steps than those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first" and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

[0138] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

[0139] It is appreciated that various features of the embodiments of the disclosure which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the embodiments of the disclosure which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0140] It will be appreciated by people skilled in the art that the embodiments of the disclosure are not limited by what has been particularly shown and described hereinabove. The10068-USscope of the embodiments of the disclosure is defined by the appended claims and equivalents thereof.

Claims

10068-USWe claim1. A communication device, comprising:a pair of dies that comprises a first die and a second die; anda die-to-die interconnect configured to convey first data signals between the first die and the second die, wherein a frequency of the first data signals is not lower than 1 Gigahertz;wherein the die-to-die interconnect comprises a first group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes;wherein first different signal conveying conductors of the first group are associated with first different skew values;wherein the pair is configured to:(a) receive, at the first die transmission lanes, first input data that is arranged at a first defined order;(b) transmit the first data signals over the die-to-die interconnect according to a first programmable virtual mapping between the first die transmission lanes and the second die reception lanes; the first data signals represent the first input data;(c) compensate for the first different skew values; and(d) reorder first data received by the second die reception lanes to provide first output data that is arranged according to the first defined order.

2. The communication device according to claim 1, wherein the pair comprises a skew compensation circuit that is configured to measure a skew per signal conveying conductor.

3. The communication device according to claim 2, wherein the skew compensation circuit is configured to convey feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.

4. The communication device according to claim 3, comprising a first sideband unit configured to convey the feedback.

5. The communication device according to claim 4, wherein the feedback is associated with a first die transmission lane identifier, and wherein the first die is configured to send a feedback message associated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier.10068-US6. The communication device according to claim 3, wherein the feedback is associated with a first die transmission lane identifier.

7. The communication device according to claim 2, wherein the skew compensation circuit comprises a clock signals generator for generating multiple clock signals that differ from each other by phase.

8. The communication device according to claim 7, wherein the skew compensation circuit is configured to select, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

9. The communication device according to claim 2, wherein the skew compensation circuit comprises a second die re-ordering circuit that is downstream to second die physical layer reception circuits.

10. The communication device according to claim 1, wherein the first group of signal conveying conductors comprise a plurality of first sub-groups of signal conveying conductors; wherein the plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between first die transmitter module and corresponding second die receiver modules; and wherein the pair is configured to transmit the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.

11. The communication device according to claim 1 , wherein the die-to-die interconnect comprises a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes;wherein different signal conveying conductors of the second group are associated with second different skew values;wherein the pair is further configured to:(a) receive, at the second die transmission lanes, second input data that is arranged at a second defined order;(b) transmit the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data;(c) compensate for the second different skew values; and10068-US(d) reorder second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.

12. A method for communication between dies, the method comprising:receiving, at a first die transmission lanes of a communication device, input data that is arranged at a first defined order;transmitting first data signals over a die-to-die interconnect according to a programmable virtual mapping between the first die transmission lanes and second die reception lanes; the first data signals represent the first input data; the die-to-die interconnect couples a first die of the communication device to a second dies of the communication device; wherein a frequency of the first data signals is not lower than 1 Gigahertz; wherein the die-to-die interconnect comprises a group of signal conveying conductors that implement a first physical mapping between first die transmission lanes and second die reception lanes; wherein different signal conveying conductors of the group are associated with different skew values;compensating for first different skew values; andreordering data received by the second die reception lanes to provide second output data that is arranged according to the second defined order.

13. The method according to claim 12, further comprising measuring, by a skew compensation circuit, a skew per signal conveying conductor.

14. The method according to claim 13, further comprising conveying, by the skew compensation circuit, feedback from the second die reception lanes regarding a synchronization of the second die reception lanes with the first data signals.

15. The method according to claim 14, comprising using first sideband unit to convey the feedback.

16. The method according to claim 15, wherein the feedback is associated with a first die transmission lane identifier, and wherein the method further comprises sending, by the first die, a feedback message associated with a given first die transmission lane identifier to a first die transmission lane identified by the first die transmission lane identifier.

17. The method according to claim 14, wherein the feedback is associated with a first die transmission lane identifier.10068-US18. The method according to claim 13, further comprising generating, by a clock signals generator of the skew compensation circuit, multiple clock signals that differ from each other by phase.

19. The method according to claim 18, comprising selecting, by the skew compensation circuit, for each second reception lane, a selected clock signal of the multiple clock signals, for compensating for a skew of a signal conveying conductor associated with the second die reception lane.

20. The method according to claim 13, further comprising reordering data units outputted by second die physical reception circuits by second die re-ordering circuit of the skew compensation circuit.

21. The method according to claim 13, wherein the first group of signal conveying conductors comprise a plurality of first sub-groups of signal conveying conductors; wherein the plurality of first sub-groups of signal conveying conductors implement a first physical sub-mappings between first die transmitter module and corresponding second die receiver modules; and wherein the pair is configured to transmit the second data signals over the die-to-die interconnect according to a second programmable virtual sub-mappings between the second die transmitter modules and the first die receiver modules.

22. The method according to claim 12, wherein the die-to-die interconnect comprises a second group of signal conveying conductors that implement a second physical mapping between second die transmission lanes and first die reception lanes; wherein different signal conveying conductors of the second group are associated with second different skew values; wherein the method further comprises:receiving, at the second die transmission lanes, second input data that is arranged at a second defined order;transmitting the second data signals over the die-to-die interconnect according to a second programmable virtual mapping between the second die transmission lanes and the first reception lanes; the second data signals represent the second input data, compensating for the second different skew values; andreordering second data received by the first die reception lanes to provide second output data that is arranged according to the second defined order.

Images