Light receiving device and light receiving circuit

Abstract

[Problem] To make it possible to suppress an increase in the time interval of a pulse signal capable of passing through a wire. [Solution] This light receiving device comprises: a photoelectric conversion unit that outputs a detection signal in response to detection of photons; a signal output unit that alternately outputs a first signal at a first level and a second signal at a second level different from the first level in response to the detection signal; and a time difference output unit that outputs a digital signal on the basis of a time difference between a first input time point of the first signal inputted via a wire, a second input time point of the second signal, and a predetermined time point.

Description

Light receiving device and light receiving circuit

[0006] ,

[0001] The present disclosure relates to a light receiving device and a light receiving circuit.

[0002] When measuring the distance to a detection target, the ToF (Time Of Flight) method is often used. In this ToF method, the detection signal of a photodetector is read out as a pulse train via a wiring, and the signal arrival time is converted into a digital value by a TDC (Time to Digital Converter) (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-092437

[0004] However, due to the higher density of wirings, the wiring RC time constant deteriorates. Due to this deterioration of the wiring RC time constant, there is a risk that the time interval (dead time) of pulse signals that can pass through the wiring will increase.

[0005] In order to solve the above problems, according to the present disclosure, there is provided a light receiving device including: a photoelectric conversion unit that outputs a detection signal in response to the detection of photons; a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal; and a time difference output unit that outputs a digital signal based on time differences between a first input time of the first signal input via a wiring, a second input time of the second signal, and a predetermined time.

[0006] The signal output unit may divide the detection signal, which is a pulse signal, by two and output it.

[0007] It may have a flip-flop that continuously and alternately outputs the first signal and the second signal in response to the detection signal.

[0008] The flip-flop may alternately hold and output the first signal and the second signal in response to the detection signal.

[0009] The flip-flop is a D flip-flop, the photoelectric conversion unit inputs the detection signal to the first input terminal of the D flip-flop, and the signal output unit may further include a first inverter connected between the output terminal of the D flip-flop and the second input terminal of the D flip-flop.

[0010] The flip-flop is a T-flip-flop, the photoelectric conversion unit inputs the detection signal to the input terminal of the T-flip-flop, and the signal output unit may alternately output the first signal and the second signal from the output terminal of the T-flip-flop.

[0011] The photoelectric conversion unit includes a single-photon avalanche diode that reacts with photons, and a second inverter whose input terminal is connected to the cathode of the single-photon avalanche diode. The detection signal may be output from the output terminal of the second inverter.

[0012] The time-difference output unit may include a first time-digital converter that outputs a digital signal based on the time difference between the first input time and the predetermined time, and a second time-digital converter that outputs a digital signal based on the time difference between the second input time and the predetermined time.

[0013] The time-difference output unit may include a pulse regeneration circuit that outputs a pulse signal of a predetermined time width from the time of input of the first signal and outputs a pulse signal of the predetermined time width from the time of input of the second signal, and a third time-digital converter that outputs a digital signal based on the time difference between the time of input of the pulse signal output by the pulse regeneration circuit and the predetermined time.

[0014] The system may further include a histogram generator that generates a histogram of the frequency of occurrence of the output values ​​of the time-delay output unit.

[0015] A pixel array section may be provided in which a plurality of photodetection circuits, each having the photoelectric conversion unit and the signal output unit, are arranged in a matrix. A plurality of the photodetection circuits at one end of the plurality of photodetection circuits arranged in the same row of the pixel array section may be connected to the time difference output unit at the one end via a first wiring, and a plurality of the photodetection circuits at the other end may be connected to the time difference output unit at the other end via a second wiring.

[0016] Multiple photodetectors, which are arranged at predetermined intervals from among the multiple photodetectors arranged in the same row, may be connected to the first wiring.

[0017] The detection signals from multiple photoelectric conversion units may be input to the signal output unit via a multiplexer.

[0018] The photoelectric conversion unit may include a plurality of pixel array units arranged in a matrix, and a plurality of signal output units corresponding to each of the plurality of photoelectric conversion units may be arranged side by side in a region different from the pixel array unit.

[0019] The output signals from multiple signal output units may be input to the time-difference output unit via a multiplexer.

[0020] The photoelectric conversion unit comprises a pixel array unit arranged in a matrix, a first stacked unit on which a plurality of signal output units corresponding to the plurality of photoelectric conversion units are arranged, and a second stacked unit on which wiring connecting the plurality of time-difference output units corresponding to the plurality of signal output units is arranged, and the pixel array unit, the first stacked unit, and the second stacked unit may be stacked.

[0021] The signal output section of the first laminated section and the corresponding wiring of the second laminated section may be electrically connected by a splicing connection.

[0022] Each of the multiple signal output units has a plurality of buffers to which it is connected, the plurality of buffers are connected to the time-difference output unit via the same third wiring, and the system may further include a control circuit for driving one of the plurality of buffers.

[0023] A fourth wiring, which is bonded and connected to the third wiring, may be arranged in the first laminated portion.

[0024] To solve the above problems, the present disclosure provides a light receiving circuit comprising: a photoelectric conversion unit that outputs a detection signal in response to the detection of a photon; and a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal.

[0025] A diagram schematically showing an example of a distance measuring device according to this disclosure. A block diagram showing an example of a light source device and a light receiving device. A plan view of the light source unit. A diagram showing a detailed arrangement example of the SPAD array, readout circuit, and ITDC block. A diagram showing an example of the configuration of the light receiving circuit. A time chart showing an example of the operation of the light receiving circuit. A diagram showing an example of the configuration of the ITDC. A schematic diagram explaining the histogram generated by the histogram generator. A diagram showing an example of the configuration of the light receiving circuit according to a comparative example. A time chart showing an example of the operation of the light receiving circuit according to a comparative example. A diagram showing an example of the configuration of the light receiving circuit of a light receiving device according to Modification 1 of the first embodiment. A diagram showing a detailed arrangement example of the SPAD array, readout circuit, and TDC block. A diagram showing an example of the configuration of the time difference output unit according to the second embodiment. A time chart showing an example of the operation of the light receiving circuit according to the second embodiment. A diagram showing an example of the arrangement of the SPAD array, readout circuit, and ITDC block according to the third embodiment. A diagram showing an example of the configuration of the light receiving circuit according to the fourth embodiment. A diagram showing an example of the arrangement of the SPAD array, readout circuit, and ITDC block according to the fifth embodiment. A diagram showing an example of stacking of the light receiving device according to the sixth embodiment. A diagram showing an example of stacking. A diagram schematically showing an example of the buffer and wiring arrangement of the reading circuit section. A diagram schematically showing an example of the buffer and multiple wiring arrangements of the reading circuit section.

[0026] Embodiments of this disclosure will be described below with reference to the drawings.

[0027] (First Embodiment) Preferred embodiments of the present disclosure will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant explanations will be omitted.

[0028] Figure 1 schematically shows an example of a distance measuring device according to the present disclosure. The distance measuring device 1 in Figure 1 comprises a light source device 2, a collimator lens 3, a focusing lens 4, a bandpass filter 5, and a light receiving device 10. The light receiving device 10 comprises a SPAD array 11. The SPAD array 11 is an example of a photodetector array. The light source device 2 also includes a light-emitting element such as a vertical-cavity surface-emitting laser (VCSEL) and a driver circuit for the light-emitting element.

[0029] The light source device 2 emits optical EM toward the subject OBJ. The collimator lens 3 aligns the optical EM into parallel rays. The reflected light RL from the optical EM, reflected by the subject OBJ, enters the light receiving device 10. The focusing lens 4 focuses the reflected light RL onto the surface of the SPAD array 11. The bandpass filter 5 selectively transmits light corresponding to the wavelength band emitted from the light source device 2. Alternatively, a focusing lens with an integrated bandpass filter function may be used. Furthermore, the bandpass filter in the light receiving device may be omitted.

[0030] The distance measuring device 1 measures, for example, the time difference between the time t0 when a trigger signal for light emission is input to the light source device 2 and the time ts when the SPAD of the SPAD array 11 reacts. Based on this time difference, the distance measuring device 1 can calculate the distance between the device 1 and the subject OBJ. For example, if the speed of light is c, the distance from the distance measuring device 1 to the subject OBJ can be calculated using the formula L = c / 2(ts - t0). This method is generally called distance measurement by time of flight (ToF).

[0031] Figure 2 is a block diagram showing an example of a light source device 2 and a light receiving device 10. The light source device 2 in Figure 2 comprises a driver circuit 6 and a light source unit 7. Figure 3 shows an example of a plan view of the light source unit. As the light source unit 7, for example, an array light source 7A including a plurality of light-emitting elements 8 arranged in an array can be used. For example, a plurality of light-emitting elements 8 can be arranged in a grid pattern such as a rectangular grid, a parallelepiped grid, or a triangular grid on substantially the same plane to form an array light source 7A. In the following, the case in which the array light source 7A in Figure 2 is used as the light source unit 7 will be explained as an example. However, the arrangement of the light-emitting elements 8 and the number of light-emitting elements 8 in the array light source 7A are not specified.

[0032] Furthermore, a light source 7B (Figure 3) in which multiple light-emitting elements 8 are arranged linearly may be used as the light source 7. For example, a VCSEL can be used as the light-emitting element 8. However, the type of light-emitting element 8 is not limited. For example, an end-face emitting semiconductor laser may be used as the light-emitting element 8. Note that the configuration of the light source shown in Figure 3 is merely an example. For example, an LED light source or an organic EL light source that emits light from its entire surface may be used as the light source.

[0033] The light receiving device 10 in Figure 2 comprises a SPAD array 11, a readout circuit 12, a TDC block 13, an arithmetic circuit 14, a control circuit 16, a trigger generation circuit 18, and an interface circuit 19. The arithmetic circuit 14 includes a histogram generator 15 as an internal component. The control circuit 16 also includes a register 17 as an internal component.

[0034] The SPAD array 11 is an example of a pixel array and includes a plurality of SPAD pixels arranged substantially on the same plane. The SPAD pixels in this embodiment have SPADs (Single Photon Avalanche Diodes) and output a detection signal in response to the detection of photons. Details of the SPAD pixels will be described later with reference to Figure 5.

[0035] For example, multiple SPADs can be arranged in a grid such as a rectangular grid, a parallelepiped grid, or a triangular grid. Here, we will explain using the example of an SPAD array in which multiple SPADs are arranged in a square grid. However, the arrangement of SPADs in the SPAD array is not limited.

[0036] The readout circuit 12 is a circuit having a state transition unit. The state transition unit, for example, in response to a detection signal output by a SPAD pixel, alternately outputs a first signal at a first level and a second signal at a second level different from the first level. In this embodiment, the first level is a high level and the second level is a low level. In other words, the state transition unit outputs a signal that alternately switches between a high level and a low level in response to the detection signal. In this embodiment, the signal that alternately switches between a high level and a low level may be referred to as a pulse. Furthermore, the pulse in this embodiment is not limited to fixed values ​​for each of the repetition period, the high-level period and the low-level period. Thus, the readout circuit 12 outputs a pulse to the subsequent circuit when the SPAD in the SPAD array 11 reacts with a photon. For example, the readout circuit 12 may include at least one of a quench circuit that stops the avalanche phenomenon in the SPAD or a recharge circuit that resets the voltage level.

[0037] The following explanation uses a SPAD (Single Photon Avalanche Diode) as the photodetector as an example. However, other types of photodetectors may be used. For example, other types of photodiodes or phototubes may be used as photodetectors.

[0038] The TDC block 13 is a circuit block containing multiple ITDCs (Interleave Time to Digital Converters) or multiple TDCs (Time to Digital Converters). For example, the ITDCs in the TDC block 13 are connected to at least one pixel in the SPAD array 11. The ITDCs alternately measure the time difference between, for example, the rise edge time t1 of the pulse output from the readout circuit 12, the fall edge time t2 of the pulse, and the time t0 when the trigger generation circuit 18 outputs the trigger signal LT to the driver circuit 6.

[0039] The arithmetic circuit 14 performs various calculations based on signals input from, for example, the TDC block 13. For example, when the light receiving device 10 performs distance measurement, the arithmetic circuit 14 may calculate the distance between the subject OBJ and the light receiving device 10. However, the calculation of the distance between the subject OBJ and the light receiving device 10 may be performed by an external device. For example, a hardware circuit such as a microprocessor, ASIC, or FPGA can be used as the arithmetic circuit 14. The arithmetic circuit 14 may also be a combination of a hardware circuit and a program executed on that hardware circuit.

[0040] The histogram generator 15 accumulates the results of multiple flight time measurements by the ITDC in the TDC block 13, for example, and generates a histogram. By measuring the flight time multiple times, it becomes possible to distinguish between background light (ambient light) and reflected light RL emitted from the light source 7. The histogram generator 15 may also generate the histogram by averaging the flight times measured multiple times. Once the peak of the histogram is found, the distance between the distance measuring device 1 and the subject OBJ can be calculated using the above formula L = c / 2(ts - t0). Details of the processing example of the histogram generator 15 will be described later with reference to Figure 8. Furthermore, if the histogram generation process is performed by an external device, the histogram generator may be omitted.

[0041] The control circuit 16, for example, enables / disables the pixels in the SPAD array 11. For example, the control circuit 16 selectively controls the output of the readout circuit 12 connected to the same wiring in the SPAD array 11.

[0042] Also, the control circuit 16 controls the trigger generation circuit 18 so that the light EM is emitted toward the subject OBJ at a predetermined timing. The trigger generation circuit 18 that receives the control signal from the control circuit 16 supplies the trigger signal LT to the driver circuit 6 of the light source device 2. Then, the driver circuit 6 operates the light emitting element 8 of the light source unit 7 based on the trigger signal LT.

[0043] Note that the control circuit 16 may include a register 17. The register 17 may be used to set the operating conditions of the pixels in the SPAD array 11. Examples of the operating conditions of the pixels include the bias voltage of the photodiode, the sampling frequency in the SPAD array 11, the recharge current, the delay at which the quenching pulse is generated, the delay at which the recharge pulse is generated, and the like. Also, in the register 17, the light emission timing or the light emission conditions in the light source device 2 may be set.

[0044] As the control circuit 16, a hardware circuit such as a microprocessor, an ASIC, or an FPGA can be used. Also, the control circuit 16 may be a combination of a hardware circuit and a program executed on the hardware circuit. The control circuit 16 may be the same circuit as the above-described arithmetic circuit 14 or may be a separate circuit.

[0045] The interface circuit 19 realizes data communication with a device outside the light receiving device 10. For example, the control circuit 16 may receive a control signal from an external device via the interface circuit 19. Also, the arithmetic circuit 14 may transfer the measured data to an external device via the interface circuit 19. Note that the type of communication standard and communication protocol used in the interface circuit 19 is not limited.

[0046] FIG. 4 is a diagram showing a detailed layout example of the SPAD array, the readout circuit, and the ITDC block. As shown in FIG. 4, the light-receiving circuits 20 are arranged in a matrix. A readout circuit 12 is mounted for each SPAD in the SPAD array 11. That is, each light-receiving circuit 20 in the SPAD array 11 has a SPAD and a readout circuit 12 corresponding to this SPAD. Note that the light-receiving circuit 20 according to the present embodiment corresponds to a SPAD pixel. Also, the light-receiving circuit 20 may be referred to as a pixel in some cases. In this specification, it will be described assuming that pixels having a substantially square shape in plan view are used in the SPAD array 11. However, the shape of the pixels in the SPAD array 11 may be different from this. Also, the TDC block 13 according to the present embodiment will be described by taking an example of the ITDC 130, but it is not limited thereto. For example, as will be described later, the TDC block 13 may be configured by a single TDC 130d (see FIG. 12 etc. described later).

[0047] For example, two wirings L10 are connected to the light-receiving circuits 20 arranged in the row direction. One of the two wirings L10 is connected to the odd-numbered light-receiving circuits 20, and the other is connected to the even-numbered light-receiving circuits 20. That is, every other light-receiving circuit 20 is connected to each wiring L10. Note that the connection wiring L10 and the light-receiving circuit 20 to be connected are an example and are not limited thereto. For example, three or more wirings L10 may be connected to the light-receiving circuits 20 arranged in the same row. However, the higher the number of wirings L10, the faster the readout is possible, but the influence of the parasitic capacitance between the wirings L10 also increases. This readout is also affected by the parasitic resistance in addition to the parasitic capacitance between the wirings L10.

[0048] This wiring L10 is connected to one end of the ITDC 130. Also, the other end of the ITDC 130 is connected to the histogram generator 15. The histogram generator 15 generates a histogram of the output values for each ITDC 130.

[0049] Figure 5 is a diagram showing an example configuration of a light receiving circuit according to the present disclosure. As shown in Figure 5, the light receiving circuit 20 has a photoelectric conversion unit 110 and a reading circuit unit 120. Furthermore, Figure 5 shows the parasitic capacitance 126 of the wiring L10 and the ITDC 130. The parasitic capacitance 126 also includes the parasitic capacitance between the wiring L10.

[0050] The photoelectric conversion unit 110 reacts with photons to cause potential fluctuations. This photoelectric conversion unit 110 includes a current source 111, a photodiode 112, and an inverse conversion circuit 113. The photodiode 112 is, for example, a single-photon avalanche diode (SPAD). One end of the current source 111 is connected to the power supply terminal via a resistor, and the other end is connected to the cathode of the photodiode 112. That is, the cathode of the photodiode 112 and the current source 111 are connected to node A. The inverse conversion circuit 113 is connected to node A. In this way, the photodiode 112 and the resistor are connected in series between the power supply terminal and the ground terminal.

[0051] The photodiode 112 reacts with photons, causing its potential to decrease from a predetermined potential and then return to that predetermined potential. Note that the photodiode 112 is not limited to a SPAD, but can be any element that reacts with photons to cause potential fluctuations.

[0052] The inverse conversion circuit 113 outputs a high-level signal when the potential of node A in the photoelectric conversion unit 110 falls below a predetermined threshold. Conversely, the inverse conversion circuit 113 outputs a low-level signal when the potential of node A in the photoelectric conversion unit 110 exceeds a predetermined threshold. In other words, the photoelectric conversion unit 110 outputs a pulse detection signal in response to the detection of photons.

[0053] The reading circuit 120 continuously outputs a first signal at a first level (high level) and a second signal at a second level (low level) that is different from the first level, in response to the detection signal. That is, the reading circuit 120 alternately outputs a high-level signal and a low-level signal each time the potential of node A in the photoelectric conversion unit 110 falls below a predetermined threshold. This reading circuit 120 has a state transition unit 122 and a buffer circuit 125, which are connected in series.

[0054] The state transition unit 122 alternately outputs a high-level signal and a low-level signal each time the output signal of the inverse conversion circuit 113 changes from a low-level signal to a high-level signal. In other words, the state transition unit 122 divides the detection signal, which is a pulse signal, by two and outputs it. This state transition unit 122 includes, for example, a D flip-flop 123 and an inverse conversion circuit (inverter) 124. In this embodiment, the state transition unit 122 corresponds to the signal output unit. Furthermore, the state transition unit 122 is not limited to a D flip-flop and may be configured with a T flip-flop or the like, as will be described later.

[0055] One of the first input terminals (CLK terminal) of the D flip-flop 123 is connected to the output terminal of the inverse transformer circuit 113, and the other second input terminal (D terminal) is connected to the output terminal of the inverse transformer circuit 124. The input terminal of the inverse transformer circuit 124 is connected to node B. Also, the output terminal (Q terminal) of the D flip-flop 123 is connected to node B. In other words, the input terminal of the inverse transformer circuit 124 is connected to the output terminal (Q terminal) of the D flip-flop 123. Furthermore, the input terminal of the buffer circuit 125 is connected to node B, and the output terminal of the buffer circuit 125 is connected to ITDC 130 via wiring L10.

[0056] Figure 6 is a time chart showing an example of the operation of the light receiving circuit 20. The vertical axis shows the potentials of nodes A, B, and C from top to bottom. The horizontal axis is time. Specifically, from top to bottom, it shows the potential of the output signal of the photodiode 112, the potential of the output signal of the state transition unit 122, and the potential of the input signal of ITDC 130. The interval from time t1 to t3 is the time interval corresponding to the reaction interval of the photodiode 112.

[0057] At time t0, no photons have been received, and node A of the photodetector 20 maintains a high-level signal with a high potential. The inverse transformer circuit 121 inverts the potential of node A, maintaining a low-level signal with a low potential. In the following description, the high-level signal is described as a signal with a higher potential than the low-level signal, but is not limited to this. For example, the low-level signal may be described as a signal with a higher potential than the high-level signal.

[0058] At this time, the potential of terminal Q (node ​​B) in the D flip-flop 123 is a low-level signal. The inverse transformer circuit 124 inverts the low-level signal and inputs it as a high-level signal to terminal D (node ​​B) in the D flip-flop 123. The potential of terminal Q (node ​​B) is also input as a low-level signal to ITDC 130 via the buffer circuit 125 and wiring L10, and then via node C.

[0059] Next, just before time t1, a photon is received, and the potential of node A in the photodetector circuit 20 falls below the threshold at time t1. As a result, the inverse transformer circuit 121 inverts the potential of node A, which is the potential of the output signal of photodiode 112, and outputs a high-level signal. This causes the potential at the first input terminal (CLK terminal) of the D flip-flop 123 to shift from a low level to a high level, and the high-level signal at terminal D is stored in the D flip-flop 123. The signal stored in the D flip-flop 123 is then output as a high-level signal from terminal Q (node ​​B). The inverse transformer circuit 124 inverts the high-level signal and inputs it as a low-level signal to terminal D (node ​​B) of the D flip-flop 123.

[0060] Furthermore, the potential of terminal Q (node ​​B) is input to ITDC130 as the potential of node C via buffer circuit 125 and wiring L10 as a high-level signal. Due to the wiring RC time constant, it takes time for the potential of node C to rise from low level to high level, and it is input to ITDC130 as a high-level signal at time t2.

[0061] Next, just before time t3, a photon is received, and the potential of node A in the photodetector circuit 20 falls below the threshold at time t3. As a result, the inverse transformer circuit 121 inverts the potential of node A, which is the potential of the output signal of photodiode 112, and outputs a high-level signal. This causes the potential at the first input terminal (CLK terminal) of the D flip-flop 123 to shift from a low level to a high level, and the low-level signal at terminal D is stored in the D flip-flop 123. The signal stored in the D flip-flop 123 is then output as a low-level signal from terminal Q (node ​​B).

[0062] Furthermore, the potential of terminal Q (node ​​B) is input to ITDC130 as the potential of node C via buffer circuit 125 and wiring L10 as a low-level signal. Due to the wiring RC time constant, it takes time for the potential of node C to change from high level to low level, and it is input to ITDC130 as a low-level signal at time t4.

[0063] In this manner, the state transition unit 122 alternately outputs a high-level signal and a low-level signal each time the photoelectric conversion unit 110 reacts with a photon and the output signal of the photodiode 112 falls below a threshold. The high-level signal and the low-level signal are then alternately input to the ITDC 130 via the buffer circuit 125 and the wiring L10.

[0064] Figure 7 shows an example of the configuration of an ITDC. The ITDC 130 includes a first TDC 130a, a second TDC 130b, and a multiplexer 134. The first TDC 130a is, for example, a TDC, which converts the signal arrival time into a digital value according to the rising edge of the input signal. The second TDC 130b is configured, for example, by connecting an inverter circuit and a TDC in series, and converts the signal arrival time into a digital value according to the falling edge of the input signal. The multiplexer 134 outputs the digital values ​​output by the first TDC 130a and the second TDC 130b to a histogram generator 15.

[0065] Figure 8 is a schematic diagram illustrating the histograms generated by the histogram generator 15. Histogram h10 shows the frequency of occurrence of the digital signal output by the first TDC 130a. Histogram h12 shows the frequency of occurrence of the digital signal output by the second TDC 130b. Histogram h14 shows the frequency of occurrence of the digital signal output by the ITDC 130. The horizontal axis represents time, and the vertical axis represents frequency of occurrence.

[0066] There may be differences in characteristics between the first TDC130a and the second TDC130b. For example, the peak of histogram h10 using the first TDC130a is at time t5, while the peak of histogram h12 using the second TDC130b is at time t7. However, histograms h10 and h12 have similar shapes. Therefore, the peak of histogram h14 is at time t6, which is the midpoint between time t5 and time t7. In this way, even if there is a difference in signal arrival time due to the characteristics of the first TDC130a and the second TDC130b, the peak of histogram h14 can be maintained at time t6, which is near the midpoint.

[0067] Figure 9 shows an example configuration of a light receiving circuit 20a according to a comparative example. The light receiving circuit 20a according to the comparative example differs from the light receiving circuit 20 according to the first embodiment in that the reading circuit section 120a does not have a state transition section 122. The differences from the light receiving circuit 20 according to the first embodiment will be explained below.

[0068] The comparative example read circuit 120a includes a D flip-flop 123, a buffer circuit 125, and a buffer 127. One first input terminal (CLK terminal) of the D flip-flop 123 is connected to the output terminal of the inverse conversion circuit 113, and the other second input terminal (D terminal) is input to a high-level signal. The input terminal of the buffer 127 is connected to the B node, and its output terminal is input to the reset terminal of the D flip-flop 123. The buffer circuit 125 is connected to the TDC 130c.

[0069] Figure 10 is a time chart showing an example of the operation of the light receiving circuit 20a according to a comparative example. The vertical axis shows the potentials of nodes A, B, and C from top to bottom. The horizontal axis is time. Specifically, it shows the potential of the output signal of the photodiode 112, the potential of the output signal of the state transition unit 122, and the potential of the input signal of TDC 130c from top to bottom. Here, we will explain an example in which photons are received at the same timing as in Figure 6. In other words, the displacement of node A is the same as in Figure 6.

[0070] At time t0, no photons have been received, and node A of the light receiving circuit 20 maintains a high-level signal with a high potential. The inverse conversion circuit 121 inverts the potential of node A, maintaining a low-level signal with a low potential.

[0071] At this time, the potential of terminal Q (node ​​B) in the D flip-flop 123 is a low-level signal. A high-level signal is always input to terminal D (node ​​B) in the D flip-flop 123. Also, the potential of terminal Q (node ​​B) is input as a low-level signal to ITDC 130 via the buffer circuit 125 and wiring L10, and then via node C.

[0072] Next, just before time t1, a photon is received, and the potential of node A in the photodetector circuit 20 falls below the threshold at time t1. As a result, the inverse transformer circuit 121 inverts the potential of node A, which is the potential of the output signal of photodiode 112, and outputs a high-level signal. This causes the potential at the first input terminal (CLK terminal) of the D flip-flop 123 to shift from a low level to a high level, and the high-level signal at terminal D is stored in the D flip-flop 123. The signal stored in the D flip-flop 123 is then output as a high-level signal from terminal Q (node ​​B).

[0073] Furthermore, the potential of terminal Q (node ​​B) is input to TDC130c as the potential of node C via buffer circuit 125 and wiring L10 as a high-level signal. Due to the wiring RC time constant, it takes time for the potential of node C to rise from low level to high level before it is input to ITDC130.

[0074] Furthermore, the potential of terminal Q (node ​​B), which becomes a high-level signal at time t1, is delayed by the buffer circuit 127 and input to the reset terminal of the D flip-flop 123 at time t2. As a result, the potential of terminal Q (node ​​B) is input to TDC 130c as the potential of node C via the buffer circuit 125 and wiring L10 as a low-bell signal. The potential of terminal Q (node ​​B) is input to ITDC 130 as the potential of node C via the buffer circuit 125 and wiring L10 as a low-level signal. Due to the wiring RC time constant, it takes time for the potential of node C to change from high level to low level, and it is input to TDC 130c as a low-level signal at time t3.

[0075] Next, just before time t3, a photon is received, and the potential of node A in the photodetector circuit 20 falls below the threshold at time t1. As a result, the inverse transformer circuit 121 inverts the potential of node A, which is the potential of the output signal of photodiode 112, and outputs a high-level signal. This causes the potential at the first input terminal (CLK terminal) of the D flip-flop 123 to shift from a low level to a high level, and the high-level signal at terminal D is stored in the D flip-flop 123. The signal stored in the D flip-flop 123 is then output as a high-level signal from terminal Q (node ​​B).

[0076] Furthermore, the potential of terminal Q (node ​​B) is input to TDC130c as the potential of node C via buffer circuit 125 and wiring L10 as a high-level signal. Due to the wiring RC time constant, it takes time for the potential of node C to rise from low level to high level before it is input to TDC130c.

[0077] Thus, in the comparative example, the light receiving circuit 20a outputs a high-level signal each time the photoelectric conversion unit 110 reacts with a photon and the output signal of the photodiode 112 falls below a threshold. The duration of this high-level signal is less than half the duration of the high-level signal in the light receiving circuit 20 according to the first embodiment. In other words, because the light receiving circuit 20 according to the first embodiment divides the potential of the Q terminal (B node) by two, the duration of the high-level signal is more than twice that of the comparative example.

[0078] Therefore, in the comparative example, the light receiving circuit 20a has a C node potential that is at the minimum time interval required to show a high level due to the wiring RC time constant. On the other hand, the duration of the high-level signal in the light receiving circuit 20 according to the first embodiment is more than twice that of the comparative example, and the influence of the wiring RC time constant is suppressed. More specifically, in the light receiving circuit 20 according to the first embodiment, a high-level signal can be generated until the period from low level to high level of the C node potential is approximately twice as long. In this way, the light receiving circuit 20 according to the first embodiment has a state transition unit 122, which suppresses the influence of the wiring RC time constant.

[0079] As described above, in this embodiment, the light receiving device 10 has a photoelectric conversion unit 110 that outputs a detection signal in response to the detection of a photon, and a state transition unit 122 that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal. This makes it possible to make the period of the high-level signal and the period of the low-level signal longer, and the influence of the wiring RC time constant can be suppressed.

[0080] (Modification 1 of the First Embodiment) The light receiving device 10 according to Modification 1 of the First Embodiment differs from the light receiving device 10 according to the First Embodiment in that the state transition unit 122 is configured with a T flip-flop. The differences from the light receiving device 10 according to the First Embodiment will be explained below.

[0081] Figure 11 shows an example of the configuration of the light receiving circuit 20 of the light receiving device 10 according to Modification 1 of the First Embodiment. As shown in Figure 11, it differs from the light receiving device 10 according to the First Embodiment in that the state transition section 122a according to Modification 1 of the First Embodiment is configured with a T flip-flop 123a.

[0082] In the T flip-flop 123a, when a low-level signal is input to the T terminal, it holds the output signal of the Q terminal, and when a high-level signal is input, it inverts the output signal of the Q terminal. In other words, when a high-level signal and a low-level signal are repeatedly input to the T terminal alternately, the high-level signal and the low-level signal are inverted in response to the input of the high-level signal. As a result, the state transition unit 122a according to Modification 1 of the First Embodiment is configured to have the same processing operation as the state transition unit 122 according to Modification 1 of the First Embodiment.

[0083] (Second Embodiment) The light receiving device 10 according to the second embodiment differs from the light receiving device 10 according to the first embodiment in that the time difference output unit 130d is composed of a pulse regeneration circuit 136 and a TDC 130e. The differences from the light receiving device 10 according to the first embodiment will be explained below.

[0084] Figure 12 shows a detailed arrangement example of the SPAD array, readout circuit, and TDC block according to the second embodiment. As shown in Figure 12, wiring L10 is connected to one end of the time-difference output unit 130d. The other end of the time-difference output unit 130d is connected to the histogram generator 15. The histogram generator 15 generates a histogram of the output values ​​for each time-difference output unit 130d.

[0085] Figure 13 shows an example of the configuration of the time-difference output unit 130d according to the second embodiment. The time-difference output unit 130d includes a pulse regeneration circuit 136 and a TDC 130e.

[0086] The pulse regeneration circuit 136 outputs a pulse signal with a predetermined time width τ from the rising edge of a pulse and a pulse signal with a predetermined time width τ from the falling edge of a pulse. More specifically, the pulse regeneration circuit 136 has a plurality of D flip-flops 138a, b, a plurality of buffers 140a, b, and a logical OR circuit 142. The plurality of buffers 140a, b transmit signals with a time delay of a predetermined time width τ.

[0087] The output signal from the readout circuit 120 is input to one of the first input terminals (CLK terminal) of the D flip-flop 138a via wiring L10, and a high-level signal is input to the other second input terminal (D terminal). The input terminal of buffer 140a is connected to the output terminal (Q terminal), and the output terminal is input to the reset terminal of the D flip-flop 123.

[0088] The output signal from the readout circuit 120 is inverted and input to one of the first input terminals (CLK terminal) of the D flip-flop 138b via wiring L10, and a high-level signal is input to the other second input terminal (D terminal). The input terminal of buffer 140b is connected to the output terminal (Q terminal), and the output terminal is input to the reset terminal of the D flip-flop 123.

[0089] Figure 14 is a time chart showing an example of operation of the light receiving circuit 20a according to the second embodiment. The vertical axis shows the potentials of nodes A, B, and D from top to bottom. The horizontal axis is time. Specifically, from top to bottom, it shows the potential of the output signal of the photodiode 112, the potential of the output signal of the state transition unit 122, and the potential of the output signal of the pulse regeneration circuit 136.

[0090] As shown in Figure 14, at time t8, when the pulse signal from the state transition unit 122 is input to one of the first input terminals (CLK terminal) of the D flip-flop 138a, a high-level signal is held and output from the Q terminal. At time t9, the buffer 140a inputs the high-level signal to the reset terminal of the D flip-flop 138a with a time delay of a predetermined time width τ. As a result, the D flip-flop 138a outputs a low-level signal.

[0091] At time t10, when the pulse signal from the state transition unit 122 is inverted and input to one of the first input terminals (CLK terminal) of the D flip-flop 138b, a high-level signal is held and output from the Q terminal. At time t11, the buffer 140b inputs the high-level signal to the reset terminal of the D flip-flop 138b with a time delay of a predetermined time width τ. As a result, the D flip-flop 138b outputs a low-level signal.

[0092] In this way, a pulse signal with a predetermined time width τ is output from the rising edge of the pulse, and a pulse signal with a predetermined time width τ is output from the falling edge of the pulse. Then, the TDC 130e converts the arrival time of each pulse into a digital value and outputs it. Since the TDC 130e is unified, it is no longer necessary to consider variations between TDCs, and it becomes possible to reduce the distance measurement error.

[0093] (Third Embodiment) The light receiving device 10 according to the third embodiment differs from the light receiving device 10 according to the first embodiment in that the SPAD array 11 is divided into left and right regions, and the IDTC (Time Difference Output Unit) 130 is configured at both the left and right ends of the SPAD array 11. The differences from the light receiving device 10 according to the first embodiment will be explained below.

[0094] Figure 15 shows an example of the arrangement of the SPAD array, readout circuit, and ITDC block according to the third embodiment. As shown in Figure 15, the light receiving device 10 according to the third embodiment is divided into a region on one end of the center line L15 and a region on the other end of the center line L15, with the SPAD array 11 and the readout circuit 12 being separated.

[0095] Multiple light-receiving circuits 20 in the region on one end are read out to the TDC block 13a on the one end via wiring L10a and output to the histogram generator 15a. Similarly, multiple light-receiving circuits 20 in the region on the other end are read out to the TDC block 13b on the one end via wiring L10b and output to the histogram generator 15b. In this way, by dividing the lead wirings L10a and L10b from the light-receiving circuits 20 with respect to the center line L15 and wiring them to the left and right, the wiring RC time constant can be reduced.

[0096] (Fourth Embodiment) The light receiving device 10 according to the fourth embodiment differs from the light receiving device 10 according to the first embodiment in that a single reading circuit 120 is connected to a plurality of photoelectric conversion units 110 in the light receiving circuit 20. The differences from the light receiving device 10 according to the first embodiment will be described below.

[0097] Figure 16 shows an example of the configuration of the light receiving circuit 20 according to the fourth embodiment. As shown in Figure 16, in the light receiving circuit 20 according to the fourth embodiment, a reading circuit 120ab is connected to a plurality of photoelectric conversion units 110a,b via a multiplexer 300. In this way, by having the plurality of photoelectric conversion units 110a,b share the reading circuit 120ab, it is possible to reduce the mounting area of ​​the light receiving device 10.

[0098] (Fifth Embodiment) The light receiving device 10 according to the fifth embodiment differs from the light receiving device 10 according to the first embodiment in that the SPAD array 11 and the region of the state transition section 122 of the reading circuit section 120 are arranged side by side on the same plane. The differences from the light receiving device 10 according to the first embodiment will be explained below.

[0099] Figure 17 shows an example of the arrangement of the SPAD array, readout circuit, and ITDC block according to the fifth embodiment. As shown in Figure 15, in the light receiving device 10 according to the fifth embodiment, the SPAD array 11 and the multiple state transition units 122 in the readout circuit 12 are arranged side by side on the same plane. The multiple state transition units 122 are connected to the IDTC 130 via a multiplexer 140.

[0100] Multiple state transition units 122 are not arranged below the photoelectric conversion unit 110. This allows the circuit of the reading circuit unit 120, excluding the state transition units 122, to be arranged below the photoelectric conversion unit 110. Furthermore, if there is a multiplexer 140 outside the SPAD array 11 that changes the connected IDTC 130, the state transition units 122 can be placed close to the multiplexer 140, thereby improving the allowable wiring RC time constant. Note that even in a configuration without a multiplexer 140, the multiple state transition units 122 in the SPAD array 11 and the reading circuit 12 may be arranged side by side on the same plane.

[0101] (Sixth Embodiment) The light receiving device 10 according to the sixth embodiment differs from the light receiving device 10 in that it has a stacked structure of multiple stacks M10, M20, and M30. The differences from the light receiving device 10 according to the first embodiment will be explained below.

[0102] Figure 18 shows an example of a stacked light receiving device 10 according to the sixth embodiment. As shown in Figure 18, the light receiving device 10 according to the sixth embodiment has a bonded structure of multiple stacks M10, M20, and M30. A SPAD array 11 is configured in stack M10. Multiple wirings L10 of this SPAD array 11 are configured in stack M20. In addition, a reading circuit section 120 (see Figure 5) including multiple state transition sections 122 is configured in stack M30.

[0103] More specifically, the detection signal output from the photoelectric conversion unit 110 (see Figure 5) of the SPAD array 11 is supplied to multiple state transition units 122 of the stacked matrix M30 via the stacked matrix M20. The output signal of the reading circuit unit 120, which includes the state transition units 122, is then output to the TDC block 13 (see Figure 2) via multiple wirings L10 of the stacked matrix M20. This configuration makes it possible to further suppress parasitic capacitance and parasitic resistance to the multiple wirings L10.

[0104] Figure 19 shows an example of lamination of laminate M20 and laminate M30. As shown in Figure 19, laminate M20 and laminate M30 are bonded together.

[0105] Figure 20 schematically shows an example of the arrangement of the buffer circuit 125 and wiring L10 of the reading circuit section 120. As described above, the wiring L10 is wired to the laminate M20, and the buffer circuit 125 (see Figure 5) is configured on the laminate M30.

[0106] Multiple buffer circuits 125 are controlled by a control circuit 16 (see Figure 2). For example, the control circuit 16 (see Figure 2) selects one of multiple light receiving circuits 20 connected to the same wiring L10 and controls its drive. In Figure 20, the buffer circuit 125 of a driven light receiving circuit 20 is shown as ON, and the buffer circuit 125 of a dormant light receiving circuit 20 is shown as OFF.

[0107] Figure 21 schematically shows an example of the arrangement of the buffer circuit 125 of the reading circuit section 120 and the multiple wirings L10a. The wirings L10a are wired to the laminate M20, and the laminate M30 is bonded to the laminate M20. As a result, the output signal of the buffer circuit 125 is output to the bonded wirings L10a.

[0108] This layered structure relaxes the pitch constraints of the wiring L10. This makes it possible to increase the amount of wiring L10 that can be drawn even with the same pixel pitch. This allows for an increase in the number of light receiving circuits 20 and an increase in the number of simultaneous distance measurement points. Furthermore, relaxing the pitch constraints of wiring L10 allows for wider wiring spacing, which reduces crosstalk. In addition, unused wiring layers (Wafer A) become available and can be used for power supply and ground reinforcement.

[0109] At least a part of the light receiving device 10 described in the above-described embodiment may be made up of hardware or software. If it is made up of software, a program that realizes at least a part of the functions of the light receiving device 10 may be stored on a recording medium such as a flexible disk or CD-ROM, and loaded into a computer and executed. The recording medium is not limited to removable ones such as magnetic disks or optical disks, but may also be a fixed recording medium such as a hard disk drive or memory.

[0110] Furthermore, a program that implements at least some of the functions of the light receiving device 10 may be distributed via a communication line such as the Internet (including wireless communication). In addition, the program may be encrypted, modulated, or compressed and distributed via a wired or wireless line such as the Internet, or stored on a recording medium.

[0111] Furthermore, this technology can take the following configuration.

[0112] (1) A photoelectric converter that outputs a detection signal in response to the detection of a photon; a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal; and a time difference output unit that outputs a digital signal based on the time difference between a first input time of the first signal input via wiring, a second input time of the second signal input, and a predetermined time.

[0113] (2) The light receiving device according to (1), wherein the signal output unit divides the detection signal, which is a pulse signal, by two and outputs it.

[0114] (3) The light receiving device according to (1) or (2), comprising a flip-flop that alternately outputs the first signal and the second signal in response to the detection signal.

[0115] (4) The light receiving device according to (3), wherein the flip-flop alternately holds and outputs the first signal and the second signal in accordance with the detection signal.

[0116] (5) The light receiving device according to (4), wherein the flip-flop is a D flip-flop, the photoelectric conversion unit inputs the detection signal to the first input terminal of the D flip-flop, and the signal output unit further comprises a first inverter connected between the output terminal of the D flip-flop and the second input terminal of the D flip-flop.

[0117] (6) The light receiving device according to (5), wherein the flip-flop is a T flip-flop, the photoelectric conversion unit inputs the detection signal to the input terminal of the T flip-flop, and the signal output unit alternately outputs the first signal and the second signal from the output terminal of the T flip-flop.

[0118] (7) The photoelectric conversion unit comprises a single-photon avalanche diode that reacts with photons, and a second inverter whose input terminal is connected to the cathode of the single-photon avalanche diode, and the detection signal is output from the output terminal of the second inverter, the photoreceiving device according to any one of (1) to (6).

[0119] (8) The light receiving device according to any one of (1) to (7), wherein the time difference output unit comprises a first time digital converter that outputs a digital signal based on the time difference between the first input time and the predetermined time, and a second time digital converter that outputs a digital signal based on the time difference between the second input time and the predetermined time.

[0120] (9) The light receiving device according to any one of (1) to (7), wherein the time difference output unit includes a pulse regeneration circuit that outputs a pulse signal of a predetermined time width from the time of input of the first signal and outputs a pulse signal of the predetermined time width from the time of input of the second signal, and a third time digital converter that outputs a digital signal based on the time difference between the time of input of the pulse signal output by the pulse regeneration circuit and the predetermined time.

[0121] (10) The light receiving device according to any one of (1) to (9), further comprising a histogram generator that generates a histogram of the frequency of occurrence of the output value of the time-difference output unit.

[0122] (11) A light receiving device according to any one of (1) to (10), wherein a plurality of photodetection circuits, each having a photoelectric conversion unit and a signal output unit, are arranged in a matrix in a pixel array unit, and a plurality of the photodetection circuits at one end of the plurality of photodetection circuits arranged in the same row of the pixel array unit are connected to the time difference output unit at the one end via a first wiring, and a plurality of the photodetection circuits at the other end of the photodetection circuits are connected to the time difference output unit at the other end via a second wiring. (12) A light receiving device according to (11), wherein a plurality of the photodetection circuits, arranged at predetermined intervals from the plurality of photodetection circuits arranged in the same row, are connected to the first wiring.

[0123] (13) The light receiving device according to any one of (1) to (12), wherein the detection signals of a plurality of photoelectric conversion units are input to the signal output unit via a multiplexer.

[0124] (14) The light receiving device according to any one of (1) to (12), wherein the photoelectric conversion unit comprises a plurality of pixel array units arranged in a matrix, and a plurality of signal output units corresponding to each of the plurality of photoelectric conversion units are arranged side by side in a region different from the pixel array unit.

[0125] (15) The light receiving device according to (14), wherein the output signals of a plurality of signal output units are input to the time difference output unit via a multiplexer.

[0126] (16) The photoelectric conversion unit comprises a pixel array unit in which a plurality of photoelectric conversion units are arranged in a matrix, a first stacked unit in which a plurality of signal output units corresponding to the plurality of photoelectric conversion units are arranged, and a second stacked unit in which wiring connecting the plurality of time difference output units corresponding to the plurality of signal output units is arranged, wherein the pixel array unit, the first stacked unit, and the second stacked unit are stacked, the photoelectric receiving device according to any one of (1) to (10).

[0127] (17) The light receiving device according to (16), wherein the signal output section of the first laminate and the corresponding wiring of the second laminate are electrically connected by a bonding connection.

[0128] (18) The light receiving device according to (17), further comprising a plurality of buffers to which each of the plurality of signal output units is connected, the plurality of buffers being connected to the time difference output unit via the same third wiring, and a control circuit for driving one of the plurality of buffers.

[0129] (19) The light receiving device according to (18), wherein a fourth wiring is arranged in the first laminated portion and is bonded to the third wiring.

[0130] (20) A light receiving circuit comprising: a photoelectric conversion unit that outputs a detection signal in response to the detection of a photon; and a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal.

[0131] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0132] 10: Light receiving device, 11: SPAD array (pixel array section), 15: Histogram generator, 16: Control circuit, 20: Light receiving circuit, 20: Light receiving circuit, 110, 110a, 110b: Photoelectric conversion section, 112: Photodiode, 113: Inverter, 122: State transition section (signal output section), 123: D flip-flop, 123a: T flip-flop, 124: Inverse conversion circuit (inverter) ), 130: ITDC (Time Difference Output Unit), 130a: First TDC (First Time Digital Converter), 130b: Second TDC (Second Time Digital Converter), 130c, e: TDC (Time Digital Converter), 130d: Time Difference Output Unit, 134: Multiplexer, 136: Pulse Regeneration Circuit, 140: Multiplexer, L10, L10a, L10b: Wiring, M10, M20, M30: Lamination

Claims

1. A light receiving device comprising: a photoelectric conversion unit that outputs a detection signal in response to the detection of a photon; a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal; and a time difference output unit that outputs a digital signal based on the time difference between a first input time of the first signal, a second input time of the second signal, and a predetermined time, which are input via wiring.

2. The light receiving device according to claim 1, wherein the signal output unit divides the detection signal, which is a pulse signal, by two and outputs it.

3. The light receiving device according to claim 1, comprising a flip-flop that alternately outputs the first signal and the second signal in response to the detection signal.

4. The light receiving device according to claim 3, wherein the flip-flop alternately holds and outputs the first signal and the second signal in accordance with the detection signal.

5. The light receiving device according to claim 4, wherein the flip-flop is a D flip-flop, the photoelectric conversion unit inputs the detection signal to the first input terminal of the D flip-flop, and the signal output unit further comprises a first inverter connected between the output terminal of the D flip-flop and the second input terminal of the D flip-flop.

6. The light receiving device according to claim 5, wherein the flip-flop is a T-flip-flop, the photoelectric conversion unit inputs the detection signal to the input terminal of the T-flip-flop, and the signal output unit alternately outputs the first signal and the second signal from the output terminal of the T-flip-flop.

7. The photoelectric conversion unit comprises a single-photon avalanche diode that reacts with photons, and a second inverter whose input terminal is connected to the cathode of the single-photon avalanche diode, and the detection signal is output from the output terminal of the second inverter, as described in claim 1.

8. The light receiving device according to claim 1, wherein the time difference output unit comprises a first time digital converter that outputs a digital signal based on the time difference between the first input time and the predetermined time, and a second time digital converter that outputs a digital signal based on the time difference between the second input time and the predetermined time.

9. The light receiving device according to claim 1, wherein the time difference output unit comprises a pulse regeneration circuit that outputs a pulse signal of a predetermined time width from the time of input of the first signal and outputs a pulse signal of the predetermined time width from the time of input of the second signal, and a third time digital converter that outputs a digital signal based on the time difference between the time of input of the pulse signal output by the pulse regeneration circuit and the predetermined time.

10. The light receiving device according to claim 1, further comprising a histogram generator that generates a histogram of the frequency of occurrence of the output value of the time-difference output unit.

11. A light receiving device according to claim 1, wherein a plurality of photodetection circuits, each having the photoelectric conversion unit and the signal output unit, are arranged in a matrix in a pixel array unit, and a plurality of the photodetection circuits at one end of the plurality of photodetection circuits arranged in the same row of the pixel array unit are connected to the time difference output unit at the one end via a first wiring, and a plurality of the photodetection circuits at the other end of the photodetection circuits are connected to the time difference output unit at the other end via a second wiring.

12. The light receiving device according to claim 11, wherein a plurality of light detection circuits, which are arranged at predetermined intervals from among a plurality of light detection circuits arranged in the same row, are connected to the first wiring.

13. The light receiving device according to claim 1, wherein the detection signals of a plurality of photoelectric conversion units are input to the signal output unit via a multiplexer.

14. The photoelectric conversion unit comprises a plurality of pixel array units arranged in a matrix, and a plurality of signal output units corresponding to each of the plurality of photoelectric conversion units are arranged side by side in a region different from the pixel array unit, according to claim 1.

15. The light receiving device according to claim 14, wherein the output signals of a plurality of signal output units are input to the time-difference output unit via a multiplexer.

16. The photoelectric conversion unit comprises a pixel array unit arranged in a matrix, a first stacked unit on which a plurality of signal output units corresponding to the plurality of photoelectric conversion units are arranged, and a second stacked unit on which wiring connecting the plurality of time-difference output units corresponding to the plurality of signal output units is arranged, wherein the pixel array unit, the first stacked unit, and the second stacked unit are stacked.

17. The light receiving device according to claim 16, wherein the signal output section of the first laminated section and the corresponding wiring of the second laminated section are electrically connected by a bonding connection.

18. The light receiving device according to claim 17, further comprising a plurality of buffers to which each of the plurality of signal output units is connected, the plurality of buffers being connected to the time difference output unit via the same third wiring, and a control circuit for driving one of the plurality of buffers.

19. The light receiving device according to claim 18, wherein a fourth wiring is arranged in the first laminated portion and is bonded to the third wiring.

20. A light receiving circuit comprising: a photoelectric conversion unit that outputs a detection signal in response to the detection of a photon; and a signal output unit that alternately outputs a first signal of a first level and a second signal of a second level different from the first level in response to the detection signal.

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