Array substrate, and display panel and display method

Abstract

Provided is an array substrate (10), comprising: an array substrate (BP1); and a pixel circuit layer, which comprises a driving layer (DR) and a photosensitive layer (SM), wherein the driving layer (DR) comprises a pixel circuit and a photosensitive circuit, the photosensitive layer (SM) comprises a photosensitive element (SM3), one of the driving layer (DR) and the photosensitive layer (SM) comprises a pixel electrode (ANO) connected to the pixel circuit (DE), and the photosensitive circuit is connected to the photosensitive element (SM3). In the embodiments of the present disclosure, by means of the photosensitive element (SM3) generating electric charges under illumination and on the basis of collection of and feedback on the charges by the photosensitive circuit, the light-responsive functionality of the array substrate (0) can be realized. That is, contactless interaction with the array substrate (10) can be realized by means of an auxiliary light-emitting device such as a button-type laser pointer. For a display panel (100) comprising the array substrate (10), the effect of performing a contactless operation on the display panel (100) can be realized by means of the auxiliary light-emitting device. (FIG. 1)

Description

Array substrate, display panel and display method Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display method. Background Technology

[0002] Handwriting panels allow users to write or erase content via touch. Their ease of use has led to their widespread adoption. However, the need for touch interaction increases the complexity of user interaction with handwriting panels.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an array substrate, a display panel, and a display method.

[0005] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0006] Array substrate;

[0007] A pixel circuit layer is located on one side of the array substrate and includes a driving layer and a photosensitive layer. The driving layer includes a pixel circuit and a photosensitive circuit, and the photosensitive layer includes a photosensitive element. One of the driving layer and the photosensitive layer includes a pixel electrode. The pixel electrode and the photosensitive element do not overlap in their orthographic projections on the array substrate.

[0008] The pixel circuit is connected to the pixel electrode, and the photosensitive element includes a photoelectric conversion unit, with the photosensitive circuit connected to the photosensitive element.

[0009] According to any of the array substrates described in this disclosure, the photosensitive layer includes a first conductive layer, a photoelectric conversion layer, and a second conductive layer sequentially stacked on one side of the array substrate.

[0010] The first conductive layer includes a first electrode, the photoelectric conversion layer includes the photoelectric conversion unit, and the second conductive layer includes a second electrode. One first electrode, one photoelectric conversion unit, and one second electrode constitute one photosensitive element.

[0011] The first electrode is connected to the photosensitive circuit, and the photoelectric conversion unit and the orthographic projection of the first electrode on the array substrate have an overlapping area, and the second electrode and the orthographic projection of the photoelectric conversion unit on the array substrate also have an overlapping area.

[0012] According to any of the array substrates described in this disclosure, at least a portion of the orthogonal projection of the photoelectric conversion unit onto the array substrate is located outside the orthogonal projection of the second electrode onto the array substrate.

[0013] According to any of the array substrates described in this disclosure, the orthographic projection of the second electrode on the array substrate at least coincides with the orthographic projection of the photoelectric conversion unit on the array substrate, and the second conductive layer is a light-transmitting layer.

[0014] According to any of the array substrates described in this disclosure, the first conductive layer or the second conductive layer further includes a voltage signal line, which is connected to the second electrode.

[0015] According to any of the array substrates described in this disclosure, the first conductive layer or the second conductive layer further includes the pixel electrode.

[0016] According to any of the array substrates described in this disclosure, the pixel circuit includes a driving transistor, and the driving layer includes:

[0017] A gate metal layer is located on one side of the array substrate and includes a first conductive portion;

[0018] A gate insulating layer is located on the side of the gate metal layer opposite to the array substrate, and at least covers the first conductive portion;

[0019] An active layer is located on the side of the gate insulating layer away from the array substrate, and includes a first active portion, the first active portion including a first channel region and a first connection portion and a second connection portion located on both sides of the first channel region;

[0020] A source / drain metal layer is located on the side of the active layer away from the array substrate, and includes a first connection line, the two ends of which are electrically connected to the first connection portion and the pixel electrode, respectively.

[0021] The first connecting portion and the second connecting portion respectively form the first electrode and the second electrode of the driving transistor. The second electrode of the driving transistor is used to load a data signal. The area on the first conductive portion that overlaps with the first channel region forms the control electrode of the driving transistor. The control electrode of the driving transistor is used to load a scan signal.

[0022] According to any of the array substrates described in this disclosure, the source / drain metal layer further includes a voltage signal line connected to the second electrode.

[0023] According to any of the array substrates described in this disclosure, the source / drain metal layer further includes the pixel electrode.

[0024] According to any of the array substrates described in this disclosure, the gate metal layer further includes an auxiliary electrode, the gate insulating layer covers the auxiliary electrode, and the auxiliary electrode and the pixel electrode have an overlapping region on the orthographic projection of the pixel electrode on the array substrate.

[0025] According to any of the array substrates described in this disclosure, the array substrate includes a display area;

[0026] The pixel circuit layer includes driving data lines and driving scan lines connected to the pixel circuit, as well as photosensitive data lines and photosensitive scan lines connected to the photosensitive circuit.

[0027] Within the display area, the driving scan lines and photosensitive scan lines extend along the row direction, and the driving data lines and photosensitive data lines extend along the column direction; the pixel electrodes and the photosensitive elements are all located within the area enclosed by the driving scan lines, photosensitive scan lines, driving data lines, and photosensitive data lines connected to the corresponding pixel circuit and photosensitive circuit.

[0028] According to any of the array substrates described in this disclosure, the array substrate includes a peripheral region located outside the display area;

[0029] The driving scan line and the photosensitive scan line, as well as the driving data line and the photosensitive data line, all extend to the peripheral area. In the peripheral area, the driving scan line and the photosensitive scan line are located on both sides of the display area along the row direction, and the driving data line and the photosensitive data line are located on the same side of the display area along the column direction, and are located in different film layers.

[0030] According to one aspect of this disclosure, a display panel is provided, including a color filter substrate and an array substrate as described above disposed opposite each other, and a liquid crystal layer and a spacer located between the array substrate and the color filter substrate.

[0031] According to any of the display panels described in this disclosure, the array substrate includes a planarization layer;

[0032] The planarization layer is located on the side of the array substrate close to the color filter substrate, and the planarization layer and the spacer are an integral structure.

[0033] According to any of the display panels described in this disclosure, the spacer is spherical.

[0034] According to one aspect of this disclosure, a display method for a display panel is provided, the display method being applied to the display panel described in the above aspect, wherein the photosensitive circuit includes a photosensitive transistor, the control electrode of the photosensitive transistor is used to load a first level signal, the first electrode of the photosensitive transistor is used to load a second level signal, the second electrode of the photosensitive transistor is connected to a first electrode of a photosensitive element, and the second electrode of the photosensitive element is used to load a third level signal;

[0035] The display panel includes a sensing stage and a display stage. The sensing stage includes a calibration stage, a photoelectric conversion stage, a reading stage, and a feedback stage. The display method includes:

[0036] During the calibration phase, a high-level first-level signal is periodically input to the control electrode of the phototransistor to periodically turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element to correct the amount of charge in the photosensitive element.

[0037] During the photoelectric conversion stage, a low-level first-level signal is input to the control electrode of the phototransistor so that when the phototransistor is turned off, light is received through the photosensitive element and photoelectric conversion is performed.

[0038] During the reading phase, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor.

[0039] During the feedback phase, the position information of the target photosensitive element is determined based on the actual charge amount;

[0040] During the display phase, based on the position information, a drive signal is transmitted to the corresponding pixel circuit to write or erase content on the current screen.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0043] Figure 1 is a cross-sectional structural diagram of a display panel provided in an embodiment of this disclosure.

[0044] Figure 2 is a cross-sectional structural diagram of another display panel provided in an embodiment of this disclosure.

[0045] Figure 3 is a schematic diagram of a driving circuit and a photosensitive circuit provided in an embodiment of this disclosure.

[0046] Figure 4 is a schematic diagram of the membrane structure of a driving layer provided in an embodiment of this disclosure.

[0047] Figure 5 is a schematic diagram of another driving layer membrane structure provided in the embodiments of this disclosure.

[0048] Figure 6 is a schematic diagram of the film structure of a pixel circuit layer provided in an embodiment of this disclosure.

[0049] Figure 7 is a schematic diagram of a partial film structure of a pixel circuit layer provided in an embodiment of this disclosure.

[0050] Figure 8 is a schematic diagram of the film structure of a photosensitive layer provided in an embodiment of this disclosure.

[0051] Figure 9 is a cross-sectional view of the display panel corresponding to Figure 8.

[0052] Figure 10 is a cross-sectional structural diagram of a display panel provided in an embodiment of this disclosure.

[0053] Figure 11 is a cross-sectional structural diagram of another display panel provided in an embodiment of this disclosure.

[0054] Figure 12 is a schematic diagram of the film structure of the pixel circuit layer corresponding to Figure 11.

[0055] Figure 13 is a top view of an array substrate provided in an embodiment of this disclosure.

[0056] Figure 14 is a schematic diagram of the array distribution of a pixel circuit provided in an embodiment of this disclosure.

[0057] Figure 15 is a schematic diagram of the display timing of a display screen provided in an embodiment of this disclosure.

[0058] Figure 16 is a schematic diagram of the display process of a display screen provided in an embodiment of this disclosure.

[0059] Reference numerals: 100, Display panel; AA, Display area; BB, Peripheral area; B1, Driving module; B2, Photosensitive module; 10, Array substrate; 20, Color filter substrate; 30, Liquid crystal layer; 40, Spacer; BP1, Array substrate; DR, Driving layer; SM, Photosensitive layer; PLN, Planarization layer; ST1, Driving transistor; ST2, Photosensitive transistor; Ga, Gate metal layer; GI, Gate insulating layer; ACT, Active layer; SD, Source / drain metal layer; PVX, Passivation layer; G1, First conductive part; G2, Second conductive part; DG, Driving scan line; MG, Photosensitive scan line; P1, First active part; P11, First channel region; P12, First connection part; P13, Second connection part; P2, Second active part; P21, Second channel region; P22, Third connection part; P23, Fourth connection part; SD1, First connecting line; SD2, Second connecting line; SD3, Third connecting line; SD4, Fourth connecting line; DD, Drive data line; MD, Photosensitive data line; SM1, First conductive layer; PIN, Photoelectric conversion layer; SM2, Second conductive layer; SM3, Photosensitive element; SM11, First electrode; PIN1, Photoelectric conversion unit; SM21, Second electrode; ANO, Pixel electrode; VDD, Voltage signal line; BP2, Color filter substrate; COM, Common electrode layer. Detailed Implementation

[0060] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0062] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0063] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region is the area through which the current primarily flows.

[0064] The first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0065] Figure 1 illustrates a cross-sectional structural schematic diagram of a display panel 100 provided in this embodiment of the present disclosure. As shown in Figure 1, the display panel 100 includes: an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and a liquid crystal layer 30 located between the array substrate 10 and the color filter substrate 20.

[0066] The liquid crystal layer 30 includes at least cholesteric liquid crystal, so that by adjusting the pitch of the cholesteric liquid crystal, the reflection of visible light of different wavelengths can be achieved, thereby realizing the display of black and white images or full-color images.

[0067] The cholesteric liquid crystal mainly includes a first stable state (P-state) and a second stable state (FC-state). In the first stable state, no voltage is required, and the cholesteric liquid crystal is arranged in an orderly manner. At this time, the color of the reflected visible light can be selectively set based on the pitch. In the second stable state, no voltage is required, and the cholesteric liquid crystal is arranged randomly. At this time, visible light scattering can be achieved, realizing the light transmission effect. In addition, for the cholesteric liquid crystal in the first stable state, applying a low voltage can control the cholesteric liquid crystal to be arranged randomly, and it will still be randomly distributed after the voltage is removed, that is, it will remain in the second stable state. For the cholesteric liquid crystal in the second stable state, applying pressure can control the cholesteric liquid crystal to be arranged in an orderly manner, and it will still be arranged in an orderly manner after the pressure is removed, that is, it will remain in the first stable state. Alternatively, a higher voltage can be applied to control the cholesteric liquid crystal to switch to an unstable state, and after the voltage drops rapidly to zero, the cholesteric liquid crystal will be arranged in an orderly manner, that is, the cholesteric liquid crystal will switch to the first stable state.

[0068] Thus, based on the cholesteric liquid crystal in the liquid crystal layer 30, the writing function can be realized by switching from the second stable state to the first stable state. That is, pressing the writing area of ​​the display panel 100, or applying a high voltage to the writing area and then quickly reducing the voltage to zero, will cause the cholesteric liquid crystal in the writing area, which is in the second stable state, to switch to the first stable state, thereby realizing writing in the writing area. At the same time, the display screen can be erased by switching from the first stable state to the second stable state. That is, applying a small voltage to the cholesteric liquid crystal in the erasure area, which is in the first stable state, will cause the cholesteric liquid crystal in the erasure area to switch to the second stable state, thereby realizing the erasure of the display screen in the erasure area.

[0069] In this embodiment of the disclosure, as shown in FIG1 or FIG2, the display panel 100 includes a spacer 40 located between the array substrate 10 and the color filter substrate 20 to ensure the cell thickness of the display panel 100, thereby ensuring the thickness of the liquid crystal layer 30.

[0070] The spacer 40 can be a right prism structure, as exemplified in Figure 1, where the cross-section of the spacer 40 is an inverted trapezoid. Alternatively, the spacer 40 can have other structures; for example, it can be spherical, as shown in Figure 2, where the cross-section of the spacer 40 is circular. When the spacer 40 is spherical, it simplifies the manufacturing process of the color filter substrate 20, thereby reducing development and manufacturing costs.

[0071] The spacer 40 can be fabricated on either the array substrate 10 or the color filter substrate 20. When the spacer 40 is fabricated on the array substrate 10, as shown in Figure 1, the array substrate 10 includes a planarization layer PLN located near the color filter substrate 20, and the planarization layer PLN and the spacer 40 are integrally formed. This simplifies the fabrication process of the array substrate 10 while ensuring the reliability of the connection between the spacer 40 and the array substrate 10. When the spacer 40 is fabricated on the color filter substrate 20, the fabrication process of the array substrate 10 is simplified, and the fabrication efficiency of the array substrate 10 is improved.

[0072] In addition, a frame is provided between the array substrate 10 and the color filter substrate 20, and the spacer 40 is located in the area enclosed by the frame. The frame is used to bond and fix the array substrate 10 and the color filter substrate 20, and at the same time, it isolates the liquid crystal layer 30 from the outside world to prevent moisture and other substances from entering.

[0073] In some embodiments, as shown in FIG1 or FIG2, the color filter substrate 20 includes a color filter substrate BP2, and a common electrode layer COM and a first alignment layer (not shown in the figure) sequentially stacked on the side of the color filter substrate BP2 near the array substrate 10.

[0074] In accordance with the above, in order to enable the writing of the area to be written on the display panel 100, the color filter substrate 20 can maintain a certain degree of flexibility, that is, under a certain external force, the color filter substrate 20 can be caused to locally indent, thereby applying pressure to the cholesteric liquid crystal and realizing the switching of the cholesteric liquid crystal from the second stable state (random arrangement) to the first stable state (ordered arrangement).

[0075] Thus, the color filter substrate BP2 included in the color filter substrate 20 can be a single-layer flexible transparent structure such as a plastic substrate; of course, the color filter substrate BP2 can also be a multi-layer transparent flexible structure. For example, the color filter substrate BP2 includes a first polyimide layer, a first protective layer, a second polyimide layer, and a second protective layer stacked sequentially. The two protective layers are used to protect the polyimide layer and prevent damage to the polyimide layer by subsequent processes.

[0076] Of course, when implementing high voltage control in the writing area on the display panel 100, the color filter substrate 20 can also be a rigid substrate, such as a glass substrate or a quartz substrate. This disclosure does not limit this.

[0077] The common electrode layer COM can be a transparent conductive layer, such as an indium tin oxide layer. Alternatively, the common electrode layer COM included in the color filter substrate 20 can also be disposed in the array substrate 10, that is, the color filter substrate 20 only includes the color filter substrate BP2 and the first alignment layer.

[0078] In some embodiments, the array substrate 10 includes an array substrate BP1, and a pixel circuit layer and a second alignment layer (not shown) sequentially stacked on the side of the array substrate BP1 near the color filter substrate 20.

[0079] The pixel circuit layer includes an array of pixel circuits (shown as driving transistor ST1 in the figure) and an array of pixel electrodes ANO, with one pixel circuit connected to one pixel electrode ANO. Additionally, the array substrate 10 includes a driving module B1, which is connected to the pixel circuits. The driving module B1 transmits driving signals to the pixel circuits, applying voltage to the pixel electrodes ANO. This voltage, combined with the electric field formed with the common electrode on the color filter substrate 20, adjusts the switching of the steady state of the cholesteric liquid crystal in the liquid crystal layer 30, thereby adjusting the image. Furthermore, after the pixel circuits stop applying voltage to the pixel electrodes ANO, the cholesteric liquid crystal maintains its current steady state, continuing to display the adjusted image.

[0080] Specifically, when switching from the current frame to the next frame, the cholesteric liquid crystal can switch from the second stable state to the first stable state based on the high voltage applied to the pixel electrode ANO, and the display of the next frame can be maintained; when writing, the cholesteric liquid crystal can switch from the second stable state to the first stable state based on the high voltage applied to the pixel electrode ANO, and the image after writing can be maintained; when erasing, the cholesteric liquid crystal can switch from the second stable state to the first stable state based on the low voltage applied to the pixel electrode ANO, and the image after erasing can be maintained.

[0081] It should be noted that, in conjunction with the color filter substrate 20 described above, when the color filter substrate 20 does not include the common electrode layer COM, the common electrode layer COM can be located between the pixel circuit layer and the second alignment layer, and an insulating layer (such as a passivation layer PVX) is provided between the pixel circuit layer and the common electrode layer COM to ensure the insulation between the pixel electrode ANO and the common electrode layer COM.

[0082] In some implementations, as shown in Figures 1 and 2, the pixel circuit layer includes a driving layer DR. Specifically, as shown in Figure 1 or 2, the driving layer DR includes a gate metal layer Ga, a gate insulating layer GI, an active layer ACT, and a source / drain metal layer SD, which are sequentially stacked on the array substrate BP1.

[0083] The array substrate BP1 can be a glass substrate, quartz substrate, plastic substrate or other transparent substrate; or the array substrate BP1 is a multilayer structure. For example, the array substrate BP1 includes a first polyimide layer, a first protective layer, a second polyimide layer and a second protective layer stacked in sequence. The two protective layers are used to protect the polyimide layer and prevent subsequent processes from damaging the polyimide layer.

[0084] In this design, the gate metal layer Ga can be a single-layer or multi-layer structure. The gate metal layer Ga is used to form the conductive portion of the transistor (i.e., the control electrode of the transistor) in the pixel circuit, as well as traces such as scan lines. The active layer ACT can be a single-layer or multi-layer structure. The active layer ACT is used to form the active portion of the transistor in the pixel circuit, including the channel region and two connection portions located on either side of the channel region (i.e., the source and drain of the transistor). The source / drain metal layer SD can be a single-layer or multi-layer structure, etc. The source / drain metal layer SD is used to form data lines, connection lines, and other traces.

[0085] In addition, as shown in Figure 1 or Figure 2, the driving layer DR also includes a passivation layer PVX located on the side of the source / drain metal layer SD away from the array substrate BP1, so as to protect the source / drain metal layer SD through the passivation layer PVX, avoid oxidation and corrosion of the source / drain metal layer SD, and extend the life of the source / drain metal layer SD.

[0086] Taking the pixel circuit shown in Figure 3, which includes a driving transistor ST1, as an example, as shown in Figure 4 or Figure 5, the gate metal layer Ga includes a first conductive portion G1; the gate insulating layer GI at least covers the first conductive portion G1; the active layer ACT includes a first active portion P1, which includes a first channel region P11 and a first connection portion P12 and a second connection portion P13 located on both sides of the first channel region P11.

[0087] Thus, the first and second electrodes of the driving transistor ST1 can be formed by the first connecting portion P12 and the second connecting portion P13 respectively, and the control electrode of the driving transistor ST1 can be formed by the area on the first conductive portion G1 that overlaps with the first channel region P11.

[0088] Additionally, as shown in Figure 3 and Figure 4 or 5, the gate metal layer Ga typically includes a drive scan line DG, and the source / drain metal layer SD includes a first connection line SD1, a second connection line SD2, and a drive data line DD. The drive scan line DG is connected to the first conductive part G1 (or is an integral design) to load a scan signal onto the first conductive part G1 (i.e., the control electrode of the drive transistor ST1), thereby controlling the conduction or disconnection of the drive transistor ST1. One end of the first connection line SD1 is connected to the first connection part P12 (the first electrode of the drive transistor ST1) (e.g., directly covering the first connection part P12), and the other end is connected to the pixel electrode ANO. One end of the second connection line SD2 is connected to the drive data line DD (or is an integral design), and the other end is connected to the second connection part P13 (the second electrode of the drive transistor ST1) (e.g., directly covering the second connection part P13), so that a data signal is loaded onto the second conductive part G2 (i.e., the second electrode of the drive transistor ST1) through the drive data line DD, thereby loading a voltage onto the pixel electrode ANO when the drive transistor ST1 is turned on.

[0089] In some embodiments, as shown in FIG1 or FIG2, the pixel circuit layer of the array substrate 10 further includes a photosensitive layer SM, the driving layer DR includes a photosensitive circuit (shown as photosensitive transistor ST2 in the figure), the photosensitive layer SM includes a photosensitive element SM3, the photosensitive element SM3 includes a photoelectric conversion unit PIN1, the photosensitive circuit is connected to the photosensitive element SM3, and there is no overlapping area between the pixel electrode ANO and the orthogonal projection of the photosensitive element SM3 on the array substrate BP1.

[0090] In this way, the photosensitive element SM3 can generate charges under illumination, and the light control characteristics of the array substrate 10 can be realized based on the collection feedback of charges by the photosensitive circuit. This allows for air-to-air interaction with the array substrate 10 via auxiliary light-emitting devices such as button-type laser pointers. As for the display panel 100 including the array substrate 10, the air-to-air operation of the display panel 100 can be achieved through auxiliary light-emitting devices, thereby improving the operability and user stickiness of the display panel 100.

[0091] The photosensitive layer SM is located on the side of the driving layer DR away from the array substrate BP1, so as to reduce the distance between the photosensitive layer SM and the color filter substrate 20 and improve the light reception efficiency of the photosensitive layer SM.

[0092] The array substrate 10 also includes a photosensitive module B2 connected to the photosensitive circuit. The photosensitive module B2 is connected to the driving module B1 so that after the photosensitive module B2 detects light based on the photosensitive element SM3, it can send the location information of the photosensitive element SM3 where the light was detected to the driving module B1. Then, the driving module B1 sends a corresponding driving signal to the pixel circuit based on the steady state of the cholesteric liquid crystal at the location of the photosensitive element SM3, so that the pixel circuit can apply a voltage to the pixel electrode ANO to realize the adjustment of the image on the display panel 100.

[0093] Taking the cholesteric liquid crystal at the location of photosensitive element SM3 in the first stable state as an example, after the driving module B1 receives the position information of photosensitive element SM3, it can control the transistor of the pixel circuit to turn on based on the driving scan line DG, and apply a low voltage to the pixel electrode ANO based on the driving data line DD and the pixel circuit, so as to control the cholesteric liquid crystal at the location of photosensitive element SM3 to switch from the first stable state to the second stable state, thereby erasing part of the content on the screen; taking the cholesteric liquid crystal at the location of photosensitive element SM3 in the second stable state as an example, after the driving module B1 receives the position information of photosensitive element SM3, it can control the transistor of the pixel circuit to turn on based on the driving scan line DG, and apply a high voltage to the pixel electrode ANO based on the driving data line DD and the pixel circuit, so as to control the cholesteric liquid crystal at the location of photosensitive element SM3 to switch from the second stable state to the first stable state, thereby writing the content on the screen.

[0094] Alternatively, after receiving the position information of the photosensitive element SM3, the driving module B1 can apply a low voltage to the pixel electrode ANO based on the erase command to control the cholesteric liquid crystal at the location of the photosensitive element SM3 to switch from the first stable state to the second stable state, thereby erasing part of the content on the screen; and apply a high voltage to the pixel electrode ANO based on the write command to control the cholesteric liquid crystal at the location of the photosensitive element SM3 to switch from the second stable state to the first stable state, thereby writing the content on the screen.

[0095] In this context, taking the photosensitive circuit including the photosensitive transistor ST2 as shown in Figure 3, and in conjunction with the film structure of the driving layer DR described above, as shown in Figure 4 or Figure 5, the gate metal layer Ga includes a second conductive portion G2; the gate insulating layer GI also covers the second conductive portion G2; the active layer ACT includes a second active portion P2, which includes a second channel region P21 and a third connection portion P22 and a fourth connection portion P23 located on both sides of the second channel region P21.

[0096] Thus, the first and second electrodes of the photosensitive transistor ST2 can be formed by the third connecting part P22 and the fourth connecting part P23 respectively, and the control electrode of the photosensitive transistor ST2 can be formed by the area on the second conductive part G2 that overlaps with the second channel region P21.

[0097] Additionally, as shown in Figure 6, the pixel circuit layer includes a voltage signal line VDD, the photosensitive element SM3 includes a photoelectric conversion unit PIN1 and a first electrode SM11 and a second electrode SM21 located on both sides of the photoelectric conversion unit PIN1, the gate metal layer Ga includes a photosensitive scan line MG, and the source / drain metal layer SD includes a third connection line SD3, a fourth connection line SD4, and a photosensitive data line MD.

[0098] The photosensitive scan line MG is connected to the second conductive part G2 (or is an integral design) to load a first level signal on the second conductive part G2 (i.e., the control electrode of the photosensitive transistor ST2) through the photosensitive scan line MG; one end of the fourth connecting line SD4 is connected to the fourth connecting part P23 (i.e., the second electrode of the photosensitive transistor ST2) (for example, directly covering the fourth connecting part P23), and the other end is connected to the photosensitive element SM3 (first electrode SM11, not shown in the figure) through a via; one end of the third connecting line SD3 is connected to the photosensitive data line MD (or is an integral design), and the other end is connected to the third connecting part P22 (i.e., the first electrode of the photosensitive transistor ST2) (for example, directly covering the third connecting part P22) to load a second level signal on the third connecting part P22 through the photosensitive data line MD; and the voltage signal line VDD is connected to the photosensitive element SM3 (second electrode SM21) and is used to load a third level signal.

[0099] Thus, a high-level first-level signal can be applied to the second conductive part G2 (i.e., the control electrode of the phototransistor) via the photosensitive scan line MG to control the conduction of the phototransistor ST2. Simultaneously, a second-level signal is applied to the third connection part P22 (i.e., the first electrode of the phototransistor ST2) via the photosensitive data line MD, and a third-level signal is applied to the second electrode SM21 of the photosensitive element SM3 via the voltage signal line VDD. It is ensured that the second-level signal and the third-level signal are different, so that the charge obtained from photoelectric conversion by the photosensitive element SM3 flows towards the high-level direction (e.g., the photosensitive data line MD), and the electrons flow towards the low-level direction (e.g., the voltage signal line VDD). Furthermore, upon detecting a change in current (change in charge or electron quantity) in either the second-level or third-level signal, it is determined that the photosensitive element SM3 has detected light.

[0100] In some embodiments, as shown in FIG1 or FIG2 and FIG6, the photosensitive layer SM includes a first conductive layer SM1, a photoelectric conversion layer PIN, and a second conductive layer SM2 sequentially stacked on one side of the array substrate BP1; the first conductive layer SM1 includes a first electrode SM11, the photoelectric conversion layer PIN includes a photoelectric conversion unit PIN1, and the second conductive layer SM2 includes a second electrode SM21. A first electrode SM11, a photoelectric conversion unit PIN1, and a second electrode SM21 constitute a photosensitive element SM3.

[0101] The first electrode SM11 is connected to the photosensitive circuit and is combined with the voltage signal line VDD mentioned above. The second electrode SM21 is connected to the voltage signal line VDD. The photoelectric conversion unit PIN1 and the first electrode SM11 have overlapping regions on the array substrate BP1. The second electrode SM21 and the photoelectric conversion unit PIN1 have overlapping regions on the array substrate BP1. This ensures that the charge and electrons after photoelectric conversion by the photoelectric conversion unit PIN1 can flow to the photosensitive circuit and the voltage signal line VDD, respectively.

[0102] The first conductive layer SM1 can be a metal layer, for example, made of the same material as the source / drain metal layer SD. In this case, the photosensitive layer SM can be, in addition to the above-mentioned film structure, also include only the photoelectric conversion layer PIN and the second conductive layer SM2. When the photosensitive layer SM does not include the first conductive layer SM1, combined with the film structure of the driving layer DR described above, the source / drain metal layer SD can include the first electrode SM11, so as to simplify the film structure of the array substrate 10 by reusing the source / drain metal layer SD.

[0103] The photoelectric conversion layer PIN may include an intrinsic layer, as well as a P-type silicon material layer and an N-type silicon material layer located on both sides of the intrinsic layer, thereby forming a positive charge space (for loading a high level) and a negative charge space (i.e., an electron space, and for loading a low level) on both sides of the intrinsic layer.

[0104] The second conductive layer SM2 includes a second electrode SM21 that may only cover a portion of the photoelectric conversion unit PIN1. That is, at least a portion of the orthogonal projection of the photoelectric conversion unit PIN1 on the array substrate BP1 is located outside the orthogonal projection of the second electrode SM21 on the array substrate BP1, so as to avoid the second electrode SM21 affecting the illumination of the photoelectric conversion unit PIN1. Alternatively, the orthogonal projection of the second electrode SM21 on the array substrate BP1 may at least coincide with the orthogonal projection of the photoelectric conversion unit PIN1 on the array substrate BP1, and the second conductive layer SM2 is a light-transmitting layer (such as a light-transmitting indium tin oxide layer). Thus, through the light-transmitting design of the second electrode SM21, the second electrode SM21 is prevented from affecting the illumination of the photoelectric conversion unit PIN1.

[0105] In conjunction with the connection between the voltage signal line VDD and the second electrode SM21 described above, since the second electrode SM21 is located on the side closer to the color filter substrate 20, to prevent the third-level signal loaded on the second electrode SM21 from causing the cholesteric liquid crystal in the liquid crystal layer 30 to deflect, the third-level signal loaded on the voltage signal line VDD can be controlled to be low. That is, the third-level signal loaded on the second electrode SM21 by the voltage signal line VDD is low. At this time, a high-level second-level signal is loaded on the photosensitive data line MD at the third connection part P22 (i.e., the first electrode of the photosensitive transistor ST2), so that the charge obtained by the photoelectric conversion of the photosensitive element SM3 flows to the photosensitive data line MD, and the electrons flow to the voltage signal line VDD. Then, after the photosensitive data line MD detects the current change (i.e., the charge change) of the second-level signal, it is determined that the photosensitive element SM3 has detected illumination.

[0106] In this embodiment of the disclosure, for the voltage signal line VDD included in the pixel circuit layer, the voltage signal can be located in the driving layer DR or in the photosensitive layer SM.

[0107] Taking the voltage signal line VDD located in the driving layer DR as an example, the source and drain metal layer SD includes the voltage signal line VDD, and the voltage signal line VDD is connected to the second electrode SM21 of the photosensitive element SM3.

[0108] Taking the voltage signal line VDD located in the photosensitive layer SM as an example, as shown in Figure 7, the first conductive layer SM1 includes the voltage signal line VDD, and the voltage signal line VDD is connected to the second electrode SM21 of the photosensitive element SM3; or as shown in Figure 8, the second conductive layer SM2 includes the voltage signal line VDD, and the voltage signal line VDD and the second electrode SM21 of the photosensitive element SM3 are designed as an integral part.

[0109] In this embodiment of the disclosure, the pixel electrode ANO included in the pixel circuit layer can be located in the driving layer DR or in the photosensitive layer SM.

[0110] Taking the pixel electrode ANO located in the driving layer DR as an example, as shown in Figures 8 and 9, the source / drain metal layer SD includes the pixel electrode ANO. In this case, the pixel electrode ANO can be directly connected to the driving transistor ST1 of the pixel circuit, meaning that there is no need to set a via in the passivation layer PVX, thus simplifying the setup of the array substrate 10. Since the via is avoided, the surface of the pixel electrode ANO can be set to white, thereby increasing the display area AA of the white image and increasing the pixel aperture ratio.

[0111] Taking the pixel electrode ANO located in the photosensitive layer SM as an example, as shown in Figure 10, the first conductive layer SM1 includes the pixel electrode ANO, that is, the first electrode SM11 and the pixel electrode ANO are disposed on the same layer. At this time, the pixel electrode ANO is connected to the transistor of the pixel circuit through a via. Due to the light-shielding characteristics of the first conductive layer SM1, the via can be blocked. Therefore, when the surface of the first conductive layer SM1 is set to white, that is, the surface of the pixel electrode ANO is white, it is convenient to increase the display area AA of the white image, so as to increase the pixel aperture ratio.

[0112] Alternatively, as shown in Figures 11 and 12, the second conductive layer SM2 includes a pixel electrode ANO, meaning the second electrode SM21 and the pixel electrode ANO are disposed on the same layer. In this case, the pixel electrode ANO is connected to the driving transistor ST1 of the pixel circuit through a via. Since the second conductive layer SM2 is closer to the color filter substrate 20, it facilitates increasing the parallel capacitance between the pixel electrode ANO and the common electrode layer COM, thereby mitigating the flickering problem of the display panel 100 and ensuring the stability of the displayed image.

[0113] In some embodiments, the gate metal layer Ga further includes an auxiliary electrode, the gate insulating layer GI covers the auxiliary electrode, and the auxiliary electrode and the pixel electrode ANO have an overlapping area in their orthogonal projections on the array substrate BP1.

[0114] The auxiliary electrode is used to connect with the common electrode layer COM of the color filter substrate 20. In this way, the auxiliary electrode and the pixel electrode ANO can form an auxiliary capacitor in parallel with the parallel capacitor (pixel electrode ANO and common electrode layer COM), so as to further increase the capacitance value between pixel electrode ANO and common electrode layer COM and ensure the stability of the display image.

[0115] In this embodiment of the disclosure, as shown in FIG13, the array substrate 10 includes a display area AA and a peripheral area BB located outside the display area AA.

[0116] The display area AA has the pixel circuit, pixel electrode ANO, photosensitive circuit and photosensitive element SM3 described above. In order to drive the pixel circuit and photosensitive circuit normally, the pixel circuit layer includes a driving data line DD and a driving scan line DG connected to the pixel circuit, as well as a photosensitive data line MD and a photosensitive scan line MG connected to the photosensitive circuit.

[0117] In some implementations, as shown in FIG14, within the display area AA, the driving scan line DG and the photosensitive scan line MG extend along the row direction X, and the driving data line DD and the photosensitive data line MD extend along the column direction Y; the pixel electrode ANO and the photosensitive element SM3 are both located within the area enclosed by the driving scan line DG, the photosensitive scan line MG, the driving data line DD, and the photosensitive data line MD connected to the corresponding pixel circuit and photosensitive circuit.

[0118] Thus, by defining the positions of the pixel electrode ANO and the photosensitive element SM3, a one-to-one correspondence between the photosensitive element SM3 and the pixel electrode ANO is achieved, thereby realizing the pixel-level air-to-air interaction of the array substrate 10. In addition, the size of the pixel electrode ANO can be maximized by the area enclosed by the driving scan line DG, the photosensitive scan line MG, the driving data line DD, and the photosensitive data line MD, so as to ensure the aperture ratio of the pixels on the array substrate 10.

[0119] Of course, in addition to achieving pixel-level air-to-air interaction as described above, the photosensitive element SM3 can also be configured to correspond with multiple pixel electrodes ANO, that is, to reduce the air-to-air interaction level of the array substrate 10, and at the same time reduce the setting of photosensitive data lines MD and / or photosensitive scan lines MG, so as to increase the size of each pixel electrode ANO, thereby further improving the pixel aperture ratio.

[0120] In some implementations, as shown in FIG13, the driving scan line DG and the photosensitive scan line MG, as well as the driving data line DD and the photosensitive data line MD, all extend to the peripheral area BB. In the peripheral area BB, the driving scan line DG and the photosensitive scan line MG are located on both sides of the display area AA along the row direction X, and the driving data line DD and the photosensitive data line MD are located on the same side of the display area AA along the column direction Y.

[0121] In this design, the driving scan line DG and photosensitive scan line MG of the peripheral area BB are respectively positioned on both sides of the display area AA along the row direction to reduce crosstalk between them. Additionally, the peripheral area BB houses a driving module B1 and a photosensitive module B2, both located on the same side of the display area AA along the column direction, and also on the same side as the driving data line DD and photosensitive data line MD. Thus, normal driving of the pixel circuit and photosensitive circuit can be achieved through the connection of the driving scan line DG and driving data line DD to the driving module B1, and through the connection of the photosensitive scan line MG and photosensitive data line MD to the photosensitive module B2.

[0122] In the display area AA, the driving data line DD and the photosensitive data line MD are both located on the source / drain metal layer SD of the driving layer DR. At this time, the driving data line DD and the photosensitive data line MD can be layered in the outer area BB (for example, one is located on the source / drain metal layer SD in the outer area BB, and the other is located on the second conductive layer SM2 in the outer area BB, etc.) to avoid interference caused when the driving data line DD and the photosensitive data line MD in the outer area BB are located on the same side of the display area AA. This makes it easier to realize the miniaturization design of the outer area BB, that is, to realize the narrow bezel design of the display panel 100.

[0123] This disclosure also provides a display method for a display panel, which is applied to the display panel described in the above embodiments.

[0124] The display panel includes a sensing stage and a display stage. The sensing stage is used to determine whether a photosensitive element has detected light, and includes a calibration stage, a photoelectric conversion stage, a reading stage, and a feedback stage. The display stage is used to adjust the image, including but not limited to switching from the current frame to the next frame.

[0125] As shown in Figures 15 and 16, the display method includes steps S110-S150.

[0126] Step S110: During the calibration phase, a high-level first-level signal is periodically input to the control electrode of the phototransistor to periodically turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element to calibrate the amount of charge in the photosensitive element.

[0127] Step S120: In the photoelectric conversion stage, a low-level first-level signal is input to the control electrode of the phototransistor so that the photosensitive element can receive light and perform photoelectric conversion when the phototransistor is turned off.

[0128] Step S130: During the reading stage, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor.

[0129] Step S140: In the feedback phase, determine the position information of the target photosensitive element based on the actual charge amount.

[0130] Step S150: During the display phase, based on the position information, a drive signal is transmitted to the corresponding pixel circuit to write or erase content on the current screen.

[0131] In this embodiment of the disclosure, when the display panel is displaying a normal image, the light can be detected by the cooperation of the photosensitive transistor and the photosensitive element. Then, based on the position information of the photosensitive element that has detected the light, the writing or erasing of content on the current image can be realized, thereby realizing the air-to-air interactive operation control mode of the display panel and improving the convenience of operating the display panel.

[0132] In step S110 above, the periodic conduction of the photosensitive transistor enables the charge in the photosensitive element to flow periodically to the first electrode of the photosensitive transistor and be released along the photosensitive data line, thereby ensuring that the amount of charge in the photosensitive element remains constant and ensuring the accuracy of subsequent photosensitive element detection.

[0133] In step S130 above, when the photosensitive transistor is turned on and the charge in the photosensitive element flows to the first electrode of the photosensitive transistor, since the first electrode of the photosensitive transistor is connected to the photosensitive data line, the actual charge amount of the second level signal at the current moment can be obtained by detecting the current change on the photosensitive data line.

[0134] In step S140 above, it can be determined whether the charge of the second level signal has changed based on the reference charge of the second level signal and the actual charge at the current moment. When the charge of the second level signal does not change (or the change is small), it can be confirmed that the corresponding photosensitive element has not detected light. When the charge of the second level signal changes (or the change is large), it can be confirmed that the corresponding photosensitive element has detected light. At this time, the photosensitive element can be designated as the target photosensitive element, and the position information of the target photosensitive element can be determined.

[0135] In step S150 above, a corresponding driving signal can be sent to the pixel circuit based on the steady state of the cholesteric liquid crystal at the location of the photosensitive element, so as to adjust the image on the display panel by the magnitude of the voltage applied to the pixel electrode by the pixel circuit.

[0136] Specifically, taking the cholesteric liquid crystal at the location of the photosensitive element being in the first stable state as an example, the transistors of the pixel circuit can be turned on based on the driving scan line, and a low voltage can be applied to the pixel electrode based on the driving data line and the pixel circuit, so as to control the cholesteric liquid crystal at the location of the photosensitive element to switch from the first stable state to the second stable state, thereby erasing part of the content on the screen; taking the cholesteric liquid crystal at the location of the photosensitive element being in the second stable state as an example, after the driving module receives the position information of the photosensitive element, the transistors of the pixel circuit can be turned on based on the driving scan line, and a high voltage can be applied to the pixel electrode based on the driving data line and the pixel circuit, so as to control the cholesteric liquid crystal at the location of the photosensitive element to switch from the second stable state to the first stable state, thereby writing the content on the screen.

[0137] Alternatively, after receiving the position information of the photosensitive element, the driving module can apply a low voltage to the pixel electrode based on the erase command to control the cholesteric liquid crystal at the location of the photosensitive element to switch from the first stable state to the second stable state, thereby erasing part of the content on the screen; and apply a high voltage to the pixel electrode based on the write command to control the cholesteric liquid crystal at the location of the photosensitive element to switch from the second stable state to the first stable state, thereby writing the content on the screen.

[0138] In addition, in the above steps S110-S150, steps S110-S140 can be implemented by the sensing module, and step S150 can be connected by the driving module, and the sensing module and the driving module can be connected to realize the transmission of the position information of the target photosensitive element.

[0139] It should be noted that although the steps of the methods shown in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0140] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: Array substrate; A pixel circuit layer is located on one side of the array substrate and includes a driving layer and a photosensitive layer. The driving layer includes a pixel circuit and a photosensitive circuit, and the photosensitive layer includes a photosensitive element. One of the driving layer and the photosensitive layer includes a pixel electrode. The pixel electrode and the photosensitive element do not overlap in their orthographic projections on the array substrate. The pixel circuit is connected to the pixel electrode, and the photosensitive element includes a photoelectric conversion unit, with the photosensitive circuit connected to the photosensitive element.

2. The array substrate as claimed in claim 1, wherein, The photosensitive layer includes a first conductive layer, a photoelectric conversion layer, and a second conductive layer sequentially stacked on one side of the array substrate. The first conductive layer includes a first electrode, the photoelectric conversion layer includes the photoelectric conversion unit, and the second conductive layer includes a second electrode. One first electrode, one photoelectric conversion unit, and one second electrode constitute one photosensitive element. The first electrode is connected to the photosensitive circuit, and the photoelectric conversion unit and the orthographic projection of the first electrode on the array substrate have an overlapping area, and the second electrode and the orthographic projection of the photoelectric conversion unit on the array substrate also have an overlapping area.

3. The array substrate as described in claim 2, wherein, At least a portion of the orthogonal projection of the photoelectric conversion unit onto the array substrate is located outside the orthogonal projection of the second electrode onto the array substrate.

4. The array substrate as claimed in claim 2, wherein, The orthographic projection of the second electrode on the array substrate coincides at least with the orthographic projection of the photoelectric conversion unit on the array substrate, and the second conductive layer is a light-transmitting layer.

5. The array substrate as described in any one of claims 2-4, wherein, The first conductive layer or the second conductive layer further includes a voltage signal line, which is connected to the second electrode.

6. The array substrate as described in any one of claims 2-4, wherein, The first conductive layer or the second conductive layer further includes the pixel electrode.

7. The array substrate as described in any one of claims 2-4, wherein, The pixel circuit includes a driving transistor, and the driving layer includes: A gate metal layer is located on one side of the array substrate and includes a first conductive portion; A gate insulating layer is located on the side of the gate metal layer opposite to the array substrate, and at least covers the first conductive portion; An active layer is located on the side of the gate insulating layer away from the array substrate, and includes a first active portion, the first active portion including a first channel region and a first connection portion and a second connection portion located on both sides of the first channel region; A source / drain metal layer is located on the side of the active layer away from the array substrate, and includes a first connection line, the two ends of which are electrically connected to the first connection portion and the pixel electrode, respectively. The first connecting portion and the second connecting portion respectively form the first electrode and the second electrode of the driving transistor. The second electrode of the driving transistor is used to load a data signal. The area on the first conductive portion that overlaps with the first channel region forms the control electrode of the driving transistor. The control electrode of the driving transistor is used to load a scan signal.

8. The array substrate as claimed in claim 7, wherein, The source / drain metal layer also includes a voltage signal line, which is connected to the second electrode.

9. The array substrate as claimed in claim 7, wherein, The source / drain metal layer also includes the pixel electrode.

10. The array substrate as claimed in claim 9, wherein, The gate metal layer further includes an auxiliary electrode, which is covered by the gate insulating layer. The auxiliary electrode and the pixel electrode have an overlapping area on the array substrate.

11. The array substrate as claimed in claim 1, wherein, The array substrate includes a display area; The pixel circuit layer includes driving data lines and driving scan lines connected to the pixel circuit, as well as photosensitive data lines and photosensitive scan lines connected to the photosensitive circuit. Within the display area, the driving scan lines and photosensitive scan lines extend along the row direction, and the driving data lines and photosensitive data lines extend along the column direction; the pixel electrodes and the photosensitive elements are all located within the area enclosed by the driving scan lines, photosensitive scan lines, driving data lines, and photosensitive data lines connected to the corresponding pixel circuit and photosensitive circuit.

12. The array substrate as claimed in claim 11, wherein, The array substrate includes a peripheral area located outside the display area; The driving scan line and the photosensitive scan line, as well as the driving data line and the photosensitive data line, all extend to the peripheral area. In the peripheral area, the driving scan line and the photosensitive scan line are located on both sides of the display area along the row direction, and the driving data line and the photosensitive data line are located on the same side of the display area along the column direction, and are located in different film layers.

13. A display panel, wherein, It includes a color filter substrate and an array substrate as described in any one of claims 1-12, which are disposed opposite to each other, and a liquid crystal layer and a spacer located between the array substrate and the color filter substrate.

14. The display panel as claimed in claim 13, wherein, The array substrate includes a planarization layer; The planarization layer is located on the side of the array substrate close to the color filter substrate, and the planarization layer and the spacer are an integral structure.

15. The display panel as claimed in claim 13, wherein, The spacer is spherical.

16. A method for displaying a display panel, wherein, The display method is applied to the display panel according to any one of claims 13-15, the photosensitive circuit includes a photosensitive transistor, the control electrode of the photosensitive transistor is used to load a first level signal, the first electrode of the photosensitive transistor is used to load a second level signal, and the second electrode of the photosensitive transistor is connected to the first electrode of the photosensitive element, the second electrode of the photosensitive element is used to load a third level signal; The display panel includes a sensing stage and a display stage. The sensing stage includes a calibration stage, a photoelectric conversion stage, a reading stage, and a feedback stage. The display method includes: During the calibration phase, a high-level first-level signal is periodically input to the control electrode of the phototransistor to periodically turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element to correct the amount of charge in the photosensitive element. During the photoelectric conversion stage, a low-level first-level signal is input to the control electrode of the phototransistor so that when the phototransistor is turned off, light is received through the photosensitive element and photoelectric conversion is performed. During the reading phase, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor. During the feedback phase, the position information of the target photosensitive element is determined based on the actual charge amount; During the display phase, based on the position information, a drive signal is transmitted to the corresponding pixel circuit to write or erase content on the current screen.

Images