Optoelectronic sensor arrangement with substrate contact and processing thereof

Abstract

The invention concerns an optoelectronic sensor arrangement comprising at least one electrical connection between a bulk semiconductor substrate associated with the optoelectronic sensor or a handling wafer and a contact pad arranged on a redistribution layer. The electrical connection allows monitoring and regulation of electrical potential within the bulk semiconductor substrate.

Description

[0001] 2024PF01477

[0002] OPTOELECTRONIC SENSOR ARRANGEMENT WITH SUBSTRATE CONTACT AND

[0003] PROCESSING THEREOF

[0004] The present application claims priority from DE application DE 10 2024 134 319 . 2 dated November 21 , 2024 , the disclosure of which is incorporated herein by reference in its entirety .

[0005] The present invention concerns an optoelectronic arrangement , in particular , a semiconductor device package comprising an optoelectronic sensor . The invention further involves a processing method for producing an optoelectronic arrangement comprising an optoelectronic sensor and associated electrical connections .

[0006] BACKGROUND

[0007] The drive towards increased device density on semiconductor wafers has led to development of innovative structural solutions for power supply to optoelectronic devices . Through-silicon vias ( TSVs ) or through-chip vias (TCVs ) have been developed to allow formation of wiring connections within semiconductor substrates used either as growth substrates or as carrier substrates , thereby resulting in significant reductions in device footprint and associated increase in device density during wafer-based processing .

[0008] Manufacture of optoelectronic devices is commonly divided into multiple stages which may take place in different facilities , possibly by different manufacturers . Such a process would, for example , involve production of a device wafer comprising semiconductor-based optoelectronic devices and associated active or passive devices during front end-of-line ( FEOL ) processes , followed by production of metal interconnect layers embedded in dielectric during a set of back end- of-line ( BEOL ) processes . Vias connecting the metal interconnect layers are typically formed within the dielectric during the BEOL stage . Thereafter , during back-end processes , also known as post-fab processes , finishing of the device wafers and packaging takes place .

[0009] TSVs and / or TCVs are typically produced as part of post-fab processes , as part of device packaging steps . The formation of TCVs involves 2024PF01477 forming recesses within the semiconductor substrate , usually originating from the sensor side of the device wafer . The recesses are electrically isolated from the surrounding semiconductor substrate by depositing a dielectric lining layer, and thereafter filled with an electrically conductive material .

[0010] As a result of the electrical isolation of the TCVs from the semiconductor substrate , electrical characterization of the TCV sidewall quality is not possible , due to lack of electrical contact to the substrate . Additionally, the isolation of the semiconductor substrate from electrical contact points results in an unknown or floating potential , which could potentially compromise device performance and / or product lifetime and is additionally associated with reduced repeatability in the manufacturing process and a corresponding inconsistency in production output .

[0011] Furthermore , structures and process-specific features on the backside of the semiconductor substrate are not directly accessible after bonding of the finished wafer to printed circuit boards .

[0012] It is an obj ect of the present application to address the abovementioned challenges and provide a structure allowing electrical characterization of TSVs and surrounding semiconductor substrate at various stages of manufacturing .

[0013] SUMMARY OF THE INVENTION

[0014] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0015] The inventors propose an optoelectronic package involving formation of a substrate contact in a semiconductor substrate comprising through- silicon vias (TSVs ) . In optoelectronic arrangements comprising a carrier substrate , for example , for implementation of backside illumination configurations on wafers comprising complementary metal oxide semiconductor ( CMOS ) sensors , the proposed invention can alternatively or additionally be implemented on the carrier substrate , 2024PF01477 thereby allowing substrate monitoring and / or contact from the carrier backside . Such a dual TSV configuration is particularly advantageous as it allows measurement from two sides of the optoelectronic arrangement , i . e . the sensor side and the carrier side , during various stages of the process flow .

[0016] The proposed optoelectronic arrangement comprises a first semiconductor substrate with a first surface and a second surface , an interconnection layer arranged on the second surface , at least one optoelectronic sensor arranged on the interconnection layer, a second semiconductor substrate arranged in contact with the interconnection layer, at least one first recess originating from the first surface through the first semiconductor substrate and comprising a first electrically conductive layer, at least one first electrical contact layer arranged on the first surface and comprising at least one contact pad, and at least one second electrical contact layer electrically connecting the first semiconductor substrate to at least one contact pad .

[0017] In some aspects , the first semiconductor substrate is associated with the device wafer, and either corresponds to a growth wafer on which the at least one optoelectronic sensor and is epitaxially grown, or to a carrier wafer onto which the optoelectronic sensor has been transferred . The device wafer in some aspects additionally comprises active and / or passive semiconductor devices associated with the at least one optoelectronic sensor, for example CMOS logic circuitry .

[0018] In other aspects , the optoelectronic arrangement comprises a carrier substrate which is bonded to a device wafer, in particular, on the surface of the interconnection layer of the device wafer . The carrier substrate may be incorporated to provide additional mechanical support during further processing, particularly for very thin device wafers , which, in some aspects , comprise thicknesses below 20 pm, making them challenging to handle without damaging the optoelectronic devices thereon . In some such aspects , the carrier substrate is removed after processing of the device wafer . In other aspects , the carrier substrate comprises additional structural features , thus forming a permanent backside of the final packaged device . In some such aspects , the carrier 2024PF01477 substrate is considered as the first semiconductor substrate , and the semiconductor substrate associated with the device wafer is considered to be a second semiconductor substrate . In other aspects , the carrier substrate is considered to be the second semiconductor substrate .

[0019] The first and optional second semiconductor substrate may comprise any suitable semiconductor material , in particular, silicon . Other suitable materials may however be preferred depending on the thermal , mechanical and / or electrical characteristics required of the device and / or the device packaging .

[0020] The interconnection layer is arranged on the second surface of the first semiconductor substrate . Any suitable wafer bonding technique may be used to connect the interconnection layer to the first semiconductor substrate . In some aspects of the proposed invention, the interconnection layer comprises a BEOL-processed structure comprising a plurality of electrical contacts , in particular , electrically conductive layers deposited in multiple levels , said plurality of electrical contacts being at least partially embedded within insulating / dielectric layers . In some aspects , the plurality of electrical contacts is fully embedded within the dielectric, i . e . all surfaces of the plurality of electrical contacts are surrounded by dielectric material . The interface between the interconnection layer and the first semiconductor substrate comprises a layer of dielectric material , also referred to as an interlayer dielectric ( ILD ) . The dielectric layers may comprise a non-conductive oxide , for example , Si02 . In some aspects , the interconnection layer further comprises a plurality of vias within the dielectric material to facilitate electrical connection between different levels of the plurality of electrical contacts .

[0021] In some aspects , at least some of the plurality of electrical contact layers comprise a sublayer structure with at least two sublayers stacked upon each other . In some such aspects , the two topmost of the at least two sublayers comprise different conductive materials and / or different thicknesses . In particular , the thickness of the topmost sublayer is smaller than the thickness of a subsequent underlying 2024PF01477 sublayer . An exemplary conf iguration involves a topmost sublayer comprising TiN and a subsequent sublayer comprising AlCu . A further , third sublayer underlying the AlCu sublayer may comprise TiN or Ti .

[0022] It is to be noted that the abovementioned configurations of the interconnection layer are provided as examples , and the proposed invention is not limited thereto . In particular , in aspects wherein a carrier substrate forms the first semiconductor substrate , the internal configuration of the interconnection layer may vary from one device manufacturer to another, thus the back-end processing of the TSVs as described herein is configured to be substantially independent of the peculiarities associated with device wafers from different sources .

[0023] The at least one optoelectronic sensor is in some exemplary aspects configured to detect and / or measure incident light impinging on a sensing surface . The sensing surface faces away from the first surface of the first semiconductor substrate . The at least one optoelectronic sensor is electrically connected to at least one of the plurality of electrical contacts within the interconnection layer . In some aspects , at least one of a plurality of vias provided within the interconnection layers is used to provide electrical connection to the at least one optoelectronic sensor . Furthermore , in some aspects , a reflective conductive layer is provided within the interconnection layer facing the at least one optoelectronic sensor , said reflective conductive layer in particular comprising Cu .

[0024] In some aspects , the at least one optoelectronic sensor is arranged such that the sensing surface faces away from the interconnection layer . Such aspects are referred to as backside illuminated devices and are characterized by an illumination path wherein incident light arrives at the sensing surface without passing through the interconnection layer . In other aspects , referred to as frontside illuminated devices , the optoelectronic sensor is arranged such that the sensing surface faces towards the interconnection layer . In such aspects , incident light travels through the interconnection layer before impinging on the sensing surface . While the disclosure herein primarily focuses on backside illuminated devices , the proposed 2024PF01477 principle is similarly applicable to frontside illuminated devices . Furthermore , in some aspects , the at least one optoelectronic sensor is at least partially embedded within the first semiconductor substrate . In other aspects , the at least one optoelectronic sensor is at least partially embedded within the second semiconductor substrate . In some aspects , the at least one optoelectronic sensor is at least partially embedded within the carrier substrate . In other aspects , the at least one optoelectronic sensor is at least partially embedded within the semiconductor substrate associated with the device wafer .

[0025] In some aspects , at least one of the first and / or the second semiconductor substrate , in particular, a semiconductor substrate corresponding to the device wafer , comprises a backside metal shielding, which improves radiofrequency immunity in the device .

[0026] The at least one first recess forms an open through-silicon via ( or a through-carrier via ) and originates from the first surface of the first semiconductor substrate , terminating at a second one of the plurality of electrical contacts in the interconnection layer . The sidewalls of the at least one first recess comprise a first electrically conductive layer, which optionally also forms the bottom of the at least one first recess . The first electrically conductive layer is isolated from the first semiconductor substrate along the sidewalls of the at least one first recess , in particular, by a dielectric layer .

[0027] In aspects wherein the at least one optoelectronic sensor is embedded within the first semiconductor substrate , the at least one first recess is preferably formed laterally distanced from the at least one optoelectronic sensor . This prevents interference with the sensor function . However, such a configuration is associated with comparably larger lateral dimensions of the final package . For aspects wherein the at least one optoelectronic sensor is embedded within the second semiconductor substrate , the lateral dimensions of the package can advantageously be reduced by forming the at least one first recess within a region defined by a proj ection of the sensor into the first semiconductor substrate , thus requiring no additional lateral area to accommodate the TSVs . However , the minimum achievable package thickness 2024PF01477 is increased, as the second semiconductor substrate forms an integral part of the resultant structure .

[0028] The sidewalls of the at least one first recess comprise a first dielectric layer between material of the first semiconductor substrate and the first electrically conductive layer . The first dielectric layer typically comprises a non-conductive oxide , in particular, at least one of Si02 and / or A12O3 .

[0029] The first electrically conductive layer is deposited on the surface of the at least one first recess , contacting at least one second one of the plurality of electrical contacts in the interconnection layer and optionally covering the bottom of the first recess . Along the sidewalls of the at least one first recess , the first dielectric layer isolates the first electrically conductive layer from the first semiconductor substrate .

[0030] In some exemplary aspects of the proposed invention, the first electrically conductive layer comprises at least one of Titanium (Ti ) , Titanium Nitride ( TiN) or Tungsten (W) . The first electrically conductive layer is preferably deposited using chemical vapor deposition (CVD ) , with a layer thickness of approximately 200 nm for Tungsten . The dimensioning of the thickness of the first electrically conductive layer relative to the lateral dimensions of the at least one first recess is such that a central opening remains even after deposition of the first electrically conductive layer, resulting in open TSVs , that is , TSVs with a central recess .

[0031] The first electrical contact layer deposited on the first surface of the first semiconductor substrate serves as a redistribution layer , and, in some aspects , facilitates flip chip bonding of the optoelectronic package via the incorporated contact pads . The first electrically conductive layer is arranged in contact with the first electrical contact layer , thereby forming an electrical connection between the electrical contact layer and the interconnection layer . 2024PF01477

[0032] In some aspects , the first electrical contact layer at least partially extends into the at least one first recess at the open end facing the first surface of the first semiconductor substrate . In some such aspects , the first electrical contact layer at least partially covers the first electrically conductive layer . Such a configuration allows provision of a sufficient overlap between the first electrical contact layer and the first electrically conductive layer, as the contact area between the two layers can be suitably dimensioned . In other aspects , the first electrical contact layer forms a substantially planar layer atop the first semiconductor substrate . In some such aspects , the first electrically conductive layer laterally abuts the first electrical contact layer . In other aspects , the first electrically conductive layer vertically abuts the first electrical contact layer from within the at least one first recess .

[0033] In some aspects , the first electrical contact layer comprises a material different from the first electrically conductive layer, in particular , an alloy comprising at least one of Al and Cu . The first electrical contact layer is in some aspects formed by physical vapor deposition ( PVD) . In some aspects the first electrical contact layer further comprises a protective layer , in particular, a capping oxide layer . The protective oxide layer is deposited directly after deposition of the first electrical contact layer .

[0034] In aspects comprising a second semiconductor substrate , the optoelectronic arrangement further comprises at least one second recess originating from a surface of the second semiconductor substrate facing away from the first semiconductor substrate and extending into the interconnection layer, such that the bottom of the at least one second recess is formed by at least one second one of the plurality of electrical contacts in the interconnection layer .

[0035] In some aspects , the bottom of the at least one second recess and the bottom of the at least one first recess are formed by opposite surfaces of a common second one of the plurality of electrical contacts within the interconnection layers . In other aspects , the bottom of the at least one first recess and the bottom of the at least one second recess 2024PF01477 are formed by an electrically connected pair of second ones of the plurality of electrical contacts , in particular, wherein the pair of electrical contacts comprise outermost layers of a multi-level stack of electrical contacts within the interconnection layer . The connection between the pair of electrical contacts is in some aspects achieved through a via in the interconnection layer . In aspects wherein the first recess and the second recess are electrically connected, mirrored access points from opposite surfaces of the optoelectronic arrangement are available , allowing increased flexibility in design of mounting options during packaging . In other aspects , the at least one first recess and the at least one second recess are electrically isolated .

[0036] The sidewalls of the at least one second recess comprise a second electrically conductive layer which is electrically isolated from material of the second semiconductor substrate by a second dielectric layer . In some aspects , the second dielectric layer and the second electrically conductive layer comprise substantially identical materials to the first dielectric layer and the first electrically conductive layer respectively . In other aspects , different materials may be used for the layers deposited within the at least one second recess .

[0037] A third electrical contact layer serving as a redistribution layer is arranged adj acent to the surface of the second semiconductor substrate facing away from the first semiconductor substrate and is electrically connected to the second electrically conductive layer . A third dielectric layer is in some aspects arranged between the third electrical contact layer and the second semiconductor substrate . In some aspects , the third electrical contact layer partially extends into the at least one second recess , optionally covering part of the surface of the second electrically conductive layer . In some aspects , the third electrical contact layer comprises a transparent conductive oxide , in particular , ITO .

[0038] The at least one second electrical contact layer provides an electrical connection between the first semiconductor substrate and at least one contact pad associated with the first electrical contact layer . In some 2024PF01477 aspects , the second electrical contact layer is formed on the first surface of the first semiconductor substrate , with an electrical connection to the first semiconductor substrate being formed through openings in the first dielectric layer . In such aspects , the second electrical contact layer may be formed during deposition of the first electrical contact layer , wherein the first dielectric layer on the first surface of the first semiconductor substrate is patterned to form at least one opening , partially exposing a surface of the first semiconductor substrate . The second electrical contact layer is thus formed from regions of the first electrical contact layer electrically connected to the first semiconductor substrate through the openings in the first dielectric layer .

[0039] In other aspects , the second electrical contact layer is formed by a third electrically conductive layer arranged at least on the sidewalls of at least one third recess from the first surface of the first semiconductor substrate , wherein the third electrically conductive layer is in contact with the first semiconductor substrate and is connected to at least one contact pad on the first electrical contact layer . In some aspects the at least one third recess comprises a depth substantially less than the thickness of the first semiconductor substrate , such that a bottom surface of the at least one third recess is formed by material of the first semiconductor substrate . In such aspects , the electrical connection to the first semiconductor substrate allows electrical characterization of the semiconductor substrate and additionally provides a current inj ection point , thus facilitating measurement and adj ustment of the electrical potential of the first semiconductor substrate . In other aspects , the at least one third recess extends through the first semiconductor substrate and at least partially into the interconnection layer , such that a bottom surface of the at least one third recess is formed by at least one third one of the plurality of electrical contacts . An electrical connection is formed between the first electrical contact layer , the first semiconductor substrate and the at least one third one of the plurality of electrical contacts . 2024PF01477

[0040] The lateral dimensions of the at least one third recess are m some aspects substantially equal to the lateral dimensions of the at least one first recess . In other aspects , the lateral dimensions of the at least one third recess are smaller than the lateral dimensions of the at least one first recess , in particular , in aspects wherein the bottom of the at least one third recess is formed by material of the second semiconductor layer .

[0041] In some aspects comprising a second semiconductor substrate , the aforementioned configurations of the second electrical contact layer with respect to the first semiconductor substrate are mirrored to form a fourth electrical contact layer providing electrical connection between at least one contact pad on the third electrical contact layer and the second semiconductor substrate .

[0042] Some exemplary aspects of the proposed optoelectronic arrangement further comprise a first structured passivation layer comprising at least one dielectric material , wherein the passivation layer is arranged on surfaces of the first electrical contact layer , the first electrically conductive layer and the third electrically conductive layer . A similar second structured passivation layer may optionally be arranged on the third electrical contact layer , and the second electrically conductive layer . In some exemplary, non-limiting aspects , the structured passivation layer comprises sublayers of SiO2and Si3N4.

[0043] Some aspects of the proposed optoelectronic arrangement further comprise at least one interference filter located above the sensing surface along the direction of light incidence . In other aspects , the optoelectronic arrangement additionally or alternatively comprises a distributed Bragg reflector ( DBR) structure above the sensing surface . The at least one interference filter and / or DBR structure is in some aspects arranged on a surface of the interconnection layer facing away from the first semiconductor substrate . This is particularly the case for aspects of the proposed invention featuring a frontside illumination configuration . In other aspects , the at least one interference filter and / or DBR structure is arranged adj acent to a surface of the second semiconductor substrate facing away from the 2024PF01477 12 first semiconductor substrate . In particular , the interference filter and / or DBR structure is arranged on a surface of the second dielectric layer . Such a configuration is implemented in particular for aspects featuring a backside illumination configuration .

[0044] Further aspects of the proposed invention relate to a method of manufacturing an optoelectronic arrangement . An initial step involves providing an optoelectronic for processing . The optoelectronic arrangement comprises a first semiconductor substrate with a first surface and a second surface opposite the first surface , an interconnection layer comprising a plurality of electrical contacts at least partially embedded within a dielectric and arranged on the second surface , and at least one optoelectronic sensor arranged on the interconnection layer and electrically connected to a first one of the plurality of electrical contacts .

[0045] In some aspects , the provided optoelectronic arrangement is a device wafer that has undergone FEOL processing to form the at least one optoelectronic sensor and, in some aspects , additional active and passive elements associated with the sensor circuitry, and subsequently been subj ected to BEOL processing to form the interconnection layer . The resultant arrangement in such aspects comprises one semiconductor substrate . In some such aspects , the first semiconductor substrate corresponds to a growth substrate in which the at least one optoelectronic sensor and / or semiconductor components associated with the at least one optoelectronic sensor has been processed . In other aspects , the first semiconductor substrate corresponds to a carrier wafer to which the at least one optoelectronic sensor and optionally, associated semiconductor components are transferred for further processing , in particular , wherein the carrier wafer is bonded to the semiconductor side of the processed device wafer .

[0046] In other aspects , the first semiconductor substrate corresponds to a permanent carrier substrate which is arranged on the interconnecting layer of a device wafer to be processed such that the resultant optoelectronic arrangement comprises two semiconductor substrates arranged on opposite surfaces of the interconnecting layer . 2024PF01477

[0047] The first surface of the first semiconductor substrate faces away from a sensing surface of the at least one optoelectronic sensor , wherein the said sensing surface is configured to receive incident radiation which is detected and / or measured by the at least one optoelectronic sensor .

[0048] For aspects wherein the provided optoelectronic arrangement is a device wafer characterized by one semiconductor substrate , the surface of the interconnection layer is optionally coated with a passivation layer and / or planarized . Subsequently, a first handling wafer is arranged on the interconnection layer . Any suitable wafer bonding technique may be used for this purpose , including but not limited to fusion bonding and use of adhesives . Assessment of the bond quality is optionally performed, for example , using confocal scanning acoustic microscopy .

[0049] In some aspects of the proposed method, the first semiconductor substrate is thinned down and / or planarized, in particular, to achieve a thickness between 50 pm and 300 m, and particularly, a thickness between 100 pm and 200 pm, and particularly between 50pm and 100pm and in particular, between 200 pm and 250 pm .

[0050] Thereafter , a first patterned dielectric mas k is deposited on the first surface of the first semiconductor substrate . The step of depositing the first dielectric mask may, for example , involve chemical vapor deposition (CVD ) of SiO2. The proposed method is not however limited thereto . Other methods such as sputtering, and other suitable dielectric materials , such as A12O3may be used, depending on the processing setup . The patterning of the dielectric mas k is configured to allow lateral alignment with at least some of the plurality of electrical contacts in the interconnect layer .

[0051] A subsequent step involves provision of at least one first recess extending from the first surface of the first semiconductor substrate towards the second surface such that a bottom surface of the at least one first recess is formed by at least one of the plurality of electrical contacts . A first dielectric layer is subsequently deposited on the first surface of the first semiconductor substrate and along 2024PF01477 the sidewalls of the at least one first recess , electrically isolating the at least one first recess from the first semiconductor substrate .

[0052] Any suitable wet and / or dry etch process may be used to produce the at least one first recess . In some aspects , deep reactive ion etching ( DRIE ) is used to etch through the first patterned dielectric mask and the underlying first semiconductor substrate . The etch may be performed as a multi-step dry etch, with different etching steps for removal of dielectric material and removal of material of the first semiconductor substrate .

[0053] In some aspects of the proposed method, provision of the at least one first recess involves an initial dry etch configured to stop at an upper surface of the interconnection layer . Thereafter , the first dielectric layer is deposited on the first surface of the first semiconductor substrate and along the sidewalls and bottom of the at least one first recess . Any suitable deposition process may be used to deposit the first dielectric layer . Examples of suitable processes include but are not limited to chemical vapor deposition ( CVD) , physical vapor deposition ( PVD ) , atomic layer deposition (ALD) . In an exemplary aspect , the first dielectric layer comprises Tetraethyl Orthosilicate (TEOS ) and / or undoped silicate glass (USG ) deposited by CVD . The thickness of the first dielectric layer is configured based on material properties and surface characteristics of the first semiconductor substrate . It is particularly beneficial to configure the thickness of the first dielectric layer to account for variations in bulk mode defects present in the first semiconductor substrate .

[0054] Thereafter , a patterned dielectric mask is deposited on the first dielectric layer , extending laterally over the first surface of the first semiconductor substrate and covering the at least one first recess . The patterned dielectric mas k optionally comprises at least one spacer opening, exposing a surface of the first dielectric layer . Subsequently, a pre-etch is performed to partially remove material of the first dielectric layer through the at least one spacer opening , wherein a residual thickness of the first dielectric layer within the at least one spacer opening is configured to correspond to a distance 2024PF01477 between at least one of the plurality of electrical contacts m the interconnection layer and an upper surface of the first dielectric layer deposited on the bottom surface of the at least one first recess . The patterned dielectric mask is subsequently removed, and an anisotropic etch is performed to remove material of the first dielectric layer within the at least one recess and the at least one spacer opening, such that a bottom surface of the at least one recess is formed by at least one electrical contact in the interconnection layer . In some aspects , material of the first semiconductor substrate is exposed within the at least one spacer opening during the anisotropic etch .

[0055] At least some of the plurality of electrical contacts may comprise a sublayer structure with at least two sublayers , in particular , comprising two different conductive materials . Some such aspects are characterized by a topmost sublayer comprising a thickness substantially lower than the thickness of an underlying second layer . In one non-limiting exemplary configuration, at least some of the plurality of electrical contacts are characterized by a topmost sublayer comprising TiN, a second sublayer with a thickness greater than the topmost sublayer and comprising an alloy of Al and Cu, and a third sublayer with a lower thickness than the second sublayer, and comprising one of Ti or TiN . In some such aspects , the depth of the at least one first recess is configured such that the sidewalls of the at least one first recess are in contact with at least two topmost sublayers of the at least two sublayers . Implementation of the spacer- assisted etching process as described is particularly beneficial for arrangements comprising electrical contacts with a sublayer structure , as the etching depth can be precisely controlled to minimize loss of contact material underlying the topmost sublayer .

[0056] The described process steps for providing the at least one first recess may be applied to provide at least one second recess within the second semiconductor substrate . Such a configuration with through-silicon vias originating from opposite sides of the optoelectronic arrangement increases flexibility in terms of available access points for different processes during manufacturing , testing and / or operation . In some 2024PF01477 16 configurations , at least one first recess and at least one second recess comprise bottom surfaces formed by opposite surfaces of a common one of the plurality of electrical contacts . In other aspects , at least one first recess and at least one second recess comprise bottom surfaces formed by different electrical contacts , which may be electrically connected, for example , through vias in the interconnection layer, or may be electrically isolated from each other .

[0057] Further aspects of the proposed method relate to further processing of the at least one first recess and provision of a first electrical contact layer, serving as a redistribution layer , and a second electrical contact layer configured to provide an electrical connection from at least one contact pad in the first electrical contact layer to the first semiconductor substrate .

[0058] In some aspects , in particular wherein the second contact layer is characterized by a third recess extending from the first semiconductor substrate , a patterned mas k, in particular, an overcoated photoresist layer, is arranged adj acent to the first surface of the first semiconductor substrate , covering the first dielectric layer on the first surface and extending over the at least one first recess and the optional at least one spacer opening . The patterning is configured to provide at least one opening laterally distanced from the at least one first recess , and optionally, from the optoelectronic sensor . In some aspects , the at least one opening is laterally aligned to at least one of the plurality of electrical contacts in the interconnection layer .

[0059] An etch process is subsequently conducted to form the at least one third recess in the material of the first semiconductor substrate . In some aspects , the depth of the at least one third recess is configured such that a bottom surface of the at least one third recess is formed by material of the first semiconductor substrate . In particular , the depth of the at least one third recess in such aspects is substantially smaller than the thickness of the first semiconductor substrate . Control of the etching depth may in such aspects be achieved by configuring the lateral cross-section of the opening in the patterned mask corresponding to the at least one third recess to be significantly 2024PF01477 smaller than the lateral cross-section of the at least one f rst recess . During the etch process , particularly during a DRIE process , the smaller diameter of the opening results in termination of the etching process within the bulk semiconductor substrate material .

[0060] In aspects where a connection between the first semiconductor substrate and the interconnection layer is desired, the etching process is configured such that the at least one third recess extends through the first semiconductor substrate and partially into the interconnection layer, so that a bottom surface of the third recess is formed by at least one of the plurality of electrical contacts in the interconnection layer . In particular , in aspects wherein the at least one of the plurality of contacts comprises a sublayer structure with at least two sublayers arranged in a stacked configuration, the bottom surface of the third recess is preferably formed by a second sublayer arranged underneath a topmost sublayer .

[0061] Thereafter , the patterned dielectric mas k is removed, and a first electrically conductive layer is deposited to cover the first dielectric layer along the first surface of the first semiconductor substrate and on the sidewalls of the at least one first recess , the first electrically conductive layer further extending to cover surfaces of the at least one third recess and the optional at least one spacer opening .

[0062] Along the sidewalls of the at least one first recess , the first electrically conductive layer is isolated from the first semiconductor substrate by the first dielectric layer . In contrast , within the at least one third recess and the optional at least one spacer opening , the first electrically conductive layer is electrically connected to the first semiconductor substrate . Furthermore , the first electrically conductive layer is arranged in contact with the at least one of the plurality of electricals contact forming the bottom of the at least one first recess and optionally forming the bottom of the at least one third recess . 2024PF01477

[0063] The first electrically conductive layer comprises at least one of Ti , TiN and / or W . The deposition method is dependent on material characteristics and desired layer thickness . In some exemplary aspects , CVD is used for deposition of TiN and / or W . In aspects comprising Ti , physical vapor deposition ( PVD) may be employed to form the first electrically conductive layer .

[0064] A dry etch process is carried out to remove material of the first electrically conductive layer adj acent to the first surface of the first semiconductor substrate , such that the first dielectric layer deposited on the first surface and optionally, material of the first semiconductor substrate within the at least one spacer opening is exposed . The etching process is configured to selectively remove material from an upper surface of the optoelectronic arrangement , such that surfaces within the at least one first recess , the at least one third recess and the at least one spacer opening retain the deposited first electrically conductive layer .

[0065] In a subsequent step , a first electrical contact layer is deposited on the upper surface adj acent to the first surface of the first semiconductor substrate , covering the first dielectric layer and surfaces of the optional at least one spacer opening . The first electrical contact layer serves as a redistribution layer and additionally provides contact pads for electrical connection of the optoelectronic arrangement , in particular , during flip chip mounting of the optoelectronic arrangement onto printed circuit boards . In some aspects , the first electrical contact layer is deposited to partially extend into the at least one first recess and the at least one third recess , such that the first electrically conductive layer is at least partially covered by material of the first electrical contact layer . This allows sufficient overlap between the first electrical contact layer and the first electrically conductive layer .

[0066] The first electrical contact layer may comprise any suitable electrically conductive material . In particular, alloys comprising at least one of Al and / or Cu display characteristics favourable to formation of a redistribution layer . 2024PF01477 19

[0067] In some aspects , the first electrical contact layer is patterned and structured to form at least one contact pad . The at least one first contact pad is electrically connected to the at least one third recess . The structuring additionally serves in some aspects to electrically isolate the at least one third recess from the at least one first recess . In other aspects , a second electrical contact layer providing an electrical connection to the first semiconductor substrate is formed by material of the first electrical contact layer within the at least one spacer opening . The at least one contact pad is electrically connected to the at least one spacer opening by material of the first electrical contact layer . In such aspects , process steps relating to the formation of the at least one third recess may be left out .

[0068] Thereafter , a passivation layer is deposited on the first electrical contact layer and on the first electrically conductive layer within the at least one first and the at least one third recess . The passivation layer may comprise at least one of Si02 and / or Si3N4 , and is in some aspects deposited through a CVD process employing a precursor comprising TEOS . In an exemplary aspect , the passivation layer comprises a first sublayer with a thickness substantially equal to 1pm and a second sublayer with a similar thickness , wherein the first sublayer and the second sublayer comprise different materials , in particular , wherein the first sublayer comprises SiO2and the second sublayer comprises Si3N4.

[0069] The described processes relating to the processing of the first and optional third recesses may be mirrored on the second semiconductor substrate for processing the at least one second recess , an optional fourth recess and / or for providing a third electrical contact layer which serves as a redistribution layer arranged adj acent to a surface of the second semiconductor substrate facing away from the first semiconductor substrate . However, the third electrical contact layer is required to be transparent within wavelengths forming an operating range of the at least one optoelectronic sensor, as the third electrical contact layer is arranged facing the sensing surface of the at least one optoelectronic sensor . Suitable material includes transparent conductive oxides , in particular , ITO . Optionally, a fourth electrical 2024PF01477 20 contact layer may be provided for provision of an electrical connection to the second semiconductor substrate . The fourth electrical contact layer is in some aspects formed in a process including formation of at least one fourth recess configured in a similar fashion to the at least one third recess described herein .

[0070] Some aspects of the proposed method relate to provision of optical elements associated with the at least one optoelectronic sensor, in particular at least one of an interference filter and / or a DBR layer .

[0071] In some aspects wherein the at least one optoelectronic sensor is embedded within the first semiconductor substrate , in particular , corresponding to a frontside illumination configuration, a first step involves providing an adhesive layer configured to temporarily bond a second handling wafer adj acent to a surface of the first semiconductor substrate , facing away from the first handling wafer . The first handling wafer is then removed, preferably in a two-step process wherein the first handling wafer is thinned down, in particular , to a thickness of approximately 20 m, followed by wet etching of the remaining substrate material such that the interconnection layer or optionally, a bond interface previously formed during bonding of the first handling wafer to the interconnect layer is exposed .

[0072] A patterned mas k is deposited on the interconnect layer, in particular , being configured to at least partially overlap with a proj ection of the at least one optoelectronic sensor onto the surface of the interconnect layer . The interference filter and / or DBR layer is deposited onto the exposed surface . The configuration of the filter and / or DBR layer is dependent on desired optical characteristics , and in some aspects involves multiple deposition cycles , depending on the number of filter and / or DBR layers required . The patterned mask is thereafter removed . Subsequently, the second handling wafer is removed, for example , through a thermal slide-off process . In some aspects , the optoelectronic arrangement is mounted on a tape and frame structure for further processing, including but not limited to under-bump metallization and deposition of solder bumps for subsequent mounting . 2024PF01477 21

[0073] In aspects wherein the at least one optoelectronic sensor is embedded within the second semiconductor substrate , in particular, corresponding to a backside illumination configuration, the deposition of the at least one interference filter and / or DBR layer involves depositing a patterned mas k on the passivation layer covering the second semiconductor substrate , followed by deposition of the required filter and / or DBR layers . In some aspects , the deposition of the at least one interference filter on the surface of the second semiconductor substrate takes place before deposition of the transparent third electrical contact layer, such that an upper surface of the at least one interference filter and / or DBR layer comprises material of the third electrical contact layer .

[0074] SHORT DESCRIPTION OF THE DRAWINGS

[0075] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0076] Figure 1 shows an optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0077] Figure 2 illustrates a magnified section of part of the optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0078] Figures 3A to 3C show some configurations for provision of electrical connection to a semiconductor substrate according to some aspects of the proposed principle ;

[0079] Figures 4A to 4L illustrate steps in the processing of an optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0080] Figures 5A to 5C illustrate steps in deposition of an interference layer during processing of an optoelectronic arrangement in accordance with some aspects of the proposed principle .

[0081] DETAILED DESCRIPTION 2024PF01477

[0082] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention. Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea.

[0083] In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct. Some aspects are highlighted by showing them enlarged. However, terms such as "above", "over", "below", "under" "larger", "smaller" and the like are correctly represented with regard to the elements in the figures. So it is possible to deduce such relations between the elements based on the figures .

[0084] Figure 1 illustrates an exemplary optoelectronic arrangement processed according to some aspects of the proposed invention. The optoelectronic arrangement comprises a first semiconductor substrate (100) having a first surface and a second surface opposite the first surface.

[0085] An interconnection layer (110) is arranged on the second surface of the first semiconductor substrate (100) . The interconnection layer comprises a plurality of electrical contacts (114, 114' ) embedded within a dielectric material (112) .

[0086] The optoelectronic arrangement further comprises an optoelectronic sensor (102) arranged on a surface of the interconnection layer (110) and electrically connected to a first one of the plurality of electrical contacts (114' ) . The optoelectronic sensor (102) comprises a sensing surface (102' ) which faces away from the first surface of the first 2024PF01477 semiconductor substrate (100) and is configured to detect and / or measure electromagnetic radiation.

[0087] An interference filter (120) is arranged on the surface of the interconnection layer in front of the optoelectronic sensor (102) , being located along a path of incident radiation, such that the filter at least partially overlaps a projection of the sensing surface onto the interconnecting layer.

[0088] At least one first recess (130) is provided through the first semiconductor substrate, said first recess (130) extending partially through the interconnection layer (110) such that a bottom of the first recess (130) is formed by a second one of the plurality of electrical contacts (114) within the interconnection layer. The first recess (130) comprises a first electrically conductive layer (105) along its sidewalls, which is electrically isolated from material of the first semiconductor substrate (100) by a first dielectric layer (104) . The first dielectric layer additionally covers the first surface of the first semiconductor substrate.

[0089] A first electrical contact layer (106) comprising at least one contact pad (108) is arranged adjacent to the first surface of the first semiconductor substrate, forming a redistribution layer. The first electrically conductive layer (105) forms an electrical connection between the at least one contact pad (108) and one of the plurality of electrical contacts (114) in the interconnection layer (110) .

[0090] The optoelectronic arrangement further comprises a second electrical contact layer formed by a third recess (140) comprising material of the first electrically conductive layer (105) along the sidewalls. The first electrically conductive layer (105) forms an electrical connection to the first semiconductor substrate (100) along the sidewalls of the third recess and is additionally connected to at least one contact pad (not shown) formed within the first electrical contact layer . 2024PF01477 24

[0091] In the illustrated aspect, the second electrical contact layer is further electrically connected to one of the plurality of contacts (114) within the interconnection layer (110) , thereby enabling regulation of the electrical potential of the first semiconductor substrate (100) through control circuitry within or connected to the interconnection layer (110) .

[0092] An alternative configuration of the second electrical contact layer is additionally illustrated in Figure 1, wherein contact to the first semiconductor substrate (100) is achieved through at least one spacer opening (141) in the first dielectric layer (104) , allowing an electrical connection between the first semiconductor substrate (100) and a contact pad (108) formed on the first electrical contact layer (106) .

[0093] To allow ease of transfer for further processing, the illustrated optoelectronic arrangement is arranged on a tape (30) and frame (32) structure such that the at least one contact pad (108) in the first contact layer remains accessible for post processing, including but not limited to deposition of under bump metallization layers and provision of solder bumps, in particular, for flip chip mounting.

[0094] The electrical connection between the first electrically conductive layer and the at least one of the plurality of electrical contacts is shown in a magnified view in Figure 2. In some aspects of the proposed invention, at least some of the plurality of electrical contacts comprise a sublayer structure, wherein at least two sublayers (114a, 114b, 114c) , preferably comprising different conductive materials, are arranged in a stacked structure. The first electrically conductive layer (105) is arranged within the third recess (140) such that contact is made between the first electrically conductive layer and at least two topmost sublayers (114a, 114b) of the sublayer structure.

[0095] Figures 3A to 3C illustrate aspects of the proposed optoelectronic arrangement comprising a first semiconductor substrate (200) corresponding to a permanently bonded carrier wafer and a second semiconductor substrate (100) associated with the device wafer. The first and second semiconductor substrates (200, 100) are arranged on 2024PF01477 opposite surfaces of an interconnection layer (110) . The first semiconductor substrate comprises a first surface and a second surface, with the second surface forming an interface with the interconnection layer ( 110 ) .

[0096] At least one first recess (130) is provided in the first semiconductor substrate (200) , extending partially into the interconnection layer (110) such that at least one electrical contact (114) in the interconnection layer forms a bottom of the at least one first recess (130) . The at least one first recess (130) comprises the first electrically conductive layer (105) , which forms an electrical connection between the first semiconductor substrate (100) , at least one of a plurality of electrical contacts (114) in the interconnection layer (110) and the first electrical contact layer (106) . Solder bumps (160) connected to contact pads on the first electrical contact layer (106) are provided for mounting the optoelectronic arrangement, in particular, in a flip chip configuration.

[0097] The second semiconductor substrate (100) comprises similarly configured structures, including a third contact layer (109) and a fourth contact layer providing an electrical connection to the second semiconductor substrate (100) , said fourth contact layer comprising a second recess (142) with sidewalls comprising a second electrically conductive layer. A second passivation layer is provided on the surface of the semiconductor substrate with at least one spacer opening (141) provided through the passivation layer to allow access to the second semiconductor substrate from the surface facing away from the first semiconductor substrate, in particular after the optoelectronic arrangement has been mounted to a circuit board using the provided solder bumps (160) .

[0098] The interconnection layer in the illustrated aspects comprises a plurality of electrical contacts (114) which are structured in a stacked multilevel configuration (114 1 to 114 N) , with an interlayer dielectric separating adjacent levels. Vias (115) formed within the interconnection layer connect multiple levels of electrical contacts such that a plurality of contact stacks is provided within the 2024PF01477 26 interconnection layer . In some aspects , as illustrated, an electrical connection is provided through a via ( 115 ) connecting the second semiconductor substrate ( 100 ) and an electrical contact ( 114 1 ) arranged at the lowest level of a multilevel stack, that is , at a distance closest to the second semiconductor substrate . A topmost electrical contact ( 114 N) of the same multilevel stack is connected through the first electrically conductive layer ( 105 ) to the first semiconductor substrate ( 200 ) . Such a configuration allows regulating the electrical potential in both the first and second semiconductor substrates relative to each other, thereby improving reliability of electrical characteristics within the optoelectronic arrangement .

[0099] Figure 3B illustrates an alternative implementation of the second contact layer for provision of an electrical connection to the first semiconductor substrate ( 200 ) . In the exemplary aspect illustrated, a third recess ( 140 ) is provided from the first surface of the first semiconductor substrate , wherein the depth of the third recess ( 140 ) is less than the thickness of the first semiconductor substrate . As a result , the bottom surface of the third recess is formed by material of the first semiconductor substrate ( 200 ) . The third recess comprises the first electrically conductive layer ( 105 ) along the sidewalls , forming an electrical connection to the first semiconductor substrate . The first electrically conductive layer is further connected to a contact pad formed on the first electrical contact layer ( 106 ) . The lateral cross-section of the third recess ( 140 ) is significantly smaller than the lateral cross-section of the first recess ( 130 ) . The reduced lateral dimension allows formation of the third recess through a self-terminating etch process , in particular, through a DRIE process . Variation of the lateral cross-section of the first and third recess allows use of a common etching process to provide both the first and the third recess while achieving the desired difference in etching depth .

[0100] Figure 3C illustrates another implementation of the second contact layer according to some aspects of the proposed invention . In these aspects , the second contact layer is provided within an opening ( 141 ) in the first dielectric layer arranged on the first surface of the 2024PF01477 first semiconductor substrate (200) , through which material of the first contact layer (106) contacts the first semiconductor substrate, forming an electrical connection to a contact pad within the first contact layer.

[0101] Figures 4A to 4L illustrate steps in a method of processing an optoelectronic arrangement according to some aspects of the proposed principle .

[0102] As shown in Figure 4A, a device wafer (10) comprising a first semiconductor substrate (100) with an initial thickness t0, an optoelectronic sensor (102) and an interconnection layer (110) is provided. The interconnection layer comprises a plurality of electrical contacts (114) embedded within a dielectric material (112) . A first handling wafer (300) is bonded onto the interconnection layer (110) , in particular, through a fusion bonding process.

[0103] In a subsequent step, illustrated in Figure 4B, the arrangement is flipped, and the first semiconductor substrate (100) is thinned down to a thickness t, wherein t is, for example, approximately equal to 200 pm. A dielectric mask layer (103) , in particular, comprising an oxide such as SiO2, is deposited on the surface of the first semiconductor layer (100) . Alignment marks (103' ) are provided within the dielectric mask layer, facilitating localization of at least some of the plurality of electrical contacts within the interconnection layer with respect to the surface of the first semiconductor substrate.

[0104] Thereafter, as shown in Figure 4C, an initial etch is performed to produce at least one first recess (130) through the first semiconductor substrate, with the etching process configured to terminate at the interface between the interconnection layer (110) and the first semiconductor substrate (100) . A first dielectric layer (104) is thereafter deposited on the surface of the first semiconductor substrate and within the at least one first recess, as illustrated in Figure 4D. The thickness of the first dielectric layer is configured to mitigate variations in bulk mode defect density within the first 2024PF01477 28 semiconductor substrate, which influences the roughness of the etched sidewalls of the at least one first recess .

[0105] Next, a patterned dielectric mask (400) , in particular, a photoresist mask layer is deposited on the first dielectric layer (104) , as illustrated in Figure 4E. The patterned dielectric mask is preferably formed through an overcoating process, though any suitable deposition techniques may be employed. The patterned dielectric mask (400) comprises at least one spacer opening (141) , which serves to facilitate improved etching depth accuracy. A pre-etch is performed, resulting in removal of material of the first dielectric layer (104) within the spacer opening. The patterned dielectric mask is subsequently removed. In processes wherein a photoresist mask was used, standard lithographic removal processes are employed.

[0106] The depth of etching and the corresponding residual thickness of the first dielectric layer (106) within the spacer opening (141) correspond to a desired etching depth within the first recess, such that during subsequent etching, in particular, involving an anisotropic etching process, illustrated in Figure 4F, the process can be accurately terminated when a surface of at least one of the plurality of electrical contacts (114) is reached and optionally, partially removed to expose material of an underlying second sublayer. Within the at least one spacer opening (141) , material of the first semiconductor substrate (100) is exposed during the subsequent etching process. The spacer opening can thereafter be advantageously configured to provide contact to the first semiconductor substrate.

[0107] In a subsequent step, shown in Figure 4G, a second patterned dielectric mask (400' ) is deposited on the surface of the first dielectric layer (106) , covering the at least one first recess (130) . An overcoating process similar to that employed during deposition of the first patterned dielectric may be used in this process step. An opening is provided within the patterned dielectric mask, laterally adjacent to the at least one first recess. In the exemplary aspect shown, the opening within the patterned dielectric mask is aligned with at least one of the plurality of electrical contacts in the interconnection 2024PF01477 29 layer. In other aspects, not shown herein, the opening may be positioned independently of the structures within the interconnection layer.

[0108] An etching process is carried out to provide a third recess (140) within the first semiconductor substrate (100) . In the exemplary aspect illustrated in Figure 4H, the etching depth is configured such that the third recess extends through the first semiconductor substrate and partly through the interconnection layer (110) , and such that a bottom of the third recess (140) is formed by one of the plurality of contacts (114) in the interconnection layer. The etching process used to provide the third recess is in some aspects configured to be faster, in particular, wherein the second patterned dielectric mask (400' ) comprises an overcoated photoresist, as the stability of the overcoated photoresist is compromised with increase in duration of the etch process. However, for the third recess, the sidewall quality is less critical than for the at least one first recess, thus a faster etch process producing increased defects is an acceptable compromise.

[0109] The second dielectric mask (400' ) is removed, and a first electrically conductive layer (105) comprising at least one of Ti, TiN and / or W is deposited on the upper surface of the optoelectronic arrangement, covering the surface of the first semiconductor substrate and further extending into the first and third recesses (130, 140) as well as the spacer opening (141) to cover the sidewalls and bottom surfaces thereof. As illustrated in Figure 41, the first electrically conductive layer (105) is electrically connected to the first semiconductor substrate (100) along the sidewalls of the third recess (140) and within the spacer opening (141) . In contrast, within the at least one first recess (130) and along the upper surface of the first semiconductor substrate (100) , the first dielectric layer (104) provides electrical isolation between the first semiconductor substrate (100) and the first electrically conductive layer (105) .

[0110] Subsequently, a selective dry etch is performed along the upper surface of the first semiconductor substrate (100) , removing material of the first electrically conductive layer (105) , such that the first dielectric layer (104) is exposed at the surface of the first 2024PF01477 semiconductor substrate (100) , as shown in Figure 4J. The sidewalls of the first and third recesses (130, 140) as well as the sidewalls of the spacer opening (141) retain the deposited first electrically conductive layer (105) . Additionally, the bottom surfaces of the first and third recesses (130, 140) connected to electrical contacts (114) within the interconnection layer (110) may optionally comprise the first electrically conductive layer (105) .

[0111] Thereafter, a first electrical contact layer (106) serving as a redistribution layer is deposited on the upper surface of the first semiconductor substrate (100) . This is illustrated in Figure 4K. In some exemplary aspects, the first electrical contact layer comprises an alloy of Al and Cu. Other materials exhibiting desirable electrical and thermal characteristics may also be employed. The first electrical contact layer is configured to partially extend into the first and third recesses, thus partially covering the first electrically conductive layer (105) . This ensures sufficient contact area between the first electrically conductive layer (105) and the first electrical contact layer (106) . The first electrical contact layer (105) is optionally patterned to form at least one region electrically isolated from other regions within the first electrical contact layer (105) . This may be particularly useful to ensure electrical isolation of contacts associated with the bulk substrate and contacts associated with optoelectronic devices forming the optoelectronic arrangement.

[0112] A subsequent processing step, illustrated in Figure 4L, involves deposition of a passivation layer to cover surfaces of the first electrically conductive layer, the first electrical contact layer and exposed surfaces of the first dielectric layer. The passivation layer is patterned and etched to expose contact pads within the first contact layer .

[0113] Figures 5A to 5C illustrate process steps in provision of an interference filter in accordance with some aspects of the proposed principle. A second handling wafer (500) is arranged opposite the first handling wafer (300) using a temporary adhesive layer. The first handling wafer (300) is mechanically thinned, for example, by 2024PF01477 31 backgrinding to a thickness lower than 50 pm, in particular to a thickness lower than or equal to 20 pm. The residual material is removed through an etch process, in particular, by wet etching, such that the interconnect layer is exposed. Thereafter, a patterned mask is 5 deposited on the interconnect layer, after which an interference filter (120) is deposited thereon. The positioning of the interference filter (120) is such that there is at least partial lateral overlap between the sensing surface of the at least one optoelectronic sensor (102) and the interference filter (120) . In some aspects, multiple filters0 are deposited, requiring multiple deposition cycles. After each cycle of filter deposition, the patterned mask is removed.

[0114] Further processing steps not illustrated herein include debonding of the second handling wafer, in particular through a thermal slide-off5 process, cleaning and inspection, mounting on a tape and frame, deposition of under bump metallization and provision of solder bumps for flip chip mounting.

[0115] 2024PF01477

[0116] LIST OF REFERENCES

[0117] 10 device wafer

[0118] 20 transfer frame

[0119] 30 transfer tape

[0120] 100 first semiconductor substrate

[0121] 102 optoelectronic sensor

[0122] 104 first dielectric layer

[0123] 105 first electrically conductive layer

[0124] 106 first electrical contact layer

[0125] 107 passivation layer

[0126] 108 contact pad

[0127] 109 third electrical contact layer

[0128] 110 interconnection layer

[0129] 112 interlayer dielectric

[0130] 114 electrical contact

[0131] 114a 114b , 114c electrical contact sublayers

[0132] 115 interconnection layer via

[0133] 120 interference filter

[0134] 130 first recess

[0135] 140 , 140 ' third recess

[0136] 141 spacer opening

[0137] 142 second recess

[0138] 160 solder bump

[0139] 200 second semiconductor substrate

[0140] 300 first handling substrate

[0141] 400 , 400 ' patterned dielectric mas k

[0142] 500 second handling substrate

[0143] 510 adhesive layer

Claims

2024PF01477CLAIMS1. Optoelectronic arrangement comprising:• A first semiconductor substrate (200) with a first surface and a second surface opposite the first surface;• An interconnection layer (110) arranged on the second surface, comprising a plurality of electrical contacts (114) at least partially embedded within a dielectric (112) ;• At least one optoelectronic sensor (102) arranged on the interconnection layer (110) and electrically connected to at least one first one of the plurality of electrical contacts (114) , the optoelectronic sensor (102) comprising a sensing surface facing away from the first surface;• At least one first recess (130) from the first surface to the second surface of the first semiconductor substrate (200) towards the second surface, wherein the at least one first recess comprises on its surface a first electrically conductive layer (105) electrically contacting at least one second electrical contact of the plurality of electrical contacts (114) and electrically isolated from material of the first semiconductor substrate (200) adjacent to the at least one first recess (130) , and wherein the first electrically conductive layer optionally forms a bottom of the recess;• At least one first electrical contact layer (106) arranged on the first surface, said first electrical contact layer contacting the first electrically conductive layer (105) , and comprising at least one contact pad (108) ;• At least one second electrical contact layer (140) electrically connecting material of the first semiconductor substrate (200) to at least one further contact pad (108) .

2. Optoelectronic arrangement according to claim 1,• wherein the at least one optoelectronic sensor is arranged in the first semiconductor substrate, wherein optionally the at least one first recess is laterally displaced from the at least one optoelectronic sensor; or2024PF01477• wherein the optoelectronic arrangement further comprises a second semiconductor substrate arranged on a surface of the interconnection layer opposite the first semiconductor substrate , and wherein the at least one optoelectronic sensor is arranged in the second semiconductor substrate , and wherein optionally the at least one first recess is arranged within a proj ection of the at least one optoelectronic sensor onto the first surface .3 . Optoelectronic arrangement according to claim 2 , further comprising :• at least one second recess from a surface of the second semiconductor substrate facing away from the interconnection layer, wherein the at least one second recess comprises a second electrically conductive layer arranged on its surface , said electrically conductive layer electrically contacting a surface of the at least one second one of the plurality of electrical contacts facing away from the first semiconductor substrate , and optionally forming a bottom of the recess ;• at least one third electrical contact layer arranged on a surface of the second semiconductor substrate facing away from the interconnection layer, wherein the at least one third electrical contact layer is electrically connected to the second electrically conductive layer , and wherein the at least one third contact layer comprises at least one contact pad .4 . Optoelectronic arrangement according to any of the preceding claims , wherein the at least one second electrical contact layer ( 140 ) is formed by material of the first conductive layer ( 105 ) arranged along sidewalls of at least one third recess , said at least one third recess extending from the first surface of the first semiconductor substrate , and wherein :• at least one of the at least one third recess extends partially through the first semiconductor substrate , such that a bottom of the at least one third recess is formed within the first semiconductor substrate ; and / or2024PF01477• at least one of the at least one third recess extends through the first semiconductor substrate and partially through the interconnection layer , such that a bottom of the at least one third recess is formed by at least one second one of the plurality of electrical contacts .5 . Arrangement according to any of the preceding claims , further comprising :• a first dielectric layer arranged on the first surface of the first semiconductor substrate and along the sidewalls of the at least one first recess , isolating the first semiconductor substrate from the first electrically conductive layer and from the first electrical contact layer ; and / or• a second dielectric layer arranged on a surface of the second semiconductor substrate , isolating the second semiconductor substrate from the second electrically conductive layer and from the third electrical contact layer .6 . Arrangement according to any of claims 3 to 5 wherein at least one of the first electrical contact layer and / or the third electrical contact layer comprises a transparent conductive oxide , in particular, ITO .7 . Optoelectronic arrangement according to any of the preceding claims , wherein• the first electrically conductive layer comprises at least one of Tungsten (W) , Titanium (Ti ) and Titanium nitride ( TiN) ; and / or• a material of the first electrically conductive layer is different from a material of the first electrical contact layer ; and / or• the first electrical contact layer comprises an alloy comprising one of Al and Cu .8 . Optoelectronic arrangement according to any of the preceding claims , wherein at least the one second of the plurality of electrical contacts in the interconnection layer comprises a sublayer structure2024PF01477 with at least two sublayers stacked on each other , and wherein the first electrically conductive layer contacts at least the two topmost of the at least two sublayers .9 . Optoelectronic arrangement according to any of the preceding claims , further comprising one of a DBR structure and / or a filter located above the sensing surface , and arranged on one of :• A surface of the interconnection layer facing away from the first semiconductor substrate ;• Adj acent to a surface of the second semiconductor substrate facing away from the first semiconductor substrate .10 . Optoelectronic arrangement according to any of claims 3 to 9 , wherein the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other through the interconnection layer .11 . Use of an optoelectronic arrangement according to any of the preceding claims to determine and / or monitor at least one electrical characteristic of the first and / or second semiconductor substrate , in particular, an electrical potential through the second electrical contact ( 140 ) .12 . Use of an optoelectronic arrangement according to any of the preceding claims to maintain the first semiconductor substrate at a predetermined electrical potential through the second electrical contact ( 140 ) .13 . Method of processing an optoelectronic arrangement , comprising the steps :• Providing an optoelectronic arrangement comprising : o a first semiconductor substrate with a first surface and a second surface opposite the first surface ; o an interconnection layer comprising a plurality of electrical contacts at least partially embedded within a dielectric and arranged on the second surface ; o At least one optoelectronic sensor arranged on the interconnection layer and electrically connected to at2024PF01477 least one first one of the plurality of electrical contacts , the at least one optoelectronic sensor comprising a sensing surface facing away from the first surface of the first semiconductor substrate ;• Providing at least one first recess extending from the first surface of the first semiconductor substrate , wherein the sidewalls of the at least one first recess are covered by a dielectric material and wherein a bottom of the at least one first recess is formed by at least one second one of the plurality of electrical contacts in the interconnection layer ;• Arranging a first electrically conductive layer on sidewalls of the at least one first recess , said first electrically conductive layer forming an electrical connection to the at least one second one of the plurality of electrical contacts ;• Depositing a first electrical contact layer ( 106 ) on the first surface of the first semiconductor substrate , said first electrical contact layer ( 106 ) contacting the first conductive layer and comprising at least one contact pad;• Forming at least one second electrical contact layer, said second electrical contact layer electrically contacting the first semiconductor substrate to the first electrical contact layer ( 106 ) .14 . Method according to claim 13 , further comprising a step of providing a handling substrate arranged on a surface of the interconnection layer facing away from the first semiconductor substrate .15 . Method according to claim 13 or 14 , wherein the step of providing an optoelectronic arrangement further comprises a step of thinning and / or planarizing the first semiconductor substrate .16 . Method according to any of claims 13 to 15 , wherein the step of forming the at least one first recess comprises the steps :• Depositing a patterned mask on the first surface of the first semiconductor substrate ;• Etching through material of the first semiconductor substrate at least to a depth corresponding to a surface of at least2024PF01477 one second electrical contact within the interconnection layer .17 . Method according to any of claims 13 to 16 , wherein the step of etching through material of the first semiconductor substrate comprises the steps :• Performing a first etch through the patterned mas k and material of the first semiconductor substrate , wherein the etching depth is configured to correspond to an upper surface of the interconnection layer facing the first semiconductor substrate ;• Depositing a first dielectric material on the first surface of the first semiconductor substrate and within the first recess ;• Depositing a patterned dielectric mask on the first dielectric material , said dielectric mask extending over the at least one first recess , and comprising at least one spacer opening ( 141 ) at a lateral distance from the at least one first recess ;• Etching through the patterned dielectric mask such that a thickness of the first dielectric material within the at least one spacer opening remaining after the etching process corresponds to at least a distance between a surface of a second one of the plurality of electrical contacts within the interconnection layer and a bottom surface of the at least one first recess formed by the first dielectric material ;• Removing the patterned dielectric mas k;• Etching through the first dielectric material and the first semiconductor substrate such that a surface of the at least one second electrical contact is exposed within the at least one first recess .18 . Method according to any of claims 13 to 17 , wherein the at least one second electrical contact of the plurality of electrical contacts comprises a sublayer structure with at least two sublayers stacked on each other, and wherein the step of providing the at least one first recess involves etching through at least one topmost layer of the at least two sublayers such that a bottom of the at2024PF01477 least one first recess is formed by at least a second one of the at least two sublayers .19 . Method according to any of claims 13 to 18 , wherein the step of arranging a first electrically conductive layer within the at least one first recess involves depositing an electrically conductive material , in particular , at least one of tungsten (W) , titanium nitride (TiN ) and titanium ( Ti ) , on the sidewalls and optionally the bottom surface of the at least one first recess .20 . Method according to any of claims 13 to 19 , wherein the step of forming at least one second electrical contact layer comprises at least one of :• Arranging the first electrical contact layer ( 106 ) on the first surface of the first semiconductor substrate through an opening in the first dielectric layer , optionally through the spacer opening ( 141 ) ; and / or• Providing at least one third recess extending partially through the first semiconductor substrate , and arranging the first conductive layer at least along the sidewalls and optionally on the bottom surface of the at least one third recess ; and / or• Providing at least one third recess extending through the first semiconductor substrate and at least partially through the interconnection layer , such that a bottom of the at least one third recess is formed by at least one of the plurality of electrical contacts , and arranging the first conductive layer at least along the sidewalls and optionally on the bottom surface of the at least one third recess .21 . Method according to any of claims 14 to 20 , wherein the handling substrate forms a second semiconductor substrate , and further comprising the steps :• Providing at least one second recess through the second semiconductor substrate , wherein the at least one second recess is processed in a similar manner to the at least one first recess to form a second electrically conductive layer along the sidewalls , said second electrically conductive layer2024PF01477 being electrically isolated from the second semiconductor substrate ;• Arranging a third electrical contact layer adj acent to the surface of the second semiconductor substrate facing away from5 the first semiconductor substrate , wherein the third electrical contact layer is electrically connected to the second electrically conductive layer .22 . Method according to claim 21 , further comprising a step of forming0 at least one fourth electrical contact layer , said fourth electrical contact layer electrically contacting the second semiconductor substrate to the third electrical contact layer .23 . Method according to claim 22 , wherein the at least one fourth5 electrical contact layer is electrically connected to the at least one second electrically contact layer, such that the first semiconductor substrate and the second semiconductor substrate are electrically connected to each other . 0

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