A dynamic low-power auto-controlled zero-crossing detector

Abstract

The present disclosure provides a dynamic low-power auto-controlled zero-crossing detector (ZCD) (102) for a power converter. The ZCD (102) includes a slow comparator (116) configured to be constantly ON, for generating a signal based on an input signal approaching a predetermined reference value. A latch (122) is operatively connected to the slow comparator (116) and configured to be set based on the signal generated by the slow comparator (116). A fast comparator (118) is operatively connected to the latch (122) and activated for generating a zero-crossing detection signal based on an output (Q) of the latch (122) being high. A feedback mechanism (128) is operatively connected between the fast comparator (118) and the latch (122) and configured for receiving the zero-crossing detection signal from the fast comparator (118) for resetting the latch (122) and switching off the fast comparator (118).

Description

A DYNAMIC LOW-POWER AUTO-CONTROLLED ZERO-CROSSING DETECTORTECHNICAL FIELD

[0001] The embodiments of the present disclosure generally relate to a field of zerocrossing detector circuits. More particularly, the present disclosure relates to a dynamic low- power auto-controlled zero-crossing detector.BACKGROUND

[0002] The following description of the related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section is used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of the prior art.

[0003] A zero-crossing detector is an electronic circuit that identifies when an input signal crosses a zero-voltage level, which is a point where the signal changes polarity from positive to negative or vice versa. The zero-crossing detectors are commonly used in various applications including, without limitation, Phase-Locked Loops (PLLs) to provide a reference signal for synchronization, signal processing units to detect a timing of signals in digital signal processing, an Alternating Current (AC) power control systems to synchronize with AC mains for controlling power devices, and a frequency measurement devices to measure a frequency of the input signal by counting zero crossings over a specific period.

[0004] Current technologies use high power static comparators for precise zerocrossing detection which in turn causes large power dissipation when not in use. Further, current technologies use very high frequency clocked comparators to satisfy the requirement of speed and power, but utilize an additional circuitry to generate a high-speed clock not suitable for low bandwidth applications. Further, current systems provide low power with low speed detection and include losses related to delays in signal generation.

[0005] Therefore, there is, a need for an efficient zero-crossing detector (ZCD) that minimizes the power consumption by overcoming the deficiencies in the prior art(s).OBJECTS OF THE PRESENT DISCLOSURE

[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are listed herein below.

[0007] It is an object of the present disclosure to provide a dynamic low-power autocontrolled zero-crossing detector (ZCD) that enables fast zero-crossing detection when needed, thereby reducing default power consumptions.

[0008] It is an object of the present disclosure to provide a ZCD that includes a slow comparator for generating a signal based on an input signal approaching a predetermined reference value, where a latch with a reset mechanism is connected to the slow comparator and configured to be set based on the signal generated by the slow comparator.

[0009] It is an object of the present disclosure to provide a ZCD that includes a fast comparator that is activated upon connection to the latch with the reset mechanism for generating a zero-crossing detection signal based on an output of the latch with the reset mechanism being high.

[0010] It is an object of the present disclosure to provide a ZCD where the fast comparator turns itself off once the zero-crossing detection signal is detected, thereby reducing effective power consumed at every detection cycle.SUMMARY

[0011] This section is provided to introduce certain objects and aspects of the present disclosure in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter.

[0012] In an aspect, the present disclosure relates to a dynamic low-power autocontrolled zero-crossing detector for a power converter. The zero-crossing detector includes a slow comparator configured to be constantly ON, for generating a signal based on an input signal approaching a predetermined reference value (Vths). A latch operatively connected to the slow comparator and configured to be set based on the signal generated by the slow comparator. A fast comparator operatively connected to the latch, and activated for generating a zero-crossing detection signal based on an output (Q) of the latch being high. A feedback mechanism operatively connected between the fast comparator and the latch, and configured for receiving the zero-crossing detection signal from the fast comparator for resetting the latch and switching off the fast comparator.

[0013] In an embodiment, the slow comparator may be configured to generate a high- level signal to set the latch when the input signal transitions from a positive value to a negative value within a specified threshold range (Vths).

[0014] In an embodiment, the fast comparator may be configured to generate a short timed high signal when the input signal transitioning from the negative value to the positive value crosses a zero-crossing threshold value (Vthf) that may be configured to be zero.

[0015] In an embodiment, the feedback mechanism may be configured to receive the short timed high signal from the fast comparator to reset the latch and switch off the fast comparator.

[0016] In an embodiment, the slow comparator may be configured to continuously monitor the input signal for subsequent zero crossing cycles after switching off the fast comparator.

[0017] In an embodiment, the fast comparator may be configured to digitally adjust an offset for precise control of a zero-crossing threshold value (Vthf) using trimming techniques.

[0018] In an embodiment, the ZCD may include a level shifter operatively connected with the slow comparator and the fast comparator, and configured to shift a voltage level of the input signal to a voltage level of a ground and a threshold voltage of a P-channel Metal- Oxide-Semiconductor (PMOS) transistor.

[0019] In an embodiment, the latch may be a flip-flop including a reset mechanism.

[0020] In an aspect, the present disclosure relates to a method for detecting zerocrossing in a signal using a dynamic low-power auto-controlled zero-crossing detector. The method includes continuously monitoring an input signal in a power converter by a slow comparator of the zero-crossing detector. The method includes generating a signal by the slow comparator, when the input signal approaches a predetermined reference value (Vths). The method includes setting a latch for activating a fast comparator based on the signal. The method includes detecting a zero-crossing in the signal by the fast comparator. The method includes generating a zero-crossing detection signal by the fast comparator based on the detection. The method includes resetting the latch for turning off the fast comparator based on the zero-crossing detection signal.

[0021] In an embodiment, the zero-crossing detection signal generated by the fast comparator may be utilized to optimize power consumption by resetting the latch and turning off the fast comparator immediately after the detection of zero-crossing in the signal.

[0022] In an embodiment, the method may include driving any or a combination of a low side Field-Effect Transistor (FET) of a Direct Current (DC)-DC power converter, a high side FET of a DC-DC boost converter, a synchronous rectifier FET of an Alternating Current (AC)-DC converter, or any logic associated with zero crossing detection, based on an output (Q) of the latch.BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated herein, and constitute a part of this disclosure, illustrate exemplary embodiments of the disclosed methods and systems which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that disclosure of such drawings includes the disclosure of electrical components, electronic components, or circuitry commonly used to implement such components.

[0024] FIG. 1 illustrates an example circuit diagram (100) incorporating a proposed zero-crossing detector (ZCD) (102), in accordance with embodiments of the present disclosure.

[0025] FIG. 2 illustrates an example flow diagram for implementing a method (200) for detecting zero-crossing in a signal using the ZCD (102), in accordance with an embodiment of the present disclosure.

[0026] FIGs. 3A-3D illustrate example implementations (300) of the proposed ZCD (102) with various circuits, in accordance with embodiments of the present disclosure.

[0027] FIGs. 4A-4C illustrate example graphical representations (400) depicting various transient responses observed with the proposed ZCD (102), in accordance with embodiments of the present disclosure.

[0028] The foregoing shall be more apparent from the following more detailed description of the disclosure.DETAILED DESCRIPTION

[0029] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features. An individual feature may not address all of the problems discussed above or might address only some of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein.

[0030] The ensuing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth.

[0031] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0032] The word “exemplary” and / or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and / or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.

[0033] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless thecontext indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0035] The present disclosure describes a zero-crossing detector (ZCD) that detects a transition of an input signal from a positive value to a negative value, and generates a signal when the input signal crosses zero. The ZCD uses two comparators, a slow comparator (e.g., a low-power comparator), and a fast comparator (e.g., a high-power comparator). As the voltage approaches a certain reference value (Vths), the slow comparator generates the signal which sets a Set-Reset (SR) latch and as a result it turns on the fast comparator which is responsible to generate an actual zero-crossing detection signal. The signal generated is setup in such a way that the signal is fed back to reset the SR latch, to disable the fast comparator once the generation of the zero-crossing detection signal is completed. Therefore, the ZCD saves effective power utilized for zero-crossing detection operation by using a precision / high power comparator only when deemed necessary. A trimming method may also be utilized to adjust an offset of the ZCD to adjust a zero-crossing threshold. Further, the ZCD observes a need for high power comparators for precise zero-crossing detection, and only enables fast detection when needed, in turn reducing default power consumption. The ZCD consumes a very low current when not in use, and also may not use a clock for its operation, which reduces any requirement for additional circuitry. The fast comparator is configured to generate the ZCD signal and disable by itself, such that the ZCD system may automatically control its power requirements, via a feedback mechanism, and may not rely on any additional external signals.

[0036] Various embodiments of the present disclosure will be explained in detail with reference to FIGs. 1-4C.

[0037] FIG. 1 illustrates an example circuit diagram (100) incorporating a proposed zero-crossing detector (ZCD) (102), in accordance with embodiments of the present disclosure.

[0038] As illustrated in FIG. 1, in an embodiment, a p-channel metal -oxide semiconductor (pMOS) including one or more transistors (QI (104), Q2 (106), Q3 (108), Q4 (110), Q5 (112), and Q6 (114)) may be electrically coupled to a slow comparator (116) and a fast comparator (118) of a dynamic low power auto-controlled ZCD (102). It may beappreciated that the dynamic low power auto-controlled ZCD (102) may be interchangeably referred to as the ZCD (102) throughout the disclosure. The ZCD (102) may be implemented in, for example, but not limited to, power converters. Further, the ZCD (102) may include a level shifter (120) and a latch (122). The latch (122) may be, for example, without limitation, a Set-Reset (SR) latch. The latch may be any flip-flop including a reset mechanism. The ZCD (102) may be configured to operate with a predetermined supply voltage ranging from, for example, but not limited to, 2.6V to 5V. Further, the ZCD (102) may be configured to perform a critical zero-crossing detection with, for example, but not limited to, a 2 millivolt (mV) threshold within, for example, but not limited to, 25 nano seconds (ns) for an input switching frequency up to, for example, but not limited to, 2 Megahertz (MHz).

[0039] In an embodiment, the ZCD (102) may include inverters cells and trimming cells. The inverter cells may be used to invert an input signal. If the input is high (logical 1), the output may be low (logical 0), and vice versa. This may be essential for certain logical operations within the ZCD (102). The inverter cells may be configured to shape the input signal, ensuring that it has a proper form for further processing stages. The inverter cells may be configured to sharpen the transitions, making it easier to detect the zero crossings accurately.

[0040] In an embodiment, the trimming cells may be configured to fine-tune a performance of the ZCD (102). The trimming cells may allow for adjustments in the circuit parameters to achieve a desired accuracy and stability. Further, the trimming cells may be used to adjust the offset voltage, ensuring that the ZCD (102) triggers accurately at the zerocrossing point. Adjusting the offset voltage may be particularly important in compensating for any mismatches or imperfections in the circuit components of the ZCD (102).

[0041] In an embodiment, the level shifter (120) may be operatively connected to the slow comparator (116). In an embodiment, the level shifter (120) may be operatively connected to the fast comparator (118). The level shifter (120) may be configured to shift a voltage level of the input signal to a voltage level of a ground and a threshold voltage of the pMOS transistor. That is, the level shifter (120) may shift the input signal to Ground + Vt (pMOS) voltage level.

[0042] In an embodiment, GND1 (124) may work as a reference for the fast comparator (116), and GND2 (126) may work as thresholds for the slow comparator (118). Both the slow and fast comparators (116, 118) may be static comparators, however the slow comparator (116) may be always kept ON.

[0043] In an embodiment, the ZCD (102) may be configured to identify the zerocrossing from the negative to positive, which serves as a major requirement for Direct Current (DC)-DC and Alternating Current (AC)-DC converters. Once the input signal (e.g., voltage or current) goes negative, the slow comparator (116) may generate a high signal which may set a Set-Reset (SR) latch (122). The SR latch (122) may be operatively connected to the slow comparator (116). An output of the SR latch (122) may turn on the fast comparator (118) in 40 to 60 ns over process, voltage, and temperature (PVT) variations. The voltage may move towards a positive direction and cross over a threshold of the slow comparator (116) turning its signal low. The SR latch (122) may still hold its previous state and keeps the fast comparator (118) ON when the signal is approaching zero. An offset of the fast comparator (118) or the ZCD threshold (Vthf) may be set by adjusting the reference voltage of the GND1 (124).

[0044] Once the signal crosses zero / threshold of the fast comparator (118), the fast comparator (118) may generate a high signal which is fed to reset the SR latch (122), and the output of the SR latch (122) may go low. For example, but not limited to, the output of the SR latch (122) may be utilized as the ZCD signal. The level shifter (120) may typically use 12 micro amps (uA) of current, and the slow comparator (116) may use 18uA of current. The fast comparator (118) may use 150 to 180uA over PVT only for a desired amount of time. The ZCD (102) may be configured to perform critical zero crossing detection with 2 mV threshold, which may be 25ns over a maximum input switching frequency of 2 MHz.

[0045] In an embodiment, the slow comparator (116) may be configured to be constantly ON, for generating a signal based on the input signal approaching a predetermined reference value. In an embodiment, the SR latch (122) may be operatively connected to the slow comparator (116) and configured to be set based on the signal generated by the slow comparator (116). In an embodiment, the fast comparator (118) may be operatively connected to the SR latch (122) and activated for generating a zero-crossing detection signal based on an output (Q) of the SR latch (122) being high. In an embodiment, a feedback mechanism (128) may be operatively connected between the fast comparator (118) and the SR latch (122). The feedback mechanism (128) may be configured for receiving the zero-crossing detection signal from the fast comparator (122) for resetting the SR latch (122) and switching off the fast comparator (118).

[0046] In an embodiment, the fast comparator (118) may be configured to generate a short timed high signal when the input signal crosses zero. Further, the fast comparator (118) may be configured to digitally adjust the offset for precise control of a zero-crossingthreshold value using trimming techniques. In an embodiment, the feedback mechanism (128) may be configured to receive the short timed high signal from the fast comparator (118) to reset the SR latch (122) and switch off the fast comparator (118). The zero-crossing detection signal generated by the fast comparator (118) may be utilized to optimize power consumption by resetting the SR latch (122) and turning off the fast comparator (118) immediately after the detection of zero-crossing in the signal.

[0047] In an embodiment, the slow comparator (116) may be configured to generate a high-level signal to set the SR latch (122), when the input signal transitions from positive to negative within a specified threshold range. In an embodiment, the slow comparator (116) may be configured to continuously monitor the input signal for subsequent zero-crossing cycles after switching off the fast comparator (118).

[0048] FIG. 2 illustrates an example flow diagram for implementing a method (200) for detecting zero-crossing in a signal using the ZCD (102), in accordance with an embodiment of the present disclosure.

[0049] As illustrated in FIG. 2, the method (200) may include the following steps.

[0050] At step 202: The method (200) may include determining if the input signal has transitioned from a positive value to a negative value crossing a voltage threshold value.

[0051] At step 204: If the input signal has not transitioned from the positive value to the negative value, the method (200) may include monitoring the input signal using the slow comparator (116).

[0052] At step 206: If the input signal has transitioned from the positive value to the negative value crossing the voltage threshold value, the slow comparator (116) may set the SR latch (122).

[0053] At step 208: The ZCD value may be set to 1 by setting the SR latch (122).

[0054] At step 210: The fast comparator (118) may be enabled or activated when the output (Q) of the SR latch (122) is high.

[0055] At step 212: The fast comparator (118) may monitor the input signal.

[0056] At step 214: The method (200) may include determining if the input signal has transitioned from the negative value to the positive value crossing the threshold of the fast comparator (118).

[0057] At step 216: The fast comparator (118) may reset the SR latch (122) based on the determination at step 214.

[0058] At step 218: The ZCD value may be set to zero.

[0059] At step 220: The fast comparator (118) may be turned off and may proceed to step 204 to continue monitoring the input signal using the slow comparator (116).

[0060] FIGs. 3A-3D illustrate example implementations (300A, 300B, 300C, 300D) of the ZCD (102) with various circuits, in accordance with embodiments of the present disclosure.

[0061] As illustrated in FIG. 3 A, in an embodiment, the ZCD (102) may be used to drive the low-side FET along with relevant driver (302) in a DC-DC circuit, for example, but not limited to, a buck converter which steps down the input DC voltage to a lower output DC voltage while maintaining high efficiency.

[0062] As illustrated in FIG. 3B, in an embodiment, the ZCD (102) may be used to drive the SR-FET along with relevant drivers (304) in an AC-DC circuit.

[0063] As illustrated in FIG. 3C, in an embodiment, the slow comparator (306) and the fast comparator (308) may be included in a top-level ZCD circuit.

[0064] As illustrated in FIG. 3D, in an embodiment, the ZCD (102) may be included as a high-side FET control in the DC-DC circuit, for example, but not limited to, a boost converter which steps up the input DC voltage from a lower level to a higher level such that the ZCD (102) may accurately and reliably detect the zero crossings of the input signal. The ZCD (102) may be used to drive the high-side FET of the DC-DC boost converter with a relevant level shifter (310) and a gate drive mechanism suitable to the boost converter while utilizing the logic proposed by the ZCD (102).

[0065] Therefore, the ZCD (102) may include driving any or a combination of a low side Field-Effect Transistor (FET) of a DC-DC power converter, a high side FET of a DC-DC boost converter, a synchronous rectifier FET of an Alternating Current AC-DC converter, or any logic associated with zero crossing detection, based on an output (Q) of the SR latch.

[0066] FIGs. 4A-4C illustrate example graphical representations (400A, 400B, 400C) of various transient responses observed with the ZCD (102), in accordance with embodiments of the present disclosure.

[0067] As illustrated in FIG. 4A, in an embodiment, the ZCD (102) may monitor the input signal using the slow comparator (116). Further, the level shifter (120) may generate the level shifted input signal (SWLS). The slow comparator (116) may generate a signal upon the input voltage nearing a predetermined reference value (Vths), and the SR latch (122) may be set based on the signal generated by the slow comparator (116). The fast comparator (118) may be activated when the output (Q) of the SR latch (122) is high. The fast comparator (118) may be activated for generating the zero-crossing detection signal. A feedbackmechanism (128) may be configured for receiving the zero-crossing detection signal from the fast comparator (118) for resetting the SR latch (122), thereby turning off the fast comparator (118). The output of the SR latch (122) may serve as the ZCD signal. The level shifter (120) and the slow comparator (116) may together consume a total current of about 30uA, optimizing the power efficiency of the ZCD (102). For example, without limitation, various transient responses of the ZCD (102) may be observed as illustrated in FIGs. 4B and 4C.

[0068] While considerable emphasis has been placed herein on the preferred embodiments, it will be appreciated that many embodiments can be made and that many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other changes in the preferred embodiments of the disclosure will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be implemented merely as illustrative of the disclosure and not as a limitation.ADVANTAGES OF THE PRESENT DISCLOSURE

[0069] The present disclosure provides a zero-crossing detector (ZCD) that uses high power comparators for precise zero-crossing detection, and only enables fast detection when needed, in turn reducing default power consumption.

[0070] The present disclosure provides a ZCD that uses very low current when not in use, and also may not use a clock for its operation, which reduces any requirement for additional circuitry.

[0071] The present disclosure provides a ZCD that uses a slow comparator for generating a signal based on an input signal approaching a predetermined reference value, where a Set-Reset (SR) latch is connected to the slow comparator and configured to be set based on the signal generated by the slow comparator.

[0072] The present disclosure provides a ZCD that uses a fast comparator that is activated upon connection to the SR latch for generating a zero-crossing detection signal based on an output of the SR latch being high.

[0073] The present disclosure provides a ZCD where the fast comparator turns itself off once the zero-crossing signal is detected, thereby reducing the effective power consumed by every detection cycle.

Claims

We Claim:

1. A dynamic low power auto-controlled zero-crossing detector (102) for a power converter, the zero-crossing detector (102) comprising: a slow comparator (116) configured to be constantly ON, for generating a signal based on an input signal approaching a predetermined reference value; a latch (122) operatively connected to the slow comparator (116) and configured to be set based on the signal generated by the slow comparator (116); a fast comparator (118) operatively connected to the latch (122) and activated for generating a zero-crossing detection signal based on an output (Q) of the latch (122) being high; and a feedback mechanism (128) operatively connected between the fast comparator (118) and the latch (122), and configured for receiving the zero-crossing detection signal from the fast comparator (118) for resetting the latch (122) and switching off the fast comparator (118).

2. The zero-crossing detector (102) as claimed in claim 1, wherein the slow comparator (116) is configured to generate a high-level signal to set the latch (122) when the input signal transitions from a positive value to a negative value within a specified threshold range (Vths).

3. The zero-crossing detector (102) as claimed in claim 1, wherein the fast comparator (118) is configured to generate a short timed high signal when the input signal transitioning from the negative value to the positive value crosses zero.

4. The zero-crossing detector (102) as claimed in claim 3, wherein the feedback mechanism (128) is configured to receive the short timed high signal from the fast comparator (118) to reset the latch (122) and switch off the fast comparator (118).

5. The zero-crossing detector (102) as claimed in claim 1, wherein the slow comparator (116) is configured to continuously monitor the input signal for subsequent zero crossing cycles after switching off the fast comparator (118).

6. The zero-crossing detector (102) as claimed in claim 1, wherein the fast comparator (118) is configured to digitally adjust an offset for precise control of a zero-crossing threshold value using trimming techniques.

7. The zero-crossing detector (102) as claimed in claim 1, comprising a level shifter (120) operatively connected with the slow comparator (116) and the fast comparator (118), and configured to shift a voltage level of the input signal to a voltage level of a ground and a threshold voltage of a P-channel Metal-Oxide-Semiconductor (PMOS) transistor.

8. The zero-crossing detector (102) as claimed in claim 1, wherein the latch is any flipflop comprising a reset mechanism.

9. A method for detecting zero-crossing in a signal using a dynamic low-power autocontrolled zero-crossing detector (102), the method comprising: continuously monitoring an input signal in a power converter by a slow comparator (116) of the zero-crossing detector (102); generating a signal by the slow comparator (116), when the input signal approaches a predetermined reference value; setting a latch (122) for activating a fast comparator (118) based on the signal; detecting a zero-crossing in the signal by the fast comparator (118); generating a zero-crossing detection signal by the fast comparator (118) based on the detection; and resetting the latch (122) for turning off the fast comparator (118) based on the zerocrossing detection signal.

10. The method as claimed in claim 9, wherein the zero-crossing detection signal generated by the fast comparator (118) is utilized to optimize power consumption by resetting the latch (122) and turning off the fast comparator (118) immediately after the detection of zero-crossing in the signal.

11. The method as claimed in claim 9, comprising driving any or a combination of a low side Field-Effect Transistor (FET) of a Direct Current (DC)-DC power converter, a high side FET of a DC-DC boost converter, a synchronous rectifier FET of an Alternating Current (AC)-DC converter, or any logic associated with zero crossing detection, based on an output (Q) of the latch.

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