Array substrate, display panel and display apparatus

Abstract

Provided in the present disclosure are an array substrate, a display panel and a display apparatus. The array substrate comprises a display area and two oppositely arranged third non-display areas, wherein each third non-display area is provided with a plurality of cascaded shift registers and a plurality of signal lines electrically connected to the plurality of shift registers; the signal lines comprise first signal lines and second signal lines; each second signal line comprises at least one bent portion at least used for avoiding an electrical connection position between a first signal line and a shift register, and a first portion and a second portion located at two ends of the bent portion; each bent portion comprises a first trace portion extending in a first direction and a second trace portion extending in a second direction; among at least some bent portions, the line width of a first trace portion is less than the line width of a second trace portion; and the first direction is the extension direction of the signal lines, and the first direction intersects the second direction.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0003] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0004] On one hand, the array substrate provided in the embodiments of this disclosure includes:

[0005] A substrate, the substrate including a display area and two third non-display areas disposed opposite each other on both sides of the display area;

[0006] A gate driving circuit is located in the third non-display area, and the gate driving circuit includes multiple shift registers arranged in cascade.

[0007] Multiple signal lines are located in the third non-display area. The multiple signal lines are electrically connected to the multiple shift registers. The multiple signal lines include a first signal line and a second signal line. The second signal line includes at least one bend for avoiding the position where the first signal line is electrically connected to the shift register, and a first part and a second part located at both ends of the bend. The bend includes a first trace extending along a first direction and a second trace extending along a second direction. In at least a portion of the bend, the line width of the first trace is smaller than the line width of the second trace. The first direction is the extension direction of the signal line, and the first direction intersects with the second direction.

[0008] In some embodiments, in the array substrate provided in the present disclosure, the bending portion further includes a third trace extending along a third direction. In at least a portion of the bending portion, the line width of the third trace is greater than the line width of the first trace, and the third direction intersects with the first direction.

[0009] In some embodiments, the array substrate provided in this disclosure further includes a plurality of first connection lines disposed on a different layer from the plurality of signal lines;

[0010] The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the first connecting line on the substrate.

[0011] The orthographic projection of the second trace on the substrate is located on the side where the orthographic projection of the electrical connection location on the substrate is away from the orthographic projection of the first connection line on the substrate;

[0012] The orthographic projection of the third trace on the substrate is located on the side of the orthographic projection of the first connecting line on the substrate that is away from the orthographic projection of the electrical connection location on the substrate.

[0013] In some embodiments, the array substrate provided in this disclosure further includes a plurality of second connecting lines disposed on the same layer as the plurality of first connecting lines, wherein the orthographic projection of the second connecting line on the substrate is located on the side of the third connecting line portion on the substrate whose line width is greater than that of the first connecting line portion, which is away from the orthographic projection of the first connecting line on the substrate.

[0014] In some embodiments, in the array substrate provided in the present disclosure, in at least a portion of the bending portions, the line width of the second trace portion is greater than the line width of the third trace portion.

[0015] In some embodiments, in the array substrate provided in the present disclosure, in the remaining bends that avoid the same electrical connection location, the line widths of the first trace, the second trace, and the third trace are approximately equal.

[0016] In some embodiments, in the array substrate provided in the present disclosure, in each of the bending portions, the linewidth of the second trace portion is approximately equal to the linewidth of the third trace portion.

[0017] In some embodiments, in the array substrate provided in this disclosure, the second signal line includes a first sub-signal line adjacent to the first signal line and a second sub-signal line located on the side of the first sub-signal line away from the first signal line; wherein...

[0018] The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register;

[0019] The second sub-signal line includes a second bend that avoids the electrical connection point between the first signal line and the shift register;

[0020] The line width of the second trace of the first bend is greater than the line width of the second trace of the second bend, and the line width of the third trace of the first bend is greater than the line width of the third trace of the second bend.

[0021] In some embodiments, in the array substrate provided in this disclosure, the second signal line includes a first sub-signal line adjacent to the first signal line, a second sub-signal line located on the side of the first sub-signal line away from the first signal line, and a third sub-signal line adjacent to the second sub-signal line on the side of the second sub-signal line away from the first sub-signal line; wherein...

[0022] The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register;

[0023] The third sub-signal line includes a third bend that avoids the electrical connection point between the second sub-signal line and the shift register;

[0024] The first bend and the third bend are sequentially arranged in the direction of signal transmission of the signal line, and the line width of the second trace of the first bend is smaller than the line width of the second trace of the third bend, and the line width of the third trace of the first bend is smaller than the line width of the third trace of the third bend.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the second signal line includes a first sub-signal line adjacent to the first signal line and a second sub-signal line adjacent to the first sub-signal line;

[0026] The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register;

[0027] The second sub-signal line includes a fourth bend that avoids the electrical connection point between the first sub-signal line and the shift register;

[0028] The first bend and the fourth bend are sequentially arranged in the direction of signal transmission of the signal line. The line width of the second trace of the fourth bend is greater than the line width of the second trace of the first bend, and the line width of the third trace of the fourth bend is greater than the line width of the third trace of the first bend.

[0029] In some embodiments, in the array substrate provided in this disclosure, in at least a portion of the bending portions, the second trace portion and the third trace portion satisfy the following relationship:

[0030] Wherein, W1 is the line width of the first routing section, the first part or the second part, W2 is the line width of the second routing section, W3 is the line width of the third routing section, θ1 is the angle between the second routing section and the fourth direction, θ2 is the angle between the third routing section and the fourth direction, and the fourth direction is the direction from the first signal line to the second signal line.

[0031] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of repeating units, wherein the plurality of signal lines of one repeating unit are electrically connected to x shift registers, where x is the total number of the plurality of signal lines;

[0032] In the direction from the first signal line to the second signal line, the first sub-signal line is the y-th signal line of the plurality of signal lines, where y is an integer greater than 1 and less than or equal to x;

[0033] In one of the repeating units, the second and third trace portions of the first sub-signal line satisfy the following relationship:

[0034] Wherein, W1 is the line width of the first routing section, the first part or the second part, W2 is the line width of the second routing section, W3 is the line width of the third routing section, θ1 is the angle between the second routing section and the fourth direction, θ2 is the angle between the third routing section and the fourth direction, and the fourth direction is the direction from the first signal line to the second signal line.

[0035] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of repeating units, wherein the plurality of signal lines of one repeating unit are adjacent to x shift registers, and x is the total number of the plurality of signal lines;

[0036] In a single signal line of a repeating unit, all second traces and all third traces satisfy the following relationship:

[0037] Wherein, W1 is the line width of the first trace portion, the first part, or the second part; W2 is the line width of the second trace portion; W3 is the line width of the third trace portion; W1' is the sum of the line widths of the first trace portion, the first part, or the second part in a single signal line of a repeating unit; W2' is the sum of the line widths of the second trace portion in a single signal line of a repeating unit; W3' is the sum of the line widths of the third trace portion in a single signal line of a repeating unit; n is the total number of bends in a single signal line of a repeating unit; θ1 is the angle between the second trace portion and the fourth direction; θ2 is the angle between the third trace portion and the fourth direction, where the fourth direction is the direction from the first signal line to the second signal line.

[0038] In some embodiments, in the array substrate provided in the present disclosure, the substrate further includes a first rounded corner area connecting the second non-display area and the third non-display area;

[0039] The gate driving circuit is also located in the first rounded corner region;

[0040] At least a portion of the shift register in the first rounded corner area has a larger size in the first direction than the shift register in the third non-display area in the first direction;

[0041] At least a portion of the shift register in the first rounded corner area has a smaller size in the fourth direction than the shift register in the third non-display area in the fourth direction, where the fourth direction is the direction from the first signal line to the second signal line.

[0042] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of gate signal output lines located in the first rounded corner region. At least a portion of the shift registers in the first rounded corner region are arranged in a first stepped configuration, and the extension direction of at least a portion of the gate signal output lines is approximately the same as the extension direction of the first step.

[0043] In some embodiments, the array substrate provided in this disclosure further includes multiple electrostatic discharge protection structures, multiple adapter lines, and multiple gate lines;

[0044] The gate driving circuit also extends to the second non-display area, and the plurality of electrostatic protection structures are located on the side of the gate driving circuit closer to the display area in the second non-display area and the first rounded corner area;

[0045] At least a portion of the gate signal output lines bypass the plurality of electrostatic discharge (ESD) protection structures and are electrically connected to the plurality of adapter lines. The plurality of adapter lines are electrically connected to the plurality of gate lines. Furthermore, at least a portion of the ESD protection structures in the first rounded corner area and the second non-display area are arranged in a second-step configuration. The extension direction of at least a portion of the adapter lines is approximately the same as the extension direction along the second step.

[0046] In some embodiments, in the array substrate provided in the present disclosure, the first signal line in the third non-display area is a straight line extending along the first direction.

[0047] In some embodiments, in the array substrate provided in the present disclosure, the substrate further includes a first non-display area and a second non-display area connecting the two third non-display areas, a first rounded corner area connecting the second non-display area and the third non-display area, and a second rounded corner area connecting the first non-display area and the third non-display area, wherein the first non-display area is used to bond a driving circuit.

[0048] The multiple signal lines are also located in the first rounded corner area and the second rounded corner area, and the first signal line and the second signal line are bent traces with approximately equal line width in the first rounded corner area and the second rounded corner area.

[0049] In some embodiments, the array substrate provided in this disclosure further includes multiple photosensitive signal lines and at least one frame start signal line, wherein the multiple photosensitive signal lines are located on the side of the at least one frame start signal line away from the multiple signal lines, and the multiple signal lines are clock signal lines.

[0050] In some embodiments, the array substrate provided in this disclosure further includes at least one fixed potential signal line, which is located between the plurality of photosensitive signal lines and the at least one frame start signal line.

[0051] In some embodiments, the array substrate provided in this disclosure further includes at least one fixed potential signal line, which is located between the plurality of signal lines and the at least one frame start signal line.

[0052] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0053] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0054] Figure 1 is a schematic diagram of the structure of the array substrate provided in an embodiment of this disclosure;

[0055] Figure 2 is a schematic diagram of the cascaded shift registers provided in an embodiment of this disclosure;

[0056] Figure 3 is a magnified structural diagram of region Z1 in Figure 1;

[0057] Figure 4 is a magnified structural diagram of region Z2 in Figure 3;

[0058] Figure 5 is an enlarged structural diagram of region Z3 in Figure 3;

[0059] Figure 6 is an enlarged structural diagram of region Z4 in Figure 3;

[0060] Figure 7 is an enlarged structural diagram of region Z5 in Figure 3;

[0061] Figure 8 is an enlarged structural diagram of region Z6 in Figure 3;

[0062] Figure 9 is an enlarged structural diagram of region Z7 in Figure 3;

[0063] Figure 10 is an enlarged structural diagram of region Z8 in Figure 3;

[0064] Figure 11 is an enlarged structural diagram of region Z9 in Figure 3;

[0065] Figure 12 is a schematic diagram of the structure of the bent portion provided in an embodiment of this disclosure;

[0066] Figure 13 is a schematic diagram of the line width compensation of the bent portion provided in an embodiment of this disclosure;

[0067] Figure 14 is a schematic diagram of the shift register in region Z10 of Figure 1;

[0068] Figure 15 is a schematic diagram of an enlarged structure of region Z11 in Figure 1;

[0069] Figure 16 is a schematic diagram of another enlarged structure of region Z11 in Figure 1;

[0070] Figure 17 is a schematic diagram of another enlarged structure of region Z11 in Figure 1;

[0071] Figure 18 is an enlarged structural diagram of region Z12 in Figure 17;

[0072] Figure 19 is an enlarged structural diagram of region Z13 in Figure 1;

[0073] Figure 20 is an enlarged structural diagram of region Z14 in Figure 19;

[0074] Figure 21 is a schematic diagram of one arrangement of different types of signal lines provided in an embodiment of this disclosure;

[0075] Figure 22 is a schematic diagram of another arrangement of different types of signal lines provided in the embodiments of this disclosure;

[0076] Figure 23 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0077] Figure 24 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0079] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0080] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0081] With the development of information technology, electronic devices are widely used in people's daily lives. As the most widely used flat panel display, liquid crystal displays (LCDs) occupy an important position in display panels. Gate drive circuit technology utilizes thin-film transistor array (TFT-LCD) processes to fabricate multiple cascaded shift registers (GOAs) on an array substrate to achieve a line-by-line scanning drive method. This can significantly reduce panel bezels and enhance product competitiveness.

[0082] In some embodiments, the grayscale image of the display panel shows periodic, fine dark horizontal lines near the DPO side. The inventors discovered that the falling edge (Tf) of the clock signal lines at different distances from the display area differs, causing differences in the coupling pull of different clock signals on the pixels, resulting in fine dark horizontal lines. The difference in the falling edge (Tf) of the clock signal lines at different distances from the display area is mainly due to differences in the load of the clock signal lines. For example, the clock signal line closest to the display area has several times more vias (used to connect the clock signal line and the shift register) than the clock signal line farther from the display area, resulting in longer traces, higher resistance, and thus fine dark horizontal lines.

[0083] To improve the above-mentioned technical problems, this disclosure provides an array substrate. Figure 1 is a structural schematic diagram of the array substrate provided in this disclosure embodiment; Figure 2 is a cascaded schematic diagram of the shift register provided in this disclosure embodiment; Figure 3 is an enlarged structural schematic diagram of region Z1 in Figure 1; Figure 4 is an enlarged structural schematic diagram of region Z2 in Figure 3; Figure 5 is an enlarged structural schematic diagram of region Z3 in Figure 3; Figure 6 is an enlarged structural schematic diagram of region Z4 in Figure 3; Figure 7 is an enlarged structural schematic diagram of region Z5 in Figure 3; Figure 8 is an enlarged structural schematic diagram of region Z6 in Figure 3; Figure 9 is an enlarged structural schematic diagram of region Z7 in Figure 3; and Figure 10 is an enlarged structural schematic diagram of region Z8 in Figure 3. As shown in Figures 1 to 10, the array substrate provided in this disclosure embodiment includes:

[0084] The substrate 101 includes a display area AA, a first non-display area DP and a second non-display area DPO disposed opposite each other on both sides of the display area AA, and two third non-display areas GL & GR connecting the first non-display area DP and the second non-display area DPO. The first non-display area DP is bonded to a driving circuit (e.g., a flexible printed circuit board FPC, a data chip Source IC, etc.). In some embodiments, the flexible printed circuit board FPC can be disposed in the first non-display area DP by means of COF encapsulation with a flip-chip thin film, or the driving circuit such as the data chip Source IC can be disposed in the first non-display area DP by means of COG encapsulation with a glass backplane. The driving circuit such as the flexible printed circuit board FPC or the data chip Source IC can provide data signals to the data line through the fan-out line FL of the first non-display area DP.

[0085] The gate driving circuit 102 is located in the third non-display area GL&GR, and includes a plurality of shift registers GOA cascaded together. In some embodiments, the plurality of shift registers GOA of this disclosure can be divided into two groups, respectively disposed in the left and right third non-display areas GL&GR, to ensure that the left and right bezels are narrow. Optionally, according to the working order of the shift registers GOA, this disclosure divides the shift registers GOA2n-1 (n is a positive integer) that are opened an odd number of times into one group and disposed in the third non-display area GR on the right, and the shift registers GOA2n that are opened an even number of times into another group and disposed in the third non-display area GL on the left. The shift registers GOA on the left and right sides can be symmetrically arranged. In some embodiments, the shift register GOAm that is opened m times (m is a positive integer) is electrically connected to the m-th gate line Gm arranged in the direction from the first non-display area DP to the second non-display area DPO.

[0086] Multiple signal lines 103 are located in the third non-display area GL&GR. This disclosure uses multiple signal lines 103 as an example of multiple clock signal lines electrically connected to multiple shift registers GOA. Optionally, this disclosure uses sixteen clock signal lines as an example, and the sixteen clock signal lines are sequentially labeled clk1 to clk16 according to the order of the output clock signals. In some embodiments, every sixteen sequentially opened shift registers GOA form a group, and the clock signal line clkp of the p-th output clock signal (p is a positive integer greater than or equal to 1 and less than or equal to 16) of the sixteen clock signal lines clk1 to clk16 is electrically connected to the corresponding p-th opened shift register GOAp in each group. The third non-display area GR on the right side of this disclosure has a shift register GOA2n-1, and the third non-display area GL on the left side has a shift register GOA2n. For proximity, the eight clock signal lines clk1, clk3, clk5, clk7, clk9, clk11, clk13, and clk15 electrically connected to the shift register GOA2n-1 can be located in the third non-display area GR on the right side, and the eight clock signal lines clk2, clk4, clk6, clk8, clk10, clk12, clk14, and clk16 electrically connected to the shift register GOA2n can be located in the third non-display area GL on the left side. The peripheral wiring of this disclosure can be symmetrical. The following description uses the left peripheral wiring as an example. The right peripheral wiring method can be the same as the left peripheral wiring.

[0087] In some embodiments, the plurality of signal lines 103 include a first signal line (e.g., clk16) and a second signal line (e.g., clk2). Signal lines clk14, clk12, clk10, clk8, and clk4 belong to either the first or second signal line, and this disclosure does not specifically limit this. In some embodiments, the first signal line (e.g., clk16) is located on the side of the second signal line (e.g., clk2) away from the display area AA. Optionally, the second signal line (e.g., clk2) in the third non-display area GL includes at least one bend B for avoiding the electrical connection position between the first signal line (e.g., clk16) and the shift register GOA, and a first part S1 and a second part S2 at both ends of the bend B. The bend B includes a first trace B1 extending along a first direction Y, a second trace B2 extending along a second direction D at one end of the first trace B1, and a third trace B3 extending along a third direction D' at the other end of the first trace B1. In at least a portion of the bend B, the line width of the first trace B1 is smaller than the line width of the second trace B2, and / or, the line width of the first trace B1 is smaller than the line width of the third trace B3. The first direction Y is the extension direction of the signal line 103 (the first direction Y can also be understood as the arrangement direction of the first non-display area DP and the second non-display area DPO), and the first direction Y, the second direction D, and the third direction D' intersect.

[0088] By widening the second trace portion B2 and / or the third trace portion B3 of the bend portion B, the resistance of the signal lines 103 (e.g., clk14, clk12, clk10, clk8, clk4, clk2) including the bend portion B can be reduced. This makes the resistance of different signal lines 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk4, clk2) similar or even the same, thereby reducing the load difference between different clock signals and improving or even avoiding horizontal stripe defects caused by the difference in the falling edge Tf of the clock signal between different rows. Furthermore, as can be seen from Figures 4 to 10, the wiring space near the electrical connection position between the signal line 103 and the shift register GOA is relatively large. Therefore, this space can be effectively utilized to increase the line width of the second trace portion B2 and / or the third trace portion B3, while still maintaining the narrow bezel effect. In addition, widening the inclined second trace portion B2 and / or the third trace portion B3 also helps to reduce the risk of wire breakage.

[0089] It should be understood that this disclosure makes full use of the space near the electrical connection point between signal line 103 and shift register GOA, increasing the line width of the second trace portion B2 and / or the third trace portion B3 on both sides above and below the electrical connection point between signal line 103 and shift register GOA to balance the resistance of clock signal lines clk1 to clk16. In other embodiments, if there is a large wiring space in other locations (e.g., area S shown in FIG4), this disclosure may also increase the line width in other locations (e.g., area S shown in FIG4) to balance the resistance of different signal lines 103.

[0090] In some embodiments, FIG11 shows an enlarged structure of the Z9 region in FIG3. Referring to FIGS. 4 to 11, the array substrate provided in the embodiments of this disclosure may further include multiple first connection lines 104 and multiple second connection lines 105 disposed on different layers from the multiple signal lines 103. For example, the signal lines 103 are located on the gate metal layer, and the first connection lines 104 and second connection lines 105 are located on the source / drain metal layer SD. In some embodiments, the first connection line 104 is connected between the shift register GOA and the vds trace, and the second connection line 105 is connected between the shift register GOA and the vgh trace.

[0091] Referring to Figures 4 through 11, the orthographic projection of the first trace portion B1 on the substrate 101 overlaps with the orthographic projection of the first connecting line 104 on the substrate 101. The orthographic projection of the second trace portion B2 on the substrate 101 is located on the side where the orthographic projection of the electrical connection between the signal line 103 and the shift register GOA on the substrate 101 is far from the orthographic projection of the first connecting line 104 on the substrate 101. The orthographic projection of the third trace portion B3 on the substrate 101 is located on the side where the orthographic projection of the first connecting line 104 on the substrate 101 is far from the orthographic projection of the electrical connection between the signal line 103 and the shift register GOA on the substrate 101. The orthographic projection of the second connecting line 105 on the substrate 101 is located on the side where the orthographic projection of the third trace portion B3, whose line width is greater than that of the first trace portion B1, is far from the orthographic projection of the first connecting line 104 on the substrate 101. In other words, the first connecting line 104 does not overlap with the second routing portion B2 and the third routing portion B3, and the second connecting line 105 does not overlap with the second routing portion B2 and the third routing portion B3, whose line width is greater than that of the first routing portion B1. This way, even if the second routing portion B2 and / or the third routing portion B3 are widened, the coupling capacitance CClk between the first connecting line 104 and the signal line 103, and the coupling capacitance CClk between the second connecting line 105 and the signal line 103, will not increase, thus preventing the first connecting line 104 and the second connecting line 105 from affecting the signal transmitted on the signal line 103 (e.g., clock signal). Due to the requirement of not overlapping with the first connecting line 104 and the second connecting line 105, in at least a partial bend in B, the line width of the second routing portion B2 can be set to be greater than the line width of the third routing portion B3.

[0092] In some embodiments, a process fluctuation value of 1.5 μm (this value depends on the process capability of the factory equipment) can be maintained between the orthographic projection of the first connection line 104 on the substrate 101 and the orthographic projection of the third trace portion B3 with increased linewidth on the substrate 101, and between the orthographic projection of the second connection line 105 on the substrate 101 and the orthographic projection of the third trace portion B3 with increased linewidth on the substrate 101, respectively. This ensures that if there is an alignment misalignment between the layer where the first connection line 104 and the second connection line 105 are located and the layer where the signal line 103 is located, the first connection line 104, the second connection line 105 and the second trace portion B2 do not overlap, and / or the first connection line 104, the second connection line 105 and the third trace portion B3 do not overlap.

[0093] In some embodiments, in this disclosure, only the line width of the second trace portion B2 and / or the third trace portion B3 contained in a portion of the bend portion B (e.g., the first bend portion B10 of clk14 shown in FIG. 10) can be increased, such that the line width of the second trace portion B2 and / or the third trace portion B3 contained in a portion of the bend portion B (e.g., the first bend portion B10 of clk14 shown in FIG. 10) is greater than the line width of the first trace portion B1 contained therein; in this case, in the remaining bend portions B (e.g., the second bend portions B20 of clk12, clk10, clk8, clk6, clk4, and clk2 shown in FIG. 10), the line width of the second trace portion B2 and the line width of the third trace portion B3 can remain approximately equal to the line width of the first trace portion B1 and remain unchanged. In other embodiments, for example, in FIG. 9, only the line width of the second trace portion B2 and / or the third trace portion B3 included in the fourth bend portion B40 of clk12 is increased, while the line width of the second trace portion B2 and the third trace portion B3 of the bend portions B included in clk10, clk8, clk6, clk4, and clk2 remains approximately equal to the line width of the first trace portion B1; in FIG. 8, only the third bend of clk10 is increased. The line widths of the second routing section B2 and / or the third routing section B3 included in section B30, and the line widths of the second routing section B2 and the third routing section B3 included in the bend sections B of clk8, clk6, clk4, and clk2, can be maintained approximately equal to the line width of the first routing section B1; in Figure 7, only the line widths of the second routing section B2 and / or the third routing section B3 included in the fifth bend section B50 of clk8 are increased, and the line widths of clk6, clk4, and clk5 are also increased. 4. The line width of the second routing portion B2 and the third routing portion B3 of the bend portion B in clk2 can be maintained approximately equal to the line width of the first routing portion B1; in Figure 6, only the line width of the second routing portion B2 and / or the third routing portion B3 of the sixth bend portion B60 of clk6 is increased, and the line width of the second routing portion B2 and the third routing portion B3 of the bend portion B in clk4 and clk2 can be maintained approximately equal to the line width of the first routing portion B1. The line widths of the first routing portion B1 are approximately equal. In Figure 5, only the line widths of the second routing portion B2 and / or the third routing portion B3 contained in the seventh bend portion B70 of clk4 are increased. The line widths of the second routing portion B2 and the third routing portion B3 contained in the bend portion B of clk2 can be approximately equal to the line width of the first routing portion B1. In Figure 4, the line widths of the second routing portion B2 and / or the third routing portion B3 contained in the eighth bend portion B80 of clk2 are increased. Optionally, in this disclosure, the line widths of the first routing portion B1 of different bend portions B are the same, thereby ensuring good uniformity of the line widths of different signal lines 103 at the bend portions B where the line widths of the second routing portion B2 and the third routing portion B3 are the same as the line width of the first routing portion B1, which is beneficial for simplifying wiring.

[0094] In other embodiments, as shown in FIG12, the present disclosure may also increase the linewidth of the second trace portion B2 and the third trace portion B3 of each bend portion B, such that the linewidth of the second trace portion B2 and the linewidth of the third trace portion B3 are approximately equal in each bend portion B, thereby reducing the risk of burn-out caused by local impedance abrupt changes due to excessive linewidth of the second trace portion B2 and / or the third trace portion B3. It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately equal" may be completely identical, or there may be some deviation (e.g., ±5% deviation). Therefore, the "approximately equal" relationship between related features is within the protection scope of this disclosure as long as the error is permissible.

[0095] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG10, the second signal line may include a first sub-signal line (e.g., clk14) adjacent to the first signal line (e.g., clk16), and a second sub-signal line (e.g., clk12) located on the side of the first sub-signal line (e.g., clk14) away from the first signal line (e.g., clk16); wherein, the first sub-signal line (e.g., clk14) includes a first bend portion B10 that avoids the electrical connection position between the first signal line (e.g., clk16) and the shift register GOA; the second sub-signal line (e.g., clk12) includes a second bend portion B20 that avoids the electrical connection position between the first signal line (e.g., clk16) and the shift register GOA; wherein, the line width of the second trace portion B2 of the first bend portion B10 is greater than the line width of the second trace portion B2 of the second bend portion B20, and the line width of the third trace portion B3 of the first bend portion B10 is greater than the line width of the third trace portion B3 of the second bend portion B20. In other words, in this disclosure, among the multiple bends B that avoid the same electrical connection location, the line width of the second wiring portion B2 closest to the electrical connection location is greater than the line width of the other second wiring portions B2, and the line width of the third wiring portion B3 closest to the electrical connection location is greater than the line width of the other third wiring portions B3.

[0096] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG8 and FIG10, the second signal line may include a first sub-signal line (e.g., clk14) adjacent to the first signal line (e.g., clk16), a second sub-signal line (e.g., ckl12) located on the side of the first sub-signal line (e.g., ckl14) away from the first signal line (e.g., clk16), and a third sub-signal line (e.g., ckl10) adjacent to the second sub-signal line (e.g., ckl12) on the side of the second sub-signal line (e.g., ckl14) away from the first sub-signal line (e.g., ckl14); wherein, the first sub-signal line (e.g., ckl14) The signal line 103 includes a first bend B10 that avoids the electrical connection between the first signal line (e.g., clk16) and the shift register GOA; the third sub-signal line (e.g., ckl10) includes a third bend B30 that avoids the electrical connection between the second sub-signal line (e.g., ckl12) and the shift register GOA; the first bend B10 and the third bend B30 are sequentially arranged in the direction of signal transmission of the signal line 103, and the line width of the second trace portion B2 of the first bend B10 is smaller than the line width of the second trace portion B2 of the third bend B30, and the line width of the third trace portion B3 of the first bend B10 is smaller than the line width of the third trace portion B3 of the third bend B30.

[0097] In some embodiments, the first signal line can be clk14, the first sub-signal line is clk12 adjacent to clk14, the second sub-signal line can be clk10, and the third sub-signal line is clk8 adjacent to clk10. In this case, as shown in Figures 7 and 9, the first bend of the first sub-signal line (e.g., clk12) avoiding the electrical connection position between the first signal line (clk14) and the shift register GOA is the fourth bend B40 shown in Figure 9. The third bend of the third sub-signal line (e.g., clk8) avoiding the electrical connection position between the second sub-signal line (e.g., clk10) and the shift register GOA is the fifth bend B50 shown in Figure 7. The line width of the second trace portion B2 of the fourth bend portion B40 is smaller than the line width of the second trace portion B2 of the fifth bend portion B50, and the line width of the third trace portion B3 of the fourth bend portion B40 is smaller than the line width of the third trace portion B3 of the fifth bend portion B50.

[0098] In some embodiments, the first signal line can be clk12, the first sub-signal line is clk10 adjacent to clk12, the second sub-signal line can be clk8, and the third sub-signal line is clk6 adjacent to clk8. In this case, as shown in Figures 6 and 8, the first bend of the first sub-signal line (e.g., clk10) that avoids the electrical connection position between the first signal line (clk12) and the shift register GOA is the third bend B30 shown in Figure 8. The third bend of the third sub-signal line (e.g., clk6) that avoids the electrical connection position between the second sub-signal line (e.g., clk8) and the shift register GOA is the sixth bend B60 shown in Figure 6. The line width of the second trace portion B2 of the third bend portion B30 is smaller than the line width of the second trace portion B2 of the sixth bend portion B60, and the line width of the third trace portion B3 of the third bend portion B30 is smaller than the line width of the third trace portion B3 of the sixth bend portion B60.

[0099] In some embodiments, the first signal line can be clk10, the first sub-signal line can be clk8 adjacent to clk10, the second sub-signal line can be clk6, and the third sub-signal line can be clk4 adjacent to clk6. In this case, as shown in Figures 5 and 7, the first bend of the first sub-signal line (e.g., clk8) that avoids the electrical connection position between the first signal line (clk10) and the shift register GOA is the fifth bend B50 shown in Figure 7. The third bend of the third sub-signal line (e.g., clk4) that avoids the electrical connection position between the second sub-signal line (e.g., clk6) and the shift register GOA is the seventh bend B70 shown in Figure 5. The line width of the second trace portion B2 of the fifth bend portion B50 is smaller than the line width of the second trace portion B2 of the seventh bend portion B70. The line width of the third trace portion B3 of the fifth bend portion B50 is smaller than the line width of the third trace portion B3 of the seventh bend portion B70.

[0100] In some embodiments, the first signal line can be clk8, the first sub-signal line is clk6 adjacent to clk8, the second sub-signal line can be clk4, and the third sub-signal line is clk2 adjacent to clk4. In this case, as shown in Figures 4 and 6, the first bend where the first sub-signal line (e.g., clk6) avoids the electrical connection position between the first signal line (clk8) and the shift register GOA is the sixth bend B60 shown in Figure 6. The third bend where the third sub-signal line (e.g., clk2) avoids the electrical connection position between the second sub-signal line (e.g., clk4) and the shift register GOA is the eighth bend B80 shown in Figure 4. The line width of the second trace portion B2 of the sixth bend portion B60 is smaller than the line width of the second trace portion B2 of the eighth bend portion B80, and the line width of the third trace portion B3 of the sixth bend portion B60 is smaller than the line width of the third trace portion B3 of the eighth bend portion B80.

[0101] It should be understood that the second sub-signal line of this disclosure can be arranged adjacent to the first sub-signal line as in the example above, or it can be arranged at a distance from the first sub-signal line. For example, if the first sub-signal line is clk14 and the second sub-signal line is clk10 arranged at a distance from clk14, then the first signal line is clk16 adjacent to clk14 and the third sub-signal line is clk8 adjacent to clk10. See Figures 7 and 10. The first sub-signal line (e.g., clk14) avoids the first signal line (clk16). The first bend 10 at the location where the shift register GOA is electrically connected, and the third bend where the third sub-signal line (e.g., clk8) avoids the third bend where the second sub-signal line (e.g., clk10) is electrically connected to the shift register GOA, is the fifth bend B50 shown in Figure 7. The line width of the second trace B2 of the first bend B10 is smaller than the line width of the second trace B2 of the fifth bend B50, and the line width of the third trace B3 of the first bend B10 is smaller than the line width of the third trace B3 of the fifth bend B50.

[0102] In some embodiments, the first signal line, the first sub-signal line, the second sub-signal line, and the third sub-signal line are sequentially adjacent. For example, the first signal line is clk16, the first sub-signal line is clk14, the second sub-signal line is clk12, and the third sub-signal line is clk10. Referring to Figures 3 and 8 to 10, the first sub-signal line (e.g., clk14) includes a first bend B10 to avoid the electrical connection position between the first signal line (e.g., clk16) and the shift register GOA; the third sub-signal line (e.g., clk10) includes a third bend B30 to avoid the electrical connection position between the second sub-signal line (e.g., clk12) and the shift register GOA; the second sub-signal line... (e.g., clk12) includes a fourth bend B40 that avoids the electrical connection position between the first sub-signal line (e.g., clk14) and the shift register GOA. The first bend B10, the fourth bend B40 and the third bend B30 are sequentially arranged in the direction of signal transmission of the signal line 103. The line width of the second trace portion B2 of the fourth bend B40 can be greater than the line width of the second trace portion B2 of the first bend B10 and less than the line width of the second trace portion B2 of the third bend B30. The line width of the third trace portion B3 of the fourth bend B40 can be greater than the line width of the third trace portion B3 of the first bend B10 and less than the line width of the third trace portion B3 of the third bend B30.

[0103] In some embodiments, the sequentially adjacent first signal line, first sub-signal line, second sub-signal line, and third sub-signal line can also be clk12, clk10, clk8, and clk6, respectively. Referring to Figures 3, 6 to 8, the first bend where the first sub-signal line (e.g., clk10) avoids the electrical connection between the first signal line (e.g., clk12) and the shift register GOA is the third bend B30 shown in Figure 8. The fourth bend where the second sub-signal line (e.g., clk8) avoids the electrical connection between the first sub-signal line (e.g., clk10) and the shift register GOA is the fourth bend shown in Figure 7. The fifth bend B50, the third bend where the third sub-signal line (e.g., clk6) avoids the electrical connection between the second sub-signal line (e.g., clk8) and the shift register GOA, is the sixth bend B60 shown in Figure 6. The line width of the second trace section B2 of the fifth bend B50 can be greater than the line width of the second trace section B2 of the third bend B30 and less than the line width of the second trace section B2 of the sixth bend B60. The line width of the third trace section B3 of the fifth bend B50 can be greater than the line width of the third trace section B3 of the third bend B30 and less than the line width of the third trace section B3 of the sixth bend B60.

[0104] In some embodiments, the sequentially adjacent first signal line, first sub-signal line, second sub-signal line, and third sub-signal line can also be clk8, clk6, clk4, and clk2, respectively. Referring to Figures 3, 4 to 6, the first bend where the first sub-signal line (e.g., clk6) avoids the electrical connection between the first signal line (e.g., clk8) and the shift register GOA is the sixth bend B60 shown in Figure 6. The fourth bend where the second sub-signal line (e.g., clk4) avoids the electrical connection between the first sub-signal line (e.g., clk6) and the shift register GOA is the seventh bend shown in Figure 5. The third bend in section B70, where the third sub-signal line (e.g., clk2) avoids the electrical connection between the second sub-signal line (e.g., clk4) and the shift register GOA, is the eighth bend section B80 shown in Figure 4. The line width of the second trace section B2 of the seventh bend section B70 can be greater than the line width of the second trace section B2 of the sixth bend section B60 and less than the line width of the second trace section B2 of the eighth bend section B80. The line width of the third trace section B3 of the seventh bend section B70 can be greater than the line width of the third trace section B3 of the sixth bend section B60 and less than the line width of the third trace section B3 of the eighth bend section B80.

[0105] As can be seen from the above, the line widths of the second wiring portion B2 of the first bend portion B10, the second wiring portion B2 of the fourth bend portion B40, the second wiring portion B2 of the third bend portion B30, the second wiring portion B2 of the fifth bend portion 50, the second wiring portion B2 of the sixth bend portion B60, the second wiring portion B2 of the seventh bend portion B70, and the second wiring portion B2 of the eighth bend portion B80 in this disclosure are as follows: The widths increase sequentially: the line width of the third trace portion B3 in the first bend B10, the third trace portion B3 in the fourth bend B40, the third trace portion B30, the fifth bend B3 in the fifth bend B50, the sixth bend B60, the seventh bend B70, and the eighth bend B80. Since the further away from the first signal line (e.g., clk16), the more bends the second signal lines (e.g., clk14, clk12, clk10, clk8, clk6, clk2) undergo, the longer the lines, and the greater the resistance, by setting the width of the second trace portion B2 and / or the third trace portion B3 of the bend portion B to gradually increase along the clock signal transmission direction, the resistance of different signal lines 103 can be effectively balanced.

[0106] In some embodiments, as shown in FIG13, in at least a partial bend B, the second wiring portion B2 and the third wiring portion B3 can satisfy the following relationship:

[0107] Wherein, W1 is the line width of the first routing section B1, the first section S1 or the second section S2, W2 is the line width of the second routing section B2, W3 is the line width of the third routing section B3, θ1 is the angle between the second routing section B2 and the fourth direction X, θ2 is the angle between the third routing section B3 and the fourth direction X, θ2 and θ1 may be equal or unequal, and the fourth direction X is the direction from the first signal line (e.g. clk16) to the second signal line (e.g. clk14).

[0108] In some embodiments, this disclosure may further include multiple repeating units RU. FIG3 shows a schematic diagram of the structure of a repeating unit RU. As can be seen from FIG3, multiple signal lines 103 of a repeating unit RU are electrically connected to x shift registers GOA, where x is the total number of multiple signal lines 103, for example, x is 8 in FIG3. Optionally, in the direction from the first signal line (e.g., clk16) to the second signal line (e.g., clk14), the first sub-signal line is the y-th signal line of the multiple signal lines 103, where y is an integer greater than 1 and less than or equal to x, and the y-th signal line includes y-1 bends B.

[0109] In some embodiments, in order to effectively balance the resistance of the first sub-signal line (i.e., the y-th signal line) and the first signal line (e.g., clk16), the line width compensation is performed on all y-1 bends B of the first sub-signal line. The second trace B2 of each bend B can be compensated according to the above formula (1), and the third trace B3 of each bend B is compensated according to the above formula (2). Considering that there is a large space at the electrical connection position between the avoidance signal line 103 and the shift register GOA, this disclosure can also only perform line width compensation on one bend B adjacent to the electrical connection position between the first sub-signal line (i.e., the y-th signal line) and the shift register GOA (e.g., only the eighth bend B80 of the 8th signal line clk2 in Figures 3 to 10), and the compensation line width of this bend B is the same as the compensation bus width of the y-1 bends B. In a repeating unit RU, the second routing portion B2 and the third routing portion B3 of the first sub-signal line (i.e., the y-th signal line) can satisfy the following relationship:

[0110] Wherein, W1 is the line width W1 of the first routing section B1, the first section B2 or the second section B3, W2 is the line width of the second routing section B2, W3 is the line width of the third routing section B3, θ1 is the angle between the second routing section B2 and the fourth direction X, θ2 is the angle between the third routing section B3 and the fourth direction X, and the fourth direction X is the direction from the first signal line (e.g. clk16) to the second signal line (e.g. clk14).

[0111] In some embodiments, such as when wiring space is limited, the line width of the compensated second trace portion B2 in any of the signal lines 103 can satisfy formula (1), and the line width of the third trace portion B3 can be less than formula (2). Alternatively, line width compensation can be performed on some or all of the bend portions B in any of the signal lines 103, but the compensation width is less than formula (1) and formula (2). The final compensated line width should be as close as possible to W2'+W3'-2W1'. This achieves impedance balance for different signal lines 103.

[0112] Based on this, in a single signal line 103 of a repeating unit RU in this disclosure, all second traces B2 and all third traces B3 satisfy the following relationship:

[0113] Wherein, W1 is the line width of the first routing section B2, the first section S1, or the second section S2; W2 is the line width of the second routing section B2; W3 is the line width of the third routing section B3; W1' is the sum of the line widths of the first routing section B1, the first section S1, or the second section S2 in a single signal line 103 of a repeating unit RU; W2' is the sum of the line widths of the second routing section B2 in a single signal line 103 of a repeating unit RU; W3' is the sum of the line widths of the third routing section B3 in a single signal line 103 of a repeating unit RU; and n is the total number of bends B in a single signal line 103 of a repeating unit RU, for example, the 8 bends in the third non-display area GL on the left side of this disclosure. The clock signal lines clk2, clk4, clk6, clk8, clk10, clk12, clk14, and clk16 have n values ​​of 7, 6, 5, 4, 3, 2, 1, and 0, respectively. The eight clock signal lines clk1, clk3, clk5, clk7, clk9, clk11, clk13, and clk15 in the third non-display area GR on the right have n values ​​of 7, 6, 5, 4, 3, 2, 1, and 0, respectively. θ1 is the angle between the second trace section B2 and the fourth direction X, and θ2 is the angle between the third trace section B3 and the fourth direction X. The fourth direction X is the direction from the first signal line (e.g., clk16) to the second signal line (e.g., clk14).

[0114] In some embodiments, FIG14 is a schematic diagram of the shift register in region Z10 of FIG1. ​​As shown in FIG1 and FIG14, in the array substrate provided in the embodiments of this disclosure, the substrate 101 further includes a first rounded corner region R1 connecting the second non-display region DPO and the third non-display region GL&GR; the gate driving circuit 102 is also located in the first rounded corner region R1. The size of at least a portion of the shift register GOA in the first rounded corner region R1 in the first direction Y is larger than the size of the shift register GOA in the third non-display region GL&GR in the first direction Y, and the size of at least a portion of the shift register GOA in the first rounded corner region R1 in the fourth direction X is smaller than the size of the shift register GOA in the third non-display region GL&GR in the fourth direction X. That is, this disclosure increases the size of at least a portion of the shift register GOA in the first rounded corner region R1 in the first direction Y and decreases its size in the fourth direction X, so that the size of at least a portion of the shift register GOA in the first rounded corner region R1 is different from that of the shift register GOA in the third non-display region GL&GR. Given the limited space available for the shift register GOA in the fourth direction X, the narrow border effect of the first rounded corner area R1 can be ensured by making good use of the space in the first direction Y to set up the shift register GOA.

[0115] In some embodiments, FIG15 is an enlarged structural schematic diagram of region Z11 in FIG1. ​​As shown in FIG1 and FIG15, the array substrate provided in the embodiments of this disclosure may further include multiple gate signal output lines 106 located in the first rounded corner region R1. Optionally, the multiple gate signal output lines 106 are located in the source-drain metal layer SD, and the gate signal output lines 106 may be connected between the shift register GOA and the gate line. Optionally, the multiple gate signal output lines 106 are wound around the shift register GOA on the side near the display area AA. For example, at least a portion of the shift register GOA in the first rounded corner region R1 is arranged in a first step, and the extension direction of at least a portion of the gate signal output lines 106 may be approximately the same as the extension direction of the first step, where "approximately the same" means that at least a portion of the gate signal output lines 106 may be attached to the first step wiring. This can reduce the load difference of the gate signal output lines 106 caused by the notch design on the DPO side and improve the uniformity of the image display on the DPO side.

[0116] In some embodiments, FIG16 is a magnified schematic diagram of another structure of region Z11 in FIG1. ​​As shown in FIG1 and FIG16, the array substrate provided in the embodiments of this disclosure may further include multiple electrostatic discharge (ESD) protection structures, multiple adapter lines 107, and multiple gate lines. Optionally, the adapter lines 107 are located in the gate metal layer. The gate driving circuit 102 also extends to the second non-display area DPO. The multiple ESD protection structures are located on the side of the gate driving circuit 102 near the display area AA in the second non-display area DPO and the first rounded corner area R1. At least a portion of the gate signal output lines 106 bypass the multiple ESD protection structures and are electrically connected to the multiple adapter lines 107. The multiple adapter lines 107 are electrically connected to the multiple gate lines. In some embodiments, the adapter lines 107 may be wound around the multiple ESD protection structures on the side away from the multiple gate signal output lines 106. For example, at least part of the electrostatic discharge (ESD) protection structure of the first rounded corner area R1 and the second non-display area DPO is arranged in a second step, and the extension direction of at least part of the adapter cable 107 is approximately the same as the extension direction of the second step. Here, "approximately the same" can be understood as at least part of the adapter cable 107 can be routed along the second step.

[0117] In some embodiments, Figure 17 is a schematic diagram of another enlarged structure of region Z11 in Figure 1, Figure 18 is a schematic diagram of an enlarged structure of region Z12 in Figure 17, Figure 19 is a schematic diagram of an enlarged structure of region Z13 in Figure 1, and Figure 20 is a schematic diagram of an enlarged structure of region Z14 in Figure 19. As shown in Figures 1 and 17 to 20, in the array substrate provided in the embodiments of this disclosure, the substrate 101 further includes a first rounded corner area R1 connecting the second non-display area DPO and the third non-display area GL&GR, and a second rounded corner area R2 connecting the first non-display area DP and the third non-display area GL&GR; multiple signal lines 103 are also located in the first rounded corner area R1 and the second rounded corner area R2. The first signal line is a straight line extending along the first direction Y in the third non-display area GL&GR. For example, the first signal line is the clock signal line clk16 that is farthest from the display area AA in the left third non-display area GL; the second signal line is other clock signal lines clk14, clk12, clk10, clk8, clk6, clk4, clk2, etc. between the first signal line (e.g., clk16) and the display area AA. In some embodiments, the first signal line (e.g., clk16) and the second signal line (e.g., clk14, clk12, clk10, clk8, clk6, clk4, clk2) are bent traces with approximately equal line widths in the first rounded corner area R1 and the second rounded corner area R2. Optionally, the line widths of the first signal line (e.g., clk16) and the second signal line (e.g., clk14, clk12, clk10, clk8, clk6, clk4, clk2) in the first rounded corner area R1 and the second rounded corner area R2 are approximately equal to the line width of the first trace portion B1. Where the first signal line (e.g., including clk16) is electrically connected to the fourth connecting line 109 (the other end of the fourth connecting line 109 is electrically connected to the shift register GOA), the second signal line (e.g., clk14, clk12, clk10, clk8, clk6, clk4, clk2) is not widened. Since the different signal lines 103 are both designed as broken lines in the first rounded corner area R1 and the second rounded corner area R2, the length difference of the different signal lines 103 is small, and the resistance difference is also small. In order to simplify the wiring, the line width of the different signal lines 103 in the first rounded corner area R1 and the second rounded corner area R2 can be set to be the same.

[0118] In some embodiments, an ambient light level can be sensed by a photosensitive device, and the backlight brightness can be adjusted based on feedback information from the light-sensing signal line to improve display quality. In related technologies, the light-sensing signal line is located on the side of signal line 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk6, clk4, clk2) away from the frame start signal line, making the light-sensing signal susceptible to crosstalk from high-frequency signals (e.g., clock signals), thus failing to accurately reflect the current ambient light level.

[0119] Figures 21 and 22 illustrate the different arrangements of the signal lines in this disclosure. As can be seen from Figures 21 and 22, in this disclosure, multiple photosensitive signal lines sen1 to sen4 are located on the side away from at least one frame start signal line stv4 and stv2, away from multiple signal lines 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk6, clk4, clk2). This movement of the frame start signal lines stv4 and stv2 between the photosensitive signal lines sen1 to sen4 and the multiple signal lines 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk6, clk4, clk2) increases the distance between the photosensitive signal and the high-frequency clock signal. Simultaneously, since the frame start signal is at a low level most of the time, it can effectively shield the photosensitive signal from interference from high-frequency signals such as the clock signal, thereby increasing photosensitivity.

[0120] Referring again to Figures 21 and 22, the array substrate provided in this embodiment may further include at least one fixed-potential signal line (e.g., VDS trace, VGH trace). This fixed-potential signal line (e.g., VDS trace, VGH trace) may be located between multiple photosensitive signal lines sen1-sen4 and at least one frame start signal line stv1-stv4, or at least one fixed-potential signal line (e.g., VDS trace, VGH trace) may also be located between multiple signal lines 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk6, clk4, clk2) and at least one frame start signal line stv1-stv4. This further increases the distance between the photosensitive signal and the high-frequency clock signal; simultaneously, the fixed-potential signal line (e.g., VDS trace, VGH trace) outputs a fixed level most of the time, effectively shielding the clock signal from interference with the photosensitive signal and increasing photosensitivity.

[0121] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3 to 12, further includes a GND trace, a VGL trace, an STV0 trace, a third connection line 108, and a fourth connection line 109. The VGL trace is electrically connected to the shift register GOA via the third connection line 108, and the signal lines 103 (e.g., clk16, clk14, clk12, clk10, clk8, clk6, clk4, clk2) are electrically connected to the shift register GOA via the fourth connection line 109. Other essential components of the array substrate are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0122] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG23, including an array substrate 001 and a counter substrate 002 placed opposite each other, wherein the array substrate 001 is the array substrate 001 provided in this disclosure embodiment. Since the principle of this display panel in solving the problem is similar to that of the array substrate in solving the problem, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.

[0123] In some embodiments, as shown in FIG23, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate and a counter substrate, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0124] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG24, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0125] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0126] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0127] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0128] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and two third non-display areas disposed opposite each other on both sides of the display area; A gate driving circuit is located in the third non-display area, and the gate driving circuit includes a plurality of cascaded shift registers. Multiple signal lines are located in the third non-display area. The multiple signal lines are electrically connected to the multiple shift registers. The multiple signal lines include a first signal line and a second signal line. The second signal line includes at least one bend for avoiding the position where the first signal line is electrically connected to the shift register, and a first part and a second part located at both ends of the bend. The bend includes a first trace extending along a first direction and a second trace extending along a second direction. In at least a portion of the bend, the line width of the first trace is smaller than the line width of the second trace. The first direction is the extension direction of the signal line, and the first direction intersects with the second direction.

2. The array substrate as claimed in claim 1, wherein, The bending portion further includes a third trace extending along a third direction. In at least a portion of the bending portion, the line width of the third trace is greater than the line width of the first trace, and the third direction intersects with the first direction.

3. The array substrate as described in claim 2, wherein, It also includes multiple first connecting lines that are disposed on a different layer from the multiple signal lines; The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the first connecting line on the substrate. The orthographic projection of the second trace on the substrate is located on the side where the orthographic projection of the electrical connection location on the substrate is away from the orthographic projection of the first connection line on the substrate; The orthographic projection of the third trace on the substrate is located on the side of the orthographic projection of the first connecting line on the substrate that is away from the orthographic projection of the electrical connection location on the substrate.

4. The array substrate as claimed in claim 3, wherein, It also includes multiple second connecting lines disposed on the same layer as the multiple first connecting lines, wherein the orthographic projection of the second connecting lines on the substrate is located on the side of the third routing portion on the substrate with a line width greater than that of the first routing portion, which is away from the orthographic projection of the first connecting lines on the substrate.

5. The array substrate according to any one of claims 2 to 4, wherein, In at least a portion of the bending portion, the line width of the second trace portion is greater than the line width of the third trace portion.

6. The array substrate as claimed in claim 5, wherein, In the remaining bends that avoid the same electrical connection location, the line widths of the first trace, the second trace, and the third trace are approximately equal.

7. The array substrate according to any one of claims 2 to 4, wherein, In each of the bending portions, the line width of the second wiring portion is approximately equal to the line width of the third wiring portion.

8. The array substrate according to any one of claims 2 to 6, wherein, The second signal line includes a first sub-signal line adjacent to the first signal line, and a second sub-signal line located on the side of the first sub-signal line away from the first signal line; wherein, The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register; The second sub-signal line includes a second bend that avoids the electrical connection point between the first signal line and the shift register; The line width of the second trace of the first bend is greater than the line width of the second trace of the second bend, and the line width of the third trace of the first bend is greater than the line width of the third trace of the second bend.

9. The array substrate according to any one of claims 2 to 8, wherein, The second signal line includes a first sub-signal line adjacent to the first signal line, a second sub-signal line located on the side of the first sub-signal line away from the first signal line, and a third sub-signal line adjacent to the second sub-signal line on the side of the second sub-signal line away from the first sub-signal line; wherein, The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register; The third sub-signal line includes a third bend that avoids the electrical connection point between the second sub-signal line and the shift register; The first bend and the third bend are sequentially arranged in the direction of signal transmission of the signal line, and the line width of the second trace of the first bend is smaller than the line width of the second trace of the third bend, and the line width of the third trace of the first bend is smaller than the line width of the third trace of the third bend.

10. The array substrate according to any one of claims 2 to 9, wherein, The second signal line includes a first sub-signal line adjacent to the first signal line and a second sub-signal line adjacent to the first sub-signal line; The first sub-signal line includes a first bend that avoids the electrical connection point between the first signal line and the shift register; The second sub-signal line includes a fourth bend that avoids the electrical connection point between the first sub-signal line and the shift register; The first bend and the fourth bend are sequentially arranged in the direction of signal transmission of the signal line. The line width of the second trace of the fourth bend is greater than the line width of the second trace of the first bend, and the line width of the third trace of the fourth bend is greater than the line width of the third trace of the first bend.

11. The array substrate according to any one of claims 2 to 10, wherein, In at least a portion of the bending portion, the second wiring portion and the third wiring portion satisfy the following relationship: Wherein, W1 is the line width of the first routing section, the first part or the second part, W2 is the line width of the second routing section, W3 is the line width of the third routing section, θ1 is the angle between the second routing section and the fourth direction, θ2 is the angle between the third routing section and the fourth direction, and the fourth direction is the direction from the first signal line to the second signal line.

12. The array substrate according to any one of claims 8 to 10, wherein, It also includes multiple repeating units, wherein the multiple signal lines of one repeating unit are electrically connected to x shift registers, where x is the total number of the multiple signal lines; In the direction from the first signal line to the second signal line, the first sub-signal line is the y-th signal line of the plurality of signal lines, where y is an integer greater than 1 and less than or equal to x; In one of the repeating units, the second and third trace portions of the first sub-signal line satisfy the following relationship: Wherein, W1 is the line width of the first routing section, the first part or the second part, W2 is the line width of the second routing section, W3 is the line width of the third routing section, θ1 is the angle between the second routing section and the fourth direction, θ2 is the angle between the third routing section and the fourth direction, and the fourth direction is the direction from the first signal line to the second signal line.

13. The array substrate according to any one of claims 2 to 12, wherein, It also includes multiple repeating units, wherein the multiple signal lines of one repeating unit are adjacent to x shift registers, where x is the total number of the multiple signal lines; In a single signal line of a repeating unit, all second traces and all third traces satisfy the following relationship: Wherein, W1 is the line width of the first trace portion, the first part, or the second part; W2 is the line width of the second trace portion; W3 is the line width of the third trace portion; W1' is the sum of the line widths of the first trace portion, the first part, or the second part in a single signal line of a repeating unit; W2' is the sum of the line widths of the second trace portion in a single signal line of a repeating unit; W3' is the sum of the line widths of the third trace portion in a single signal line of a repeating unit; n is the total number of bends in a single signal line of a repeating unit; θ1 is the angle between the second trace portion and the fourth direction; θ2 is the angle between the third trace portion and the fourth direction, where the fourth direction is the direction from the first signal line to the second signal line.

14. The array substrate according to any one of claims 1 to 13, wherein, The substrate further includes a first rounded corner area connecting the second non-display area and the third non-display area; The gate driving circuit is also located in the first rounded corner region; At least a portion of the shift register in the first rounded corner area has a larger size in the first direction than the shift register in the third non-display area in the first direction; At least a portion of the shift register in the first rounded corner area has a smaller size in the fourth direction than the shift register in the third non-display area in the fourth direction, where the fourth direction is the direction from the first signal line to the second signal line.

15. The array substrate as claimed in claim 14, wherein, It also includes multiple gate signal output lines located in the first rounded corner region, at least a portion of the shift registers in the first rounded corner region are arranged in a first step, and the extension direction of at least a portion of the gate signal output lines is approximately the same as the extension direction of the first step.

16. The array substrate as claimed in claim 15, wherein, It also includes multiple electrostatic protection structures, multiple adapter cables, and multiple grid lines; The gate driving circuit also extends to the second non-display area, and the plurality of electrostatic protection structures are located on the side of the gate driving circuit closer to the display area in the second non-display area and the first rounded corner area; At least a portion of the gate signal output lines bypass the plurality of electrostatic discharge (ESD) protection structures and are electrically connected to the plurality of adapter lines. The plurality of adapter lines are electrically connected to the plurality of gate lines. Furthermore, at least a portion of the ESD protection structures in the first rounded corner area and the second non-display area are arranged in a second-step configuration, and the extension direction of at least a portion of the adapter lines is approximately the same as the extension direction of the second step.

17. The array substrate according to any one of claims 1 to 16, wherein, The first signal line is a straight line extending along the first direction in the third non-display area.

18. The array substrate as claimed in claim 17, wherein, The substrate further includes a first non-display area and a second non-display area connecting the two third non-display areas, a first rounded corner area connecting the second non-display area and the third non-display area, and a second rounded corner area connecting the first non-display area and the third non-display area. The first non-display area is used to bond the driving circuit. The multiple signal lines are also located in the first rounded corner area and the second rounded corner area, and the first signal line and the second signal line are bent traces with approximately equal line width in the first rounded corner area and the second rounded corner area.

19. The array substrate according to any one of claims 1 to 18, wherein, It also includes multiple optical sensing signal lines and at least one frame start signal line, wherein the multiple optical sensing signal lines are located on the side of the at least one frame start signal line away from the multiple signal lines, and the multiple signal lines are clock signal lines.

20. The array substrate as claimed in claim 19, wherein, It also includes at least one fixed potential signal line, which is located between the plurality of light-sensing signal lines and the at least one frame start signal line.

21. The array substrate as claimed in claim 19, wherein, It also includes at least one fixed-potential signal line, which is located between the plurality of signal lines and the at least one frame start signal line.

22. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 21.

23. A display device, wherein, It includes the display panel as described in claim 22, and a backlight module located on the light-incident side of the display panel.

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