Preparation method for trench capacitor, and trench capacitor and package structure
By setting dielectric layers of different thicknesses between the electrode layers, the problem of leakage between electrode plates in deep trench capacitors is solved, improving the performance and stability of the capacitor while maintaining the capacitance value.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-03-05
- Publication Date
- 2026-06-04
AI Technical Summary
With the advancement of semiconductor integrated circuit manufacturing technology, the miniaturization of device size has led to leakage current between electrode plates, which has become an urgent problem to be solved. In particular, the leakage current between electrode plates in deep trench capacitors seriously affects the performance and stability of the capacitor structure.
By setting a first dielectric layer and a second dielectric layer between the first electrode layer and the second electrode layer, with the thickness of the second dielectric layer being greater than that of the first dielectric layer, and using PECVD technology to form a thicker second dielectric layer on the substrate surface, the isolation performance between the electrode layers is enhanced.
It effectively prevents leakage current between electrode layers, improves the performance and capacitance value of trench capacitors, and ensures the stability and normal use of capacitor structure.
Smart Images
Figure CN2025080722_04062026_PF_FP_ABST
Abstract
Description
A method for fabricating a trench capacitor, the trench capacitor itself, and its packaging structure.
[0001] Cross-referencing
[0002] This application claims priority to Chinese Patent Application No. 202411724295.7, filed on November 27, 2024, entitled "A method for preparing a trench capacitor, a trench capacitor and a packaging structure", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of packaging, and in particular to a method for preparing a trench capacitor, the trench capacitor itself, and its packaging structure. Background Technology
[0004] With advancements in semiconductor integrated circuit manufacturing technology, miniaturization of device dimensions has become crucial for improving integration density and device performance. The application of deep trench capacitors (DTCs) in integrated circuits (ICs) is becoming increasingly important as chip integration density increases. However, with the miniaturization of the distance between electrode plates, leakage current between the electrode plates has become a pressing issue that needs to be addressed. Summary of the Invention
[0005] This disclosure provides a method for preparing a trench capacitor, a trench capacitor, and a packaging structure, which at least helps to solve the problem of reducing leakage current between electrode plates.
[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for preparing a trench capacitor, characterized in that it includes:
[0007] A substrate is provided, the substrate having a first trench;
[0008] A first electrode layer is formed in the first trench, the first electrode layer covering the first trench and covering the substrate surface;
[0009] A first dielectric layer is formed, and the first dielectric layer covers the first electrode layer;
[0010] A second dielectric layer is formed, which at least covers the first dielectric layer located on the substrate surface; the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
[0011] A second electrode layer is formed on the second dielectric layer, and the second electrode layer covers the second dielectric layer;
[0012] A third dielectric layer is formed, which fills the remaining first trench.
[0013] In some embodiments, the thickness of the second sub-dielectric layer gradually decreases from the top of the second sub-dielectric layer to the bottom of the first trench.
[0014] In some embodiments, a first deposition process is used to form a second dielectric layer, wherein the first deposition process is plasma-enhanced chemical vapor deposition.
[0015] In some embodiments, the second electrode layer includes a first sub-electrode layer and a second sub-electrode layer, wherein the first sub-electrode layer is formed on the surface of the second dielectric layer and the second sub-electrode layer covers the first sub-electrode layer.
[0016] In some embodiments, the dielectric constant of the first dielectric layer is greater than the dielectric constant of the second dielectric layer.
[0017] In some embodiments, prior to forming the first electrode layer, the method further includes forming an initial dielectric layer that covers the first trench and the substrate surface.
[0018] In some embodiments, the first electrode layer, the second electrode layer, the first dielectric layer, the second dielectric layer, and the initial dielectric layer together constitute a capacitor structure layer. After forming the third dielectric layer, the method further includes: removing a portion of the capacitor structure layer and a portion of the third dielectric layer on both sides of the first trench to expose a portion of the substrate; the remaining capacitor structure layer includes a first capacitor structure layer located on the substrate surface and a second capacitor structure layer located in the first trench; the first capacitor structure layer includes a first side and a second side, the first side and the second side being located on both sides of the first trench; the length of the first side in the direction parallel to the substrate is greater than the length of the second side in the direction parallel to the substrate.
[0019] In some embodiments, the method further includes removing a portion of the second electrode layer, the first dielectric layer, the second dielectric layer, and the third dielectric layer on the first side to expose the first electrode layer, with the exposed first electrode layer serving as an extension.
[0020] In some embodiments, a contact structure is further formed, the contact structure including a first contact structure and a second contact structure, the first contact structure being electrically connected to the extension and the second contact structure being electrically connected to the second sub-electrode layer on the second side.
[0021] In some embodiments, forming a contact structure specifically includes: forming a fourth dielectric layer, the fourth dielectric layer covering the third dielectric layer and covering the extension and a portion of the substrate; forming an initial opening on the fourth dielectric layer, the initial opening including a first initial opening and a second initial opening, the opening size of the first initial opening being larger than the opening size of the second initial opening; continuing to etch along the initial opening to form the first opening and the second opening; the first opening exposing the extension, the second opening exposing the second sub-electrode layer on the second side; filling the first opening and the second opening with conductive material to form a first contact structure and a second contact structure; the depth of the first contact structure being greater than the depth of the second contact structure, the first contact structure and the second contact structure together constituting a contact structure.
[0022] In some embodiments, forming a contact structure specifically includes: forming a fourth dielectric layer, the fourth dielectric layer covering the third dielectric layer and covering the extension and a portion of the substrate; forming an initial opening on the fourth dielectric layer, the initial opening including a first initial opening and a second initial opening, the opening size of the first initial opening being larger than the opening size of the second initial opening; forming a fifth dielectric layer on the fourth dielectric layer, the fifth dielectric layer filling the second initial opening and covering the sidewalls and bottom of the first initial opening, the remaining first initial opening serving as a third initial opening, etching along the third initial opening to form a third opening; forming a fourth initial opening on a second side, the opening size of the fourth initial opening being smaller than the opening size of the third initial opening; continuing to etch along the fourth initial opening to form a fourth opening; the third opening exposing the extension, the fourth opening exposing the second sub-electrode layer on the second side; filling the third and fourth openings with conductive material to form a first contact structure and a second contact structure; the depth of the first contact structure being greater than the depth of the second contact structure, the first contact structure and the second contact structure together constituting a contact structure.
[0023] Another aspect of this disclosure provides a trench capacitor, including:
[0024] The substrate has a first groove;
[0025] The first electrode layer covers the first trench and a portion of the substrate surface;
[0026] A first dielectric layer, the first dielectric layer covering the first electrode layer;
[0027] A second dielectric layer, wherein the second dielectric layer at least covers the first sub-dielectric layer on the substrate surface; the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
[0028] A second electrode layer, the second electrode layer covering the second dielectric layer;
[0029] A third dielectric layer covers the second electrode layer and fills the remaining first trench;
[0030] In some embodiments, the thickness of the second sub-dielectric layer gradually decreases from the top of the second sub-dielectric layer to the bottom of the first trench.
[0031] In some embodiments, the second electrode layer includes a first sub-electrode layer and a second sub-electrode layer, wherein the first sub-electrode layer is located on the surface of the second dielectric layer and the second sub-electrode layer covers the first sub-electrode layer.
[0032] In some embodiments, the dielectric constant of the first dielectric layer is greater than the dielectric constant of the second dielectric layer.
[0033] In some embodiments, an initial dielectric layer is further included between the first electrode layer and the substrate, the initial dielectric layer covering the first trench and a portion of the substrate surface.
[0034] In some embodiments, the first electrode layer, the second electrode layer, the first dielectric layer, the second dielectric layer, and the initial dielectric layer together constitute a capacitor structure layer; the capacitor structure layer includes a first capacitor structure layer located on the substrate surface and a second capacitor structure layer located in a first trench; the first capacitor structure layer includes a first side and a second side, the first side and the second side being located on opposite sides of the first trench; the length of the first side in the direction parallel to the substrate is greater than the length of the second side in the direction parallel to the substrate; and the first electrode layer on the first side has an extension in the direction parallel to the substrate.
[0035] In some embodiments, a fourth dielectric layer is further included, which covers the third dielectric layer and the extension and covers a portion of the substrate.
[0036] In some embodiments, a contact structure is further included, comprising a first contact structure and a second contact structure. The first contact structure passes through the fourth dielectric layer and is electrically connected to the extension. The second contact structure passes through the fourth dielectric layer and the third dielectric layer and is electrically connected to the second sub-electrode layer on the second side. The depth of the first contact structure is greater than the depth of the second contact structure.
[0037] In another aspect, embodiments of this disclosure provide a packaging structure, including:
[0038] Circuit board;
[0039] Packaging substrate; The packaging substrate is located on the circuit board;
[0040] Adapter board, the adapter board comprising the trench capacitor of any one of claims 12-19;
[0041] The memory is located on the adapter board and is electrically connected to the adapter board.
[0042] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by providing a first dielectric layer and a second dielectric layer between the first electrode layer and the second electrode layer, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer, the thickness of the dielectric layer between the first electrode layer and the second electrode layer located on the substrate surface is made larger, preventing leakage between the first electrode layer and the second electrode layer and improving the performance of the trench capacitor. Attached Figure Description
[0043] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 is a schematic diagram of a capacitor structure;
[0045] Figures 2 to 17 are process flow diagrams of a trench capacitor fabrication method according to an embodiment of the present disclosure, wherein Figure 7 is an enlarged view of the second dielectric layer in Figure 6;
[0046] Figures 18 to 23 are process flow diagrams of a contact structure formation method in one embodiment of this disclosure;
[0047] Figure 24 is a schematic diagram of a trench capacitor provided in an embodiment of this disclosure;
[0048] Figure 25 is a schematic diagram of the packaging structure provided in an embodiment of this disclosure. Detailed Implementation
[0049] As the background technology indicates, with the advancement of semiconductor integrated circuit manufacturing technology, the miniaturization of device size has become crucial for improving integration density and device performance. The application of deep trench capacitors (DTCs) in the integrated circuit (IC) field has become increasingly important with the increase in chip integration density. However, with the miniaturization of the distance between electrode plates, leakage current between the electrode plates has become a problem that urgently needs to be solved.
[0050] This disclosure provides a method for fabricating a trench capacitor, a trench capacitor, and a packaging structure. By setting a first dielectric layer and a second dielectric layer between a first electrode layer and a second electrode layer, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer, the thickness of the dielectric layer between the first electrode layer and the second electrode layer located on the substrate surface is increased, preventing leakage between the first electrode layer and the second electrode layer and improving the performance of the trench capacitor.
[0051] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be achieved even without these technical details and various variations and modifications based on the following embodiments. The disclosure is described in more detail below with reference to the accompanying drawings. The advantages and features of this disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this disclosure.
[0052] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0053] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0054] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0055] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0056] Figure 1 is a schematic diagram of a capacitor structure;
[0057] Figures 2 to 17 are process flow diagrams of a trench capacitor fabrication method according to an embodiment of the present disclosure, wherein Figure 7 is an enlarged view of the second dielectric layer in Figure 6;
[0058] Figures 18 to 23 are process flow diagrams of a contact structure formation method in one embodiment of this disclosure;
[0059] Figure 24 is a schematic diagram of a trench capacitor provided in an embodiment of this disclosure;
[0060] Figure 25 is a schematic diagram of the packaging structure provided in an embodiment of this disclosure.
[0061] Figure 1 is a schematic diagram of a capacitor structure. Referring to Figure 1, a capacitor structure generally includes an upper electrode plate M1, a lower electrode plate M2, and a dielectric layer K. However, leakage current L is prone to exist at the edges of the upper and lower electrode plates. Here, leakage current L is only for illustrative purposes. The presence of leakage current causes charge loss, and during the charging and discharging process, it causes energy loss, leading to a decrease in the performance and stability of the capacitor structure. Furthermore, severe leakage current may cause a short circuit between the upper and lower electrode plates, affecting the normal use of the capacitor structure. With the miniaturization of semiconductor integrated devices, deep trench capacitors (DTCs) are becoming increasingly widely used. However, leakage current between the electrode plates in deep trench capacitors remains a problem that urgently needs to be solved, especially at the edges of the capacitor where leakage current is most severe.
[0062] This application provides a method for fabricating trench capacitors, which at least helps to solve the aforementioned capacitor leakage problem. The method includes: providing a substrate having a first trench; forming a first electrode layer in the first trench, the first electrode layer covering the first trench and the substrate surface; forming a first dielectric layer, the first dielectric layer covering the first electrode layer; forming a second dielectric layer, the second dielectric layer at least covering the first dielectric layer located on the substrate surface; the thickness of the second dielectric layer being greater than the thickness of the first dielectric layer; forming a second electrode layer on the second dielectric layer, the second electrode layer covering the second dielectric layer; and forming a third dielectric layer, the third dielectric layer filling the remaining portion of the first trench. Figures 2 to 17 are process flow diagrams of a trench capacitor fabrication method according to an embodiment of this disclosure, wherein Figure 7 is an enlarged view of the second dielectric layer in Figure 6.
[0063] Referring specifically to Figure 2, a substrate 10 is provided, having a first surface P1, and a first trench 201 extending from the first surface P1 into the substrate 10. The substrate 10 can be a silicon interposer, or it can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the substrate type based on the type of transistors formed on the substrate; therefore, the type of substrate should not limit the scope of protection of this application.
[0064] Next, referring to Figure 4, a first electrode layer 401 is formed in the first trench 201. The first electrode layer 401 covers the first trench 201 and the surface of the substrate 10. The material of the first electrode layer 401 can be titanium nitride or tungsten.
[0065] In one specific embodiment, referring to FIG3, before forming the first electrode layer 401, the method further includes forming an initial dielectric layer 301', which covers the first trench 201 and the surface of the substrate 10. The initial dielectric layer 301' may be made of one or more of silicon nitride, silicon oxide, or cobalt oxynitride.
[0066] Next, please refer to Figure 5 to form a first dielectric layer 301, which covers the first electrode layer 401.
[0067] Next, referring to Figure 6, a second dielectric layer 302 is formed on the first dielectric layer 301. The second dielectric layer 302 at least covers the first dielectric layer 301 located on the surface of the substrate 10, and the thickness of the second dielectric layer 302 is greater than the thickness of the first dielectric layer 301. In one specific embodiment, the second dielectric layer 302 only covers the first dielectric layer 301 located on the surface of the substrate 10; in another specific embodiment, the second dielectric layer 302 includes a first sub-dielectric layer 3021 located on the surface of the substrate 10 and a second sub-dielectric layer 3022 located in the first trench 201; the thickness of the first sub-dielectric layer 3021 is H1, the thickness of the second sub-dielectric layer 3022 is H2, and the thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness H2 of the second sub-dielectric layer 3022. In one specific embodiment, the first dielectric layer 301 and the second dielectric layer 302 can both be high dielectric constant materials. For example, the first dielectric layer 301 and the second dielectric layer 302 can be one or more of hafnium oxide, zirconium oxide, hafnium silicate, hafnium zirconate, lanthanum oxide, lanthanum silicate, barium strontium titanate, or lanthanum aluminate. Both the first dielectric layer 301 and the second dielectric layer 302 can be single-layered or multi-layered. In another specific embodiment, the dielectric constant of the first dielectric layer 301 is greater than that of the second dielectric layer 302. In one specific embodiment, the first dielectric layer 301 can be one or more of hafnium oxide, zirconium oxide, hafnium silicate, hafnium zirconate, lanthanum oxide, lanthanum silicate, barium strontium titanate, or lanthanum aluminate. The first dielectric layer 301 can be single-layered or multi-layered. The material of the second dielectric layer 302 can be one or more of silicon oxide, silicon nitride, or silicon oxynitride. The second dielectric layer 302 can be single-layered or multi-layered.
[0068] Figure 7 is an enlarged view of the second dielectric layer 302 in Figure 6. As can be seen from the figure, the thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness H2 of the second sub-dielectric layer 3022. Here, the thickness H1 of the first sub-dielectric layer 3021 refers to its length along the direction perpendicular to the substrate 10, and the thickness H2 of the second sub-dielectric layer 3022 refers to its length along the direction parallel to the substrate 10. In one specific embodiment, the thickness of the second sub-dielectric layer 3022 gradually decreases from its top to the bottom of the first trench 201. It should be noted that the top of the second sub-dielectric layer 3022 refers to a position flush with the surface of the first dielectric layer 301. The thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness of the second sub-dielectric layer 3022 at any position. In one specific embodiment, the thickness H1 of the first sub-dielectric layer 3021 is 3-8 times the thickness H2 of the second sub-dielectric layer 3022.
[0069] In one specific embodiment, a first deposition process, plasma-enhanced chemical vapor deposition (PECVD), is used to form the second dielectric layer 302. PECVD typically performs well on flat surfaces, but in high aspect ratio structures, such as deep trench capacitors (DTCs), its filling capacity within the trenches is weak. This is mainly because the plasma has limited penetration power at the bottom of deep holes or trenches, resulting in insufficient filling at the bottom. The characteristics of PECVD cause the thickness H1 of the first sub-dielectric layer 3021 on the surface of the substrate 10 of the second dielectric layer 3022 to be greater than the thickness of the second sub-dielectric layer 3022 within the first trench 201, and the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201.
[0070] Referring next to Figures 8 and 9, a second electrode layer 402 is formed on the second dielectric layer 302, covering the second dielectric layer 302. The material of the second electrode layer 402 can be titanium nitride or tungsten. In a specific embodiment, the second electrode layer 402 includes a first sub-electrode layer 4021 and a second sub-electrode layer 4022. The first sub-electrode layer 4021 is formed on the surface of the second dielectric layer 302, and the second sub-electrode layer 4022 covers the first sub-electrode layer 4021. The first electrode layer 401, the second electrode layer 402, the first dielectric layer 301, and the second dielectric layer 302 constitute a capacitor structure. The first electrode layer 401, the second electrode layer 402, the first dielectric layer 301, the second dielectric layer 302, and the initial dielectric layer 301' together constitute the capacitor structure layer 4.
[0071] Next, referring to Figure 10, a third dielectric layer 303 is formed, which fills the remaining first trench 201. The third dielectric layer 303 can be one or more of silicon nitride, silicon oxide, or silicon oxynitride.
[0072] Referring to Figure 11, after forming the third dielectric layer 303, the process further includes: removing portions of the capacitor structure layer 4 and the third dielectric layer 303 on both sides of the first trench 201 to expose a portion of the substrate 10; that is, removing the edge portion of the capacitor structure layer 4 located on the surface of the substrate 10; the remaining capacitor structure layer 4 includes a first capacitor structure layer 41 located on the surface of the substrate 10 and a second capacitor structure layer 42 located in the first trench 201; the first capacitor structure layer 41 includes a first side S1 and a second side S2, which are located on both sides of the first trench 201; the length of the first side S1 along the direction parallel to the substrate 10 is greater than the length of the second side S2 along the direction parallel to the substrate 10. Specifically, the dashed lines in Figure 11 show the first capacitor structure layer 41, the second capacitor structure layer 42, the first side S1, and the second side S2. The purpose of removing portions of the capacitor structure layer 4 and the third dielectric layer 303 on both sides of the first trench 201 to expose a portion of the substrate 10 is to cut off adjacent capacitor structures to form independent capacitor structures.
[0073] Next, referring to Figures 12 and 13, a portion of the second electrode layer 402, a portion of the first dielectric layer 301, a portion of the second dielectric layer 302, and a portion of the third dielectric layer 303 on the first side S1 are removed so that the first electrode layer 401 at the edge of the first side S1 is exposed, and the exposed first electrode layer 401 serves as an extension 4011.
[0074] Next, referring to Figures 14 to 17, it also includes forming a contact structure 60, which includes a first contact structure 601 and a second contact structure 602. The first contact structure 601 is electrically connected to the extension 4011, and the second contact structure 602 is electrically connected to the second sub-electrode layer 4022 of the second side S2.
[0075] Please refer to Figure 14 for details. A fourth dielectric layer 304 is formed, which covers the third dielectric layer 303 and the extension 4011 and part of the substrate 10.
[0076] Referring specifically to Figure 15, an initial opening 50' is formed on the fourth dielectric layer 304. The initial opening 50' includes a first initial opening 501' and a second initial opening 502'. The opening size D1 of the first initial opening 501' is larger than the opening size D2 of the second initial opening 502'. The fourth dielectric layer 304 can be silicon nitride, silicon oxide, or silicon oxynitride.
[0077] Next, referring to Figure 16, etching continues along the initial opening 50' to form a first opening 501 and a second opening 502; the opening size C1 of the first opening 501 is larger than the opening size C2 of the second opening 502; the first opening 501 exposes a portion of the extension 4011, and the second opening 502 exposes the second sub-electrode layer 4022 of the second side S2; the projection of the first opening 501 onto the first electrode layer 401 is located within the extension 4011. The opening size D1 of the first initial opening 501' is larger than the opening size D2 of the second initial opening 502' because a larger opening size makes it easier for etching gas to enter the opening, resulting in a faster etching rate. Since the depth of the subsequently formed first opening 501 is greater than the depth of the second opening 502, in order to accelerate the formation rate of the first opening 501, the opening size D1 of the first initial opening 501' is made larger than the opening size D2 of the second initial opening 502' when setting the initial opening 50'.
[0078] Next, referring to Figure 17, conductive material is filled into the first opening 501 and the second opening 502 to form a first contact structure 601 and a second contact structure 602; the depth of the first contact structure 601 is greater than the depth of the second contact structure 602, and the width C1 of the first contact structure 601 is greater than the width C2 of the second contact structure 602. The first contact structure 601 and the second contact structure 602 together constitute a contact structure 60, and the material of the contact structure 60 can be titanium nitride or tungsten.
[0079] As shown in Figure 17, the trench capacitor 100 is finally formed through the above steps. In a specific embodiment, a second dielectric layer 302 is formed on the first dielectric layer 301. The second dielectric layer 302 only covers the first dielectric layer 301 located on the surface of the substrate 10, and the thickness of the second dielectric layer 302 is greater than the thickness of the first dielectric layer 301. Originally, leakage was prone to occur between the upper and lower electrode plates at the edge of the trench capacitor. This application addresses this by forming a second dielectric layer 302 on the first dielectric layer 301, with the thickness of the second dielectric layer 302 being greater than the thickness of the first dielectric layer 301. This increases the thickness of the dielectric layer between the first electrode layer 401 and the second electrode layer 402, which was originally prone to leakage, thereby improving the isolation performance between the first electrode layer 401 and the second electrode layer 402 and preventing leakage current. For those skilled in the art, the capacitance formula is C = εS / 4πkd, where ε represents the dielectric constant of the dielectric layer, k represents the electrostatic constant, S represents the area of the opposing electrode plates, and d represents the distance between the electrode plates. This formula is used to calculate the capacitance value given a dielectric layer, area, and distance. Since the capacitance depends not only on the electrode area but also on the thickness of the dielectric layer, a smaller thickness results in a larger capacitance, and a larger thickness results in a smaller capacitance. In this application, the second dielectric layer 302 only covers the first dielectric layer 301 located on the surface of the substrate 10. That is, the second dielectric layer 302 does not exist in the first trench 201. In other words, the thickness of the dielectric layer between the first electrode layer 401 and the second electrode layer 402 in the first trench 201 is not increased, preventing a decrease in capacitance due to an increase in dielectric layer thickness, thus ensuring the capacitance value of the trench capacitor 100. In other words, this application not only solves the leakage problem between the first electrode layer 401 and the second electrode layer 402 but also ensures the capacitance value of the trench capacitor 100, preventing a decrease in capacitance caused by an excessively thick dielectric layer between the first electrode layer 401 and the second electrode layer 402.
[0080] In another embodiment, PECVD is used because it has good surface filling ability but weak hole filling ability. By forming a second dielectric layer 302 on the surface of the first dielectric layer 301, the characteristics of PECVD make the thickness H1 of the first sub-dielectric layer 3021 on the surface of the substrate 10 of the second dielectric layer 3022 greater than the thickness of the second sub-dielectric layer 3022 in the first trench 201. Since the thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness of the second sub-dielectric layer 3022, the thickness of the second sub-dielectric layer 3022 on the surface of the substrate 10 is thicker. Originally, leakage was easy between the upper and lower electrode plates at the edge of the trench capacitor. In this application, by forming a second dielectric layer 302 on the first dielectric layer 301, and the thickness of the second sub-dielectric layer 3022 on the substrate surface is thicker, the thickness of the dielectric layer between the first electrode layer 401 and the second electrode layer 402, which was originally prone to leakage, is increased, thereby improving the isolation performance between the first electrode layer 401 and the second electrode layer 402 and preventing leakage current. In this application, besides the fact that the thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness H2 of the second sub-dielectric layer 3022, and the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201; since PECVD has a weak filling capacity in the first trench 201, that is, the second sub-dielectric layer 3022 fills less in the first trench 201, and the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201. For those skilled in the art, the capacitance is determined by the formula C = εS / 4πkd, where ε represents the dielectric constant of the dielectric layer, k represents the electrostatic constant, S represents the area of the opposing electrode plates, and d represents the distance between the electrode plates. This formula is used to calculate the capacitance value given a dielectric layer, area, and distance. Since the capacitance value depends not only on the electrode area but also on the thickness of the dielectric layer, the smaller the thickness, the larger the capacitance value, and the larger the thickness, the smaller the capacitance value. In this application, PECVD has a weaker filling ability in the first trench 201, resulting in a thinner deposition thickness of the second sub-dielectric layer 3022 within the first trench 201. Furthermore, the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201. This ensures the capacitance value of the trench capacitor 100. In other words, this application not only solves the leakage problem between the first electrode layer 401 and the second electrode layer 402 but also ensures the capacitance value of the trench capacitor 100, preventing the capacitance value from decreasing due to an excessively thick dielectric layer between the first electrode layer 401 and the second electrode layer 402.
[0081] Figures 18 to 23 are process flow diagrams of a contact structure formation method in one embodiment of this disclosure.
[0082] Please refer to Figure 18 for details. A fourth dielectric layer 304 is formed, which covers the third dielectric layer 303 and the extension 4011 and part of the substrate 10. An initial opening 50' is formed on the fourth dielectric layer 304. The initial opening 50' includes a first initial opening 501' and a second initial opening 502'. The opening size D1 of the first initial opening 501' is larger than the opening size D2 of the second initial opening 502'.
[0083] Next, referring to Figures 19 to 22, a fifth dielectric layer 305 is formed on the fourth dielectric layer 304. The fifth dielectric layer 305 fills the second initial opening 502' and covers the sidewalls and bottom of the first initial opening 501'. The remaining first initial opening 501' serves as the third initial opening 503'. Etching is performed along the third initial opening 503' to form the third opening 503. A fourth initial opening 504' is formed on the second side, with the opening size of the fourth initial opening 504' being smaller than the opening size of the third initial opening 503'. Etching continues along the fourth initial opening 504' to form the fourth opening 504. The third opening 503 exposes the extension 4011, and the fourth opening exposes the second sub-electrode layer 4022 on the second side. The fifth dielectric layer 305 can be silicon nitride, silicon oxide, or silicon oxynitride.
[0084] Referring next to Figure 23, conductive material is filled into the third opening 503 and the fourth opening 504 to form a first contact structure 601 and a second contact structure 602. The first contact structure 601 is electrically connected to the extension 4011, and the second contact structure 602 is electrically connected to the second sub-electrode layer 4022 on the second side. The depth of the first contact structure 601 is greater than the depth of the second contact structure 602, and the first contact structure 601 and the second contact structure 602 together constitute the contact structure 60.
[0085] The difference between this embodiment and the previous embodiment is that the third opening 503 and the fourth opening 504 can be formed separately in this embodiment. Since the etching depths of the third opening 503 and the fourth opening 504 are different, the thicknesses of the first electrode layer 401 and the second sub-electrode layer 4022 are both relatively thin. Simultaneous etching to form the third opening 503 and the fourth opening 504 may cause over-etching of the first electrode layer 401 and the second sub-electrode layer 4022, resulting in inaccurate connection of the contact structure 60. Step-by-step etching can control the etching stop points of the third opening 503 and the fourth opening 504 respectively to prevent over-etching, so that the first contact structure 601 is accurately electrically connected to the extension 4011, and the second contact structure 602 is accurately electrically connected to the second sub-electrode layer 4022 on the second side. In one specific embodiment, both the fifth dielectric layer 305 and the fourth dielectric layer 304 can be silicon oxide. During the etching process to form the third opening 503, since both are silicon oxide etching, the extension 4011 can be etched and exposed in one step without changing the etching gas, thus simplifying the process. In addition, there is a fourth dielectric layer 304 between the third opening 503 and its adjacent capacitor structure layer 4. The presence of the fourth dielectric layer 304 can also prevent the breakdown effect that may occur when the first contact structure 601 is subjected to an applied voltage.
[0086] Figure 24 is a schematic diagram of a trench capacitor provided in an embodiment of this disclosure.
[0087] Please refer to Figure 24 for details. For a clearer understanding, please refer to Figures 9 to 13. The trench capacitor 100 includes a substrate 10 having a first trench 201; a first electrode layer 401 covering the first trench 201 and partially covering the surface of the substrate 10; a first dielectric layer 301 covering the first electrode layer 401; a second dielectric layer 302 covering the first dielectric layer 301, the second dielectric layer 302 including a first sub-dielectric layer 3021 located on the surface of the substrate 10 and a second sub-dielectric layer 3022 located in the first trench 201; the thickness of the first sub-dielectric layer 3021 is greater than the thickness of the second sub-dielectric layer 3022; the second electrode layer 402 covering the second dielectric layer 302; and a third dielectric layer 303 covering the second electrode layer 402 and filling the remaining portion of the first trench 201. In a specific embodiment, the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201. The second electrode layer 402 includes a first sub-electrode layer 4021 and a second sub-electrode layer 4022. The first sub-electrode layer 4021 is located on the surface of the second dielectric layer 302, and the second sub-electrode layer 4022 covers the first sub-electrode layer 4021. The dielectric constant of the first dielectric layer 301 is greater than that of the second dielectric layer 302. In one specific embodiment, the first dielectric layer 301 can be one or more of hafnium oxide, zirconium oxide, hafnium silicate, hafnium zirconate, lanthanum oxide, lanthanum silicate, barium strontium titanate, or lanthanum aluminate; the material of the second dielectric layer 302 can be one or more of silicon oxide, silicon nitride, or silicon oxynitride. In one specific embodiment, the dielectric constant of hafnium oxide is approximately 20, which is much higher than that of silicon dioxide (3.9). Between the first electrode layer 401 and the substrate 10, there is also an initial dielectric layer 301', which covers the first trench 201 and partially covers the surface of the substrate 10. The first electrode layer 401, the second electrode layer 402, the first dielectric layer 301, the second dielectric layer 302, and the initial dielectric layer 301' together constitute the capacitor structure layer 4. The capacitor structure layer 4 includes a first capacitor structure layer 41 located on the surface of the substrate 10 and a second capacitor structure layer 42 located in the first trench. The first capacitor structure layer 41 includes a first side S1 and a second side S2, which are located on opposite sides of the first trench 201. The length of the first side S1 along the direction parallel to the substrate 10 is greater than the length of the second side along the direction parallel to the substrate 10. The first electrode layer 401 of the first side S1 has an extension 4011 along the direction parallel to the substrate 10. The trench capacitor 100 also includes a fourth dielectric layer 304, which covers the third dielectric layer 303 and the extension 4011 and partially covers the substrate 10.The trench capacitor 100 also includes a contact structure 60, which includes a first contact structure 601 and a second contact structure 602. The first contact structure 601 passes through the fourth dielectric layer 304 and is electrically connected to the extension 4011. The second contact structure 602 passes through the fourth dielectric layer 304 and the third dielectric layer 303 and is electrically connected to the second sub-electrode layer 4022 of the second side S2. The depth of the first contact structure 601 is greater than the depth of the second contact structure 602, and the width C1 of the first contact structure 601 is greater than the width C2 of the second contact structure 602.
[0088] In this embodiment, a second dielectric layer 302 is formed on the surface of the first dielectric layer 301. The thickness H1 of the first sub-dielectric layer 3021 is greater than the thickness of the second sub-dielectric layer 3022, meaning the second sub-dielectric layer 3022 located on the surface of the substrate 10 is thicker. This increases the thickness of the dielectric layer between the first electrode layer 401 and the second electrode layer 402, which are prone to leakage, thereby improving the isolation performance between the first electrode layer 401 and the second electrode layer 402 and preventing leakage current. In this application, in addition to the thickness H1 of the first sub-dielectric layer 3021 being greater than the thickness H2 of the second sub-dielectric layer 3022, the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201. For those skilled in the art, the capacitance formula is C = εS / 4πkd, where ε represents the dielectric constant of the dielectric layer, k represents the electrostatic constant, S represents the area of the opposing electrode plates, and d represents the distance between the electrode plates. This formula is used to calculate the capacitance value given a dielectric layer, area, and distance. Since the capacitance value depends not only on the electrode area but also on the thickness of the dielectric layer, the smaller the thickness, the larger the capacitance value, and the larger the thickness, the smaller the capacitance value. In this application, PECVD has a weaker filling ability in the first trench 201, resulting in a thinner deposition thickness of the second sub-dielectric layer 3022 within the first trench 201. Furthermore, the thickness of the second sub-dielectric layer 3022 gradually decreases from the top of the second sub-dielectric layer 3022 to the bottom of the first trench 201. This ensures the capacitance value of the trench capacitor 100. In other words, this application not only solves the leakage problem between the first electrode layer 401 and the second electrode layer 402 but also ensures the capacitance value of the trench capacitor 100, preventing the capacitance value from decreasing due to an excessively thick dielectric layer between the first electrode layer 401 and the second electrode layer 402.
[0089] Figure 25 is a schematic diagram of the packaging structure provided in an embodiment of this disclosure.
[0090] Please refer to Figure 25 for details. The package structure includes: a circuit board 110, a package substrate 120, an adapter plate 130, and a memory 140. The package substrate 120 is located on the circuit board 110. The adapter plate 130 includes the aforementioned trench capacitor 100. The memory 140 is located on the adapter plate 130 and is electrically connected to the adapter plate 130.
[0091] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method for preparing a trench capacitor (100), characterized in that, include: A substrate (10) is provided, the substrate (10) having a first trench (201); A first electrode layer (401) is formed in the first trench (201), the first electrode layer (401) covering the first trench (201) and covering the surface of the substrate (10); A first dielectric layer (301) is formed, and the first dielectric layer (301) covers the first electrode layer (401); A second dielectric layer (302) is formed, which at least covers the first dielectric layer (301) on the surface of the substrate (10); the thickness of the second dielectric layer (302) is greater than the thickness of the first dielectric layer (301). A second electrode layer (402) is formed on the second dielectric layer (302), and the second electrode layer (402) covers the second dielectric layer (302); A third dielectric layer (303) is formed, which fills the remaining first trench (201).
2. The method for preparing the trench capacitor (100) according to claim 1, characterized in that, The second dielectric layer (302) includes a first sub-dielectric layer (3021) located on the surface of the substrate (10) and a second sub-dielectric layer (3022) located in the first trench (201); the thickness of the first sub-dielectric layer (3021) is greater than the thickness of the second sub-dielectric layer (3022); the thickness of the second sub-dielectric layer (3022) gradually decreases from the top of the second sub-dielectric layer (3022) to the bottom of the first trench (201).
3. The method for preparing the trench capacitor (100) according to claim 1, characterized in that, The second dielectric layer (302) is formed using a first deposition process, wherein the first deposition process is plasma-enhanced chemical vapor deposition.
4. The method for preparing the trench capacitor (100) according to claim 1, characterized in that, The second electrode layer (402) includes a first sub-electrode layer (4021) and a second sub-electrode layer (4022), the first sub-electrode layer (4021) is formed on the surface of the second dielectric layer (302), and the second sub-electrode layer (4022) covers the first sub-electrode layer (4021).
5. The method for preparing the trench capacitor (100) according to claim 1, characterized in that, The dielectric constant of the first dielectric layer (301) is greater than that of the second dielectric layer (302).
6. The method for preparing the trench capacitor (100) according to claim 1, characterized in that, Before forming the first electrode layer (401), the method further includes forming an initial dielectric layer (301') that covers the first trench (201) and the surface of the substrate (10).
7. The method for preparing the trench capacitor (100) according to claim 6, characterized in that, The first electrode layer (401), the second electrode layer (402), the first dielectric layer (301), the second dielectric layer (302), and the initial dielectric layer (301') together constitute a capacitor structure layer (4). After forming the third dielectric layer (303), the process further includes: removing a portion of the capacitor structure layer (4) and a portion of the third dielectric layer (303) on both sides of the first trench (201) to expose a portion of the substrate (10); the remaining capacitor structure layer (4) includes a first capacitor structure layer (41) located on the surface of the substrate (10) and a second capacitor structure layer (42) located in the first trench (201); the first capacitor structure layer (41) includes a first side (S1) and a second side (S2), the first side (S1) and the second side (S2) being located on both sides of the first trench (201); the length of the first side (S1) in the direction parallel to the substrate (10) is greater than the length of the second side (S2) in the direction parallel to the substrate (10).
8. The method for preparing the trench capacitor (100) according to claim 7, characterized in that, It also includes removing a portion of the second electrode layer (402), the first dielectric layer (301), the second dielectric layer (302), and the third dielectric layer (303) on the first side (S1) to expose the first electrode layer (401), with the exposed first electrode layer (401) serving as an extension (4011).
9. The method for preparing the trench capacitor (100) according to claim 8, characterized in that, It also includes forming a contact structure (60), the contact structure (60) including a first contact structure (601) and a second contact structure (602), the first contact structure (601) being electrically connected to the extension (4011), and the second contact structure (602) being electrically connected to the second sub-electrode layer (4022) of the second side (S2).
10. The method for preparing the trench capacitor (100) according to claim 9, characterized in that, Forming the contact structure (60) specifically includes: forming a fourth dielectric layer (304), the fourth dielectric layer (304) covering the third dielectric layer (303) and covering the extension (4011) and part of the substrate (10); forming an initial opening (50') on the fourth dielectric layer (304), the initial opening (50') including a first initial opening (501') and a second initial opening (502'), the opening size of the first initial opening (501') being larger than the opening size of the second initial opening (502'); and continuing etching along the initial opening (50') to form the first opening (501'). 1) and a second opening (502); the first opening (501) exposes the extension (4011), and the second opening (502) exposes the second sub-electrode layer (4022) of the second side (S2); the first opening (501) and the second opening (502) are filled with conductive material to form the first contact structure (601) and the second contact structure (602); the depth of the first contact structure (601) is greater than the depth of the second contact structure (602), and the first contact structure (601) and the second contact structure (602) together constitute the contact structure (60).
11. The method for preparing the trench capacitor (100) according to claim 9, characterized in that, Forming the contact structure (60) specifically includes: forming a fourth dielectric layer (304) that covers the third dielectric layer (303) and the extension (4011) and part of the substrate (10); forming an initial opening (50') on the fourth dielectric layer (304), the initial opening (50') including a first initial opening (501') and a second initial opening (502'), the opening size of the first initial opening (501') being larger than the opening size of the second initial opening (502'); forming a fifth dielectric layer (305) on the fourth dielectric layer (304), the fifth dielectric layer (305) filling the second initial opening (502') and covering the sidewalls and bottom of the first initial opening (501'), the remaining first initial opening (501') serving as a third initial opening (503'), along the third initial opening (503'). Etching is performed to form a third opening (503); a fourth initial opening (504') is formed on the second side (S2), the opening size of the fourth initial opening (504') being smaller than the opening size of the third initial opening (503'); etching continues along the fourth initial opening (504') to form a fourth opening (504); the third opening (503) exposes the extension (4011), and the fourth opening (504) exposes the second sub-electrode layer (4022) on the second side (S2); conductive material is filled into the third opening (503) and the fourth opening (504) to form a first contact structure (601) and a second contact structure (602); the depth of the first contact structure (601) is greater than the depth of the second contact structure (602), and the first contact structure (601) and the second contact structure (602) together constitute the contact structure (60).
12. A trench capacitor (100), characterized in that, include: A substrate (10) having a first trench (201); A first electrode layer (401) covers the first trench (201) and partially covers the surface of the substrate (10); A first dielectric layer (301) covers the first electrode layer (401); A second dielectric layer (302) that at least covers the first dielectric layer (301) on the surface of the substrate (10); the thickness of the second dielectric layer (302) is greater than the thickness of the first dielectric layer (301); A second electrode layer (402) is provided, which covers the second dielectric layer (302). A third dielectric layer (303) covers the second electrode layer (402) and fills the remaining first trench (201).
13. The trench capacitor (100) according to claim 12, characterized in that, The second dielectric layer (302) includes a first sub-dielectric layer (3021) located on the surface of the substrate (10) and a second sub-dielectric layer (3022) located in the first trench (201); the thickness of the first sub-dielectric layer (3021) is greater than the thickness of the second sub-dielectric layer (3022); the thickness of the second sub-dielectric layer (3022) gradually decreases from the top of the second sub-dielectric layer (3022) to the bottom of the first trench (201).
14. The trench capacitor (100) according to claim 12, characterized in that, The second electrode layer (402) includes a first sub-electrode layer (4021) and a second sub-electrode layer (4022), wherein the first sub-electrode layer (4021) is located on the surface of the second dielectric layer (302) and the second sub-electrode layer (4022) covers the first sub-electrode layer (4021).
15. The trench capacitor (100) according to claim 12, characterized in that, The dielectric constant of the first dielectric layer (301) is greater than that of the second dielectric layer (302).
16. The trench capacitor (100) according to claim 12, characterized in that, Between the first electrode layer (401) and the substrate (10), there is also an initial dielectric layer (301'), which covers the first trench (201) and a portion of the surface of the substrate (10).
17. The trench capacitor (100) according to claim 16, characterized in that, The first electrode layer (401), the second electrode layer (402), the first dielectric layer (301), the second dielectric layer (302), and the initial dielectric layer (301') together constitute a capacitor structure layer (4); the capacitor structure layer (4) includes a first capacitor structure layer (41) located on the surface of the substrate (10) and a second capacitor structure layer (42) located in the first trench (201); the first capacitor structure layer (41) includes a first side (S1) and a second side (S2), the first side (S1) and the second side (S2) are respectively located on both sides of the first trench (201); the length of the first side (S1) in the direction parallel to the substrate (10) is greater than the length of the second side (S2) in the direction parallel to the substrate (10); and the first electrode layer (401) of the first side (S1) has an extension (4011) in the direction parallel to the substrate (10).
18. The trench capacitor (100) according to claim 17, characterized in that, It also includes a fourth dielectric layer (304) that covers the third dielectric layer (303) and the extension (4011) and partially covers the substrate (10).
19. The trench capacitor (100) according to claim 18, characterized in that, It also includes a contact structure (60), which includes a first contact structure (601) and a second contact structure (602). The first contact structure (601) passes through the fourth dielectric layer (304) and is electrically connected to the extension (4011). The second contact structure (602) passes through the fourth dielectric layer (304) and the third dielectric layer (303) and is electrically connected to the second sub-electrode layer (4022) of the second side (S2). The depth of the first contact structure (601) is greater than the depth of the second contact structure (602).
20. A packaging structure, characterized in that, include: Circuit board (110); Packaging substrate (120); the packaging substrate (120) is located on the circuit board (110); Adapter board (130), the adapter board (130) comprising the trench capacitor (100) according to any one of claims 12-19; A memory (140) is located on the adapter plate (130) and is electrically connected to the adapter plate (130).