Impedance calibration circuit and impedance calibration method

Abstract

Disclosed is an impedance calibration control circuit, comprising a calibration control circuit, which is configured to output a first calibration code; a logic conversion circuit, which is configured to receive the first calibration code and a second calibration code, and output a third calibration code after performing calculation on the first calibration code and the second calibration code; and a plurality of calibrated units, which are configured to receive the third calibration code, and perform impedance adjustment on the basis of the third calibration code.

Description

Impedance calibration circuit and impedance calibration method

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411709317.2, filed on November 26, 2024, entitled "Impedance Calibration Circuit and Impedance Calibration Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to an impedance calibration circuit and impedance calibration method. Background Technology

[0004] With the rapid development of semiconductor technology, signal rise times are becoming increasingly shorter, leading to a growing concern about signal integrity. To improve signal integrity during high-speed signal propagation, DDR3 and DDR4 designs incorporate on-die termination (ODT) resistors and output drive resistors. This impedance matching of the transmission line using ODT and output drive resistors reduces energy loss and reflection during transmission, ensuring the correctness and integrity of the received signal. The accuracy of the ODT and output drive resistors is crucial for improving signal correctness and integrity. However, due to the influence of chip manufacturing, testing, and packaging technologies, the actual resistance values ​​of ODT and output drive resistors often have some error. Furthermore, due to these errors and limitations in adjustment precision, the linearity of ODT and output drive resistor adjustments in related technologies is poor, making it difficult to accurately obtain the required standard design resistance values ​​and resulting in poor matching with the transmission line resistance. Therefore, memory systems require ZQ calibration of the relevant ODT and output drive resistor values.

[0005] In integrated circuit design, different ODT resistors and output drive resistors typically share the same ZQ calibration result to simplify design and ensure signal integrity. However, due to process technology limitations, even after calibration, the ODT and output drive resistors for some DQs may be adjusted to the desired values, while the ODT and output drive resistors for other DQs may exceed the expected range. This results in significant differences in the ODT and output drive resistor values ​​for different DQs within the same memory. Inconsistencies in ODT and output drive resistor values ​​negatively impact signal integrity during high-speed data transmission testing, potentially leading to signal reflection, crosstalk, and other problems, thus affecting data transmission accuracy and system performance. Therefore, reducing ZQ calibration errors is a crucial technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned problems, one embodiment of this disclosure provides an impedance calibration control circuit, comprising:

[0007] The calibration control circuit is configured to output the first calibration code;

[0008] The logic conversion circuit is configured to receive the first calibration code and the second calibration code, and after calculating the first calibration code and the second calibration code, output the third calibration code;

[0009] Multiple calibrated units are configured to receive the third calibration code and perform impedance adjustment based on the third calibration code.

[0010] In some embodiments, when the calibrated unit adjusts the calibration resistance value to the target resistance value, the logic conversion circuit is further configured to perform bias latching on the second calibration code corresponding to the third calibration code.

[0011] In some embodiments, a plurality of the logic conversion circuits are connected to each of the calibrated units.

[0012] In some embodiments, the calibrated unit is a pull-up calibrated unit, and multiple pull-up calibrated units are connected in parallel.

[0013] In some embodiments, the pull-up calibration unit includes a plurality of PMOS transistors connected in parallel.

[0014] In some embodiments, the calibrated unit is connected to a reference resistor, and the logic conversion circuit includes a full adder.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure also provides an impedance calibration method, including:

[0016] Determine the initial reference voltage for the impedance calibration circuit and latch the initial reference voltage.

[0017] Under the initial reference voltage, the impedance calibration circuit is traversed through multiple calibrated units until the calibration resistance value of each calibrated unit is adjusted to the target resistance value.

[0018] In some embodiments, determining an initial reference voltage for the impedance calibration control circuit and latching the initial reference voltage includes: selecting one of the calibrated units as an initial calibrated unit; adjusting the calibration resistance value of the initial calibrated unit under different reference voltages until the calibration resistance value of the initial calibrated unit is the target resistance value; and determining and latching the initial reference voltage corresponding to the target resistance value.

[0019] In some embodiments, under the initial reference voltage, the plurality of calibrated units of the impedance calibration circuit are traversed until the calibration resistance value of each calibrated unit is adjusted to the target resistance value, and the method further includes latching the bias level corresponding to the target resistance value of each calibrated unit.

[0020] In some embodiments, the target resistance value is the same for each of the calibrated units.

[0021] The technical solutions provided in this disclosure have at least the following advantages:

[0022] On the one hand, by setting a logic conversion circuit between the calibration control circuit and the calibrated unit, the logic conversion circuit is configured to receive the first calibration code and the second calibration code, and after calculating the first calibration code and the second calibration code, output the third calibration code; multiple calibrated units are configured to receive the third calibration code and adjust the interface impedance of the memory, thereby realizing the fine adjustment of the adjustment resistance value of each calibrated unit, so that the calibration resistance value of each calibrated unit can reach the target resistance value.

[0023] On the other hand, after determining the initial reference voltage of the impedance calibration control circuit and latching the initial reference voltage, the calibration resistance of each calibration unit is adjusted by traversing multiple calibration units of the impedance calibration control circuit under the initial reference voltage until the calibration resistance of each calibration unit is the target resistance value. This improves the consistency of different impedance adjustments and ensures the integrity of the signal during data transmission. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 is a functional block diagram of an impedance calibration circuit provided in an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of the circuit structure of a calibration unit provided in an embodiment of this disclosure;

[0027] Figure 3 is a flowchart of a calibration method provided in an embodiment of this disclosure;

[0028] Figure 4 is a functional block diagram of a memory provided in an embodiment of this disclosure;

[0029] Figure 5 is a functional block diagram of a storage system provided in an embodiment of this disclosure. Detailed Implementation

[0030] In integrated circuit design, on-die termination (ODT) and output drive resistor technologies are widely used to address the signal integrity challenges of high-speed data transmission. ODT achieves impedance matching by integrating termination resistors within the memory, effectively reducing signal reflection and improving signal quality. Output drive resistors, in high-speed signal transmission, match the load resistance and the characteristic impedance of the transmission line, reducing signal reflection and signal integrity issues. However, due to technological limitations in chip manufacturing, testing, and packaging, the actual resistance values ​​of ODT resistors and output drive resistors may deviate from the design values. This deviation can affect signal accuracy and integrity, especially in high-speed data transmission scenarios, where even small resistance differences can lead to signal reflection and crosstalk, thus impacting data transmission accuracy and overall system performance.

[0031] To overcome this issue, a ZQ calibration mechanism is introduced into memory design. ZQ calibration is a correction process used to adjust the values ​​of the ODT resistor and output drive resistor to match design standards. Through ZQ calibration, the ODT resistor and output drive resistor can be adjusted to more closely approximate the ideal impedance of the transmission line, thereby improving signal integrity. In the design, the ODT resistor and output drive resistor on different DQ lines typically share the same ZQ calibration result to simplify the design and ensure consistent signal integrity. However, due to differences in manufacturing processes, even after ZQ calibration, the resistance values ​​of the ODT resistor and output drive resistor on different DQ lines may still vary. This difference can lead to signal crosstalk, especially in high-speed data transmission tests, negatively impacting signal integrity and consequently affecting data transmission accuracy and system performance.

[0032] To address the aforementioned technical problems, this disclosure provides an impedance calibration control circuit and an impedance calibration method. The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] The impedance calibration control circuit provided in the embodiments of this disclosure will be described below with reference to the accompanying drawings. Figure 1 is a functional block diagram of an impedance calibration circuit provided in an embodiment of this disclosure; Figure 2 is a schematic diagram of the circuit structure of a calibrated unit provided in an embodiment of this disclosure.

[0034] Referring to Figure 1, the impedance calibration circuit 100 provided in this embodiment includes: a calibration control circuit 101 configured to output a first calibration code ZQPU<5:0>; a logic conversion circuit 102 configured to receive the first calibration code ZQPU<5:0> and a second calibration code ZQPU_CM<3:0>, calculate the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>, and output a third calibration code ZQPU_loc_dqm_<5:0>; and a plurality of calibration units 103 configured to receive the third calibration code ZQPU_loc_dqm_<5:0> and perform impedance adjustment according to the third calibration code ZQPU_loc_dqm_<5:0>.

[0035] In some embodiments, the calibration control circuit 101 is further configured to receive a data calibration command Enter_Cal and an exit calibration command Exit_Cal. For example, when the calibration control circuit 101 receives the data calibration command Enter_Cal, it begins calibrating the unit 103 to be calibrated; when it receives the exit calibration command Exit_Cal, it stops calibrating the unit 103 to be calibrated. Specifically, when the calibration control circuit 101 receives the data calibration command Enter_Cal and begins calibrating the unit 103 to be calibrated, the power control signal PUP is driven low by the calibration control circuit 101. At this time, the PMOS transistor MP7 connected to VDDQ is turned on to provide power supply voltage during the calibration process of the unit 103 to be calibrated.

[0036] In some embodiments, the logic conversion circuit 102 is configured to receive a first calibration code ZQPU<5:0> and a second calibration code ZQPU_CM<3:0>, calculate the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>, and output a third calibration code ZQPU_loc_dqm_<5:0>, wherein the first calibration code ZQPU<5:0> represents ZQPU <0> ~ZQPU <5> The set of corresponding calibration codes for each bit, where the second calibration code ZQPU_CM<3:0> represents ZQPU_CM. <0> ~ZQPU_CM <3> The set of corresponding calibration codes for each bit, the third calibration code ZQPU_loc_dqm_<5:0> represents ZQPU_loc_dqm_ <0> ~ZQPU_loc_dqm_ <5> The set of corresponding calibration codes for each bit, the third calibration code ZQPU_loc_dqm_<5:0> can be any one of ZQPU_loc_dq0_<5:0> to ZQPU_loc_dqn+1_<5:0>. Specifically, during the calibration of the unit 103, the first calibration code ZQPU<5:0> can be a fixed value, and the logic conversion circuit 102 can include a full adder. The first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0> are calculated by the full adder to obtain the third calibration code ZQPU_loc_dqm_<5:0>, as shown in Table 1. For example, when the first calibration code ZQPU<5:0> is "000000" and the second calibration code ZQPU_CM<3:0> is "0000", the third calibration code ZQPU_loc_dqm_<5:0> calculated by the full adder is "000000". It is understandable that after receiving the third calibration code ZQPU_loc_dqm_<5:0>, the calibration unit 103 can adjust the calibration resistance value of the calibration unit 103 to the target resistance value.

[0037] Table 1 Logical Transition Table

[0038] In some embodiments, multiple logic conversion circuits 102 are connected to each calibrated unit 103. It is understood that one logic conversion circuit 102 is connected to one calibrated unit 103, thereby enabling fine-tuning of the calibration resistance value of each calibrated unit 103, ensuring that the calibration resistance value of each calibrated unit 103 reaches the target resistance value. The target resistance value is the resistance value required for the interface impedance calibration of the calibrated unit to the memory, i.e., the target resistance value is set according to the impedance calibration requirements of the memory's data input / output signal DQ. For example, it can be the calibration resistance value specified in the design specification (SPEC: Standard Performance Evaluation Organization). Exemplarily, referring to FIG1, multiple logic conversion circuits 102 (DQ0 Adder…DQ ... n+1Adder) corresponds to multiple calibrated units 103 (DQ0 Local Block…DQ) respectively. n+1 Local Block), where n can be an integer greater than or equal to 1, for example, n can be 14, and multiple logic conversion circuits 102 can be DQ0 Adder…DQ 15 Adder, multiple calibrated units 103 can be DQ0 Local Block…DQ 15 Local Block, or n can be 6, multiple logic conversion circuits 102 can be DQ0 Adder...DQ7 Adder, multiple calibration units 103 can be DQ0 Local Block...DQ7 Local Block, which are not limited here.

[0039] In some embodiments, when the calibration resistance value of the calibrated unit 103 is adjusted to the target resistance value, the logic conversion circuit 102 is further configured to bias and latch the second calibration code ZQPU_CM<3:0> corresponding to the third calibration code ZQPU_loc_dqm_<5:0>. Specifically, the second calibration code ZQPU_CM<3:0> corresponding to the third calibration code ZQPU_loc_dqm_<5:0> can be programmed through the redundant circuit corresponding to the logic conversion circuit 102, thereby achieving a fixed bias of the third calibration code ZQPU_loc_dqm_<5:0>. The third calibration code ZQPU_loc_dqm_<5:0> can be any one of ZQPU_loc_dq0_<5:0> to ZQPU_loc_dqn+1_<5:0>.For example, referring to Table 1-2, taking multiple logic conversion circuits 102 as DQ0 Adder…DQ7 Adder and multiple calibrated units 103 as DQ0 Local Block…DQ7 Local Block as an example, when the target resistance of the calibrated unit 103 is 40Ω, after the calibrated unit 103 (DQ0 Local Block) traverses ZQPU_CM<3:0>, it confirms that the corresponding setting of the logic conversion circuit 102 is "1". At this time, the logic conversion circuit 102 burns the bias setting corresponding to ZQPU_CM<3:0> to the logic conversion circuit 102 (DQ0…DQ7 Local Block). In the redundant circuit corresponding to Adder), the first calibration code ZQPU<5:0> "000000" is then logically operated on the fixed calibration code Fuse_dq0<3:0> fixed in the redundant circuit in the logic conversion circuit 102 to obtain the third calibration code ZQPU_loc_dq0_<5:0>, which is the third calibration code ZQPU_loc_dq0_<5:0> "00001" after logical operation on the second calibration code ZQPU_CM<3:0> "0001" corresponding to position "1". When the calibrated unit 103 (DQ1 Local Block) reaches the target resistance value, the corresponding position of the logic conversion circuit 102 is "2". Then, the logic conversion circuit 102 will burn the bias position corresponding to the second calibration code ZQPU_CM<3:0> "0010" corresponding to position "2" into the logic conversion circuit 102 (DQ1 Local Block). In the redundant circuit corresponding to Adder), the first calibration code ZQPU<5:0> "000000" is then logically operated in the logic conversion circuit 102 to obtain the third calibration code ZQPU_loc_dq1_<5:0> "000010", which is the third calibration code ZQPU_loc_dq1_<5:0> after logical operation of the second calibration code ZQPU_CM<3:0> corresponding to gear "2". This process continues until the resistance value adjustment of all calibrated units 103 is completed, that is, the adjustment of all calibrated units 103 ends when the calibration resistance value of all calibrated units 103 reaches the target resistance value. When the calibrated unit 103 reaches the target resistance value, the value of the second calibration code ZQPU_CM<3:0> is the same as that of the fixed calibration code Fuse_dq1<3:0>.

[0040] Table 2. Calibrated Unit Gear Correspondence Table

[0041] In some embodiments, referring to FIG1-2, the calibration control circuit 101 further includes a comparator. When the calibration resistance value of the calibration unit 103 is adjusted to the target resistance value, the pull-up voltage VPULL_UP on both sides of the DQ pin is compared with the target reference voltage Vref_ZQPU to finally output the adjusted first calibration code ZQPU<5:0>.

[0042] In some embodiments, before the logic conversion circuit 102 calculates the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>, the calibration control circuit 101 can first perform a preliminary adjustment on the calibrated unit 103 to determine the initial reference voltage Vref_ZQPU. Specifically, one of the multiple calibrated units 103 can be selected as the initial calibrated unit. Under different reference voltages, the adjustment resistance value of the initial calibrated unit is adjusted until the calibration resistance value of the initial calibrated unit is the target resistance value. Then, the initial reference voltage Vref_ZQPU corresponding to the target resistance value is determined and the initial reference voltage Vref_ZQPU is latched. It should be noted that when the calibration control circuit 101 performs preliminary calibration on the unit 103 being calibrated, the logic conversion circuit 102 can be in a non-operating state. That is, it can be understood that the calibration control circuit 101 is directly electrically connected to the unit 103 being calibrated, and the latched initial reference voltage Vref_ZQPU can be set as the reference voltage when the logic conversion circuit 102 performs traversal logic operations on the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>.

[0043] In some embodiments, referring to FIG2, the calibration unit 103 is connected between the power supply voltage VDDQ and the DQ pin, and includes a plurality of parallel metal-oxide-semiconductor (MOS) transistors. The MOS transistors can be P-channel metal-oxide-semiconductor (PMOS) transistors. Exemplarily, the number of PMOS transistors can be set to 6 to 10 according to the calibrated resistance value specified in the SPEC, which is not limited here. The calibration control circuit 103 can control different numbers of PMOS transistors to be turned on by adjusting the first calibration code ZQPU<5:0>.

[0044] In some embodiments, the calibration unit 103 is a pull-up calibration unit, and multiple pull-up calibration units are connected in parallel. In other embodiments, the calibration unit 103 may also be a pull-down adjustment circuit or a combination of both, which is not limited here. Referring to FIG2, taking the calibration unit 103 as a pull-up calibration unit as an example, the pull-up calibration unit may have 6 pull-up transistors MP0 to MP5 connected in parallel; before the logic conversion circuit 102 calculates the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>, each calibration code of the first calibration code ZQPU<5:0> (the first calibration code ZQPU... <0> ~ZQPU <5> One of them) corresponds to turning on / off a pull-up transistor (one of pull-up transistors MP0 to MP5). Pull-up transistors MP0 to MP5 can be PMOS transistors. For example, when the first calibration code ZQPU<5:0> is "000000", pull-up transistors MP0 to MP5 are all turned on. During the calculation of the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0> by the logic conversion circuit 102, that is, when calibrating the calibrated unit 103 (DQ0 Local Block), each calibration code of the third calibration code ZQPU_loc_dq0_<5:0> (the first calibration code ZQPU) is turned on / off. <0> ~ZQPU <5> One of them corresponds to turning on / off a pull-up transistor (one of the pull-up transistors MP0 to MP5). For example, when the third calibration code ZQPU_loc_dq0_<5:0> is “000110”, pull-up transistors MP0, MP3, MP4, and MP5 are turned on, and MP1 and MP2 are turned off.

[0045] In addition, the pull-up calibration unit also includes a comparator transistor MP6 connected in parallel with the pull-up transistors MP0 to MP5. The source or drain of one end of the comparator transistor MP6 is connected to the DQ pin. Referring to Figure 2, the transistor MP6 can be kept in a normally open state by the normally open signal Puman in the memory to compare the resistance on both sides of the DQ pin, thereby adjusting the impedance of the calibration unit 103 according to the comparison result.

[0046] The DQ pin is the primary channel for data exchange between the memory and external systems (such as the CPU or memory controller). During read operations, the DQ pin outputs data stored in the memory to the external system; during write operations, it receives data from the external system and stores it in the memory. For example, when DQ is used as an output, a pull-up or pull-down calibration unit is connected to DQ, and the calibration resistance value output by the corresponding pull-up or pull-down calibration unit is adjusted by controlling the number of transistors turned on in the pull-up or pull-down calibration unit, thereby ultimately calibrating the impedance of the DQ pin.

[0047] During impedance calibration, the impedance calibration circuit 100 adjusts the output impedance of the unit 103 to be calibrated by comparing it with an external standard resistor to meet the calibration resistance value specified in the design specifications (SPEC: Standard Performance Evaluation Organization). In some embodiments, the unit 103 to be calibrated further includes a reference resistor RZQ, the resistance of which is 40–240 Ω. The reference resistor RZQ, as an external standard resistor, does not change with environmental factors and can serve as a reference resistor when the calibration resistance value required by the calibration unit 103 is reached, thereby achieving accurate adjustment of the impedance of the calibration unit 103. For example, when the unit 103 to be calibrated includes both a pull-up calibrated unit and a pull-down calibrated unit, the pull-down calibrated unit of the unit 103 can be calibrated first using an external 240-ohm standard resistor, and then the calibrated pull-down calibrated unit can be used to calibrate the pull-up calibrated unit of the unit 103, so that the pull-up calibrated unit also meets the preset impedance requirements. Since both the pull-up and pull-down units of the calibration unit 103 are composed of transistors, their equivalent resistance is greatly affected by process, voltage, and temperature (PVT). Therefore, the final calibration result may be somewhat deviated. In this embodiment, multiple logic conversion circuits 102 are connected to each calibration unit 103, thereby realizing the fine adjustment of the calibration resistance value of each calibration unit 103. This ensures that the calibration resistance value of each calibration unit 103 can reach the target resistance value, avoiding the deviation of calibration results caused by process conditions, improving the accuracy of calibration results, and thus ensuring the integrity of the signal.

[0048] Accordingly, another embodiment of this disclosure provides an impedance calibration method. Figure 3 is a flowchart of calibration provided in an embodiment of this disclosure, Figure 4 is a functional block diagram of a memory provided in an embodiment of this disclosure, and Figure 5 is a functional block diagram of a storage system provided in an embodiment of this disclosure. The impedance calibration method provided in this embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to the above embodiments will not be described in detail below.

[0049] S100 determines the initial reference voltage of the impedance calibration control circuit and latches the initial reference voltage.

[0050] In some embodiments, referring to Figures 1-3, determining the initial reference voltage Vref_ZQPU of the impedance calibration control circuit 100 and latching the initial reference voltage Vref_ZQPU includes: selecting a calibration unit 103 as the initial calibration unit; adjusting the calibration resistance value of the initial calibration unit under different reference voltages until the calibration resistance value of the initial calibration unit is the target resistance value; determining the initial reference voltage Vref_ZQPU corresponding to the target resistance value; and latching the initial reference voltage Vref_ZQPU. Specifically, the number of calibration units 103 can be 8, 16, or 32, which is not limited here. One of the calibration units 103 can be randomly selected as the initial calibration unit or selected according to the calibration requirements. It should be noted that when the calibration control circuit 101 performs preliminary calibration on the calibration unit 103, the logic conversion circuit 102 is in a non-operating state, which can be understood as the calibration control circuit 101 being directly electrically connected to the calibration unit 103. The reference voltage is set by the calibration control circuit 101. Under different reference voltages, the value of the first calibration code ZQPU<5:0> is different. For example, when the reference voltage is 260mV, the corresponding first calibration code ZQPU<5:0> can be "000001", and when the reference voltage is 240mV, the corresponding reference voltage is "010010". Referring to Figure 2, the calibration unit 103 is configured to receive a first calibration code or a third calibration code. During the stage of determining the initial reference voltage of the impedance calibration control circuit 100, the calibration unit 103 is configured to receive the first calibration code, thereby turning on different numbers of PMOS transistors. Taking the calibration unit 103 as a pull-up calibration unit as an example, the pull-up calibration unit can be six pull-up transistors MP0 to MP5 connected in parallel. When the reference voltage is 260mV, the first calibration code ZQPU<5:0> is "000001", the pull-up transistor MP0 is turned off, and MP1, MP2, MP3, MP4, and MP5 are turned on. If the initial calibration unit reaches the target resistance value at this time, the reference voltage at this time is determined as the initial reference voltage Vref_ZQPU. For example, the initial reference voltage Vref_ZQPU at this time can be determined as 260mV. After determining the initial reference voltage Vref_ZQPU, the corresponding redundant circuit can be enabled by the calibration control circuit 101 to latch the initial reference voltage Vref_ZQPU at this time.

[0051] In some embodiments, when adjusting the initial calibrated unit, the reference voltage of the calibrated units 103 other than the initial calibrated unit is the same as the reference voltage of the initial calibrated unit. That is, when the initial calibrated unit is adjusted, the remaining calibrated units are also adjusted synchronously. When the calibration resistance value of the initial calibrated unit is adjusted to the target resistance value, the reference voltage at this time is determined to be the initial reference voltage Vref_ZQPU. It should be noted that as the physical size of the memory continues to shrink, due to the influence of the process technology, there will be certain differences between the transistors in different calibrated units 103. When the initial calibrated unit reaches the target resistance value under the initial reference voltage, the remaining calibrated units 103 may have a resistance value exceeding or falling below the target resistance value. This may affect the signal integrity in high-speed testing. Therefore, it is necessary to further calibrate the remaining calibrated units 103 so that the remaining calibrated units also reach the target resistance value.

[0052] Under the initial reference voltage Vref_ZQPU, S200 traverses multiple calibrated cells 103 until the calibration resistance value of each calibrated cell 103 is adjusted to the target resistance value. Specifically, referring to Figures 1-3, when the initially calibrated unit reaches the target resistance value under the initial reference voltage Vref_ZQPU, the impedance calibration control circuit 10 can enter the test mode by sending a test command to the memory through the test equipment. The impedance calibration circuit 100 may include a calibration control circuit 101, a logic conversion circuit 102, and multiple calibrated units 103. The calibration control circuit 101 is configured to generate a first calibration code ZQPU<5:0> for determining the target resistance. The logic conversion circuit 102 is configured to receive the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>. The second calibration code ZQPU_CM<3:0> can be a calibration code generated by the memory after receiving the test command sent by the test equipment. It should be noted that after entering the test mode, when the initial reference voltage Vref_ZQPU is determined, the first calibration code ZQPU<5:0> can remain unchanged during the calibration of the calibration unit 103.

[0053] In some embodiments, under an initial reference voltage Vref_ZQPU, the step of traversing a plurality of calibrated units 103 of the impedance calibration circuit 100 until the calibration resistance value of each calibrated unit 103 is adjusted to the target resistance value further includes latching the bias level corresponding to the target resistance value of each calibrated unit 103. For example, multiple logic conversion circuits 102 are connected to each calibrated unit 103. It can be understood that each logic conversion circuit 102 is connected to each calibrated unit 103. That is, each logic conversion circuit is configured to receive the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>, and calculate the received first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0> to obtain the third calibration code ZQPU_loc_dqm_<5:0>. The multiple calibrated units 103 are configured to receive the third calibration code ZQPU_loc_dqm_<5:0> until the adjustment calibration resistance value of the calibrated unit 103 is adjusted to the target resistance value. Referring to Figures 1-2, during the calibration of the unit 103, with the initial reference voltage Vref_ZQPU determined, the first calibration code ZQPU<5:0> is a fixed value. The logic conversion circuit 102 can be a full adder. The first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0> are calculated by the full adder to obtain the third calibration code ZQPU_loc_dqm_<5:0>. For example, when the first calibration code ZQPU<5:0> is “000000” and the second calibration code ZQPU_CM<3:0> is “0001”, the third calibration code ZQPU_loc_dqm_<5:0> calculated by the full adder is “000001”.When one of the logic conversion circuits 102 calculates and outputs the third calibration code ZQPU_loc_dqm_<5:0>, and calibrates the corresponding connected calibration unit 103 to achieve the required target resistance value, after the calibration unit 103 (DQ0 Local Block) traverses ZQPU_CM<3:0>, it confirms that the corresponding setting of the logic conversion circuit 102 is "1". At this time, the logic conversion circuit 102 burns the bias setting corresponding to ZQPU_CM<3:0> to the logic conversion circuit 102 (DQ0... In the redundant circuit corresponding to Adder), the first calibration code ZQPU<5:0> is then logically operated on the fixed calibration code Fuse_dq0<3:0> fixed in the redundant circuit in the logic conversion circuit 102 to obtain the third calibration code ZQPU_loc_dq0_<5:0>, which is the third calibration code ZQPU_loc_dq0_<5:0> after the logical operation of the second calibration code ZQPU_CM<3:0> corresponding to position "1". After the resistance value of one of the calibrated units 103 is adjusted, the remaining logic conversion circuits 102 continue to receive the first calibration code ZQPU<5:0> and the second calibration code ZQPU_CM<3:0>. When the calibrated unit 103 (DQ1 Local Block) reaches the target resistance value, the corresponding position of the logic conversion circuit 102 is "2". Then the logic conversion circuit 102 will burn the bias position corresponding to the second calibration code ZQPU_CM<3:0> corresponding to position "2" to the logic conversion circuit 102 (DQ1 Local Block). In the redundant circuit corresponding to Adder), the first calibration code ZQPU<5:0> is then logically operated on in the logic conversion circuit 102 to obtain the third calibration code ZQPU_loc_dq0_<5:0>, which is the third calibration code ZQPU_loc_dq1_<5:0> after the logical operation of the second calibration code ZQPU_CM<3:0> corresponding to gear "2". This process continues until the resistance value adjustment of all calibrated units 103 is completed, that is, the adjustment of all calibrated units 103 ends when the calibration resistance value of all calibrated units 103 reaches the target resistance value. The bias setting can be understood as the value of the fixed calibration code Fuse_dq1<3:0> corresponding to the second calibration code ZQPU_CM<3:0> after it is burned into the redundant circuit when the calibrated unit 103 reaches the target resistance value. That is, the value of the second calibration code ZQPU_CM<3:0> is the same as the value of the burned fixed calibration code Fuse_dq1<3:0>. The fixed calibration code Fuse_dqm<3:0> of the redundant circuit can be any one of Fuse_dq1<3:0> to Fuse_dqn+1<3:0>.

[0054] Multiple logic conversion circuits 102 are connected to each calibrated unit 103, and the calibration resistance of each calibrated unit 103 is precisely adjusted according to the difference between the calibration resistance value and the target resistance value of each calibrated unit. This achieves fine-tuning of the calibration resistance value of each calibrated unit 103, so that the calibration resistance value of each calibrated unit 103 can reach the target resistance value. The target resistance value is the resistance value required for the interface impedance calibration of the calibrated unit to the memory. That is, the target resistance value is set according to the impedance calibration requirements of the data input / output signal DQ of the memory. For example, it can be the calibration resistance value specified by the design specification (SPEC: Standard Performance Evaluation Organization).

[0055] In some embodiments, the target resistance value of each calibrated unit 103 can be the same, that is, multiple calibrated units 103 can be adjusted to achieve the same target resistance value. For example, the target resistance value can all be 40Ω. In other embodiments, the target resistance value of each calibrated unit 103 can also be different, which is not limited here.

[0056] In some embodiments, after the calibration control circuit 101 receives the Exit_Cal command to end the calibration, the multiple calibrated units 103 can have multiple different resistance values. For example, the reference resistor RZQ has a resistance of 240Ω. After calibration, the resistance values ​​obtainable through the calibrated units 103 include 240Ω, 120Ω, 80Ω, and 40Ω. During ODT circuit adjustment, the ODT resistance value can be adjusted to different values ​​such as 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, and 34Ω by selecting suitable calibrated units 103, i.e., by changing the number of transistors in the calibrated unit 103 or the number of calibrated units 103 connected in parallel. It is understood that the number of transistors included in each calibrated unit 103 can be the same or different.

[0057] In some embodiments, referring to Figures 4-5, the memory 10 can be any of various memory devices supporting high-speed operation. Exemplarily, the memory can include, but is not limited to, DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory. Exemplarily, the memory 10 is provided with an impedance calibration circuit 100. The memory 10 can respond to an impedance calibration command sent by the memory controller 20 and perform a calibration operation on the DQ pin impedance of the memory 10 based on the calibrated plurality of calibrated units 103. For example, in response to an impedance calibration command sent by the memory controller 20, i.e., after the calibration control circuit 101 in the impedance calibration circuit 100 receives the data calibration command Enter_Cal, it begins to calibrate the impedance of the plurality of calibrated units 103. Furthermore, the memory controller 20 can also send a stop calibration command to the memory 10; that is, when the calibration control circuit receives the exit calibration command Exit_Cal, it stops calibrating the impedance of the plurality of calibrated units 103.

[0058] Before the memory 10 sends and / or receives data, an impedance calibration operation is performed by the impedance calibration circuit 100. After calibration, the input / output impedance of the memory 10 is adjusted to reduce or eliminate impedance mismatch between the memory 10 and the memory controller 20, thereby facilitating high-speed data transmission.

[0059] Another embodiment of this disclosure also provides a storage system. Referring to FIG5, the memory system 30 includes at least one memory 10 and a memory controller 20 coupled to the at least one memory. The memory system 30 may be implemented in a modular structure such as a dual-inline-memory module (DIMM) or a high-bandwidth memory (HBM) device, in which the memory 10 and the memory controller 20 are integrated into a single substrate. Under the control of a host or test instrument, the memory controller 20 may send write commands, read commands, and impedance calibration commands to the memory 10. The memory 10 may perform a write operation in response to a write command, a read operation in response to a read command, and an impedance calibration operation in response to an impedance calibration command.

[0060] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. An impedance calibration circuit (100), comprising: The calibration control circuit (101) is configured to output the first calibration code (ZQPU<5:0>); The logic conversion circuit (102) is configured to receive the first calibration code (ZQPU<5:0>) and the second calibration code ZQPU_CM<3:0>, and after calculating the first calibration code (ZQPU<5:0>) and the second calibration code (ZQPU_CM<3:0>), output the third calibration code (ZQPU_loc_dqm_<5:0>); Multiple calibrated units (103) are configured to receive the third calibration code (ZQPU_loc_dqm_<5:0>) and perform impedance adjustment according to the third calibration code (ZQPU_loc_dqm_<5:0>).

2. The impedance calibration circuit (100) according to claim 1, characterized in that, When the calibration resistance of the calibrated unit (103) is adjusted to the target resistance, the logic conversion circuit (102) is also configured to perform bias latching on the second calibration code (ZQPU_CM<3:0>) corresponding to the third calibration code (ZQPU_loc_dqm_<5:0>).

3. The impedance calibration circuit (100) of claim 1, characterized in that, The plurality of logic conversion circuits (102) are connected to each of the calibrated units (103).

4. The impedance calibration circuit (100) of claim 1, wherein, The calibrated unit (103) is a pull-up calibrated unit (103), and multiple pull-up calibrated units (103) are connected in parallel.

5. The impedance calibration circuit (100) according to claim 4, characterized in that, The pull-up calibration unit (103) includes multiple PMOS transistors connected in parallel.

6. The impedance calibration circuit (100) according to claim 5, characterized in that, The logic conversion circuit (102) includes a full adder.

7. An impedance calibration method, comprising: Determine the initial reference voltage (Vref_ZQPU) of the impedance calibration circuit (100) and latch the initial reference voltage (Vref_ZQPU); Under the initial reference voltage (Vref_ZQPU), the plurality of calibrated units (103) of the impedance calibration circuit (100) are traversed until the calibration resistance value of each calibrated unit (103) is adjusted to the target resistance value.

8. The impedance calibration method according to claim 7, characterized in that, Determining the initial reference voltage (Vref_ZQPU) of the impedance calibration circuit (100) and latching the initial reference voltage (Vref_ZQPU) includes: Select one of the calibrated units (103) as the initial calibrated unit (103); Under different reference voltages, the calibration resistance value of the initial calibration unit (103) is adjusted until the calibration resistance value of the initial calibration unit (103) is the target resistance value. Then, the initial reference voltage (Vref_ZQPU) corresponding to the target resistance value is determined and latched.

9. The impedance calibration method according to claim 8, characterized in that, Under the initial reference voltage (Vref_ZQPU), the multiple calibrated units (103) of the impedance calibration circuit (100) are traversed until the calibration resistance value of each calibrated unit (103) is adjusted to the target resistance value, and the bias range corresponding to the target resistance value of each calibrated unit (103) is latched.

10. The impedance calibration method according to claim 8, characterized in that, The target resistance value is the same for each of the calibrated units (103).

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