LVDS transmission system

Abstract

Provided in the present invention is an LVDS transmission system, comprising an LVDS sending apparatus and a first receiving apparatus, wherein the LVDS sending apparatus is connected to the first receiving apparatus by means of a first LVDS bus, which comprises an LVDS clock line and a plurality of LVDS data lines, the LVDS sending apparatus sends data to the first receiving apparatus by means of the first LVDS bus, and the first receiving apparatus can eliminate delay skew among the LVDS clock line and the plurality of LVDS data lines, and receive the data by means of the first LVDS bus. The present invention can support LVDS data transmission schemes having relatively high rates and relatively long ranges.

Description

LVDS transmission system Technical Field

[0001] This invention relates to the field of data transmission, and in particular to an LVDS transmission system and an LVDS receiving device. Background Technology

[0002] LVDS (Low Voltage Differential Signaling) bus, or simply LVDS bus, uses extremely low voltage swing for high-speed differential data transmission. It enables point-to-point or point-to-multipoint connections and features high efficiency, low power consumption, high speed, low cost, low noise interference, and support for high resolutions. LVDS is widely used in telecommunications, consumer electronics, automotive, and medical instruments where signal integrity, low jitter, and common-mode characteristics are critical. An LVDS bus consists of an LVDS clock line and multiple LVDS data lines. Both the LVDS clock line and each LVDS data line use differential signal transmission; that is, each LVDS clock line and each LVDS data line contains a pair of differential signal lines. The Open LDI (Open LVDS Display Interface) standard, based on the LVDS bus, was proposed and drafted by National Semiconductor in 1999. It is a transmission protocol using the LVDS bus as the physical layer, aiming to establish an open standard for digital connections between display sources and display devices. It incorporates the work of other widely used standards such as the Video Electronics Standards Association (VESA) and the American National Standards Institute (ANSI), providing a fully digital, plug-and-play interface that ensures clear, sharp video images on digital display devices. In Open LDI, the data rate transmitted on each LVDS data line is seven times the clock frequency transmitted on each LVDS clock line.

[0003] During the transmission of data signals from the transmitting device to the receiving device via the LVDS bus, differences in transmission medium, transmission speed, and transmission path will cause a certain delay deviation between the clock line and data signal received by the receiving device. This greatly limits the use of LVDS in many high-speed, long-distance application scenarios. Summary of the Invention

[0004] The problem this invention aims to solve is: how to eliminate the delay deviation between LVDS clock lines and multiple LVDS data lines in high-speed, long-distance LVDS transmission scenarios.

[0005] To address the problems in the prior art, the present invention adopts the following technical solution: As an LVDS transmission system of the present invention, it includes an LVDS transmitting device and a first receiving device. The LVDS transmitting device is connected to the first receiving device through a first LVDS bus. The first LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS transmitting device transmits data to the first receiving device through the first LVDS bus. The first receiving device includes an LVDS alignment module, which is used to eliminate the delay deviation of the LVDS clock line and multiple LVDS data lines and to receive data from the first LVDS bus.

[0006] Preferably, the LVDS alignment module includes a phase-locked loop (PLL) module connected to the LVDS clock line, and uses the LVDS clock line as the reference clock for the PLL module to generate one or more sampling clocks for sampling the data transmitted on the LVDS data line.

[0007] Furthermore, the LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more data line delay modules delay one or more LVDS data lines respectively, so that the sampling clock can correctly sample the data.

[0008] Furthermore, the LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

[0009] Furthermore, the LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

[0010] Preferably, the LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

[0011] Preferably, the LVDS transmission system further includes a second receiving device, and the first receiving device further includes a transmitting module connected to the second receiving device. The first receiving device forwards data received from the first LVDS bus to the second receiving device through the transmitting module.

[0012] Furthermore, the first receiving device includes an LVDS transmitting module, which is connected to the second receiving device via a second LVDS bus.

[0013] Furthermore, the second LVDS bus contains twice the number of LVDS data lines as the first LVDS bus, and the transmission rate of the LVDS data lines in the second LVDS bus is half the transmission rate of the LVDS data lines in the first LVDS bus.

[0014] Preferably, one or more pixel data points are transmitted on the LVDS data line during each clock cycle of the LVDS clock line.

[0015] As a first receiving device of the present invention, it includes an LVDS alignment module. The first receiving device is connected to an LVDS transmitting device through a first LVDS bus. The first LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS transmitting device transmits data to the first receiving device through the first LVDS bus. The LVDS alignment module is used to eliminate the delay deviation of the LVDS clock line and multiple LVDS data lines and to receive data from the first LVDS bus.

[0016] Preferably, the LVDS alignment module includes a phase-locked loop (PLL) module connected to the LVDS clock line, and uses the LVDS clock line as the reference clock for the PLL module to generate one or more sampling clocks for sampling the data transmitted on the LVDS data line.

[0017] Furthermore, the LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more data line delay modules delay one or more LVDS data lines respectively, so that the sampling clock can correctly sample the data.

[0018] Furthermore, the LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

[0019] Furthermore, the LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

[0020] Preferably, the LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

[0021] Preferably, the first receiving device further includes a transmitting module, which is connected to the second receiving device. The first receiving device forwards data received from the first LVDS bus to the second receiving device through the transmitting module.

[0022] Furthermore, the first receiving device includes an LVDS transmitting module, which is connected to the second receiving device via a second LVDS bus.

[0023] Furthermore, the second LVDS bus contains twice the number of LVDS data lines as the first LVDS bus, and the transmission rate of the LVDS data lines in the second LVDS bus is half the transmission rate of the LVDS data lines in the first LVDS bus.

[0024] Preferably, one or more pixel data points are transmitted on the LVDS data line during each clock cycle of the LVDS clock line.

[0025] The beneficial effects of this invention are:

[0026] This invention provides an LVDS transmission system and an LVDS receiving device, which can eliminate the delay deviation between the LVDS clock line and multiple LVDS data lines during LVDS data transmission, improve the transmission speed of LVDS data, increase the transmission distance of LVDS data, and expand the application scope of LVDS data transmission. Attached Figure Description

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0028] Figure 1 is a schematic diagram of a module of an embodiment of the LVDS transmission system of the present invention.

[0029] Figure 2 is a data transmission timing diagram of an embodiment of the LVDS transmission system of the present invention.

[0030] Figure 3 is a schematic diagram of a phase-locked loop module of one embodiment of the first receiving device of the present invention.

[0031] Figure 4 is a timing diagram of the phase-locked loop module of an embodiment of the first receiving device of the present invention.

[0032] Figure 5 is a schematic diagram of the reference clock delay module of one embodiment of the first receiving device of the present invention.

[0033] Figure 6 is a timing diagram of the reference clock delay module of an embodiment of the first receiving device of the present invention.

[0034] Figure 7 is a schematic diagram of the sampling clock phase adjustment module of one embodiment of the first receiving device of the present invention.

[0035] Figure 8 is a timing diagram of the sampling clock phase adjustment module of an embodiment of the first receiving device of the present invention.

[0036] Figure 9 is a schematic diagram of the sampling clock phase adjustment module of another embodiment of the first receiving device of the present invention.

[0037] Figure 10 is a schematic diagram of the sampling clock phase adjustment module in another embodiment of the first receiving device of the present invention.

[0038] Figure 11 is a timing diagram of the sampling clock phase adjustment module of the first receiving device of the present invention.

[0039] Figure 12 is a schematic diagram of the data line delay module of an embodiment of the first receiving device of the present invention.

[0040] Figure 13 is a timing diagram of the data line delay module of an embodiment of the first receiving device of the present invention.

[0041] Figure 14 is a schematic diagram of an embodiment of the LVDS transmission system of the present invention with a control bus.

[0042] Figure 15 is a schematic diagram of another embodiment of the LVDS transmission system of the present invention.

[0043] Figure 16 is a schematic diagram of another embodiment of the LVDS transmission system of the present invention with a control bus.

[0044] Figure 17 is a schematic diagram of another embodiment of the LVDS transmission system of the present invention.

[0045] Figure 18 is a schematic diagram of an embodiment of the first receiving device in the LVDS transmission system of the present invention, which is equipped with an LVDS transmitting module.

[0046] Figure 19 is a schematic diagram of the second LVDS bus transmission timing in the LVDS transmission system of the present invention.

[0047] The numerical symbols in the above figures have the following meanings: 100: LVDS transmitting device; 200: First receiving device; 201: LVDS alignment module; 202: Transmitting module; 211: Phase-locked loop module; 221: Reference clock delay module; 231: Sampling clock phase adjustment module; 241: Data line delay module; 300: Second receiving device; 400: First LVDS bus; 401: LVDS clock line; 402: LVDS data line; 500: Control bus; 600: Second LVDS bus. Detailed Implementation

[0048] The LVDS transmission system and the first receiving device will be further described below with reference to the embodiments shown in the accompanying drawings.

[0049] As shown in Figure 1, this is an embodiment of the LVDS transmission system of the present invention. The LVDS transmission system includes an LVDS transmitting device (100) and a first receiving device (200). The LVDS transmitting device is connected to the first receiving device (200) through a first LVDS bus (400). The first LVDS bus (400) includes an LVDS clock line (401) and multiple LVDS data lines (402). The LVDS transmitting device (100) transmits data to the first receiving device (200) through the first LVDS bus (400). The first receiving device (200) includes an LVDS alignment module (201). The LVDS alignment module is used to eliminate the delay deviation between the LVDS clock line (401) and the multiple LVDS data lines (402) and to receive data from the first LVDS bus (400). In this invention, the LVDS clock line (401) and each LVDS data line (402) use differential signal transmission, that is, the LVDS clock line (401) and each LVDS data line (402) contain a pair of differential signal lines, as shown in Figure 1.

[0050] For convenience, unless otherwise specified, the description of this invention is based on an LVDS bus comprising four LVDS data lines. As shown in FIG1, the first LVDS bus (400) includes four LVDS data lines (402), which are respectively denoted as LVDS data line A0, LVDS data line A1, LVDS data line A2, and LVDS data line A3. In this invention, the LVDS clock line (401) included in the first LVDS bus (400) is represented by the LVDS clock line CLK_IN.

[0051] The present invention does not limit the number of LVDS data lines included in the LVDS bus. For example, as shown in Figure 19, the LVDS bus includes 8 LVDS data lines A0, A1 to A7.

[0052] The Open LDI (Open LVDS display interface) standard is a transmission protocol based on the LVDS bus, proposed and drafted by National Semiconductor in 1999. It uses the LVDS bus as the physical layer and aims to establish an open standard for digital connections between display sources and display devices. It incorporates the work of other widely used standards such as the Video Electronics Standards Association (VESA) and the American National Standards Institute (ANSI), providing a fully digital, plug-and-play interface that ensures clear and sharp video images on digital display devices. In Open LDI, the data rate transmitted on each LVDS data line is seven times the clock frequency transmitted on each LVDS clock line. For ease of description, in the embodiments described below, the data rate transmitted on each LVDS data line is seven times the clock frequency transmitted on each LVDS clock line. However, this invention does not limit the relationship between the data rate transmitted on the LVDS data line and the clock frequency transmitted on the LVDS clock line; other quantitative relationships between the two are also within the scope of this invention.

[0053] As shown in the embodiment of Figure 2, a signal timing diagram is provided for the Open LDI protocol transmitting image data on the first LVDS bus (400) based on the LVDS bus. Using the LVDS bus to transmit other protocol data is also within the scope of this invention; that is, this invention does not limit the type of data or protocol transmitted based on the LVDS bus.

[0054] As shown in Figure 2, one pixel's data is transmitted within each LVDS clock cycle (one CLK_IN clock cycle) via LVDS data lines A0, A1, A2, and A3 (402). R0, R1 to R7 represent 8-bit binary data for red, G0, G1 to G7 represent 8-bit binary data for green, and B0, B1 to B7 represent 8-bit binary data for blue. HSYNC, VSYNC, and DE represent the binary data for the synchronization signal, and RES is a reserved bit. As shown in Figure 2, within one LVDS clock cycle, each LVDS data line transmits 7 cycles of serial data (7 bits of binary data), with the width of one cycle of serial data being one UI.

[0055] In the embodiment shown in Figure 2, one pixel data is transmitted in each LVDS clock cycle. This invention does not limit the number of pixels transmitted in each LVDS clock cycle, and transmitting more than one pixel data in each LVDS clock cycle is also within the scope of protection of this invention.

[0056] Figure 3 shows a schematic diagram of a phase-locked loop (PLL) module in one embodiment of the first receiving device of the present invention. The LVDS alignment module (201) includes a PLL module (211), which is connected to the LVDS clock line (401). The LVDS clock line (401) is used as the reference clock for the PLL module (211) to generate a sampling clock for sampling the data transmitted on the LVDS data line (402). The PLL module (211) can also generate multiple sampling clocks. The present invention does not limit the number of sampling clocks generated by the PLL module.

[0057] As shown in the timing diagram in Figure 4, the sampling clock frequency is 7 times the reference clock frequency. However, the present invention does not limit the ratio between the sampling clock and the reference clock. For example, in another embodiment, the sampling clock uses both the rising edge and the falling edge to sample data, then the frequency of the sampling clock is 3.5 times the reference clock frequency.

[0058] As shown in the timing diagram in Figure 4, the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the input reference clock of the phase-locked loop module (211), that is, the rising edge of the sampling clock is aligned with the rising edge of the reference clock. This invention does not limit the phase relationship between the output sampling clock and the input reference clock of the phase-locked loop module (211). In different implementations of the phase-locked loop module (211), its output sampling clock may also have a phase difference with the input reference clock. That is, in different implementations of the phase-locked loop module (211), the rising edge of its output sampling clock may also be misaligned with the rising edge of the input reference clock. In the above description, the alignment of the rising edge of the sampling clock with the rising edge of the reference clock indicates that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the input reference clock of the phase-locked loop module (211), and there is no phase difference between the two. In other descriptions of the present invention, the alignment of the rising edge of the sampling clock with the falling edge of the reference clock, or the alignment of the falling edge of the sampling clock with the rising edge of the reference clock, or the alignment of the falling edge of the sampling clock with the falling edge of the reference clock, can also indicate that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the input reference clock of the phase-locked loop module (211).

[0059] For ease of description, in the following description of the present invention, the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the input reference clock of the phase-locked loop module (211), and the alignment of the rising edge of the sampling clock with the rising edge of the reference clock indicates that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the input reference clock of the phase-locked loop module (211).

[0060] The LVDS alignment module (201) may also include a reference clock delay module (221). The method by which the LVDS alignment module (201) eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module (221) delays the reference clock of the phase-locked loop module (211), thereby delaying the sampling clock so that the sampling clock can correctly sample the data. Figure 5 shows a schematic diagram of a reference clock delay module in an embodiment of the first receiving device of the present invention. In this embodiment, the LVDS alignment module (201) includes a phase-locked loop module (211) and a reference clock delay module (221). The reference clock delay module (221) is connected to the LVDS clock line (401) and uses the LVDS clock line (401) as its input signal. The output of the reference clock delay module (221) is connected to the phase-locked loop module (211), and the output of the reference clock delay module (221) is the reference clock of the phase-locked loop module (211). The reference clock delay module (221) is used to delay the reference clock of the phase-locked loop module (211), thereby delaying the sampling clock so that the sampling clock can correctly sample data. The delay value of the reference clock delay module (221) is configurable. In this embodiment, the phase-locked loop module (211) generates four sampling clocks: the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock, which are used to sample the LVDS data lines (402) (A0, A1, A2, A3), respectively.

[0061] Figure 6 is a timing diagram of the reference clock delay module based on the embodiment shown in Figure 5. As shown in Figure 6, the undelayed reference clock, the undelayed first sampling clock, the undelayed second sampling clock, the undelayed third sampling clock, and the undelayed fourth sampling clock are the input reference clock of the phase-locked loop module (211) and the output first sampling clock, second sampling clock, third sampling clock, and fourth sampling clock of the phase-locked loop module (211) when the delay value of the reference clock delay module (221) in Figure 5 is configured to be 0.

[0062] In the embodiment shown in Figure 6, the rising edge of the sampling clock is used to sample LVDS data, that is, the rising edge of the sampling clock is the sampling edge. This invention does not limit the sampling edge of the sampling clock. Using the rising edge of the sampling clock to sample LVDS data, or using the falling edge of the sampling clock to sample LVDS data, or using both the rising and falling edges of the sampling clock to sample LVDS data are all within the protection scope of this invention.

[0063] For ease of description, in the following description of the present invention, LVDS data is sampled at the rising edge of the sampling clock.

[0064] As shown in Figure 6, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402). This causes the rising edge of the undelayed reference clock to be misaligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), but instead aligned to the unstable part (shown as the grid shaded area). Consequently, the undelayed first sampling clock, the undelayed second sampling clock, the undelayed third sampling clock, and the undelayed fourth sampling clock cannot correctly sample the LVDS data on the LVDS data lines A0, A1, A2, A3 (402).

[0065] As shown in Figure 6, the delayed reference clock, delayed first sampling clock, delayed second sampling clock, delayed third sampling clock, and delayed fourth sampling clock are respectively the input reference clock of the phase-locked loop module (211) configured with the correct delay value of the reference clock delay module (221) in Figure 5, and the first sampling clock, second sampling clock, third sampling clock, and fourth sampling clock output by the phase-locked loop module (211).

[0066] As shown in Figure 6, after the delay value of the reference clock delay module (221) is configured to the correct delay value, the input reference clock of the phase-locked loop module (211) output by the LVDS clock line (401) (CLK_IN) after the delay is aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402). Thus, the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock after the delay are also aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the LVDS data lines A0, A1, A2, A3 (402) can be sampled correctly.

[0067] Users can use the LVDS transmitting device (100) to send a preset data sequence on the LVDS data lines A0, A1, A2, A3 (402), and configure the delay of the reference clock delay module (221) to different delay values, check whether the LVDS data sampled under different delay values ​​is correct, and search for the correct delay value.

[0068] This invention does not limit the method for searching and configuring the correct delay value; any method for searching and configuring the correct delay value is within the scope of protection of this invention.

[0069] The LVDS alignment module (201) may also include one or more sampling clock phase adjustment modules (231). The method by which the LVDS alignment module (201) eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: one or more sampling clock phase adjustment modules (231) adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

[0070] Figure 7 is a schematic diagram of the clock phase adjustment module of an embodiment of the first receiving device of the present invention. In this embodiment, the LVDS alignment module (201) includes a phase-locked loop module (211) and a sampling clock phase adjustment module (231). The phase-locked loop module (211) is connected to the LVDS clock line (401) and uses the LVDS clock line (401) as a reference clock. The phase-locked loop module (211) outputs a sampling clock. The sampling clock phase adjustment module (231) is used to adjust the phase of the sampling clock generated by the phase-locked loop module (211) so that the adjusted sampling clock can correctly sample the data of the four data lines A0, A1, A2, and A3. The sampling clock phase adjustment module (231) takes the sampling clock output by the phase-locked loop module (211) as input and outputs a phase-adjusted sampling clock. In this invention, the phase of the sampling clock after phase adjustment refers to the delay relative to the sampling clock input to the sampling clock phase adjustment module (231). The phase value of the sampling clock phase adjustment module (231) can be configured. When the sampling clock phase adjustment module (231) is configured to different phase values, the phase of the sampling clock after phase adjustment is adjusted accordingly.

[0071] Figure 8 is a timing diagram of the sampling clock phase adjustment module based on the embodiment shown in Figure 7. As shown in Figure 8, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402), which causes the rising edge of the reference clock and the sampling clock to be not aligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), but to the unstable part of the LVDS data lines A0, A1, A2, A3 (402) (shown as the grid shaded part), thus failing to correctly sample the LVDS data on the LVDS data lines A0, A1, A2, A3 (402).

[0072] As shown in Figure 8, after the phase value of the sampling clock phase adjustment module (231) is configured to the correct phase value, the rising edge of the sampling clock after phase adjustment is aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the LVDS data lines A0, A1, A2, A3 (402) can be sampled correctly.

[0073] Users can send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402) through the LVDS transmitting device (100), and configure the sampling clock phase adjustment module (231) to different phase values. Then, by checking whether the LVDS data sampled by the sampling clock after phase adjustment under different phase value configurations is correct, the correct phase value can be found.

[0074] This invention does not limit the method for searching and configuring the correct phase value; any method for searching and configuring the correct phase value is within the scope of protection of this invention.

[0075] Figure 9 is a schematic diagram of the clock phase adjustment module of another embodiment of the first receiving device of the present invention. Compared with the embodiment shown in Figure 7, in the embodiment shown in Figure 9, the LVDS alignment module (201) includes four sampling clock phase adjustment modules (231). The phase-locked loop module (211) generates a sampling clock, which is sent to the four sampling clock phase adjustment modules (231) respectively. The four sampling clock phase adjustment modules (231) adjust the phase of the sampling clock respectively and generate a phase-adjusted first sampling clock, a phase-adjusted second sampling clock, a phase-adjusted third sampling clock, and a phase-adjusted fourth sampling clock respectively.

[0076] Figure 10 is a schematic diagram of the clock phase adjustment module in another embodiment of the first receiving device of the present invention. Compared with the embodiment shown in Figure 9, in the embodiment shown in Figure 10, the phase-locked loop module (211) generates multiple sampling clocks, namely, a first sampling clock, a second sampling clock, a third sampling clock, and a fourth sampling clock, which are respectively connected to four sampling clock phase adjustment modules (231). The four sampling clock phase adjustment modules (231) adjust the phase of the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock, respectively, thereby generating the phase-adjusted first sampling clock, the phase-adjusted second sampling clock, the phase-adjusted third sampling clock, and the phase-adjusted fourth sampling clock.

[0077] Figure 11 is a timing diagram of the sampling clock phase adjustment module based on the embodiment shown in Figure 9 or Figure 10. After phase adjustment, the first sampling clock is used to sample LVDS data line A0 (402), the second sampling clock is used to sample LVDS data line A1 (402), the third sampling clock is used to sample LVDS data line A2 (402), and the fourth sampling clock is used to sample LVDS data line A3 (402). When Figure 11 is based on Figure 9, the first, second, third, and fourth sampling clocks shown in Figure 11 are all the sampling clocks shown in Figure 9.

[0078] As shown in Figure 11, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402), and there is also a delay deviation among the LVDS data lines A0, A1, A2, A3 (402). This causes the rising edges of the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock to be misaligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), or misaligned to the middle part of the stable part. As a result, the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be sampled correctly or cannot be sampled stably and correctly.

[0079] As shown in Figure 11, after the phase values ​​of the four sampling clock phase adjustment modules (231) are configured to the correct phase values, the rising edges of the first, second, third, and fourth sampling clocks after phase adjustment are aligned to the middle part of the stable portion of the LVDS data lines A0, A1, A2, and A3 (402), respectively, so that the LVDS data lines A0, A1, A2, and A3 (402) can be sampled stably and correctly.

[0080] Users can send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402) through the LVDS transmitting device (100), and configure the four sampling clock phase adjustment modules (231) to different phase values ​​respectively. Then, by checking whether the LVDS data sampled by the sampling clock after phase adjustment under different phase value configurations is correct, the correct phase value can be found.

[0081] This invention does not limit the method for searching and configuring the correct phase value; any method for searching and configuring the correct phase value is within the scope of protection of this invention.

[0082] The LVDS alignment module (201) may also include one or more data line delay modules (241). The method by which the LVDS alignment module (201) eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: one or more data line delay modules (241) delay one or more LVDS data lines respectively, so that the sampling clock can correctly sample the data. For ease of description, in the embodiment shown in FIG12 of the present invention, four data line delay modules (241) delaying four LVDS data lines respectively are used as an example for explanation.

[0083] Figure 12 shows a schematic diagram of a data line delay module in an embodiment of the first receiving device of the present invention. In this embodiment, the LVDS alignment module (201) includes four data line delay modules (241), which are respectively connected to LVDS data lines A0 (402), A1 (402), A2 (402), and A3 (402). The four data line delay modules (241) can delay the connected LVDS data lines A0, A1, A2, and A3 (402) respectively, and output the delayed LVDS data lines A0, A1, A2, and A3 respectively.

[0084] Figure 13 is a schematic diagram of the data line delay timing based on the embodiment shown in Figure 12. As shown in Figure 13, there is a delay deviation between the reference clock of the phase-locked loop module (211) and the LVDS data lines A0, A1, A2, A3 (402). At the same time, there is also a delay deviation between the LVDS data lines A0, A1, A2, A3 (402). This causes the rising edge of the sampling clock generated by the phase-locked loop module (211) to be misaligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), or misaligned to the middle part of the stable part. As a result, the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be sampled correctly or the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be sampled stably and correctly.

[0085] As shown in Figure 13, after the four data line delay modules (241) are configured with the correct delay values, the middle part of the stable part of the delayed LVDS data A0, A1, A2, and A3 is aligned with the sampling clock, so that the sampling clock can stably and correctly sample the delayed LVDS data A0, A1, A2, and A3.

[0086] Users can send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402) through the LVDS transmitting device (100), and configure the four data line delay modules (241) to different delay values. Then, by checking whether the LVDS data after the delay of the sampling clock under different delay values ​​is correct, the correct delay value can be found.

[0087] This invention does not limit the method for searching and configuring the correct delay value; any method for searching and configuring the correct delay value is within the scope of protection of this invention.

[0088] In this invention, one or more of the reference clock delay module (221), sampling clock phase adjustment module (231), and data line delay module (241) may coexist in the embodiments of this invention. This invention does not limit the number or combination of the above functional modules.

[0089] Figure 14 shows an embodiment of the LVDS transmission system of the present invention with a control bus. Compared with the embodiment shown in Figure 1, the embodiment shown in Figure 14, based on the embodiment shown in Figure 1, further connects the LVDS transmitting device (100) to the first receiving device (200) via the control bus (500); the LVDS transmitting device (100) controls the alignment module (201) of the first receiving device (200) via the control bus (500).

[0090] In this embodiment, the method for eliminating delay deviations of the LVDS clock line (401) and multiple LVDS data lines (402) in the LVDS transmission system is as follows: the LVDS transmitting device (100) transmits a preset data sequence on the LVDS data lines A0, A1, A2, A3 (402), and controls the alignment module (201) to search for and configure the correct phase value of the sampling clock phase adjustment module (231) described above in the present invention through the control bus (500), or controls the alignment module (201) to search for and configure the correct delay value of the data line delay module (241) described above in the present invention through the control bus (500), or controls the alignment module (201) to search for and configure the correct delay value of the reference clock delay module (221) described above in the present invention through the control bus (500).

[0091] Figure 15 shows another embodiment of the LVDS transmission system of the present invention. Compared with the embodiment shown in Figure 1, the embodiment shown in Figure 15, based on the embodiment shown in Figure 1, further includes a second receiving device (300) in the LVDS transmission system, and the first receiving device (200) further includes a transmitting module (202). The transmitting module (202) is connected to the second receiving device (300), and the first receiving device (200) forwards the data received from the first LVDS bus (400) to the second receiving device (300) through the transmitting module (202).

[0092] In the embodiment shown in Figure 15, the alignment module (201) in the first receiving device (200) can eliminate the delay deviation of the LVDS clock line (401) and multiple LVDS data lines (402) in the first LVDS bus (400) and receive data from the first LVDS bus (400). The data received from the first LVDS bus (400) is then forwarded to the second receiving device (300) through the transmitting module (202). The first receiving device (200) acts as a bridge between the LVDS transmitting device (100) and the second receiving device (300), thereby extending the transmission distance between the LVDS transmitting device (100) and the second receiving device (300). The method by which the alignment module (201) eliminates the delay deviation of the LVDS clock line (401) and multiple LVDS data lines (402) in the first LVDS bus (400) has been described in the embodiments shown in Figures 3 to 13 and will not be repeated here.

[0093] When the first receiving device (200) forwards the data received from the first LVDS bus (400) to the second receiving device (300) through the transmitting module (202), it can modify, add or delete the data.

[0094] Figure 16 shows another embodiment of the LVDS transmission system of the present invention with a control bus. Compared with the embodiment shown in Figure 15, the embodiment shown in Figure 16, based on the embodiment shown in Figure 15, further connects the LVDS transmitting device (100) to the first receiving device (200) via a control bus (500). The LVDS transmitting device (100) controls the alignment module (201) of the first receiving device (200) via the control bus (500). The role of the control bus (500) in eliminating the delay deviation of the LVDS clock line (401) and multiple LVDS data lines (402) in the alignment module (201) has been described in the embodiment shown in Figure 14 and will not be repeated here.

[0095] As shown in Figure 17, in another embodiment of the LVDS transmission system of the present invention, compared with the embodiment shown in Figure 15, the embodiment shown in Figure 17 adds multiple cascaded first receiving devices (200) between the LVDS transmitting device (100) and the second receiving device (300), and the first receiving devices (200) are connected to each other via an LVDS bus. Compared with the embodiment shown in Figure 15, the embodiment shown in Figure 17 can further extend the transmission distance between the LVDS transmitting device (100) and the second receiving device (300).

[0096] Figure 18 shows a schematic diagram of another embodiment of the LVDS transmission system of the present invention. In this embodiment, the first receiving device (200) includes a transmitting module (202) which is an LVDS transmitting module. The LVDS transmitting module is connected to the second receiving device (300) through a second LVDS bus (600). The second LVDS bus (600) includes one LVDS clock line CLK_OUT and eight LVDS data lines A0_OUT, A1_OUT to A7_OUT.

[0097] This invention does not limit the number of LVDS data lines included in the second LVDS bus (600). In the embodiment shown in FIG18, the number of LVDS data lines included in the second LVDS bus (600) is twice the number of LVDS data lines (402) included in the first LVDS bus. In other embodiments, the number of LVDS data lines included in the second LVDS bus (600) may be equal to the number of LVDS data lines (402) included in the first LVDS bus or other multiples thereof.

[0098] Figure 19 shows the timing diagram of the second LVDS bus (600) based on Figure 18. Two pixel data points are transmitted within each LVDS clock cycle (one CLK_OUT clock cycle) via LVDS data lines A0_OUT, A1_OUT to A7_OUT. RU0, RU1 to RU7 represent the first pixel (8-bit red binary data), GU0, GU1 to GU7 represent the first pixel (8-bit green binary data), BU0, BU1 to BU7 represent the first pixel (8-bit blue binary data), RL0, RL1 to RL7 represent the second pixel (8-bit red binary data), GL0, GL1 to GL7 represent the second pixel (8-bit green binary data), BL0, BL1 to BL7 represent the second pixel (8-bit blue binary data), HSYNC, VSYNC, and DE represent the binary data of the synchronization signal, RES is a reserved bit, and CNTL and CNTE are two user-defined control bits. As shown in Figure 19, within one LVDS clock cycle, each LVDS data line transmits 7 cycles of serial data (7 bits of binary data), and the width of one cycle of serial data is one UI.

[0099] In the embodiment shown in Figure 19, the transmission rate of the LVDS data lines included in the second LVDS bus (600) can be half the transmission rate of the LVDS data lines included in the first LVDS bus (400). Because the number of LVDS data lines included in the second LVDS bus (600) is twice the number of LVDS data lines (402) included in the first LVDS bus, the total transmission rate of the second LVDS bus (600) is equal to the total transmission rate of the first LVDS bus (400).

[0100] In other embodiments of the present invention, the second LVDS bus may also include additional LVDS clock lines and LVDS data lines, and the present invention does not limit this. The transmitting module (202) of the present invention may also be other types of transmitting modules, such as transmitting modules that support protocols such as DP / eDP, MIPI, and HDMI, and the present invention does not limit this.

[0101] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

[0102] In summary, this invention fully meets the needs of industrial development in terms of structural design, usability, and cost-effectiveness. Furthermore, the disclosed structure is an unprecedented innovative construction, possessing novelty, inventiveness, and practicality, and meets the requirements for relevant utility model patents. Therefore, this application is filed in accordance with the law.

Claims

1. An LVDS transmission system, characterized in that: The LVDS transmission system includes an LVDS transmitter and a first receiver. The LVDS transmitter is connected to the first receiver via a first LVDS bus. The first LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS transmitting device sends data to the first receiving device via the first LVDS bus. The first receiving device includes an LVDS alignment module, which is used to eliminate delay deviations of the LVDS clock line and multiple LVDS data lines and to receive data from the first LVDS bus.

2. The LVDS transmission system according to claim 1, characterized in that: The LVDS alignment module includes a phase-locked loop (PLL) module. The PLL module is connected to the LVDS clock line and uses the LVDS clock line as the reference clock for the PLL module to generate one or more sampling clocks for sampling the data transmitted on the LVDS data line.

3. The LVDS transmission system according to claim 2, characterized in that: The LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more data line delay modules delay one or more LVDS data lines respectively, so that the sampling clock can correctly sample the data.

4. An LVDS transmission system according to claim 2, characterized in that: The LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

5. An LVDS transmission system according to claim 2, characterized in that: The LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

6. An LVDS transmission system according to claim 1, characterized in that: The LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

7. An LVDS transmission system according to claim 1, characterized in that: The LVDS transmission system further includes a second receiving device, and the first receiving device further includes a transmitting module. The transmitting module is connected to the second receiving device, and the first receiving device forwards the data received from the first LVDS bus to the second receiving device through the transmitting module.

8. An LVDS transmission system according to claim 7, characterized in that: The first receiving device includes an LVDS transmitting module, which is connected to the second receiving device via a second LVDS bus.

9. An LVDS transmission system according to claim 8, characterized in that: The second LVDS bus contains twice the number of LVDS data lines as the first LVDS bus, and the transmission rate of the LVDS data lines in the second LVDS bus is half that of the LVDS data lines in the first LVDS bus.

10. An LVDS transmission system according to claim 1, characterized in that: During each clock cycle of the LVDS clock line, one or more pixel data points are transmitted on the LVDS data line.

11. A first receiving device, comprising an LVDS alignment module, characterized in that: The first receiving device is connected to the LVDS transmitting device via the first LVDS bus. The first LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS transmitting device sends data to the first receiving device via the first LVDS bus. The LVDS alignment module is used to eliminate delay deviations in the LVDS clock line and multiple LVDS data lines and to receive data from the first LVDS bus.

12. The first receiving device according to claim 11, characterized in that: The LVDS alignment module includes a phase-locked loop (PLL) module. The PLL module is connected to the LVDS clock line and uses the LVDS clock line as the reference clock for the PLL module to generate one or more sampling clocks for sampling the data transmitted on the LVDS data line.

13. The first receiving device according to claim 12, characterized in that: The LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more data line delay modules delay one or more LVDS data lines respectively, so that the sampling clock can correctly sample the data.

14. The first receiving device according to claim 12, characterized in that: The LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

15. The first receiving device according to claim 12, characterized in that: The LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

16. The first receiving device according to claim 11, characterized in that: The LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

17. The first receiving device according to claim 11, characterized in that: The first receiving device further includes a transmitting module, which is connected to the second receiving device. The first receiving device forwards data received from the first LVDS bus to the second receiving device through the transmitting module.

18. The first receiving device according to claim 17, characterized in that: The first receiving device includes an LVDS transmitting module, which is connected to the second receiving device via a second LVDS bus.

19. The first receiving device according to claim 18, characterized in that: The second LVDS bus contains twice the number of LVDS data lines as the first LVDS bus, and the transmission rate of the LVDS data lines in the second LVDS bus is half that of the LVDS data lines in the first LVDS bus.

20. The first receiving device according to claim 11, characterized in that: During each clock cycle of the LVDS clock line, one or more pixel data points are transmitted on the LVDS data line.

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