Chip packaging structure and electronic device

Abstract

The present application can be applied to the technical field of chip packaging, and provides a chip packaging structure and an electronic device. The chip packaging structure may comprise: multiple chips, and an adapter board, the adapter board comprising: a bridge chip, a functional device, a first redistribution layer, and a second redistribution layer. The functional device comprises: an active device and / or a passive device. The bridge chip is located between the first redistribution layer and the second redistribution layer, and the chips are located at a side of the first redistribution layer distant from the second redistribution layer. The bridge chip is electrically connected to the first redistribution layer, at least two chips are electrically connected by means of the bridge chip, and at least one chip is electrically connected to the functional device. The second redistribution layer comprises: multiple circuit structures separately disposed. The chip packaging structure provided in the present application can alleviate the problems of insufficient vertical power supply, poor power supply performance, high noise, and high power consumption, and implement high performance expression of packaging multiple chips.

Description

A chip packaging structure and electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411765684.4, filed on November 29, 2024, entitled "A Chip Packaging Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and electronic device. Background Technology

[0004] With the continuous evolution of chip packaging technology, chip packaging structures are becoming increasingly complex, and chip packaging technology is gradually developing towards multi-dimensional packaging. Among them, fanout packaging (FOP) enables chips to be connected to the circuit board in a "fan-out" manner through a redistribution layer (RDL), which can achieve high-speed and high-density interconnection of chips, and has received widespread attention and application in recent years.

[0005] However, in the field of FOP packaging, the chip packaging structure is composed of multiple chips. The chip packaging structure faces problems such as insufficient vertical power supply, poor power supply stability, high noise, and high power consumption, which affect the performance of the chip packaging structure. Summary of the Invention

[0006] This application provides a chip packaging structure and electronic device to improve the problems of insufficient vertical power supply, poor power supply stability, high noise, and high power consumption in chip packaging structures, thereby achieving high-performance expression of chip packaging structures.

[0007] In a first aspect, embodiments of this application provide a chip packaging structure, which may include: multiple chips and an adapter board. The adapter board may include: a bridging chip, functional devices, a first wiring layer, and a second wiring layer. The functional devices may include: active devices and / or passive devices. A functional device may include only active devices, or only passive devices, or may include both active and passive devices. The bridging chip is located between the first wiring layer and the second wiring layer, with each chip located on the side of the first wiring layer facing away from the second wiring layer. The bridging chip is electrically connected to the first wiring layer, at least two chips are electrically connected through the bridging chip, and at least one chip is electrically connected to a functional device. The second wiring layer may include: multiple discretely arranged circuit structures.

[0008] In the chip packaging structure provided in this application embodiment, a bridging chip is provided in the adapter board. The bridging chip is electrically connected to at least two chips through a first wiring layer, which can improve the interconnection density of the chips and reduce signal transmission delay. In addition, the adapter board also provides functional devices, which may include active devices and / or passive devices. Furthermore, the second wiring layer includes discretely arranged circuit structures, which can reduce the power consumption and noise of the chip packaging structure and improve the vertical power supply capability and power supply stability. Therefore, the chip packaging structure provided in this application embodiment can improve the problems of insufficient vertical power supply, poor power supply stability, high noise, and high power consumption, and improve the problem of large signal transmission delay, achieving high-performance expression of multiple chips packaged together.

[0009] In this embodiment, the chip packaging structure can encapsulate multiple chips, with the number of chips being greater than or equal to two. The chips in the chip packaging structure can be arranged side-by-side to achieve 2.5D packaging; or, the chips in the chip packaging structure can be stacked to achieve 3D packaging; or, some chips in the chip packaging structure can be arranged side-by-side, while others can be stacked to achieve 3.5D packaging. In specific configurations, the number and arrangement of chips in the chip packaging structure can be reasonably set according to actual needs. In specific configurations, the chips can be interconnected with the first wiring layer using a flip-chip (FC) method, and the chips can be electrically connected to the first wiring layer through bonding methods such as reflow soldering and thermal compression bonding (TCB). To make the surface of the chip packaging structure flush, a filler structure can be provided in the chip packaging structure. In specific configurations, the position and size of the filler structure can be reasonably set according to the specific structure of each chip.

[0010] In some embodiments of this application, the bridging chip may include a first conductive via extending from the interior of the bridging chip to its surface, with a diameter between 3 μm and 20 μm. The functional device may include a second conductive via with a diameter between 3 μm and 20 μm. In one possible implementation, the functional device may further include a redistribution layer located on the surface of an active or passive device, with the second conductive via electrically connected to the redistribution layer. For ease of distinction, in this application embodiment, the redistribution layer located on the surface of the active device is referred to as the third redistribution layer, and the redistribution layer located on the surface of the passive device is referred to as the fourth redistribution layer. In this application embodiment, by providing conductive vias (the first or second conductive via) in the bridging chip and functional device, the interconnection distance in the chip package structure can be shortened. Furthermore, the diameter of the conductive via is related to the interconnection density of the bridging chip or functional device; the smaller the diameter of the conductive via, the greater the interconnection density of the bridging chip or functional device. Furthermore, the aperture of the conductive via is related to the electrical performance of the bridging chip or functional device. The larger the aperture of the conductive via, the greater the current that can flow through it. In the embodiments of this application, the aperture of the first conductive via is set between 3μm and 20μm, and the aperture of the second conductive via is set between 3μm and 20μm. The aperture range of the conductive via is relatively large. In specific settings, the aperture of the conductive via can be reasonably set according to the density and electrical performance requirements of the bridging chip and functional device, thereby effectively improving the current sharing effect and achieving more stable power transmission, higher bandwidth, and lower latency.

[0011] In one possible implementation, the functional device may include an active device, which, exemplarily, may be an integrated voltage regulator (IVR). The aperture of the second conductive via in the active device may be less than or equal to the aperture of the first conductive via. Specifically, the aperture of the first conductive via may be in the range of 10μm to 20μm, and the aperture of the second conductive via in the active device may be in the range of 3μm to 8μm. The bridging chip can be used to provide power to the chip. Setting a larger aperture for the first conductive via in the bridging chip can effectively simplify the process, reduce manufacturing costs, improve yield, and expand current carrying capacity, thereby providing sufficient power current to the chip through the bridging chip and effectively improving the problem of insufficient vertical power supply. Setting a smaller aperture for the second conductive via in the active device can reduce the area occupied by a single via, thereby increasing density and optimizing chip performance.

[0012] In another possible implementation, the functional devices may include active and passive devices. For example, the active device may be an integrated voltage regulator (IVR); the passive device may be an integrated passive device (IPD), which may include passive components such as capacitors, resistors, and inductors. The diameter of the second conductive via in the active device is smaller than or equal to the diameter of the second conductive via in the passive device. The active device can be used to provide control signals to the chip, and the current required for the control signals is relatively small; therefore, the diameter of the second conductive via in the active device is set to be smaller. The passive device can perform functions such as signal transmission, energy storage, and signal filtering; the current required for the passive device is relatively large; therefore, the diameter of the second conductive via in the passive device is set to be larger. The diameter of the second conductive via in the active device is smaller than or equal to the diameter of the first conductive via. Bridge chips can be used to supply power to chips. By setting a larger aperture for the first conductive via in the bridge chip, the process can be simplified, manufacturing costs reduced, yield improved, and current carrying capacity increased. This allows the bridge chip to provide sufficient power to the chip, effectively addressing the problem of insufficient vertical power supply. Specifically, the aperture of the first conductive via can be in the range of 10μm to 20μm, the aperture of the second conductive via in active devices can be in the range of 3μm to 8μm, and the aperture of the second conductive via in passive devices can be in the range of 10μm to 20μm.

[0013] Of course, in some cases, the aperture of the first conductive via in the bridging chip can also be set to be smaller. For example, the aperture of the first conductive via can be in the range of 3μm to 12μm, thereby increasing the interconnection density of the bridging chip. In specific settings, the aperture of the first conductive via can be reasonably set according to actual needs.

[0014] In this embodiment, the adapter board may further include conductive posts located between the first and second wiring layers, positioned excluding the bridging chip and functional devices. The diameters of the first and second conductive vias are both smaller than or equal to the diameter of the conductive posts. The conductive posts can provide power to the chip; by setting a larger diameter, sufficient power supply current can be provided to the chip. Specifically, one end of the conductive post is electrically connected to the first wiring layer, and the other end is electrically connected to the second wiring layer. Specifically, the conductive post can be in contact with the circuit structure, allowing for non-soldering connection to the second wiring layer, improving structural stability and reliability. Furthermore, the conductive posts can connect to different circuit structures with the bridging chip and functional devices, thereby reducing power consumption and noise in the chip packaging structure.

[0015] In practical implementation, the adapter board may further include an insulating dielectric layer, which fills the area between the first and second wiring layers, excluding the bridging chip, functional devices, and conductive pillars. The insulating dielectric layer serves to insulate the bridging chip, functional devices, and conductive pillars, as well as to provide structural support between the first and second wiring layers.

[0016] In one possible implementation, a first conductive via extends from the interior of the bridging chip to the side of the bridging chip facing the second wiring layer, and the first conductive via makes contact with the circuit structure. This eliminates the need for soldering between the bridging chip and the second wiring layer, improving the connection reliability between them, effectively enhancing the structural stability of the chip package, and reducing manufacturing complexity.

[0017] In a specific implementation, a first conductive connection post is provided on the side of the chip facing the first multi-layer wiring layer, and a first connection terminal is provided on the side of the first multi-layer wiring layer facing the chip. The first conductive connection post is electrically connected to the first connection terminal via solder. In one possible implementation, the aperture of the first conductive connection post can be less than or equal to the size of the first connection terminal; alternatively, the aperture of the first conductive connection post can be greater than the size of the first connection terminal. In practical applications, the aperture of the first conductive connection post and the size of the first connection terminal can be reasonably set according to actual needs.

[0018] In one possible implementation, the second wiring layer has a second connection terminal on the side facing the bridging chip, and a first conductive via in the bridging chip is in contact with the second connection terminal. The diameter of the first conductive via can be less than or equal to the size of the second connection terminal; alternatively, the diameter of the first conductive via can also be greater than the size of the second connection terminal. In practical applications, the diameter of the first conductive via and the size of the second connection terminal can be reasonably set according to actual needs.

[0019] In one possible implementation, when the functional device is located between the first and second wiring layers, a second conductive connection post is provided on the side of the third wiring layer facing away from the active device, and the second conductive connection post is in contact with the second connection terminal. The aperture of the second conductive connection post can be less than or equal to the size of the second connection terminal; or, the aperture of the second conductive connection post can also be greater than the size of the second connection terminal. Similarly, a third conductive connection post is provided on the side of the fourth wiring layer facing away from the passive device, and the third conductive connection post is in contact with the second connection terminal. The aperture of the third conductive connection post can be less than or equal to the size of the second connection terminal; or, the aperture of the third conductive connection post can also be greater than the size of the second connection terminal. In practical applications, the apertures of the second and third conductive connection posts can be reasonably set according to actual needs.

[0020] In one possible implementation, a third connection terminal is provided on the side of the first wiring layer facing the bridging chip, and a fourth conductive connection post is provided on the side of the bridging chip facing the first wiring layer. The third connection terminal and the fourth conductive connection post are in contact. Similarly, when the functional device is located between the first and second wiring layers, a fourth conductive connection post can also be provided on the side of the active or passive device facing the first wiring layer. The active or passive device can be electrically connected to the third connection terminal through the fourth conductive connection post. In specific settings, the size of the third connection terminal can be less than or equal to the aperture of the fourth conductive connection post; or, the size of the third connection terminal can be greater than the aperture of the fourth conductive connection post. The size of the third connection terminal and the aperture of the fourth conductive connection post can be reasonably set according to actual needs.

[0021] In some embodiments of this application, a pre-bonding layer may be provided inside the active or passive components of the functional device. Exemplarily, the pre-bonding layer may be made of inorganic materials such as silicon oxide or silicon carbonitride. By providing a pre-bonding layer in the active or passive device, the diffusion of copper, silicon, or other ions from the back side of the functional device towards the front side can be prevented, thus avoiding interference with the active or metal layer on the front side. Furthermore, a metal interconnect layer and an organic dielectric layer may also be provided on the back side of the active or passive device. The metal interconnect layer may include copper bumps, and the second conductive via can be electrically connected to the circuit structure through the metal interconnect layer. The organic dielectric layer can act as an isolation layer, preventing leakage from the second conductive via.

[0022] In a specific configuration, the second wiring layer may include multiple dielectric layers, and each circuit structure may include multiple conductive layers. Adjacent conductive layers are insulated from each other by dielectric layers and electrically connected through vias in the dielectric layers. In the thickness direction of the second wiring layer, the vias in adjacent dielectric layers do not overlap. In this embodiment, the inclusion of multiple dielectric layers in the second wiring layer can alleviate stress. Furthermore, the inclusion of multiple conductive layers in the second wiring layer allows for the discrete configuration of different circuit structures, effectively improving current sharing. Additionally, the chip packaging structure may also include a substrate located on the side of the adapter plate away from the chip. By incorporating multiple dielectric and conductive layers in the second wiring layer, it can support a greater number of circuit structures. In a specific configuration, some circuits from the substrate can be transferred to the second wiring layer, thereby simplifying the internal structure of the substrate, reducing its thickness, and improving the structural reliability of the chip packaging structure.

[0023] In one possible implementation, the second rewiring layer may include a first dielectric layer and a second dielectric layer, with the second dielectric layer located on the side of the first dielectric layer facing away from the first rewiring layer. The first dielectric layer and the second dielectric layer comprise different materials, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer. In this embodiment, by providing a thicker second dielectric layer in the second rewiring layer, on the one hand, the second dielectric layer can carry multiple layers of traces, enabling more complex patterns and functional designs, and improving the electrical performance of the chip package structure; on the other hand, some circuits in the substrate can be selectively transferred to the second dielectric layer, thereby simplifying the internal structure of the substrate and reducing the thickness of the substrate. Since the substrate may pose a stress risk, thinning the substrate can reduce the overall stress of the chip package structure and improve the overall structural reliability.

[0024] In a specific configuration, the substrate may include a first circuit layer, a second circuit layer, and a support layer. The first circuit layer is located between the second circuit layer and the adapter plate, and the support layer is located between the first circuit layer and the second circuit layer. In a chip packaging structure, due to the different coefficients of thermal expansion of different materials, tension will occur between different film layers under the action of heat during manufacturing or use, forming stress in the chip packaging structure. In this embodiment, by providing a support layer in the substrate, the support layer can play a structural support role, thereby alleviating the stress in the chip packaging structure and improving the reliability of the chip packaging structure. In one possible implementation, the support layer may include, but is not limited to, glass materials or organic materials, which can reduce the overall thermal expansion coefficient mismatch of the packaging structure and make the support layer have a better support effect.

[0025] In the embodiments of this application, the positions of functional devices can be reasonably set according to actual needs. The specific setting methods of functional devices are described in detail below.

[0026] In some embodiments of this application, functional devices can be embedded in an adapter board and disposed between a first wiring layer and a second wiring layer. The functional devices are electrically connected to at least one chip through the first wiring layer. When the functional devices are active or passive, the electrical performance of the chip package structure can be improved and noise reduced. Furthermore, by providing bridging chips and conductive pillars in the adapter board, vertical power supply can be provided to the chips, effectively solving the problem of insufficient vertical power supply. Moreover, different chips can be interconnected through the bridging chips, increasing the interconnection density between chips. In one possible implementation, by providing conductive vias in the bridging chips and functional devices, the interconnection distance in the chip package structure can be shortened.

[0027] In some other embodiments of this application, the functional device can be disposed at the location of the first wiring layer. One possible arrangement is that at least a portion of the functional device can be located inside the first wiring layer, and the functional device is electrically connected to the first wiring layer. That is, the functional device can be completely embedded inside the first wiring layer; or, the functional device can be partially embedded inside the first wiring layer, with another portion protruding from the surface of the first wiring layer. Alternatively, it can be completely non-embedded, taking an external form. Another possible arrangement is that the functional device can be located on the side of the first wiring layer opposite to the second wiring layer, and the functional device is electrically connected to the first wiring layer. During the manufacturing process, a third wiring layer can be formed on the surface of the active device, and a fourth wiring layer can be formed on the surface of the passive device. Afterward, the fabricated functional device is installed at the location of the first wiring layer, and the active or passive device can be electrically connected to the first wiring layer or the chip via solder.

[0028] In some other embodiments of this application, the functional device can be disposed at the location of the second wiring layer. One possible arrangement is that at least a portion of the functional device can be located inside the second wiring layer, and the functional device and the circuit structure can be electrically connected via solder. That is, the functional device can be completely embedded inside the second wiring layer; or, a portion of the functional device is embedded inside the second wiring layer, and another portion protrudes from the surface of the second wiring layer. In other words, the functional device can be completely or partially embedded. Another possible arrangement is that the functional device can be located on the side of the second wiring layer opposite to the first wiring layer, and the functional device and the circuit structure can be electrically connected via solder. During fabrication, a third wiring layer can be formed on the surface of the active device, and a fourth wiring layer can be formed on the surface of the passive device. The fabricated functional device can be fixed inside or on the surface of the second wiring layer using bonding or adhesive methods.

[0029] Secondly, embodiments of this application also provide an electronic device, which may include any of the chip packaging structures and circuit boards described in the first aspect above, with the chip packaging structure electrically connected to the circuit board. Since the chip packaging structure described in the first aspect can improve the problems of insufficient vertical power supply, high noise, and high power consumption, and achieve high-performance expression of multiple chips packaged together, the electronic device including the chip packaging structure described in the first aspect also has better performance. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0031] Figure 2 is a schematic diagram of the chip packaging structure provided in an embodiment of this application;

[0032] Figure 3a is another schematic diagram of the chip packaging structure provided in the embodiment of this application;

[0033] Figure 3b is another schematic diagram of the chip packaging structure provided in the embodiment of this application;

[0034] Figure 4 is another schematic diagram of the chip packaging structure provided in the embodiment of this application;

[0035] Figure 5 is another schematic diagram of the chip packaging structure provided in the embodiment of this application;

[0036] Figure 6 is another schematic diagram of the chip packaging structure provided in the embodiment of this application;

[0037] Figure 7 is another schematic diagram of the chip packaging structure provided in the embodiment of this application.

[0038] Reference numerals: 100 - Electronic device; 101 - Chip package structure; 102 - Circuit board; 11, 11a, 11b, 11c, 11d - Chip; 12 - Adapter board; 121 - Bridge chip; 121a - First bridge chip; 121b - Second bridge chip; 122 - Functional device; 122a - Active device; 122b - Passive device; 123 - First redistribution layer; 124 - Second redistribution layer; m1 - First dielectric layer; m2 - Second dielectric layer; 125 - Conductive pillar; 125a - First conductive pillar; 125b - Second conductive pillar; 126 - Insulating dielectric layer; 13 - Filling structure; 14 - Substrate; 141 - First circuit layer; 142 - Second Circuit layer; 143-Support layer; W-Circuit structure; W1-Conductive layer; T1-First conductive via; T2-Second conductive via; V-Through via; R1-Third redistribution layer; R2-Fourth redistribution layer; U1-First conductive connection post; U2-First connection terminal; U3-Second connection terminal; U4-Second conductive connection post; U5-Third conductive connection post; U6-Third connection terminal; U7-Fourth conductive connection post; k1-Pre-bonding layer; k2-Metallic connection layer; k3-Organic dielectric layer. Detailed Implementation

[0039] To address the issues of insufficient vertical power supply, poor power supply stability, high noise, and high power consumption in chip packaging structures, and to achieve high-performance chip packaging, this application provides a chip packaging structure and an electronic device. The chip packaging structure in this application can adopt a fan-out packaging (FOP) form. FOP packaging allows the chip to be connected to the circuit board in a "fan-out" manner through a redistribution layer (RDL), enabling high-speed, high-density interconnection of the chip. Of course, in some cases, the chip packaging structure in this application can also adopt other packaging forms, which are not limited here.

[0040] This application can be applied to various fields such as artificial intelligence (AI) computing, network information processing, 5G, 6G, autonomous driving, and high-performance computing. The chip packaging structure provided in this application's embodiments enables high-performance expression of multiple devices within the same packaging structure, allowing for rapid and efficient processing and transmission of large amounts of information. The chip packaging structure in this application's embodiments can be applied to various types of electronic devices, such as AI computers, servers, base stations, autonomous driving intelligent chips, high-performance computer chips, etc., or to mobile phones, tablets, laptops, smart wearable devices, smart TVs, smart door locks, smart home appliances, and other electronic devices.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0042] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.

[0043] The terms describing position and direction used in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are merely illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are intended solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all such changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] Figure 1 is a structural schematic diagram of the electronic device provided in an embodiment of this application. The left side of Figure 1 is a top view of the electronic device, and the right side of Figure 1 is a cross-sectional view of the top view of the electronic device at the dashed line AA'. As shown in Figure 1, the electronic device 100 provided in this embodiment of the application may include: a chip package structure 101 and a circuit board 102, wherein the chip package structure 101 and the circuit board 102 are electrically connected. Figure 1 illustrates the electronic device 100 as a mobile phone. When the electronic device 100 is another device, the position, shape, size, etc. of the chip package structure 101 and the circuit board 102 in the electronic device 100 can be reasonably set according to actual needs.

[0045] Figure 2 is a schematic diagram of the chip packaging structure provided in an embodiment of this application. As shown in Figure 2, the chip packaging structure 101 provided in this embodiment may include: multiple chips 11 and an adapter board 12. The adapter board 12 may include: a bridging chip 121, a functional device 122, a first rewiring layer 123, and a second rewiring layer 124. The functional device 122 may include: an active device 122a and / or a passive device 122b. Figure 2 illustrates this by showing the functional device 122 including both active and passive devices 122b. In a specific configuration, the functional device 122 may also include only the active device 122a, or it may include only the passive device 122b. The bridging chip 121 is located between the first rewiring layer 123 and the second rewiring layer 124, and each chip 11 is located on the side of the first rewiring layer 123 facing away from the second rewiring layer 124. The bridging chip 121 is electrically connected to the first wiring layer 123, at least two chips 11 are electrically connected through the bridging chip 121, and at least one chip 11 is electrically connected to the functional device 122. The second wiring layer 124 may include multiple discretely arranged circuit structures W.

[0046] In the chip packaging structure 101 provided in this application embodiment, a bridging chip 121 is provided in the adapter board 12. The bridging chip 121 is electrically connected to at least two chips 11 through a first rewiring layer 123, which can improve the interconnection density of the chips 11 and reduce signal transmission delay. In addition, the adapter board 12 is also provided with functional devices 122, which may include active devices 122a and / or passive devices 122b. Furthermore, the second rewiring layer 124 includes multiple discretely arranged circuit structures W, which can reduce the power consumption and noise of the chip packaging structure 101 and improve the vertical power supply capability and power supply stability. Therefore, the chip packaging structure 101 provided in this application embodiment can improve the problems of insufficient vertical power supply, poor power supply stability, high noise, and high power consumption, and improve the problem of large signal transmission delay, realizing high-performance expression of multiple chips 11 packaged together.

[0047] In this embodiment, the chip packaging structure 101 can encapsulate multiple chips 11, with the number of chips 11 being greater than or equal to two. The chips 11 in the chip packaging structure 101 can be arranged side-by-side to achieve 2.5D chip packaging; or, the chips 11 in the chip packaging structure 101 can be stacked to achieve 3D chip packaging; or, some chips 11 in the chip packaging structure 101 can be arranged side-by-side, while others can be stacked to achieve 3.5D chip packaging. For example, in Figure 2, chips 11a, 11b, and 11c are stacked, and chip 11d is arranged side-by-side with the stacked structure formed by chips 11a, 11b, and 11c, thus achieving 3.5D chip packaging. In specific configurations, the number and arrangement of chips 11 in the chip packaging structure 101 can be reasonably set according to actual needs. In specific configurations, chip 11 can be interconnected with the first wiring layer 123 using a flip chip (FC) method. Chip 11 can be electrically connected to the first wiring layer 123 through bonding methods such as reflow soldering and thermal compression bonding (TCB).

[0048] Referring again to Figure 2, in some embodiments of this application, the bridging chip 121 may include a first conductive via T1, which extends from the interior of the bridging chip 121 to its surface, and the aperture of the first conductive via T1 is between 3 μm and 20 μm. The functional device 122 may include a second conductive via T2, the aperture of which is between 3 μm and 20 μm. Exemplarily, when the bridging chip 121 includes a silicon substrate, the first conductive via T1 may be a through-silicon via (TSV), and when the functional device 122 includes a silicon substrate, the second conductive via T2 may be a through-silicon via (TSV).

[0049] In one possible implementation, the functional device 122 may further include a redistribution layer located on the surface of the active device 122a or the passive device 122b, wherein the second conductive via T2 may be electrically connected to the redistribution layer. For ease of distinction, in this embodiment, the redistribution layer located on the surface of the active device 122a is referred to as the third redistribution layer R1, and the redistribution layer located on the surface of the passive device 122b is referred to as the fourth redistribution layer R2.

[0050] In this embodiment, by providing conductive vias (first conductive via T1 or second conductive via T2) in the bridging chip 121 and the functional device 122, the interconnection distance in the chip package structure 101 can be shortened. For example, in FIG2, the first redistribution layer 123 is connected to the second redistribution layer 124 through the wiring layer in the bridging chip 121 and the first conductive via T1, and the first redistribution layer 123 is connected to the second redistribution layer 124 through the wiring layer in the functional device 122, the second conductive via T2, and the redistribution layer (R1 or R2), thus shortening the interconnection distance between the first redistribution layer 123 and the second redistribution layer 124. Furthermore, the aperture of the conductive via is related to the interconnection density of the bridging chip 121 or the functional device 122; the smaller the aperture of the conductive via, the greater the interconnection density of the bridging chip 121 or the functional device 122. Furthermore, the aperture of the conductive via is related to the electrical performance of the bridging chip 121 or the functional device 122. The larger the aperture of the conductive via, the greater the current that can flow through it. In this embodiment, the aperture of the first conductive via T1 is set between 3μm and 20μm, and the aperture of the second conductive via T2 is set between 3μm and 20μm. The aperture range of the conductive vias is relatively large. In specific settings, the aperture of the conductive vias can be reasonably set according to the density and electrical performance requirements of the bridging chip 121 and the functional device 122, thereby effectively improving the current sharing effect and achieving more stable power transmission, higher bandwidth, and lower latency.

[0051] In one possible implementation, the functional device 122 may include an active device 122a, which, exemplarily, may be an integrated voltage regulator (IVR). The aperture of the second conductive via T2 in the active device 122a may be less than or equal to the aperture of the first conductive via T1. In specific configurations, the aperture of the first conductive via T1 may be in the range of 10 μm to 20 μm, and the aperture of the second conductive via T2 in the active device 122a may be in the range of 3 μm to 8 μm. The bridging chip 121 can be used to provide power to the chip 11. Setting the aperture of the first conductive via T1 in the bridging chip 121 to be larger can effectively simplify the process, reduce manufacturing costs, improve yield, and expand current carrying capacity. Thus, sufficient power supply current can be provided to the chip through the bridging chip 121, effectively improving the problem of insufficient vertical power supply. The smaller aperture of the second conductive via T2 in the active device 122a reduces the area occupied by a single via, thereby increasing density and optimizing chip performance.

[0052] In another possible implementation, the functional device 122 may include an active device 122a and a passive device 122b. For example, the active device 122a may be an integrated voltage regulator (IVR); the passive device 122b may be an integrated passive device (IPD), which may include passive components such as capacitors, resistors, and inductors. The aperture of the second conductive via T2 in the active device 122a is less than or equal to the aperture of the first conductive via T1. The bridging chip 121 can be used to provide power to the chip 11. Setting the aperture of the first conductive via T1 in the bridging chip 121 to a larger size can effectively simplify the process, reduce manufacturing costs, improve yield, and expand current carrying capacity. This allows the bridging chip 121 to provide sufficient power to the chip, effectively improving the problem of insufficient vertical power supply. In specific configurations, the aperture of the first conductive via T1 can be in the range of 10μm to 20μm, the aperture of the second conductive via T2 in the active device 122a can be in the range of 3μm to 8μm, and the aperture of the second conductive via T2 in the passive device 122b can be in the range of 10μm to 20μm.

[0053] Of course, in some cases, the aperture of the first conductive via T1 in the bridge chip 121 can also be set to be smaller. For example, the aperture of the first conductive via T1 can be in the range of 3μm to 12μm, thereby increasing the interconnection density of the bridge chip 121. In specific settings, the aperture of the first conductive via T1 can be reasonably set according to actual needs.

[0054] Referring again to Figure 2, in this embodiment, the adapter board 12 may further include a conductive post 125, located between the first rewiring layer 123 and the second rewiring layer 124. The conductive post 125 is positioned other than the bridging chip 121 and the functional device 122. The diameters of the first conductive via T1 and the second conductive via T2 are both smaller than or equal to the diameter of the conductive post 125. The conductive post 125 can be used to provide power to the chip 11. By setting the diameter of the conductive post 125 to be relatively large, sufficient power supply current can be provided to the chip 11. In a specific configuration, one end of the conductive post 125 is electrically connected to the first rewiring layer 123, and the other end is electrically connected to the second rewiring layer 124. Specifically, the conductive post 125 can be in contact with the circuit structure W. In this way, the conductive post 125 can be connected to the second rewiring layer 124 in a non-soldering manner, improving structural stability and reliability. In addition, the conductive post 125 can be connected to different circuit structures W with the bridging chip 121 and the functional device 122, thereby reducing the power consumption and noise of the chip package structure 101.

[0055] In a specific implementation, the adapter board 12 may further include an insulating dielectric layer 126, which fills the area between the first rewiring layer 123 and the second rewiring layer 124, excluding the bridging chip 121, the functional device 122, and the conductive pillar 125. The insulating dielectric layer 126 serves to insulate the bridging chip 121, the functional device 122, and the conductive pillar 125, and also provides structural support between the first rewiring layer 123 and the second rewiring layer 124.

[0056] Referring again to Figure 2, in one possible implementation, a first conductive via T1 extends from the interior of the bridging chip 121 to the side of the bridging chip 121 facing the second redistribution layer 124, and the first conductive via T1 is in contact with the circuit structure W. In this way, the bridging chip 121 and the second redistribution layer 124 do not need to be connected by soldering, which can improve the connection reliability between the bridging chip 121 and the second redistribution layer 124, effectively improve the structural stability of the chip package structure 101, and reduce the manufacturing difficulty.

[0057] In a specific implementation, as shown in Figure 2, a first conductive connection post U1 is provided on the side of the chip 11 facing the first redistribution layer 123, and a first connection terminal U2 is provided on the side of the first redistribution layer 123 facing the chip 11. The first conductive connection post U1 is electrically connected to the first connection terminal U2 through solder Q. In one possible implementation, the aperture of the first conductive connection post U1 can be less than or equal to the size of the first connection terminal U2. Figure 3a is another schematic diagram of the chip packaging structure provided in the embodiment of this application. As shown in Figure 3a, in some cases, the aperture of the first conductive connection post U1 can also be larger than the size of the first connection terminal U2. In practical applications, the aperture of the first conductive connection post U1 and the size of the first connection terminal U2 can be reasonably set according to actual needs.

[0058] In one possible implementation, the second redistribution layer 124 has a second connection terminal U3 on the side facing the bridging chip 121, and the first conductive via T1 in the bridging chip 121 is in contact with the second connection terminal U3. As shown in Figure 2, the diameter of the first conductive via T1 can be less than or equal to the size of the second connection terminal U3; or, as shown in Figure 3a, the diameter of the first conductive via T1 can also be greater than the size of the second connection terminal U3. In practical applications, the diameter of the first conductive via T1 and the size of the second connection terminal U3 can be reasonably set according to actual needs.

[0059] In one possible implementation, when the functional device 122 is located between the first redistribution layer 123 and the second redistribution layer 124, the third redistribution layer R1 has a second conductive connection post U4 on the side facing away from the active device 122a, and the second conductive connection post U4 is in contact with the second connection terminal U3. As shown in Figure 2, the aperture of the second conductive connection post U4 can be less than or equal to the size of the second connection terminal U3; or, as shown in Figure 3a, the aperture of the second conductive connection post U4 can also be greater than the size of the second connection terminal U3. Similarly, the fourth redistribution layer R2 has a third conductive connection post U5 on the side facing away from the passive device 122b, and the third conductive connection post U5 is in contact with the second connection terminal U3. As shown in Figure 2, the aperture of the third conductive connection post U5 can be less than or equal to the size of the second connection terminal U3; or, as shown in Figure 3a, the aperture of the third conductive connection post U5 can also be greater than the size of the second connection terminal U3. In practical applications, the apertures of the second conductive connection post U4 and the third conductive connection post U5 can be reasonably set according to actual needs.

[0060] In one possible implementation, the first wiring layer 123 has a third connection terminal U6 on the side facing the bridging chip 121, and the bridging chip 121 has a fourth conductive connection post U7 on the side facing the first wiring layer 123. The third connection terminal U6 and the fourth conductive connection post U7 are in contact connection. Similarly, when the functional device 122 is located between the first wiring layer 123 and the second wiring layer 124, the active device 122a or the passive device 122b can also have a fourth conductive connection post U7 on the side facing the first wiring layer 123. The active device 122a or the passive device 122b can be electrically connected to the third connection terminal U6 through the fourth conductive connection post U7. In a specific setting, as shown in Figure 2, the size of the third connection terminal U6 can be less than or equal to the aperture of the fourth conductive connection post U7; or, as shown in Figure 3a, the size of the third connection terminal U6 can also be greater than the aperture of the fourth conductive connection post U7. The size of the third connection terminal U6 and the aperture of the fourth conductive connection post U7 can be reasonably set according to actual needs.

[0061] Figure 3b is another schematic diagram of the chip packaging structure provided in an embodiment of this application. As shown in Figure 3b, in some embodiments of this application, a pre-bonding layer k1 may be provided inside the active device 122a or passive device 122b in the functional device 122. Exemplarily, the pre-bonding layer k1 may be made of inorganic materials such as silicon oxide or silicon carbonitride. By providing the pre-bonding layer k1 in the active device 122a or passive device 122b, the diffusion of copper, silicon, and other ions from the back side of the functional device 122 towards the front side can be prevented, thus preventing them from affecting the active layer or metal layer on the front side. In addition, a metal connection layer k2 and an organic dielectric layer k3 may also be provided on the back side of the active device 122a or passive device 122b. The metal connection layer k2 may include copper bumps, and the second conductive via T2 can be electrically connected to the circuit structure W through the metal connection layer k2. The organic dielectric layer k3 can act as an isolation layer to prevent leakage from the second conductive via T2.

[0062] In a specific configuration, as shown in Figure 2, the second rewiring layer 124 may include multiple dielectric layers. For example, in Figure 2, the second rewiring layer 124 may include a first dielectric layer m1 and a second dielectric layer m2. Each circuit structure W may include multiple conductive layers W1, with adjacent conductive layers W1 insulated from each other by dielectric layers and electrically connected by vias V in the dielectric layers. In the thickness direction of the second rewiring layer 124, the vias V in adjacent dielectric layers do not overlap. In this embodiment, the second rewiring layer 124 has multiple dielectric layers, which can alleviate stress. Furthermore, the second rewiring layer 124 has multiple conductive layers W1, which allows for the discrete configuration of different circuit structures W, effectively improving current sharing. In addition, the chip packaging structure 101 may also include a substrate 14, which is located on the side of the adapter plate 12 away from the chip 11. By providing multiple dielectric layers and multiple conductive layers W1 in the second wiring layer 124, the second wiring layer 124 can carry more circuit structures W. In specific configuration, some circuits in the substrate 14 can be transferred to the second wiring layer 124, thereby simplifying the internal structure of the substrate 14, reducing the thickness of the substrate 14, and improving the structural reliability of the chip packaging structure 101.

[0063] In one possible implementation, as shown in FIG2, the second redistribution layer 124 may include a first dielectric layer m1 and a second dielectric layer m2, wherein the second dielectric layer m2 is located on the side of the first dielectric layer m1 opposite to the first redistribution layer 123. The first dielectric layer m1 and the second dielectric layer m2 comprise different materials, and the thickness of the second dielectric layer m2 is greater than the thickness of the first dielectric layer m1. Exemplarily, the first dielectric layer m1 may include, but is not limited to, organic materials such as polyimide (PI), acrylonitrile butadiene styrene (ABS), and Ajinomoto build-up film (ABF), and the second dielectric layer m2 may include, but is not limited to, organic materials such as polyimide, acrylonitrile butadiene styrene, and Ajinomoto build-up film. In this embodiment, by providing a thicker second dielectric layer m2 within the second redistribution layer 124, on the one hand, the second dielectric layer m2 can support multiple layers of traces, enabling more complex patterns and functional designs, and improving the electrical performance of the chip package structure 101; on the other hand, some circuitry in the substrate 14 can be selectively transferred to the second dielectric layer m2, thereby simplifying the internal structure of the substrate 14 and reducing its thickness. Since the substrate 14 may pose a stress risk, thinning the substrate 14 can reduce the overall stress of the chip package structure 101 and improve the overall structural reliability.

[0064] Referring again to Figure 2, the substrate 14 may include a first circuit layer 141, a second circuit layer 142, and a support layer 143. The first circuit layer 141 is located between the second circuit layer 142 and the adapter plate 12, and the support layer 143 is located between the first circuit layer 141 and the second circuit layer 142. In the chip packaging structure 101, due to the different coefficients of thermal expansion of different materials, under the action of heat during manufacturing or use, tension will occur between different film layers, forming stress in the chip packaging structure 101. In this embodiment, by providing a support layer 143 in the substrate 14, the support layer 143 can play a structural support role, thereby alleviating the stress in the chip packaging structure 101 and improving the reliability of the chip packaging structure 101. In one possible implementation, the support layer 143 may be, but is not limited to, glass or organic materials, which can reduce the overall thermal expansion coefficient mismatch of the packaging structure and make the support effect of the support layer 143 better.

[0065] In the embodiments of this application, the position of the functional device 122 can be reasonably set according to actual needs. The specific setting method of the functional device 122 will be described in detail below with reference to the accompanying drawings.

[0066] In some embodiments of this application, as shown in Figures 2 and 3a, the functional device 122 can be embedded in the adapter board 12. The functional device 122 can be disposed between the first rewiring layer 123 and the second rewiring layer 124, and the functional device 122 is electrically connected to at least one chip 11 through the first rewiring layer 123. When the functional device 122 is an active device 122a or a passive device 122b, the electrical performance of the chip package structure 101 can be improved and noise reduced. In addition, by providing a bridging chip 121 and conductive pillars 125 in the adapter board 12, vertical power supply can be provided to the chip 11, effectively solving the problem of insufficient vertical power supply. Furthermore, different chips 11 can be interconnected through the bridging chip 121, increasing the interconnection density between chips 11. In one possible implementation, by providing conductive vias in the bridging chip 121 and the functional device 122, the interconnection distance in the chip package structure 101 can be shortened.

[0067] In some other embodiments of this application, the functional device 122 may be disposed at the location of the first wiring layer 123. Figure 4 is another structural schematic diagram of the chip packaging structure provided in the embodiment of this application. As shown in Figure 4, one possible arrangement is that at least a portion of the functional device 122 may be located inside the first wiring layer 123, and the functional device 122 is electrically connected to the first wiring layer 123. That is, the functional device 122 may be completely embedded inside the first wiring layer 123; or, the functional device 122 may be partially embedded inside the first wiring layer 123, and the other portion may protrude from the surface of the first wiring layer 123. Alternatively, it may not be embedded at all, and may be externally mounted. Figure 5 is another structural schematic diagram of the chip packaging structure provided in the embodiment of this application. As shown in Figure 5, another possible arrangement is that the functional device 122 may be located on the side of the first wiring layer 123 opposite to the second wiring layer 124, and the functional device 122 is electrically connected to the first wiring layer 123. Referring to Figures 4 and 5, during the manufacturing process, a third wiring layer R1 can be formed on the surface of the active device 122a, and a fourth wiring layer R2 can be formed on the surface of the passive device 122b. After that, the fabricated functional device 122 is installed at the position of the first wiring layer 123. The active device 122a or the passive device 122b can be electrically connected to the first wiring layer 123 or the chip 11 through solder Q.

[0068] Multiple chips 11 can be packaged in the chip package structure 101. For example, in Figures 4 and 5, chips 11a and 11b can be interconnected through chip 11c. Chip 11d is arranged side by side with the stacked structure formed by chips 11a, 11b and 11c. In order to make the surface of the chip package structure 101 flush, a filling structure 13 can be provided in the chip package structure 101. For example, the filling structure 13 may include silicon material or organic material. In Figures 4 and 5, the filling structure is located on top of chips 11a and 11b. In specific settings, the position and size of the filling structure 13 can be reasonably set according to the specific structure of each chip 11.

[0069] In one possible implementation, as shown in Figures 4 and 5, the adapter board 12 may further include a first conductive post 125a. The first conductive post 125a is located between the first rewiring layer 123 and the second rewiring layer 124, and is located at a position other than the bridge chip 121. The functional device 122 is electrically connected to the circuit structure W through the first rewiring layer 123 and the first conductive post 125a. By providing the first conductive post 125a in the adapter board 12 for supplying power to the functional device 122, sufficient power can be provided to the functional device 122.

[0070] In another possible implementation, continuing to refer to Figures 4 and 5, at least two bridging chips 121 can be provided in the adapter board 12. For example, the adapter board 12 may include a first bridging chip 121a and a second bridging chip 121b, located between the first rewiring layer 123 and the second rewiring layer 124. The first bridging chip 121a can be electrically connected to at least two chips 11 through the first rewiring layer 123, enabling at least two chips 11 to be interconnected through the first bridging chip 121a, thereby increasing the interconnection density of the chip package structure 101. The functional device 122 can be electrically connected to the circuit structure W through the first rewiring layer 123 and the second bridging chip 121b. That is, sufficient power can also be provided to the functional device 122 through the second bridging chip 121b, effectively improving the problem of insufficient vertical power supply.

[0071] In some other embodiments of this application, the functional device 122 may be disposed at the location of the second wiring layer 124. Figure 6 is another schematic diagram of the chip packaging structure provided in the embodiment of this application. As shown in Figure 6, one possible arrangement is that at least a portion of the functional device 122 may be located inside the second wiring layer 124, and the functional device 122 and the circuit structure W may be electrically connected by solder Q. That is, the functional device 122 may be completely embedded inside the second wiring layer 124; or, a portion of the functional device 122 may be embedded inside the second wiring layer 124, and another portion may protrude from the surface of the second wiring layer 124. That is, the functional device 122 may be completely embedded or partially embedded. Figure 7 is another schematic diagram of the chip packaging structure provided in the embodiment of this application. As shown in Figure 7, another possible arrangement is that the functional device 122 may be located on the side of the second wiring layer 124 away from the first wiring layer 123, and the functional device 122 may be electrically connected to the circuit structure W by solder Q. Referring to Figures 6 and 7, during the fabrication process, a third wiring layer R1 can be formed on the surface of the active device 122a, and a fourth wiring layer R2 can be formed on the surface of the passive device 122b. The fabricated functional device 122 can be fixed inside or on the surface of the second wiring layer 124 by bonding or adhesive methods.

[0072] In one possible implementation, as shown in Figures 6 and 7, the adapter board 12 may further include a second conductive post 125b, located between the first rewiring layer 123 and the second rewiring layer 124, and situated at a location other than the bridging chip 121. The functional device 122 can be electrically connected to the first rewiring layer 123 via the circuit structure W and the second conductive post 125b. The larger aperture of the second conductive post 125b reduces signal loss during transmission of the functional device 122. Furthermore, at least two bridging chips 121 can be provided in the adapter board 12, thereby enabling power supply to the chip 11 through multiple bridging chips 121, effectively solving the problem of insufficient vertical charging. Additionally, the bridging chips 121 can be used to interconnect different chips 11, increasing the interconnection density of the chip package structure 101.

[0073] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0074] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip packaging structure, characterized in that, include: Multiple chips and adapter boards; The adapter board includes: a bridging chip, functional devices, a first wiring layer, and a second wiring layer; the functional devices include: active devices and / or passive devices. The bridging chip is located between the first rewiring layer and the second rewiring layer, and the plurality of chips are located on the side of the first rewiring layer away from the second rewiring layer; The bridging chip is electrically connected to the first redistribution layer, and at least two of the plurality of chips are electrically connected through the bridging chip; at least one of the plurality of chips is electrically connected to the functional device. The second wiring layer includes multiple discrete circuit structures.

2. The chip packaging structure as described in claim 1, characterized in that, The bridging chip includes a first conductive via, which extends from the interior of the bridging chip to the surface of the bridging chip, and the diameter of the first conductive via is between 3μm and 20μm. The functional device includes a second conductive via, the diameter of which is between 3 μm and 20 μm.

3. The chip packaging structure as described in claim 2, characterized in that, The functional device includes an active device, wherein the diameter of the second conductive via in the active device is less than or equal to the diameter of the first conductive via.

4. The chip packaging structure as described in claim 2, characterized in that, The functional device includes: an active device and a passive device, wherein the aperture of the second conductive via in the active device is less than or equal to the aperture of the second conductive via in the passive device; The diameter of the second conductive via in the active device is less than or equal to the diameter of the first conductive via.

5. The chip packaging structure according to any one of claims 2 to 4, characterized in that, The first conductive via extends from the interior of the bridging chip to the side of the bridging chip facing the second redistribution layer, and the first conductive via is in contact with the circuit structure.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that, The functional device is disposed between the first rewiring layer and the second rewiring layer; The functional device is electrically connected to at least one of the chips through the first rewiring layer.

7. The chip packaging structure according to any one of claims 1 to 5, characterized in that, At least a portion of the functional device is located inside the first rewiring layer; or, the functional device is located on the side of the first rewiring layer opposite to the second rewiring layer. The functional device is electrically connected to the first overlay layer.

8. The chip packaging structure as described in claim 7, characterized in that, The adapter board further includes: a first conductive post, which is located between the first redistribution layer and the second redistribution layer, and the first conductive post is located at a position other than the bridge chip; The functional device is electrically connected to the circuit structure through the first rewiring layer and the first conductive pillar.

9. The chip packaging structure as described in claim 7 or 8, characterized in that, The adapter board includes: a first bridging chip and a second bridging chip, wherein the first bridging chip and the second bridging chip are located between the first redistribution layer and the second redistribution layer; The first bridging chip is electrically connected to at least two of the chips through the first rewiring layer, and the functional device is electrically connected to the circuit structure through the first rewiring layer and the second bridging chip.

10. The chip packaging structure according to any one of claims 1 to 5, characterized in that, At least a portion of the functional device is located inside the second rewiring layer; or, the functional device is located on the side of the second rewiring layer opposite to the first rewiring layer. The functional device is in contact with the circuit structure.

11. The chip packaging structure as described in claim 10, characterized in that, The adapter board further includes: a second conductive post; the second conductive post is located between the first redistribution layer and the second redistribution layer, and the second conductive post is located at a position other than the bridge chip; The functional device is electrically connected to the first rewiring layer through the circuit structure and the second conductive post.

12. The chip packaging structure according to any one of claims 1 to 11, characterized in that, The second rewiring layer includes: multiple dielectric layers; Each of the plurality of circuit structures includes: multiple conductive layers, wherein two adjacent conductive layers are insulated from each other through the dielectric layer, and two adjacent conductive layers are electrically connected through through-holes in the dielectric layer.

13. The chip packaging structure as described in claim 12, characterized in that, The multilayer dielectric layer includes: a first dielectric layer and a second dielectric layer; The second dielectric layer is located on the side of the first dielectric layer that is opposite to the first redistribution layer; The first dielectric layer and the second dielectric layer are made of different materials, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.

14. The chip packaging structure according to any one of claims 1 to 13, characterized in that, The chip packaging structure further includes: a substrate, the substrate being located on the side of the adapter plate opposite to the chip; The substrate includes a first circuit layer, a second circuit layer, and a support layer. The first circuit layer is located between the second circuit layer and the adapter board, and the support layer is located between the first circuit layer and the second circuit layer.

15. An electronic device, characterized in that, include: The chip packaging structure and circuit board according to any one of claims 1 to 14, wherein the chip packaging structure is electrically connected to the circuit board.

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