Photonic integrated chip and forming method therefor

Abstract

A photonic integrated chip and a forming method therefor. The method comprises: providing a first substrate having a first side and a second side opposite to each other, the first substrate comprising a bottom structural layer and a MEMS structural material layer located on the bottom structural layer; etching the MEMS structural material layer from the second side to form a MEMS structural layer, the MEMS structural layer comprising a movable portion; forming a silicon photonic structural layer from the second side, the silicon photonic structural layer being stacked with the MEMS structural layer, the silicon photonic structural layer comprising a first waveguide layer, and the movable portion being used for driving the first waveguide layer; after forming the silicon photonic structural layer, bonding the first substrate to a second substrate; after bonding the first substrate to the second substrate, removing the bottom structural layer from the first side; and after removing the bottom structural layer, forming a first oxide layer from the first side, the first oxide layer being stacked with the MEMS structural layer, and the MEMS structural layer being located between the silicon photonic structural layer and the first oxide layer. The photonic integrated chip formed by the method provided by the present invention has high performance and is easy to drive.

Description

Photonic integrated chips and their fabrication methods

[0001] This application claims priority to Chinese Patent Application No. 202411719253.4, filed on November 28, 2024, entitled "Photonic Integrated Chip and Method for Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of optical communication, and more particularly to a photonic integrated chip and a method for forming the same. Background Technology

[0003] By combining silicon photonics technology with microelectromechanical systems (MEMS) technology, photonic integrated chips can not only achieve higher performance levels, higher sensitivity and responsivity, but also have advantages such as integration, thus having broad application prospects.

[0004] In existing technologies, silicon is typically used as the material for MEMS structures to provide better mechanical properties. However, since silicon photonic structures contain many temperature-sensitive materials that cannot withstand the temperatures required for silicon deposition (above 1000°C), to avoid the impact of the high temperatures of silicon deposition on the silicon photonic structure during the fabrication of silicon photonic MEMS chips, a silicon photonic structure is usually formed on top of the MEMS structure after the MEMS structure is formed.

[0005] The following is a commonly used method for fabricating silicon photonics MEMS chips:

[0006] Please refer to Figure 1 to form a MEMS structure 10, and fill the MEMS structure 10 with a sacrificial layer 20. The MEMS structure 10 has a cavity 11 (as shown in Figure 2) and a functional through hole 12 connecting the cavity 11 (as shown in Figure 2).

[0007] Referring to Figure 2, a silicon photonics structure 30 is formed on the MEMS structure 10. The silicon photonics structure 30 includes a lower cladding layer 31, an upper cladding layer 32, and several waveguide structures 33. The waveguide structures 33 are located within the lower cladding layer 31 and the upper cladding layer 32, and the number of waveguide structures 33 can be one or more depending on the requirements.

[0008] Please continue to refer to Figure 2. After forming the silicon photonics structure 30, a release opening 21 is formed to expose the sacrificial layer 20, and the sacrificial material in the cavity 11 and the functional via 12 is removed based on the release opening 21 to release the MEMS structure.

[0009] However, silicon photonic devices require a thicker cladding layer (typically, the thickness of silicon photonic devices is in the nanometer range, while the thickness of the cladding layer is in the micrometer range). That is, the lower cladding layer 31 needs to have a large layer thickness. Therefore, due to the limitation of the layer thickness, the MEMS structure 10 is far away from the waveguide structure 33, resulting in poor driving performance when the MEMS structure 10 drives the waveguide structure 33. Summary of the Invention

[0010] The technical problem solved by the present invention is to provide a photonic integrated chip and a method for forming the same, so that the photonic integrated chip has high performance and is easy to drive.

[0011] To address the aforementioned technical problems, the present invention provides a method for forming a photonic integrated chip, comprising: providing a first substrate having a first side and a second side opposite to each other; the first substrate including a bottom structural layer and a MEMS structural material layer located on the bottom structural layer; the second side exposing the MEMS structural material layer; etching the MEMS structural material layer from the second side to form a MEMS structural layer, the MEMS structural layer including a movable portion; after forming the MEMS structural layer, forming a silicon photonic structure layer from the second side, the silicon photonic structure layer being stacked with the MEMS structural layer, the silicon photonic structure layer including a first waveguide layer, the movable portion being used to drive the first waveguide layer; after forming the silicon photonic structure layer, bonding the first substrate to a second substrate, the second side facing the second substrate; after bonding the first substrate to the second substrate, removing the bottom structural layer from the first side; after removing the bottom structural layer, forming a first oxide layer from the first side, the first oxide layer being stacked with the MEMS structural layer, the MEMS structural layer being located between the silicon photonic structure layer and the first oxide layer.

[0012] Optionally, the method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the first waveguide layer from the second side; and / or, the method for forming the photonic integrated chip further includes: forming a third waveguide layer from the first side after removing the bottom structure layer, the third waveguide layer being located within the first oxide layer, and the movable part being used to selectively drive the first waveguide layer and the third waveguide layer.

[0013] Optionally, the method for forming the silicon photonic structure layer further includes: forming a second oxide layer on the first substrate from the second side; and forming a first waveguide layer located within the second oxide layer from the second side before forming the second oxide layer, or during the process of forming the second oxide layer.

[0014] Optionally, the method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the second oxide layer from the second side; and forming a third oxide layer on the second oxide layer and on the surface of the second waveguide layer.

[0015] Optionally, before forming the second waveguide layer and the third oxide layer, the method for forming the silicon photonic structure layer further includes: forming a plurality of first conductive vias in the second oxide layer from the second side, wherein one end of any first conductive via contacts the MEMS structure layer or the first waveguide layer, and the other end of the first conductive via is exposed by the surface of the second oxide layer; forming an electrostatic driver electrode layer on the end face of the other end of the first conductive via and the surface of the second oxide layer from the second side; after forming the second waveguide layer and the third oxide layer, the method for forming the silicon photonic structure layer further includes: forming a plurality of second conductive vias in the third oxide layer from the second side, wherein one end of the second conductive via contacts the electrostatic driver electrode layer, and the other end of the second conductive via is exposed by the surface of the third oxide layer.

[0016] Optionally, the second substrate has an integrated driving circuit, and after the first substrate and the second substrate are bonded, the second conductive via is electrically interconnected with the circuitry within the integrated driving circuit.

[0017] Optionally, the first substrate further includes: an insulating layer located between the bottom structural layer and the MEMS structural material layer; the method of etching the MEMS structural material layer from the second side to form the MEMS structural layer further includes: etching the MEMS structural material layer from the second side until the insulating layer is exposed to form the MEMS structural layer; the method of removing the bottom structural layer includes: using the insulating layer as a stop layer, grinding the bottom structural layer from the first side until the bottom structural layer is removed.

[0018] Optionally, the first substrate is an SOI substrate, and the MEMS structural material layer is the top silicon layer of the SOI substrate.

[0019] Optionally, it further includes: forming a release opening patterned layer on the surface of the first oxide layer from the first side; using the release opening patterned layer as a mask, etching the first oxide layer from the first side until a first release opening is formed in the first oxide layer to release the MEMS structure layer.

[0020] Optionally, it further includes: filling the MEMS structure layer with sacrificial material before forming the silicon photonic structure layer; and after forming the first release opening, continuing to etch the sacrificial material from the first side until the sacrificial material is removed.

[0021] Optionally, the silicon photonic structure layer includes a second oxide layer, wherein the first waveguide layer is located within the second oxide layer; the method for forming the photonic integrated chip further includes: after etching the sacrificial material, continuing to etch the second oxide layer from the first side to form a cavity communicating with the first release opening within the second oxide layer, wherein the first waveguide layer is at least partially located within the cavity.

[0022] Optionally, the method for forming the silicon photonic structure layer further includes: forming a first protective film encapsulating the first waveguide layer before forming the second oxide layer; forming a release barrier layer on the second oxide layer from the second side; the method for forming the cavity further includes: etching the second oxide layer to the release barrier layer.

[0023] The present invention also provides a method for forming a photonic integrated chip, comprising: providing a first substrate having a first side and a second side opposite to each other; the first substrate including a bottom structural layer and a MEMS structural material layer located on the bottom structural layer, the second side exposing the MEMS structural material layer; forming a silicon photonic structure layer from the second side, the silicon photonic structure layer being stacked with the MEMS structural material layer, the silicon photonic structure layer including a first waveguide layer; after forming the silicon photonic structure layer, bonding the first substrate to a second substrate, the second side facing the second substrate; after bonding the first substrate to the second substrate, removing the bottom structural layer from the first side; after removing the bottom structural layer, etching the MEMS structural material layer from the first side to form a MEMS structural layer, the MEMS structural layer including a movable portion for driving the first waveguide layer; after forming the MEMS structural layer, forming a first oxide layer from the first side, the first oxide layer being stacked with the MEMS structural layer, the MEMS structural layer being located between the silicon photonic structure layer and the first oxide layer.

[0024] Optionally, the method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the first waveguide layer from the second side; and / or, the method for forming the photonic integrated chip further includes: forming a third waveguide layer from the first side after forming the MEMS structure layer, the third waveguide layer being located within the first oxide layer, and the movable part being used to selectively drive the first waveguide layer and the third waveguide layer.

[0025] Optionally, the method for forming the silicon photonic structure layer includes: forming a second oxide layer on the initial first substrate from the second side; and forming a first waveguide layer located within the second oxide layer from the second side before forming the second oxide layer or during forming the second oxide layer.

[0026] Optionally, the method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the second oxide layer from the second side; and forming a third oxide layer on the second oxide layer and on the surface of the second waveguide layer.

[0027] Optionally, the first substrate further includes an insulating layer located between the bottom structural layer and the MEMS structural material layer; the method for forming the photonic integrated chip further includes: after removing the bottom structural layer and before etching the MEMS structural material layer, removing the insulating layer to expose the MEMS structural material layer from the first side.

[0028] Optionally, it further includes: forming a release opening patterned layer on the surface of the first oxide layer from the first side; using the release opening patterned layer as a mask, etching the first oxide layer from the first side until a first release opening is formed in the first oxide layer to release the MEMS structure layer.

[0029] Accordingly, the technical solution of the present invention also provides a photonic integrated chip formed by the above method. The photonic integrated chip includes: a MEMS structure layer having a first side and a second side opposite to each other, the MEMS structure layer including a movable part; a silicon photonic structure layer including a first waveguide layer, the movable part being used to drive the first waveguide layer; a second substrate bonded to the silicon photonic structure layer; and a first oxide layer, which is arranged in sequence from the first side to the second side. The first oxide layer, the MEMS structure layer, the silicon photonic structure layer and the second substrate are stacked in sequence.

[0030] Optionally, the first waveguide layer is located on the surface of the MEMS structure layer.

[0031] Optionally, the silicon photonic structure layer further includes: a second waveguide layer located on the second side of the first waveguide layer; and / or, the photonic integrated chip further includes: a third waveguide layer located within the first oxide layer, wherein the movable part is used to selectively drive the first waveguide layer and the third waveguide layer.

[0032] Optionally, the third waveguide layer is also located on the surface of the MEMS structure layer on the first side.

[0033] Optionally, the first oxide layer has a first release opening from the first side, and the MEMS structure layer is exposed through the first release opening.

[0034] Optionally, the silicon photonic structure layer further includes: a second oxide layer, wherein the first waveguide layer is located within the second oxide layer, and the second oxide layer has a cavity communicating with the first release opening, wherein part or all of the first waveguide layer is located within the cavity.

[0035] Optionally, it further includes: an insulating layer located between the MEMS structure layer and the first oxide layer, the insulating layer having a second release opening communicating with the first release opening, the first release opening exposing the MEMS structure layer through the second release opening.

[0036] Optionally, the material of the first waveguide layer includes silicon nitride or aluminum nitride, and the material of the MEMS structure layer includes silicon.

[0037] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0038] In the photonic integrated chip formation method provided by the present invention, the material of the MEMS structure layer is provided before the formation of the silicon photonic structure layer. Therefore, the high-temperature silicon deposition process is completed before the formation of the silicon photonic structure layer, avoiding the performance impact of high temperature on the silicon photonic structure layer. Furthermore, by bonding the first substrate to the second substrate and using the second substrate as a carrier substrate, processing can be performed from the second side of the first substrate, and then the first substrate can be flipped to continue processing on the first side. Based on this, a first oxide layer is formed from the first side as a cladding. The distance between the first waveguide layer and the MEMS structure layer is less limited by the cladding thickness, and the first waveguide layer and the movable part can achieve a close or zero distance. Therefore, when the MEMS device drives the first waveguide layer to move, the accuracy of the movement range and distance is less limited by the distance between the two, resulting in good driving performance. In summary, the above formation method can form a photonic integrated chip with high performance and good driving performance.

[0039] The photonic integrated chip provided by the technical solution of the present invention has the effects described in the above method because it is formed by the above method, and will not be repeated here. Attached Figure Description

[0040] Figures 1 and 2 are schematic diagrams of a method for forming a silicon photonics MEMS chip;

[0041] Figures 3 to 15 are schematic diagrams of the structure of each step in the method for forming a photonic integrated chip according to the first embodiment of the present invention;

[0042] Figures 16 to 19 are schematic diagrams of the structure of each step in the method for forming a photonic integrated chip according to the second embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 10 - MEMS structure; 11 - Cavity; 12 - Functional via;

[0045] 20 - Sacrificial layer; 21 - Release opening;

[0046] 30 - Silicon photonics structure; 31 - Lower cladding; 32 - Upper cladding; 33 - Waveguide structure;

[0047] 1-First base; 101-First side; 102-Second side;

[0048] 110 - MEMS structural layer; 1101 - Movable part; 1102 - Fixed part; 111 - MEMS structural material layer; 120 - Insulating layer; 130 - Bottom structural layer; 140 - Second release opening; 150 - Sacrificial material;

[0049] 200 - Silicon photonic structure layer; 211 - First waveguide layer; 212 - First protective film; 220 - Second oxide layer; 221 - Cavity; 230 - Second waveguide layer; 240 - Third oxide layer; 251 - First conductive via; 252 - Second conductive via; 253 - Electrostatic driver electrode layer; 260 - Release barrier layer; 271 - Third waveguide layer; 272 - Second protective film; 300 - First oxide layer; 310 - First release opening;

[0050] 400 - Release the opening graphical layer;

[0051] 4-Second basement. Detailed Implementation

[0052] To make the objectives, features, and beneficial effects of this invention more apparent and understandable, specific embodiments of the invention are described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0053] It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment in the following embodiments have their own emphasis; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0054] [First Embodiment]

[0055] The first embodiment of the present invention provides a method for forming a photonic integrated chip. Figures 3 to 15 are schematic diagrams of the structure of each step in the method for forming a photonic integrated chip according to the first embodiment of the present invention.

[0056] Please refer to Figure 3 for the formation of the first substrate 1.

[0057] The first base 1 has a first side 101 and a second side 102 that are opposite each other.

[0058] The first substrate 1 includes a bottom structural layer 130 and a MEMS structural material layer 111.

[0059] The MEMS structural material layer 111 is located on the bottom structural layer 130, and the first side 101 exposes the bottom structural layer 130, while the second side 102 exposes the MEMS structural material layer 111.

[0060] MEMS structural material layer 111 provides materials for forming MEMS structural layer 110 (as shown in Figure 4).

[0061] The bottom structural layer 130 is made of silicon. The MEMS structural material layer 111 is also made of silicon.

[0062] In this embodiment, the first substrate 1 further includes an insulating layer 120.

[0063] The insulating layer 120 is located between the bottom structural layer 130 and the MEMS structural material layer 111.

[0064] By positioning the insulating layer 120 between the bottom structural layer 130 and the MEMS structural material layer 111, the etching process during the subsequent etching of the MEMS structural layer 110 allows for a greater selectivity between the MEMS structural material layer 111 and the insulating layer 120. Furthermore, during the subsequent removal of the bottom structural layer 130, the polishing process also allows for a greater selectivity between the bottom structural layer 130 and the insulating layer 120. Therefore, the insulating layer 120 not only acts as a stop layer in both of the aforementioned processes but also maintains good surface flatness, making its morphology and dimensions controllable. It can also be used together with the subsequently formed first oxide layer to form a cladding layer, thereby saving materials and time required for cladding layer formation, reducing the manufacturing cost of photonic integrated chips, and improving the manufacturing efficiency of photonic integrated chips.

[0065] The insulating layer 120 is made of silicon oxide.

[0066] Furthermore, the first substrate 1 is an SOI substrate.

[0067] Among them, the MEMS structure material layer 111 is the top silicon layer of the SOI substrate, and its material is single crystal silicon.

[0068] In some other embodiments, the MEMS structure material layer 111 is polycrystalline silicon.

[0069] In another embodiment, the first substrate does not include an insulating layer 120, but is divided into a bottom structural layer 130 and a MEMS structural material layer 111.

[0070] Please refer to Figure 4. Etch the MEMS structure material layer 111 from the second side 102 until the insulating layer 120 is exposed to form the MEMS structure layer 110.

[0071] The MEMS structure layer 110 includes a movable part 1101 and a fixed part 1102.

[0072] The method for etching the MEMS structure material layer 111 includes: forming a MEMS structure mask layer (not shown) on the surface of the MEMS structure material layer 111 from the second side 102, the MEMS structure mask layer exposing part of the MEMS structure material layer 111; using the MEMS structure mask layer as a mask, etching the MEMS structure material layer 111 until the insulating layer 120 is exposed.

[0073] Please refer to Figure 5. Starting from the second side 102, the MEMS structure layer 110 is filled with sacrificial material 150.

[0074] Specifically, the method for forming the sacrificial material 150 includes: depositing the sacrificial material in the MEMS structure layer 110 and on the surface of the MEMS structure layer 110 from the second side 102; and grinding the sacrificial material deposited on the surface of the MEMS structure layer 110 until the surface of the MEMS structure layer 110 is exposed.

[0075] The process for grinding the sacrificial material layer is CMP (Chemical Mechanical Polishing).

[0076] The sacrificial material is the same as the insulating layer 120 and the subsequently formed first oxide layer, which is silicon oxide. This simplifies the subsequent etching process for releasing the MEMS structure layer 110.

[0077] The purpose of filling the sacrificial material 150 is to prevent contaminants from entering the MEMS structure layer 110 in the future, and to strengthen the structural strength of the MEMS structure layer 110 before releasing it, so as to prevent other processes from damaging the MEMS structure layer 110.

[0078] Next, a silicon photonic structure layer 200 is formed from the second side 102.

[0079] The silicon photonics structure layer 200 is stacked with the MEMS structure layer 110.

[0080] The silicon photonics structure layer 200 includes a first waveguide layer 211. A movable part 1101 is used to drive the first waveguide layer 211.

[0081] It should be noted that the first waveguide layer 211 includes at least one waveguide device, and the waveguide device of the first waveguide layer 211 can be driven by the movable part 1101.

[0082] The specific steps for forming the silicon photonic structure layer 200 are described below with reference to Figures 6 to 11.

[0083] Please refer to Figures 6 and 7. Figure 7 is an enlarged schematic diagram of the first waveguide layer 211 in Figure 6. The first waveguide layer 211 is formed on the surface of the MEMS structure layer 110 from the second side 102.

[0084] Since a first waveguide layer 211 is formed on the surface of the MEMS structure layer 110, there is zero distance between the first waveguide layer 211 and the MEMS structure layer 110.

[0085] In this embodiment, the silicon photonics structure layer 200 further includes a first protective film 212.

[0086] The first protective film 212 wraps around the first waveguide layer 211.

[0087] Since the first waveguide layer 211 is wrapped by the first protective film 212, the first protective film 212 can act as a barrier layer to protect the first waveguide layer 211 during the subsequent etching process of releasing the MEMS structure layer 110 and forming the cavity 221, thus preventing the first waveguide layer 211 from being damaged during the etching process and affecting the device performance.

[0088] The material of the first waveguide layer 211 is silicon nitride or aluminum nitride.

[0089] The material of the first protective film 212 is aluminum oxide.

[0090] The method for forming the first protective film 212 and the first waveguide layer 211 includes: depositing a first protective film under-material layer (not shown) on the surface of the MEMS structure layer 110 and the surface of the sacrificial material 150; depositing a first waveguide material layer (not shown) on the surface of the first protective film under-material layer; patterning the first waveguide material layer and the first protective film under-material layer to form the first waveguide layer 211 and the first protective film under-material layer (not shown) located between the first waveguide layer 211 and the MEMS structure layer 110, and exposing the MEMS structure layer 110 and the sacrificial material 150; depositing a first protective film upper-material layer (not shown) on the exposed surfaces of the MEMS structure layer 110 and the sacrificial material 150 and on the surface of the first waveguide layer 211; patterning the first protective film upper-material layer to remove the first protective film upper-material layer on the exposed surfaces of the MEMS structure layer 110 and the sacrificial material 150, and forming a first protective film upper-material layer (not shown) on the surface of the first waveguide layer 211, wherein the first protective film under-material layer and the first protective film upper-material layer constitute the first protective film 212.

[0091] Please refer to Figure 8. A second oxide layer 220 is deposited on the surface of MEMS structure layer 110, the surface of sacrificial material 150 and the surface of first protective film 212. The first waveguide layer 211 is located within the second oxide layer 220.

[0092] Correspondingly, the silicon photonics structure layer 200 also includes a second oxide layer 220.

[0093] In some other embodiments, the first protective film 212 is not formed. Instead, a second oxide layer 220 is deposited on the surface of the first waveguide layer 211.

[0094] The material of the second oxide layer 220 is silicon oxide.

[0095] In some other embodiments, unlike the zero spacing in this embodiment, the spacing between the first waveguide layer 211 and the MEMS structure layer 110 is a preset spacing to meet other device requirements.

[0096] Furthermore, the method for forming the second oxide layer 220, the first waveguide layer 211, and the first protective film 212 includes: depositing a second lower oxide layer (not shown) on the surface of the MEMS structure layer 110 and the surface of the sacrificial material 150; forming the first waveguide layer 211 and the first protective film 212 on the surface of the second lower oxide layer; and depositing a second upper oxide layer (not shown) on the surface of the first protective film 212 and the surface of the second lower oxide layer. The second lower oxide layer and the second upper oxide layer constitute the second oxide layer, and the first waveguide layer 211 and the first protective film 212 are located between the second lower oxide layer and the second upper oxide layer. By controlling the thickness of the second lower oxide layer, a preset spacing can be achieved between the first waveguide layer 211 and the MEMS structure layer 110.

[0097] Please continue to refer to Figure 8. From the second side 102, a plurality of first conductive vias 251 are formed in the second oxide layer 220.

[0098] In a plurality of first conductive vias 251, one end of any first conductive via 251 contacts the MEMS structure layer 110 or the first waveguide layer 211, and the other end is exposed by the surface of the second oxide layer 220.

[0099] The reason for exposing the other end of any first conductive via 251 to the surface of the second oxide layer 220 is that an electrostatic driver electrode layer 253 can be formed on the exposed end face to achieve electrical connection between the first conductive via 251 and the electrostatic driver electrode layer 253. This allows the MEMS structure layer 110 or the first waveguide layer 211 that is contacted by one end of the first conductive via 251 to be led out and coupled to other devices or circuits.

[0100] The first conductive via 251 is made of metal.

[0101] Furthermore, the material of the first conductive via 251 is copper.

[0102] The method for forming the first conductive via 251 includes: etching the second oxide layer 220 from the second side 102, forming a first via (not shown) in the second oxide layer 220, exposing the bottom of the first via to the MEMS structure layer 110 or the first waveguide layer 211; and filling the first via with conductive material to form the first conductive via 251.

[0103] The process of filling the first through-hole with conductive material includes deposition or electroplating.

[0104] Please continue to refer to Figure 8, where an electrostatic driver electrode layer 253 is formed on the end face of the other end of the first conductive via 251 and the surface of the second oxide layer 220 from the second side 102.

[0105] The material of the electrostatic driver electrode layer 253 is metal.

[0106] Furthermore, the material of the electrostatic driver electrode layer 253 is aluminum.

[0107] The method for forming the electrostatic driver electrode layer 253 includes: depositing an electrostatic driver electrode material layer (not shown) on the end face of the other end of the first conductive via 251 and on the surface of the second oxide layer 220; patterning the electrostatic driver electrode material layer to form the electrostatic driver electrode layer 253.

[0108] Please refer to Figure 9, where a release barrier layer 260 is formed on the second oxide layer 220 from the second side 102.

[0109] Since a release barrier layer 260 is formed on the second oxide layer 220 from the second side 102, the release barrier layer 260 can serve as a stop layer in the etching process when the second oxide layer 220 is subsequently etched from the first side to form the cavity 221. At the same time, the release barrier layer 260 also protects other devices facing the second side 102 from the release barrier layer 260, especially protecting the subsequently formed second waveguide layer 230 and third oxide layer 240 to prevent them from being damaged and affecting device performance.

[0110] In this embodiment, the release barrier layer 260 is located on the surface of the electrostatic driver electrode layer 253 facing the second side 102. Furthermore, the release barrier layer 260 exposes a portion of the surface of the electrostatic driver electrode layer 253 facing the second side 102, allowing the subsequently formed second conductive via 252 to contact it.

[0111] The material of the release barrier layer 260 is the same as the material of the first protective film 212.

[0112] The material of the release barrier layer 260 is aluminum oxide.

[0113] In some other embodiments, no release barrier layer is formed, that is, the silicon photonics structure layer does not have a release barrier layer.

[0114] Please refer to Figure 10. A second waveguide layer 230 is formed on the second oxide layer 220 from the second side 102.

[0115] It should be noted that the second waveguide layer 230 includes at least one waveguide device.

[0116] Thus, a second waveguide layer 230 is formed on the first waveguide layer 211 from the second side 102.

[0117] Specifically, a second waveguide layer 230 is formed on the surface of the release blocking layer 260 from the second side 102.

[0118] The method for forming the second waveguide layer 230 includes: depositing a second waveguide material layer (not shown) on the surface of the release barrier layer 260; and patterning the second waveguide material layer to form the second waveguide layer 230. Thus, the release barrier layer 260 also serves as a stop layer in the etching process of the patterned second waveguide material layer.

[0119] Please refer to Figure 11. A third oxide layer 240 is deposited on the second oxide layer 220 and on the surface of the second waveguide layer 230.

[0120] Accordingly, the silicon photonics structure layer 200 also includes a third oxide layer 240 and a second waveguide layer 230 located within the third oxide layer 240. The third oxide layer 240 is a cladding layer.

[0121] By controlling the thickness of the third oxide layer 240, the cladding on one side (on the second side 102) of the waveguide device can achieve the target thickness.

[0122] The material of the third oxide layer 240 is silicon oxide.

[0123] Please continue to refer to Figure 11, where several second conductive vias 252 are formed in the third oxide layer 240 from the second side 102.

[0124] One end of the second conductive via 252 contacts the electrostatic driver electrode layer 253, and the other end of the second conductive via 252 is exposed by the surface of the third oxide layer 240.

[0125] One end of the second conductive via 252 contacts the electrostatic driver electrode layer 253, thus the second conductive via 252 and the electrostatic driver electrode layer 253 are electrically connected. The purpose of exposing the other end of the second conductive via 252 to the surface of the third oxide layer 240 is to allow it to contact the subsequently bonded second substrate 4 and be electrically connected to its internal circuitry, or to be led out and electrically connected to other circuitry, so that the MEMS structure layer 110 or the first waveguide layer 211 can be coupled to the circuitry or other device circuitry within the second substrate 4.

[0126] In this embodiment, referring to the steps shown in Figures 8 and 11, the electrical interconnect structure, including the first conductive via 251, the electrostatic driver electrode layer 253, and the second conductive via 252, is formed within the silicon photonic structure layer 200 during the formation of the silicon photonic structure layer 200. This simplifies the structure and reduces process complexity, resulting in a more compact structure and improved integration. Furthermore, since the first conductive via 251, the electrostatic driver electrode layer 253, and the second conductive via 252 are encapsulated by the second oxide layer 220 and the third oxide layer 240, the device exhibits high reliability.

[0127] The material of the second conductive via 252 is metal.

[0128] Furthermore, the material of the second conductive via 252 is copper.

[0129] The method for forming the second conductive via 252 includes: etching the third oxide layer 240 from the second side 102, forming a second via (not shown) in the third oxide layer 240, the bottom of the second via exposing the surface of the electrostatic driver electrode layer 253; and filling the second via with conductive material to form the second conductive via 252.

[0130] The process of filling the second through hole with conductive material includes deposition or electroplating.

[0131] Please refer to Figure 12. After forming the silicon photonics structure layer 200, the first substrate 1 and the second substrate 4 are bonded together, with the second side 102 facing the second substrate 4.

[0132] In this embodiment, the second substrate 4 has an integrated driving circuit. After the first substrate 1 and the second substrate 4 are bonded, the second conductive via 252 is electrically interconnected with the circuit in the integrated driving circuit.

[0133] Specifically, the bonding between the first substrate 1 and the second substrate 4 includes at least one of the following: mixed bonding of silicon oxide and copper, silicon oxide to silicon oxide, and direct bonding of copper to copper.

[0134] In some other embodiments, the second substrate 4 may also be a carrier substrate or a transfer substrate with an internal electrical interconnection structure.

[0135] After bonding the first substrate 1 to the second substrate 4, the first substrate 1 is flipped so that subsequent processing can continue from the first side 101.

[0136] Next, please refer to Figure 13 and remove the bottom structural layer 130 from the first side 101.

[0137] The process for removing the bottom structural layer 130 is a grinding process.

[0138] Specifically, the process for removing the bottom structural layer 130 is the CMP process.

[0139] In this embodiment, the method for removing the bottom structural layer 130 includes: using the insulating layer 120 as a stop layer, grinding the bottom structural layer 130 from the first side 101 until the bottom structural layer 130 is removed.

[0140] During the removal of the bottom structural layer 130, the grinding process has a large selectivity between the bottom structural layer 130 and the insulating layer 120. Therefore, the requirements for process control precision can be reduced, the process difficulty is low, and the bottom structural layer 130 can be removed more thoroughly without damaging the insulating layer 120. In addition, the residual contaminants are reduced, so the insulating layer 120 maintains a good surface flatness, has fewer surface contaminants, and its morphology and size are controllable.

[0141] In another embodiment, the initial first substrate does not contain an insulating layer 120, but is divided into a bottom structural layer 130 and a MEMS structural material layer 111. Therefore, the bottom structural layer 130 is removed by controlling the grinding process.

[0142] Please refer to Figure 14. After removing the bottom structural layer 130, the material of the first oxide layer is deposited from the first side 101 to form the first oxide layer 300.

[0143] Specifically, the silicon photonics structure layer 200 and the second substrate 4 are both located on the second side 102 of the MEMS structure layer 110, while the first oxide layer 300 is located on the first side 101 of the MEMS structure layer 110.

[0144] The first oxide layer 300 is stacked with the MEMS structure layer 110, and the MEMS structure layer 110 is located between the silicon photonic structure layer 200 and the first oxide layer 300, while the silicon photonic structure layer 200 is located between the second substrate 4 and the MEMS structure layer 110.

[0145] In this embodiment, the first oxide layer 300 and the insulating layer 120 constitute a cladding layer.

[0146] In another embodiment, since the initial first substrate does not contain an insulating layer 120, the first oxide layer is a cladding layer.

[0147] In this embodiment, the third oxide layer 240 forms the cladding on the second side 102, and the insulating layer 120 and the first oxide layer 300 form the cladding on the first side 101, so that the waveguide device has cladding on both sides.

[0148] Since a silicon photonic structure layer 200 is formed on the second side 102 after the formation of the first substrate 1 including the MEMS structure layer 110, the material of the MEMS structure layer 110 is provided before the formation of the silicon photonic structure layer. That is, the high-temperature process of silicon deposition is completed before the formation of the silicon photonic structure layer 200. Thus, the performance impact of high temperature on the silicon photonic structure layer 200 is avoided, enabling the photonic integrated chip to have higher performance.

[0149] Furthermore, by bonding the first substrate 1 to the second substrate 4 via the third oxide layer 240, and using the second substrate 4 as a support substrate, the first substrate 1 can be flipped after processing from its second side 102 to continue processing on its first side 101. Based on this, a first oxide layer 300 is formed from the first side 101 as a cladding. The distance between the first waveguide layer 211 and the MEMS structure layer 110 is less limited by the cladding thickness. The first waveguide layer 211 and the movable part 1101 can achieve close or zero distance, thus, when the MEMS device drives the first waveguide layer 211 to move, the accuracy of the movement range and distance is less limited by the distance between them, resulting in good driving performance.

[0150] As a result, the resulting photonic integrated chip combines high performance and good driving ability.

[0151] Furthermore, since the MEMS device has good driving performance when driving the first waveguide layer 211, the spacing between the second waveguide layer 230 and the first waveguide layer 211 is less restricted when driving the second waveguide layer 230 via the first waveguide layer 211. In other words, the first waveguide layer 211 can drive the second waveguide layer 230 which is further away, thereby improving the driving performance in the case of multiple waveguides.

[0152] The material of the first oxide layer 300 is silicon oxide.

[0153] Please continue to refer to Figure 14, where a release opening patterned layer 400 is formed on the surface of the first oxide layer 300 from the first side 101.

[0154] The method for forming the release opening patterned layer 400 includes: depositing a release opening material layer (not shown) on the surface of the first oxide layer 300 from the first side 101; forming a patterned illumination layer on the surface of the release opening material layer based on a photolithography process; etching the release opening material layer with the illumination layer as a mask until the surface of the first oxide layer 300 is exposed, so as to transfer the pattern of the illumination layer to the release opening material layer and form the patterned release opening patterned layer 400.

[0155] The material of the release opening patterned layer 400 is aluminum oxide.

[0156] Please refer to Figure 15. Using the release opening patterned layer 400 as a mask, the first oxide layer 300 is etched from the first side 101 to expose the insulating layer 120 on the surface of the first side 101, forming the first release opening 310.

[0157] The first release opening 310 is used to release the MEMS structure layer 110.

[0158] The silicon photonic structure layer 200 and the second substrate 4 are both located on the second side 102 of the MEMS structure layer 110. The first oxide layer 300 is located on the first side 101 of the MEMS structure layer 110. Since the first oxide layer 300 is etched from the first side 101 to form a first release opening 310 for releasing the MEMS structure layer 110, there is less device obstruction and fewer devices to avoid when releasing the MEMS structure, making the release of the MEMS structure easier.

[0159] Please continue referring to Figure 15. After forming the first release opening 310, continue etching the insulating layer 120 until the MEMS structure layer 110 and the sacrificial material 150 are exposed. A second release opening 140 is then formed within the insulating layer 120.

[0160] The second release opening 140 is also used to release the MEMS structure layer 110.

[0161] Specifically, the second release opening 140 connects to the first release opening 310 and exposes the MEMS structure layer 110 and the sacrificial material 150.

[0162] Please continue to refer to Figure 15. After forming the second release opening 140, continue to etch the sacrificial material 150 until the sacrificial material 150 is removed to release the MEMS structure layer 110.

[0163] Please continue to refer to Figure 15. After etching the sacrificial material 150, continue to etch the second oxide layer 220 to form a cavity 221 that connects to the first release opening 310 in the second oxide layer 220.

[0164] At least a portion of the cavity 221 is projected onto the surface of the MEMS structure layer 110 within the MEMS device region Q to realize the function of the MEMS device. Furthermore, the first waveguide layer 211 is at least partially located within the cavity 221.

[0165] Since the cavity 221 is directly formed by etching the second oxide layer 220 after removing the sacrificial material 150, the removal of the sacrificial material 150 and related steps (such as forming the first release opening 310, the second release opening 140, etc.) and the formation of the cavity 221 share the same mask. This reduces one photolithography step, simplifying the manufacturing process and reducing its complexity.

[0166] After forming cavity 221, the first substrate 1 and the second substrate 4 are cut to form several photonic integrated chips. These photonic integrated chips are used in optical switches, optical modulators, or photodetectors, etc.

[0167] Accordingly, embodiments of the present invention also provide a photonic integrated chip formed using the formation method of the first embodiment described above.

[0168] Photonic integrated chips can be used in optical switches, optical modulators, or photodetectors, etc.

[0169] Please continue to refer to Figure 15. The photonic integrated chip includes: MEMS structure layer 110, silicon photonic structure layer 200, second substrate 4 and first oxide layer 300.

[0170] The MEMS structural layer 110 has a first side 101 and a second side 102 opposite to each other. The MEMS structural layer 110 includes a movable part 1101 and a fixed part 1102.

[0171] In the direction from the first side 101 to the second side 102, the first oxide layer 300, the MEMS structure layer 110, the silicon photonic structure layer 200, and the second substrate 4 are stacked sequentially, wherein the silicon photonic structure layer 200 is bonded to the second substrate 4.

[0172] The silicon photonics structure layer 200 includes a first waveguide layer 211. A movable part 1101 is used to drive the first waveguide layer 211.

[0173] The silicon photonic structure layer 200 also includes a second oxide layer 220.

[0174] The first waveguide layer 211 is located within the second oxide layer 220.

[0175] In this embodiment, the first waveguide layer 211 is located on the surface of the MEMS structure layer 110.

[0176] In some other embodiments, unlike the zero-pitch spacing in this embodiment, the spacing between the first waveguide layer 211 and the MEMS structure layer 110 is a preset spacing to meet other device requirements. Specifically, a partial second oxide layer is formed between the first waveguide layer 211 and the MEMS structure layer 110.

[0177] The second oxide layer 220 has a cavity 221, at least a portion of which is projected onto the surface of the MEMS structure layer 110 within the movable portion 1101, and part or all of the first waveguide layer 211 is located within the cavity 221.

[0178] The silicon photonics structure layer 200 also includes a second waveguide layer 230.

[0179] Specifically, the silicon photonics structure layer 200 also includes a third oxide layer 240.

[0180] The third oxide layer 240 is located on the second side 102 of the second oxide layer 220, and the second waveguide layer 230 is located on the surface of the second side 102.

[0181] The first oxide layer 300 has a first release opening 310 on the first side 101, and the MEMS structure layer 110 is exposed through the first release opening 310. In addition, the first release opening 310 is also connected to the cavity 221.

[0182] The photonic integrated chip also includes: insulating layer 120.

[0183] The insulating layer 120 is located between the MEMS structure layer 110 and the first oxide layer 300.

[0184] In this embodiment, the third oxide layer 240 forms the cladding on the second side 102, and the insulating layer 120 and the first oxide layer 300 form the cladding on the first side 101, so that the waveguide device has cladding on both sides.

[0185] The insulating layer 120 has a second release opening 140 that connects to the first release opening 310, and the first release opening 310 exposes the MEMS structure layer 110 through the second release opening 140.

[0186] Specifically, since the photonic integrated chip in this embodiment is formed using the first embodiment described above, the detailed descriptions of each structure and related effects are the same as those in the method embodiment. Please refer to the relevant descriptions and explanations in the first embodiment for details, which will not be repeated here.

[0187] [Second Embodiment]

[0188] Figures 17 to 19 are schematic diagrams of the steps in the method for forming a photonic integrated chip according to the second embodiment of the present invention. The second embodiment of the present invention is a modified embodiment of the first embodiment. The main difference between the second embodiment and the first embodiment is that a third waveguide layer 271 is also formed within the first oxide layer 300 in the second embodiment.

[0189] A multilayer waveguide is formed by forming a third waveguide layer 271 within the first oxide layer 300. The waveguide located in the middle (i.e., the first waveguide layer 211 located between the second waveguide layer 230 and the third waveguide layer 271) is connected to the MEMS structure layer 110. The first waveguide layer 211 in the middle position serves as the driving waveguide driven by the MEMS structure layer 110. In this way, in the case of a multilayer waveguide, the driving waveguide can have a smaller spacing with the waveguides above and below it, thereby further improving the driving performance.

[0190] The second embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0191] Please refer to Figures 16 and 17 based on Figure 13. Figure 17 is an enlarged schematic diagram of the third waveguide layer in Figure 16. After removing the bottom structural layer 130, the third waveguide layer 271 is formed on the surface of the insulating layer 120 from the first side 101.

[0192] In this embodiment, the movable part 1101 is used to selectively drive the first waveguide layer 211 and the third waveguide layer 271.

[0193] The surface of the third waveguide layer 271 is covered with a second protective film 272.

[0194] Since the third waveguide layer 271 is wrapped by the second protective film 272, the second protective film 272 can act as a barrier layer to protect the third waveguide layer 271 during the subsequent etching process of releasing the MEMS structure layer 110 and forming the cavity 221, thus preventing the third waveguide layer 271 from being damaged during the etching process and affecting the device performance.

[0195] The material of the third waveguide layer 271 is silicon nitride or aluminum nitride.

[0196] The material of the second protective film 272 is aluminum oxide.

[0197] In this embodiment, an insulating layer 120 is spaced between the third waveguide layer 271 and the MEMS structure layer 110.

[0198] It should be understood that, in order to achieve a preset spacing between the third waveguide layer 271 and the MEMS structure layer 110, in some other embodiments, after removing the bottom structure layer 130 and before forming the third waveguide layer 271, the insulating layer 120 may be thinned or removed to bring the spacing between the third waveguide layer 271 and the MEMS structure layer 110 closer, or to keep the third waveguide layer 271 on the surface of the MEMS structure layer 110 on the first side 101 (i.e., zero spacing between the third waveguide layer 271 and the MEMS structure layer 110). Of course, in other embodiments, a similar method of controlling the preset spacing between the first waveguide layer 211 and the MEMS structure layer 110 may be used (i.e., the aforementioned method of forming a second oxide layer consisting of a second oxide lower layer and a second oxide upper layer), followed by the formation of a first oxide layer consisting of a first oxide lower layer and a first oxide upper layer, to increase the spacing between the third waveguide layer 271 and the MEMS structure layer 110.

[0199] Please refer to Figure 18. Material for the first oxide layer is deposited from the first side 101 on the surface of the insulating layer 120 and the surface of the third waveguide layer 271 to form the first oxide layer 300.

[0200] The third waveguide layer 271 is located within the first oxide layer 300.

[0201] In this embodiment, the first oxide layer 300 is a cladding layer.

[0202] In some other embodiments, when the third waveguide layer 271 is still located on the surface of the MEMS structure layer 110 on the first side 101, material for the first oxide layer is deposited from the first side 101 onto the surface of the third waveguide layer 271 and the surface of the MEMS structure layer 110 to form the first oxide layer. It should be understood that, similar to the positional relationship between the first waveguide layer 211 and the second oxide layer 220, since at least a portion of the material for the first oxide layer 300 is deposited from the first side 101 onto the surface of the third waveguide layer 271 to form the first oxide layer 300, the third waveguide layer 271 is located within the first oxide layer 300 regardless of whether it is located on the surface of the MEMS structure layer 110 (i.e., regardless of whether there is zero spacing between the third waveguide layer 271 and the MEMS structure layer 110).

[0203] Referring to Figure 19, a release opening patterned layer 400 is formed on the surface of the first oxide layer 300 from the first side 101. Using the release opening patterned layer 400 as a mask, the first oxide layer 300, the insulating layer 120, the sacrificial material 150, and the second oxide layer 220 are etched to form the cavity 221 and the release MEMS structure layer 110. The steps described here are as explained in the first embodiment and will not be repeated here.

[0204] Accordingly, the embodiments of the present invention also provide a photonic integrated chip formed by the formation method of the second embodiment described above. Please continue to refer to FIG18. The difference between the photonic integrated chip formed by the formation method of the first embodiment and the photonic integrated chip formed by the second embodiment is that the second embodiment further includes a third waveguide layer 271.

[0205] The third waveguide layer 271 is located within the first oxide layer 300.

[0206] The surface of the third waveguide layer 271 is covered with a second protective film 272. Specifically, since the photonic integrated chip in this embodiment is formed using the method described in the second embodiment, the detailed descriptions of each structure and related effects are the same as those in the method embodiment. Please refer to the relevant descriptions and explanations in the second embodiment for details, which will not be repeated here.

[0207] [Third Embodiment]

[0208] The third embodiment of the present invention is a modified embodiment based on the second embodiment. The main difference between the third embodiment and the second embodiment is that the third oxide layer 240, the second waveguide layer 230, and the second conductive via 252 are not formed in the third embodiment.

[0209] Therefore, in the technical solution of this invention, when the number of waveguides is two or more, any waveguide can be driven adjacent to the MEMS structure layer 110. Thus, the selection freedom for the waveguide driven by the MEMS structure layer 110 is extremely high, thereby adapting to and meeting a wider range of device requirements.

[0210] Specifically, in this embodiment, after depositing the second oxide layer 220, the third oxide layer 240, the second waveguide layer 230, and the second conductive via 252 are not formed, but are bonded to the second substrate 4, and then the corresponding subsequent steps in the second embodiment are performed.

[0211] In this embodiment, the second oxide layer 220 is a cladding layer.

[0212] Accordingly, embodiments of the present invention also provide a photonic integrated chip formed using the formation method of the third embodiment described above. Since it is formed using the third embodiment described above, the detailed description of each structure and related effects are the same as those described in the method embodiment. For details, please refer to the relevant descriptions and explanations in the third embodiment, which will not be repeated here.

[0213] [Fourth Embodiment]

[0214] The fourth embodiment of the present invention is a modified embodiment of the first embodiment, and the fourth embodiment provides a different method of forming the MEMS structure layer 110 than that in the first embodiment.

[0215] It should be understood that, apart from the differences described above, the other steps in the method for forming the photonic integrated chip in this embodiment are described in the relevant description in the first embodiment, and will not be repeated here.

[0216] Specifically, in this embodiment, after providing the initial first substrate as in the first embodiment, a silicon photonic structure layer 200 is formed from the second side 102, and the silicon photonic structure layer 200 is stacked with the MEMS structure material layer 111.

[0217] Next, the initial first substrate is bonded to the second substrate 4, and the bottom structural layer 130 and insulating layer 120 are removed to expose the MEMS structural material layer 111 on the first side 101.

[0218] Next, the exposed MEMS structure material layer 111 is etched from the first side 101 to form the MEMS structure layer 110.

[0219] Similar to the first embodiment, since the silicon photonic structure layer 200 is formed from the second side 102 after the initial first substrate as in the first embodiment is provided, the material of the MEMS structure layer 110 is provided before the silicon photonic structure layer 200 is formed. That is, the high-temperature process of silicon deposition is completed before the silicon photonic structure layer 200 is formed, thereby avoiding the performance impact of high temperature on the silicon photonic structure layer 200 and enabling the photonic integrated chip to have high performance.

[0220] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for forming a photonic integrated chip, characterized in that, include: A first substrate is provided, the first substrate having opposing first and second sides, the first substrate including a bottom structural layer and a MEMS structural material layer located on the bottom structural layer, the second side exposing the MEMS structural material layer; The MEMS structure material layer is etched from the second side to form a MEMS structure layer, the MEMS structure layer including a movable part; After the MEMS structure layer is formed, a silicon photonics structure layer is formed from the second side. The silicon photonics structure layer is stacked with the MEMS structure layer. The silicon photonics structure layer includes a first waveguide layer. The movable part is used to drive the first waveguide layer. After forming the silicon photonic structure layer, the first substrate and the second substrate are bonded together, with the second side facing the second substrate; After bonding the first substrate to the second substrate, the bottom structural layer is removed from the first side; After removing the bottom structural layer, a first oxide layer is formed from the first side. The first oxide layer is stacked with the MEMS structural layer, and the MEMS structural layer is located between the silicon photonics structural layer and the first oxide layer.

2. The method for forming a photonic integrated chip as described in claim 1, characterized in that: The method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the first waveguide layer from the second side; And / or, the method for forming the photonic integrated chip further includes: after removing the bottom structural layer, forming a third waveguide layer from the first side, the third waveguide layer being located within the first oxide layer, and the movable part being used to selectively drive the first waveguide layer and the third waveguide layer.

3. The method for forming a photonic integrated chip as described in claim 2, characterized in that, The method for forming the silicon photonic structure layer further includes: A second oxide layer is formed on the first substrate from the second side; Before or during the formation of the second oxide layer, a first waveguide layer is formed from the second side within the second oxide layer.

4. The method for forming a photonic integrated chip as described in claim 3, characterized in that, The method for forming the silicon photonic structure layer further includes: A second waveguide layer is formed on the second oxide layer from the second side; A third oxide layer is formed on the second oxide layer and on the surface of the second waveguide layer.

5. The method for forming a photonic integrated chip as described in claim 4, characterized in that: Before forming the second waveguide layer and the third oxide layer, the method for forming the silicon photonic structure layer further includes: forming a plurality of first conductive vias in the second oxide layer from the second side, wherein one end of any first conductive via contacts the MEMS structure layer or the first waveguide layer, and the other end of the first conductive via is exposed by the surface of the second oxide layer; and forming an electrostatic driver electrode layer on the end face of the other end of the first conductive via and the surface of the second oxide layer from the second side. After forming the second waveguide layer and the third oxide layer, the method for forming the silicon photonic structure layer further includes: forming a plurality of second conductive vias in the third oxide layer from the second side, one end of the second conductive vias contacting the electrostatic driver electrode layer, and the other end of the second conductive vias being exposed by the surface of the third oxide layer.

6. The method for forming a photonic integrated chip as described in claim 5, characterized in that, The second substrate has an integrated driving circuit, and after the first substrate and the second substrate are bonded, the second conductive via is electrically interconnected with the circuit in the integrated driving circuit.

7. The method for forming a photonic integrated chip as described in claim 1, characterized in that, The first substrate further includes: an insulating layer located between the bottom structural layer and the MEMS structural material layer; The method of etching the MEMS structural material layer from the second side to form the MEMS structural layer further includes: etching the MEMS structural material layer from the second side until the insulating layer is exposed to form the MEMS structural layer; The method for removing the bottom structural layer includes: using the insulating layer as a stop layer, grinding the bottom structural layer from the first side until the bottom structural layer is removed.

8. The method for forming a photonic integrated chip as described in claim 1, characterized in that, The first substrate is an SOI substrate, and the MEMS structural material layer is the top silicon layer of the SOI substrate.

9. The method for forming a photonic integrated chip as described in claim 1, characterized in that, Also includes: From the first side, a release opening patterned layer is formed on the surface of the first oxide layer; Using the patterned release opening layer as a mask, the first oxide layer is etched from the first side until a first release opening is formed in the first oxide layer to release the MEMS structure layer.

10. The method for forming a photonic integrated chip as described in claim 9, characterized in that, Also includes: Before forming the silicon photonics structure layer, the MEMS structure layer is filled with sacrificial material. After the first release opening is formed, the sacrificial material is etched from the first side until the sacrificial material is removed.

11. The method for forming a photonic integrated chip as described in claim 10, characterized in that, The silicon photonic structure layer includes: a second oxide layer, wherein the first waveguide layer is located within the second oxide layer; The method for forming the photonic integrated chip further includes: after etching the sacrificial material, continuing to etch the second oxide layer from the first side to form a cavity communicating with the first release opening in the second oxide layer, wherein the first waveguide layer is at least partially located in the cavity.

12. The method for forming a photonic integrated chip as described in claim 11, characterized in that, The method for forming the silicon photonic structure layer further includes: forming a first protective film encapsulating the first waveguide layer before forming the second oxide layer; and forming a release barrier layer on the second oxide layer from the second side. The method of forming the cavity further includes: etching the second oxide layer to the release barrier layer.

13. A method for forming a photonic integrated chip, characterized in that, include: A first substrate is provided, the first substrate having opposing first and second sides, the first substrate including a bottom structural layer and a MEMS structural material layer located on the bottom structural layer, the second side exposing the MEMS structural material layer; A silicon photonic structure layer is formed from the second side, the silicon photonic structure layer is stacked with the MEMS structure material layer, and the silicon photonic structure layer includes a first waveguide layer; After forming the silicon photonic structure layer, the first substrate and the second substrate are bonded together, with the second side facing the second substrate; After bonding the first substrate to the second substrate, the bottom structural layer is removed from the first side; After removing the bottom structural layer, the MEMS structural material layer is etched from the first side to form a MEMS structural layer. The MEMS structural layer includes a movable part, which is used to drive the first waveguide layer. After the MEMS structure layer is formed, a first oxide layer is formed from the first side. The first oxide layer is stacked with the MEMS structure layer, and the MEMS structure layer is located between the silicon photonic structure layer and the first oxide layer.

14. The method for forming a photonic integrated chip as described in claim 13, characterized in that: The method for forming the silicon photonic structure layer further includes: forming a second waveguide layer on the first waveguide layer from the second side; And / or, the method for forming the photonic integrated chip further includes: after forming the MEMS structure layer, forming a third waveguide layer from the first side, the third waveguide layer being located within the first oxide layer, and the movable part being used to selectively drive the first waveguide layer and the third waveguide layer.

15. The method for forming a photonic integrated chip as described in claim 14, characterized in that, The method for forming the silicon photonic structure layer includes: A second oxide layer is formed on the initial first substrate from the second side; From the second side, a first waveguide layer is formed within the second oxide layer before or during the formation of the second oxide layer.

16. The method for forming a photonic integrated chip as described in claim 15, characterized in that, The method for forming the silicon photonic structure layer further includes: A second waveguide layer is formed on the second oxide layer from the second side; A third oxide layer is formed on the second oxide layer and on the surface of the second waveguide layer.

17. The method for forming a photonic integrated chip as described in claim 13, characterized in that, The first substrate further includes an insulating layer located between the bottom structural layer and the MEMS structural material layer; The method for forming the photonic integrated chip further includes: after removing the bottom structural layer and before etching the MEMS structural material layer, removing the insulating layer to expose the MEMS structural material layer from the first side.

18. The method for forming a photonic integrated chip as described in claim 13, characterized in that, Also includes: From the first side, a release opening patterned layer is formed on the surface of the first oxide layer; Using the patterned release opening layer as a mask, the first oxide layer is etched from the first side until a first release opening is formed in the first oxide layer to release the MEMS structure layer.

19. A photonic integrated chip, characterized in that, The photonic integrated chip, formed using any one of claims 1 to 18, comprises: A MEMS structure layer having a first side and a second side opposite to each other, the MEMS structure layer including a movable part; A silicon photonics structure layer, including a first waveguide layer, wherein the movable part is used to drive the first waveguide layer; A second substrate bonded to the silicon photonic structure layer; The first oxide layer, the MEMS structure layer, the silicon photonic structure layer and the second substrate are stacked sequentially in the direction from the first side to the second side.

20. The photonic integrated chip as described in claim 19, characterized in that, The first waveguide layer is located on the surface of the MEMS structure layer.

21. The photonic integrated chip as described in claim 19, characterized in that: The silicon photonic structure layer further includes: a second waveguide layer located on the second side of the first waveguide layer; And / or, the photonic integrated chip further includes: a third waveguide layer located within the first oxide layer, the movable part being used to selectively drive the first waveguide layer and the third waveguide layer.

22. The photonic integrated chip as described in claim 21, characterized in that, The third waveguide layer is also located on the surface of the MEMS structure layer on the first side.

23. The photonic integrated chip as described in claim 19, characterized in that, The first oxide layer has a first release opening from the first side, and the MEMS structure layer is exposed through the first release opening.

24. The photonic integrated chip as described in claim 23, characterized in that, The silicon photonic structure layer further includes: a second oxide layer, wherein the first waveguide layer is located within the second oxide layer, and the second oxide layer has a cavity communicating with the first release opening, wherein part or all of the first waveguide layer is located within the cavity.

25. The photonic integrated chip as described in claim 23, characterized in that, Also includes: An insulating layer is located between the MEMS structure layer and the first oxide layer, and the insulating layer has a second release opening that communicates with the first release opening, through which the first release opening exposes the MEMS structure layer.

26. The photonic integrated chip as described in claim 19, characterized in that, The material of the first waveguide layer includes silicon nitride or aluminum nitride, and the material of the MEMS structure layer includes silicon.

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