Shift register unit and driving method therefor, gate driving circuit, and display device

Abstract

A shift register unit and a driving method therefor, a gate driving circuit (000), and a display device, which relate to the technical field of display. The shift register unit comprises two input circuits (01, 02) and one output circuit (03). Since the input circuits (01, 02) can reliably and flexibly control potentials of two nodes under the control of a plurality of clock signals, the output circuit (03) is enabled to reliably output a clock signal or a power supply signal to an output terminal (GOUT) under the control of the potentials of the two nodes; furthermore, in a holding state, transistors in the output circuit (03) are prevented from being in a normally-on or normally-off state. Accordingly, transistors in the input circuits (01, 02) are prevented from being in a strong bias state, thereby ensuring that the input circuits (01, 02) can reliably control the potentials of the nodes and avoiding abnormal output of the shift register unit.

Description

Shift register unit and its driving method, gate driving circuit, display device

[0001] This application claims priority to Chinese Patent Application No. 202411718570.4, filed on November 27, 2024, entitled "Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0003] A gate driver circuit is a circuit used to drive pixels in a display device to emit light. Furthermore, to facilitate narrow bezel designs, gate driver circuits are often integrated onto the display panel using gate drive on array (GOA) technology. Accordingly, the gate driver circuit can also be called a GOA circuit.

[0004] In related technologies, GOA circuits typically include multiple cascaded shift register units (also called GOA units). These multiple GOA units are connected to multiple rows of pixels in the display panel and are used to output gate drive signals to the multiple rows of pixels row by row to drive the pixels to emit light. Accordingly, for each row of pixels, the GOA unit only needs to output the gate drive signal to drive the pixel to emit light for 1H time within one frame, and the output can remain in a holding state at other times, that is, it remains unchanged. Furthermore, each GOA unit typically includes interconnected input and output transistors, with the input transistors controlling the output transistors to output the gate drive signal through the output terminal.

[0005] However, because the output transistor is usually in a normally open or normally closed state when in holding state, the input transistor will be in a bias state, which will cause the input transistor to be unable to reliably control the output transistor to output the gate drive signal. In severe cases, it will also cause abnormal output of the GOA unit. Summary of the Invention

[0006] A shift register unit and its driving method, a gate driving circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] The first input circuit is connected to the input terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is used to control the connection and disconnection between the input terminal and the first node, control the connection and disconnection between the first power supply terminal and the first node, and control the connection and disconnection between the second power supply terminal and the first node in response to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the potential of the second node.

[0009] The second input circuit is connected to the input terminal, the second clock terminal, the first power terminal, the second power terminal, the first node, and the second node, respectively, and is used to control the on / off state of the first power terminal and the second node in response to the input signal provided by the input terminal, the second clock signal, and the potential of the first node;

[0010] The output circuit is connected to the first node, the second node, the third clock terminal, the second power supply terminal, and the output terminal respectively, and is used to control the connection and disconnection of the third clock terminal and the output terminal in response to the potential of the first node and the potential of the second node, and to control the connection and disconnection of the second power supply terminal and the output terminal.

[0011] Optionally, the first input circuit includes:

[0012] The first input sub-circuit is connected to the first clock terminal, the first power supply terminal, and the first node respectively, and is used to control the on / off state of the first power supply terminal and the first node in response to the first clock signal.

[0013] The second input sub-circuit is connected to the second clock terminal, the input terminal, and the first node respectively, and is used to control the connection and disconnection between the input terminal and the first node in response to the second clock signal;

[0014] The third input sub-circuit is connected to the second node, the third clock terminal, the second power supply terminal, and the first node, respectively, and is used to control the connection and disconnection between the second power supply terminal and the first node in response to the potential of the second node and the third clock signal.

[0015] Optionally, the first input sub-circuit includes: a first transistor;

[0016] The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first node.

[0017] Optionally, the second input sub-circuit includes: a second transistor;

[0018] The gate of the second transistor is connected to the second clock terminal, the first terminal of the second transistor is connected to the input terminal, and the second terminal of the second transistor is connected to the first node.

[0019] Optionally, the third input sub-circuit includes: a third transistor and a fourth transistor;

[0020] The gate of the third transistor is connected to the second node, the first terminal of the third transistor is connected to the second power supply terminal, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, the gate of the fourth transistor is connected to the third clock terminal, and the second terminal of the fourth transistor is connected to the first node.

[0021] Optionally, the second input circuit includes:

[0022] The fourth input sub-circuit is connected to the input terminal, the second clock terminal, the second power supply terminal, and the third node respectively, and is used to control the on / off state of the second power supply terminal and the third node or control the on / off state of the second node and the third node in response to the input signal, and is also used to adjust the potential of the third node in response to the second clock signal.

[0023] The fifth input sub-circuit is connected to the third node, the first power supply terminal and the second node respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the potential of the third node.

[0024] The sixth input sub-circuit is connected to the first node, the second power supply terminal, and the second node respectively, and is used to control the connection and disconnection between the second power supply terminal and the second node in response to the potential of the first node.

[0025] Optionally, the fourth input sub-circuit includes: a fifth transistor and a first capacitor;

[0026] When the fourth input sub-circuit responds to the input signal and controls the switching between the second power supply terminal and the third node, the gate of the fifth transistor is connected to the input terminal, the first terminal of the fifth transistor is connected to the second power supply terminal, and the second terminal of the fifth transistor is connected to the third node;

[0027] When the fourth input sub-circuit responds to the input signal and controls the switching on and off of the second node and the third node, the gate of the fifth transistor is connected to the input terminal, the first terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the third node;

[0028] One end of the first capacitor is connected to the second clock terminal, and the other end of the first capacitor is connected to the third node.

[0029] Optionally, the fifth input sub-circuit includes: a sixth transistor;

[0030] The gate of the sixth transistor is connected to the third node, the first terminal of the sixth transistor is connected to the first power supply terminal, and the second terminal of the sixth transistor is connected to the second node.

[0031] Optionally, the sixth input sub-circuit includes: a seventh transistor;

[0032] The gate of the seventh transistor is connected to the first node, the first terminal of the seventh transistor is connected to the second power supply terminal, and the second terminal of the seventh transistor is connected to the second node.

[0033] Optionally, the output circuit includes:

[0034] The first output sub-circuit is connected to the first node, the third clock terminal, and the output terminal respectively, and is used to control the on / off state of the third clock terminal and the output terminal in response to the potential of the first node, and is also used to adjust the potential of the first node based on the signal output through the output terminal.

[0035] The second output sub-circuit is connected to the second node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the second node, and is also used to adjust the potential of the second node based on the second power supply signal provided by the second power supply terminal.

[0036] Optionally, the first output sub-circuit includes an eighth transistor and a second capacitor; the second output sub-circuit includes a ninth transistor and a third capacitor.

[0037] The gate of the eighth transistor is connected to the first node, the first terminal of the eighth transistor is connected to the third clock terminal, and the second terminal of the eighth transistor is connected to the output terminal.

[0038] One end of the second capacitor is connected to the output terminal, and the other end of the second capacitor is connected to the first node;

[0039] The gate of the ninth transistor is connected to the second node, the first terminal of the ninth transistor is connected to the second power supply terminal, and the second terminal of the ninth transistor is connected to the output terminal.

[0040] One end of the third capacitor is connected to the second power supply terminal, and the other end of the third capacitor is connected to the second node.

[0041] Optionally, the first node includes: a first child node and a second child node; both the first input circuit and the second input circuit are connected to the first child node, and the output circuit is connected to the second child node; the shift register unit further includes:

[0042] An isolation circuit is connected to the first power supply terminal, the first sub-node, and the second sub-node respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to the first power supply signal provided by the first power supply terminal.

[0043] Optionally, the isolation circuit includes: a tenth transistor;

[0044] The gate of the tenth transistor is connected to the first power supply terminal, the first electrode of the tenth transistor is connected to the first sub-node, and the second electrode of the tenth transistor is connected to the second sub-node.

[0045] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0046] In the first stage, the first input circuit responds to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the potential of the second node, and controls the input terminal to be connected to the first node. The second input circuit responds to the input signal provided by the input terminal, the second clock signal, and the potential of the first node, and controls the second power supply terminal to be connected to the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to be connected to the output terminal.

[0047] In the second stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the first power supply terminal to be connected to the first node; the second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the second power supply terminal to be connected to the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to be connected to the output terminal.

[0048] In the third stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the input terminal to be connected to the first node; the second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the first power supply terminal to be connected to the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to be connected to the output terminal.

[0049] In the fourth stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the second power supply terminal to be connected to the first node. The second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the first power supply terminal to be connected to the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to be connected to the output terminal.

[0050] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: a plurality of cascaded shift register units as described in the preceding aspect.

[0051] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0052] The gate driving circuit is connected to the plurality of pixels via its output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0055] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0056] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0057] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0058] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0059] Figure 6 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

[0060] Figure 7 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0061] Figure 8 is a flowchart of a driving method for a shift register unit provided in an embodiment of this application;

[0062] Figure 9 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this application;

[0063] Figure 10 is a schematic diagram of the driving timing simulation of a shift register unit based on Figure 9;

[0064] Figure 11 is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0065] Figure 12 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0067] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. An example of a FET is a metal-oxide-semiconductor (MOS) FET, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include either P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential can refer to an effective potential, and the second potential can refer to an ineffective potential. Furthermore, the first potential and the second potential only represent that the potential of the signal has two state variables, and do not mean that the first potential or the second potential has a specific value throughout the text.

[0068] In the display field, in the panel driving circuits of various display devices, the gate driving signals received by the TFTs in the pixels all come from the GOA circuit surrounding the display panel. For example, in the driving circuit of an active-matrix organic light-emitting diode (AMOLED) panel.

[0069] It is understandable that a GOA circuit typically includes multiple cascaded GOA units. The output of each GOA unit can be connected to the data writing TFT in a row of pixels, and the gate drive signal required to output to the data writing TFT in a row of pixels can be transmitted through row pass. Furthermore, when the output gate drive signal is at an effective potential, the data writing TFT can be turned on, allowing the data voltage Vdata to be transmitted to the driving TFT in the pixel. The driving TFT can then drive the light-emitting element (e.g., AMOLED) in the pixel to emit light based on this data voltage. When the output gate drive signal is at an ineffective potential, the data writing TFT can be turned off. Based on this, assuming the data writing TFT is a P-type transistor, the effective potential can be low relative to the ineffective potential; assuming the data writing TFT is an N-type transistor, the effective potential can be high relative to the ineffective potential. Taking a low effective potential as an example, as described in the background, the GOA unit only needs to output a low-potential gate drive signal for 1H within a frame, and the gate drive signal can be kept at a high potential at other times, meaning the output of the GOA unit can remain in a holding state at other times.

[0070] In some embodiments, the GOA (Gateway Auxiliary) cell typically includes multiple input TFTs and two output TFTs. The multiple input TFTs control the potentials of the pull-up and pull-down nodes. Of the two output TFTs, one output TFT responds to the pull-up node potential by outputting a gate drive signal with an effective potential (e.g., low potential) at its output terminal, while the other output TFT responds to the pull-down node potential by outputting an ineffective potential (e.g., high potential) at its output terminal. Furthermore, when the GOA cell is held in a holding state, the TFT responding to the pull-up node potential is generally normally off, while the TFT responding to the pull-down node potential is generally normally on. This results in the TFT among the multiple input TFTs that controls the pull-up node potential in response to the pull-down node potential being constantly under a strong bias (e.g., a strong negative bias), which in turn leads to unreliable control of the pull-up node potential, causing the GOA cell to output a not-good (NG) signal. Tests revealed that, especially under vehicle-mounted environments or other more stringent temperature bias stress (BTS) testing conditions, the GOA unit is more prone to outputting NG.

[0071] Based on this, this application provides a GOA unit (i.e., shift register unit). The GOA unit controls the output through multiple signals. In the holding state, the output TFT will not be in a normally open or normally closed state, which can help improve the BTS of the GOA unit and ensure the normal output of the GOA unit.

[0072] Figure 1 illustrates a shift register unit provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes a first input circuit 01, a second input circuit 02, and an output circuit 03.

[0073] The first input circuit 01 is connected to the input terminal GIN, the first clock terminal CK1, the second clock terminal CK2, the third clock terminal CK3, the first power supply terminal VGL, the second power supply terminal VGH, the first node N1, and the second node N2, respectively. Furthermore, the first input circuit 01 is used to control the connection and disconnection of the input terminal GIN with the first node N1, the first power supply terminal VGL with the first node N1, and the second power supply terminal VGH with the first node N1, in response to the first clock signal provided by the first clock terminal CK1, the second clock signal provided by the second clock terminal CK2, the third clock signal provided by the third clock terminal CK3, and the potential of the second node N2.

[0074] For example, the first input circuit 01 can control the first power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal provided by the first clock terminal CK1 is at a first potential, so that the first power signal provided by the first power supply terminal VGL can be transmitted to the first node N1; and can control the first power supply terminal VGL to disconnect from the first node N1 when the potential of the first clock signal provided by the first clock terminal CK1 is at a second potential. Similarly, the first input circuit 01 can control the input terminal GIN to conduct with the first node N1 when the potential of the second clock signal provided by the second clock terminal CK2 is at a first potential, so that the input signal provided by the input terminal GIN can be transmitted to the first node N1; and can control the input terminal GIN to disconnect from the first node N1 when the potential of the second clock signal provided by the second clock terminal CK2 is at a second potential. The first input circuit 01 can control the second power supply terminal VGH to conduct with the first node N1 when the potential of the second node N2 and the potential of the third clock signal provided by the third clock terminal CK3 are both the first potential, so that the second power signal provided by the second power supply terminal VGH can be transmitted to the first node N1; and can control the second power supply terminal VGH to disconnect from the first node N1 when the potential of the second node N2 and / or the potential of the third clock signal provided by the third clock terminal CK3 are the second potential.

[0075] Optionally, in the embodiments of this application, the first potential can be an effective potential, the second potential can be an ineffective potential, and the effective potential can be a lower potential relative to the ineffective potential. That is, the effective potential can be a low potential, and the ineffective potential can be a high potential. Correspondingly, it can be understood that the transistors included in the circuits described in the embodiments of this application can be P-type transistors. Of course, for N-type transistors, as described above, the effective potential can be a higher potential relative to the ineffective potential. Based on this, the potential of the first power signal provided by the first power supply terminal VGL can be a low potential, and the potential of the second power signal provided by the second power supply terminal VGH can be a high potential. It can be understood that high potential and low potential are relative here.

[0076] The second input circuit 02 is connected to the input terminal GIN, the second clock terminal CK2, the first power supply terminal VGL, the second power supply terminal VGH, the first node N1, and the second node N2, respectively. Furthermore, the second input circuit 02 is used to control the switching between the first power supply terminal VGL and the second node N2 in response to the input signal provided by the input terminal GIN, the second clock signal, and the potential of the first node N1, and also controls the switching between the second power supply terminal VGH and the second node N2.

[0077] For example, the second input circuit 02 can control the first power supply terminal VGL to conduct with the second node N2 when the potential of the second clock signal provided by the second clock terminal CK2 is the first potential and the potential of the input signal provided by the input terminal GIN is the second potential, so that the first power supply signal provided by the first power supply terminal VGL can be transmitted to the second node N2; and can control the first power supply terminal VGL to disconnect from the second node N2 when the potential of the second clock signal provided by the second clock terminal CK2 is the second potential and / or the potential of the input signal provided by the input terminal GIN is the first potential. Similarly, the second input circuit 02 can control the second power supply terminal VGH to conduct with the second node N2 when the potential of the first node N1 is the first potential, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the second node N2; and can control the second power supply terminal VGH to disconnect from the second node N2 when the potential of the first node N1 is the second potential.

[0078] Output circuit 03 is connected to the first node N1, the second node N2, the third clock terminal CK3, the second power supply terminal VGH, and the output terminal GOUT, respectively. Furthermore, output circuit 03 is used to control the switching between the third clock terminal CK3 and the output terminal GOUT in response to the potential of the first node N1 and the second node N2, and also controls the switching between the second power supply terminal VGH and the output terminal GOUT.

[0079] For example, when the potential of the first node N1 is at the first potential, the output circuit 03 can control the third clock terminal CK3 to be connected to the output terminal GOUT, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT and output through the output terminal GOUT; and when the potential of the first node N1 is at the second potential, the output circuit 03 can control the third clock terminal CK3 to be disconnected from the output terminal GOUT. Similarly, when the potential of the second node N2 is at the first potential, the output circuit 03 can control the second power supply terminal VGH to be connected to the output terminal GOUT, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the output terminal GOUT and output through the output terminal GOUT; and when the potential of the second node N2 is at the second potential, the output circuit 03 can control the second power supply terminal VGH to be disconnected from the output terminal GOUT.

[0080] Optionally, the output terminal GOUT can be connected to a pixel. Correspondingly, the signal output from GOUT can be transmitted to the pixel as a gate drive signal to drive the pixel to emit light. Furthermore, as described above, GOUT can be connected to the data writing TFT in the pixel via a gate line. Additionally, GOUT can also be connected to the input terminal GIN of other cascaded shift register units to transmit the required input signals to their respective input terminals GIN. Of course, the input terminal GIN of the first-stage shift register unit can be connected to an additional enable signal terminal GSTV to receive the enable signal provided by GSTV.

[0081] Based on the above description, the input circuit (including the first input circuit 01 and the second input circuit 02) provided in this application embodiment can control the potential of the first node N1 and the potential of the second node N2 respectively under the drive of different clock signals provided by three clock terminals (including the first clock terminal CK1, the second clock terminal CK2, and the third clock terminal CK3). Thus, by flexibly setting these different clock signals, when the GOA unit is in a holding state, such as when it outputs a high-potential second power supply signal to the output terminal GOUT, the transistors included in the output circuit 03 can be alternately turned on and off, so that the transistors included in the output circuit 03 are not in a normally on or normally off state. This avoids the transistors in the input circuit that control the potential of the first node N1 in response to the potential of the second node N2 (i.e., the transistors in the first input circuit 01) from always being in a strongly negative bias state, thereby enabling the first input circuit 01 to reliably control the potential of the first node N1 and ensure the normal and stable output of the GOA unit. That is, it can reliably prevent the GOA unit from outputting NG. It is understandable that the first node N1 can refer to the pull-up node mentioned earlier, and the second node N2 can refer to the pull-down node mentioned earlier.

[0082] In summary, this application provides a shift register unit. This shift register unit includes two input circuits and one output circuit. Because the input circuits can reliably and flexibly control the potentials of the two nodes under the control of clock signals provided by multiple clock terminals, the output circuit can reliably output clock or power signals to the output terminal under the potential control of the two nodes. Furthermore, in the holding state, the transistors in the output circuit will not be in a normally on or normally off state, thereby preventing the transistors in the input circuits from being in a strongly biased state. This ensures that the input circuits can reliably control the node potentials and avoids abnormal output from the shift register unit.

[0083] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the first node N1 may include: a first child node N1-1 and a second child node N1-2. The first input circuit 01 and the second input circuit 02 may both be connected to the first child node N1-1, and the output circuit 03 may be connected to the second child node N1-2. That is, the first input circuit 01 can control the potential of the first child node N1-1 in the first node N1, and the second input circuit 02 can control the potential of the second node N2 in response to the potential of the first child node N1-1 in the first node N1, and the output circuit 03 can control the switching of the third clock terminal CK3 and the output terminal GOUT in response to the potential of the second child node N1-2 in the first node N1. Based on this, referring to Figure 2 further, it can be seen that the shift register unit may also include: an isolation circuit 04.

[0084] The isolation circuit 04 can be connected to the first power supply terminal VGL, the first sub-node N1-1, and the second sub-node N1-2, respectively. Furthermore, the isolation circuit 04 can be used to control the switching on and off of the first sub-node N1-1 and the second sub-node N1-2 in response to the first power supply signal provided by the first power supply terminal VGL.

[0085] For example, the isolation circuit 04 can control the first sub-node N1-1 and the second sub-node N1-2 to be turned on under the control of the first power signal provided by the first power supply terminal VGL, so that the signal transmitted to the first sub-node N1-1 can be further transmitted to the second sub-node N1-2.

[0086] It is understandable that by dividing the first node N1 into two nodes and setting up isolation circuit 04 to perform the above functions, the first child node N1-1 and the second child node N1-2 can be isolated, preventing voltage backflow from the output circuit 03 from causing potential instability in the first child node N1-1. This also protects the transistor controlling the potential of the first child node N1-1, thereby ensuring better output stability of the shift register unit. Based on this, in some other embodiments, the second node N2 can also be divided into two nodes, and isolation circuit 04 can be set between the two nodes to achieve the same isolation effect.

[0087] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the first input circuit 01 may include: a first input sub-circuit 011, a second input sub-circuit 012, and a third input sub-circuit 013.

[0088] The first input sub-circuit 011 can be connected to the first clock terminal CK1, the first power supply terminal VGL, and the first node N1, respectively. Furthermore, the first input sub-circuit 011 can be used to control the switching on and off of the first power supply terminal VGL and the first node N1 in response to the first clock signal.

[0089] For example, the first input sub-circuit 011 can control the first power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal is the first potential, so that the first power supply signal provided by the first power supply terminal VGL can be transmitted to the first node N1; and can control the first power supply terminal VGL to disconnect from the first node N1 when the potential of the first clock signal is the second potential.

[0090] The second input sub-circuit 012 can be connected to the second clock terminal CK2, the input terminal GIN, and the first node N1, respectively. Furthermore, the second input sub-circuit 012 can be used to control the on / off state of the input terminal GIN and the first node N1 in response to the second clock signal.

[0091] For example, the second input sub-circuit 012 can control the input terminal GIN to be connected to the first node N1 when the potential of the second clock signal is the first potential, so that the input signal provided by the input terminal GIN can be transmitted to the first node N1; and can control the input terminal GIN to be disconnected from the first node N1 when the potential of the second clock signal is the second potential.

[0092] The third input sub-circuit 013 can be connected to the second node N2, the third clock terminal CK3, the second power supply terminal VGH, and the first node N1, respectively. Furthermore, the third input sub-circuit 013 can be used to control the connection and disconnection between the second power supply terminal VGH and the first node N1 in response to the potential of the second node N2 and the third clock signal.

[0093] For example, the third input sub-circuit 013 can control the second power supply terminal VGH to conduct with the first node N1 when the potential of the second node N2 and the potential of the third clock signal are both the first potential, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the first node N1; and can control the second power supply terminal VGH to disconnect from the first node N1 when the potential of the second node N2 and / or the potential of the third clock signal are the second potential.

[0094] That is, the potential of the first node N1 can be reliably controlled by the cooperation of the first input sub-circuit 011, the second input sub-circuit 012 and the third input sub-circuit 013.

[0095] Furthermore, as can be seen from Figure 2 and the preceding description, based on dividing the first node N1 into the first sub-node N1-1 and the second sub-node N1-2, the first input sub-circuit 011, the second input sub-circuit 012 and the third input sub-circuit 013 can all be connected to the first sub-node N1-1 and can be used to control the potential of the first sub-node N1-1.

[0096] Optionally, Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 4, the second input circuit 02 may include: a fourth input sub-circuit 021, a fifth input sub-circuit 022, and a sixth input sub-circuit 023.

[0097] The fourth input sub-circuit 021 can be connected to the input terminal GIN, the second clock terminal CK2, the second power supply terminal VGH, and the third node N3, respectively. Furthermore, the fourth input sub-circuit 021 can be used to control the switching on / off of the second power supply terminal VGH and the third node N3, or to control the switching on / off of the second node N2 and the third node N3, in response to an input signal. It can also be used to adjust the potential of the third node N3 in response to a second clock signal.

[0098] For example, the fourth input sub-circuit 021 can control the second power supply terminal VGH to conduct with the third node N3 when the input signal potential is the first potential, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the third node N3; or control the second node N2 to conduct with the third node N3, so that the signal transmitted to the second node N2 can be further transmitted to the third node N3; and can control the second power supply terminal VGH to disconnect from the third node N3 when the input signal potential is the second potential. Furthermore, the fourth input sub-circuit 021 can adjust the potential of the third node N3 through coupling based on the second clock signal.

[0099] The fifth input sub-circuit 022 can be connected to the third node N3, the first power supply terminal VGL, and the second node N2, respectively. Furthermore, the fifth input sub-circuit 022 can be used to control the switching between the first power supply terminal VGL and the second node N2 in response to the potential of the third node N3.

[0100] For example, the fifth input sub-circuit 022 can control the first power supply terminal VGL to conduct with the second node N2 when the potential of the third node N3 is the first potential, so that the first power signal provided by the first power supply terminal VGL can be transmitted to the second node N2; and can control the first power supply terminal VGL to disconnect from the second node N2 when the potential of the third node N3 is the second potential.

[0101] The sixth input sub-circuit 023 can be connected to the first node N1, the second power supply terminal VGH, and the second node N2, respectively. Furthermore, the sixth input sub-circuit 023 can be used to control the switching between the second power supply terminal VGH and the second node N2 in response to the potential of the first node N1.

[0102] For example, the sixth input sub-circuit 023 can control the second power supply terminal VGH to conduct with the second node N2 when the potential of the first node N1 is the first potential, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the second node N2; and can control the second power supply terminal VGH to disconnect from the second node N2 when the potential of the first node N1 is the second potential.

[0103] That is, the potential of the second node N2 can be reliably controlled by the cooperation of the fourth input sub-circuit 021, the fifth input sub-circuit 022 and the sixth input sub-circuit 023.

[0104] Furthermore, as can be seen from Figure 2 and the preceding description, based on dividing the first node N1 into the first sub-node N1-1 and the second sub-node N1-2, the sixth input sub-circuit 023 can be connected to the first sub-node N1-1 and can be used to control the potential of the second node N2 in response to the potential of the first sub-node N1-1.

[0105] Optionally, Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 5, the output circuit 03 may include: a first output sub-circuit 031 and a second output sub-circuit 032.

[0106] The first output sub-circuit 031 can be connected to the first node N1, the third clock terminal CK3, and the output terminal GOUT, respectively. Furthermore, the first output sub-circuit 031 can be used to control the switching between the third clock terminal CK3 and the output terminal GOUT in response to the potential of the first node N1, and can also be used to adjust the potential of the first node N1 based on the signal output through the output terminal GOUT.

[0107] For example, the first output sub-circuit 031 can control the third clock terminal CK3 to conduct with the output terminal GOUT when the potential of the first node N1 is at the first potential, so that the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT and output through the output terminal GOUT; and can control the third clock terminal CK3 to disconnect from the output terminal GOUT when the potential of the first node N1 is at the second potential. In addition, the first output sub-circuit 031 can also adjust the potential of the first node N1 through coupling based on the signal output through the output terminal GOUT.

[0108] The second output sub-circuit 032 can be connected to the second node N2, the second power supply terminal VGH, and the output terminal GOUT, respectively. Furthermore, the second output sub-circuit 032 can be used to control the switching between the second power supply terminal VGH and the output terminal GOUT in response to the potential of the second node N2, and can also be used to adjust the potential of the second node N2 based on the second power supply signal provided by the second power supply terminal VGH.

[0109] For example, the second output sub-circuit 032 can control the second power supply terminal VGH to conduct with the output terminal GOUT when the potential of the second node N2 is the first potential, so that the second power signal provided by the second power supply terminal VGH can be transmitted to the output terminal GOUT and output through the output terminal GOUT; and can control the second power supply terminal VGH to disconnect from the output terminal GOUT when the potential of the second node N2 is the second potential. In addition, the second output sub-circuit 032 can also adjust the potential of the second node N2 through coupling based on the second power signal provided by the second power supply terminal VGH.

[0110] That is, the first output sub-circuit 031 and the second output sub-circuit 032 can respond to the potentials of the first node N1 and the second node N2 respectively, and output the gate drive signal through the output terminal GOUT.

[0111] Furthermore, as can be seen from Figure 2 and the preceding description, based on dividing the first node N1 into the first sub-node N1-1 and the second sub-node N1-2, the first output sub-circuit 031 can be connected to the second sub-node N1-2 and can be used to transmit a signal to the output terminal GOUT in response to the potential of the second sub-node N1-2.

[0112] Optionally, based on Figure 5, taking the fourth input sub-circuit 021 responding to the input signal to control the on / off state of the second power supply terminal VGH and the third node N3 as an example, Figure 6 shows a schematic diagram of the circuit structure of one shift register unit. Taking the fourth input sub-circuit 021 responding to the input signal to control the on / off state of the second node N2 and the third node N3, Figure 7 shows a schematic diagram of the circuit structure of another shift register unit. Furthermore, the input terminal GIN of the shift register units shown in Figures 6 and 7 is connected to the enable signal terminal GSTV, with GSTV representing the input terminal GIN. Referring to Figures 6 and 7, it can be seen that:

[0113] The first input sub-circuit 011 may include: a first transistor T1.

[0114] The gate of the first transistor T1 can be connected to the first clock terminal CK1, the first terminal of the first transistor T1 can be connected to the first power supply terminal VGL, and the second terminal of the first transistor T1 can be connected to the first node N1 (e.g., the first child node N1-1).

[0115] The second input sub-circuit 012 may include: the second transistor T2.

[0116] The gate of the second transistor T2 can be connected to the second clock terminal CK2, the first terminal of the second transistor T2 can be connected to the input terminal GIN (i.e., GSTV), and the second terminal of the second transistor T2 can be connected to the first node N1 (e.g., the first child node N1-1).

[0117] The third input sub-circuit 013 may include: a third transistor T3 and a fourth transistor T4.

[0118] The gate of the third transistor T3 can be connected to the second node N2, the first terminal of the third transistor T3 can be connected to the second power supply terminal VGH, the second terminal of the third transistor T3 can be connected to the first terminal of the fourth transistor T4, the gate of the fourth transistor T4 can be connected to the third clock terminal CK3, and the second terminal of the fourth transistor T4 can be connected to the first node N1 (e.g., the first child node N1-1).

[0119] The fourth input sub-circuit 021 may include: a fifth transistor T5 and a first capacitor C1.

[0120] As an optional implementation: when the fourth input sub-circuit 021 responds to the input signal and controls the switching of the second power supply terminal VGH and the third node N3, as shown in Figure 6, the gate of the fifth transistor T5 can be connected to the input terminal GIN (i.e., GSTV), the first terminal of the fifth transistor T5 can be connected to the second power supply terminal VGH, and the second terminal of the fifth transistor T5 can be connected to the third node N3.

[0121] As another optional implementation: when the fourth input sub-circuit 021 responds to the input signal and controls the on / off state of the second node N2 and the third node N3, as shown in Figure 7, the gate of the fifth transistor T5 can be connected to the input terminal GIN (i.e., GSTV), the first terminal of the fifth transistor T5 can be connected to the second node N2, and the second terminal of the fifth transistor T5 can be connected to the third node N3.

[0122] One end of the first capacitor C1 can be connected to the second clock terminal CK2, and the other end of the first capacitor C1 can be connected to the third node N3.

[0123] The fifth input sub-circuit 022 may include: the sixth transistor T6.

[0124] The gate of the sixth transistor T6 can be connected to the third node N3, the first terminal of the sixth transistor T6 can be connected to the first power supply terminal VGL, and the second terminal of the sixth transistor T6 can be connected to the second node N2.

[0125] The sixth input sub-circuit 023 may include: the seventh transistor T7.

[0126] The gate of the seventh transistor T7 can be connected to the first node N1 (e.g., the first child node N1-1), the first terminal of the seventh transistor T7 can be connected to the second power supply terminal VGH, and the second terminal of the seventh transistor T7 can be connected to the second node N2.

[0127] The first output sub-circuit 031 may include: an eighth transistor T8 and a second capacitor C2. The second output sub-circuit 032 may include: a ninth transistor T9 and a third capacitor C3.

[0128] The gate of the eighth transistor T8 can be connected to the first node N1 (e.g., the second child node N1-2), the first terminal of the eighth transistor T8 can be connected to the third clock terminal CK3, and the second terminal of the eighth transistor T8 can be connected to the output terminal GOUT.

[0129] One end of the second capacitor C2 can be connected to the output terminal GOUT, and the other end of the second capacitor C2 can be connected to the first node N1 (e.g., the second sub-node N1-2).

[0130] The gate of the ninth transistor T9 can be connected to the second node N2, the first terminal of the ninth transistor T9 can be connected to the second power supply terminal VGH, and the second terminal of the ninth transistor T9 can be connected to the output terminal GOUT.

[0131] One end of the third capacitor C3 can be connected to the second power supply terminal VGH, and the other end of the third capacitor C3 can be connected to the second node N2.

[0132] The isolation circuit 04 may include: the tenth transistor T10.

[0133] The gate of the tenth transistor T10 can be connected to the first power supply terminal VGL, the first terminal of the tenth transistor T10 can be connected to the first sub-node N1-1, and the second terminal of the tenth transistor T10 can be connected to the second sub-node N1-2.

[0134] Referring to Figures 6 and 7, the shift register unit provided in this embodiment can be a 10T3C structure (i.e., a structure including 10 transistors and 3 capacitors). However, in some other embodiments, the shift register unit can also be other structures, such as 12T3C. Furthermore, each transistor in the shift register unit provided in this embodiment can be a P-type transistor. However, in some other embodiments, each transistor in the shift register unit can also be an N-type transistor; or it can include both P-type and N-type transistors. This embodiment does not limit these aspects.

[0135] In summary, this application provides a shift register unit. This shift register unit includes two input circuits and one output circuit. Because the input circuits can reliably and flexibly control the potentials of the two nodes under the control of clock signals provided by multiple clock terminals, the output circuit can reliably output clock or power signals to the output terminal under the potential control of the two nodes. Furthermore, in the holding state, the transistors in the output circuit will not be in a normally on or normally off state, thereby preventing the transistors in the input circuits from being in a strongly biased state. This ensures that the input circuits can reliably control the node potentials and avoids abnormal output from the shift register unit.

[0136] This application also provides a method for driving a shift register unit, used to drive any of the shift register units shown in Figures 1 to 7. As shown in Figure 8, the method includes:

[0137] Step 801, First stage: The first input circuit responds to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the potential of the second node, and controls the input terminal to be connected to the first node. The second input circuit responds to the input signal provided by the input terminal, the second clock signal, and the potential of the first node, and controls the second power supply terminal to be connected to the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to be connected to the output terminal.

[0138] Step 802, Second Stage: The first input circuit responds to the first clock signal, the second clock signal, the third clock signal, and the potential of the second node, and controls the first power supply terminal to conduct with the first node. The second input circuit responds to the input signal, the second clock signal, and the potential of the first node, and controls the second power supply terminal to conduct with the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to conduct with the output terminal.

[0139] Step 803, the third stage: the first input circuit responds to the first clock signal, the second clock signal, the third clock signal, and the potential of the second node, and controls the input terminal to be connected to the first node; the second input circuit responds to the input signal, the second clock signal, and the potential of the first node, and controls the first power supply terminal to be connected to the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to be connected to the output terminal.

[0140] Step 804, the fourth stage: the first input circuit responds to the first clock signal, the second clock signal, the third clock signal, and the potential of the second node, and controls the second power supply terminal to conduct with the first node; the second input circuit responds to the input signal, the second clock signal, and the potential of the first node, and controls the first power supply terminal to conduct with the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to conduct with the output terminal.

[0141] Optionally, taking the structure shown in Figure 6 as an example, that is, taking the shift register unit as the first-stage shift register unit, with the input terminal GIN connected to the enable signal terminal GSTV, and each transistor in the shift register unit being a P-type transistor, with the first potential (i.e., the effective potential) being low and the second potential (i.e., the ineffective potential) being high, the driving method of the shift register unit is explained as follows, in conjunction with the driving timing diagram shown in Figure 9:

[0142] (1) In stage T01, the potential of the first clock signal provided by the first clock terminal CK1 is low, and the potential of the input signal provided by the input terminal GSTV, the potential of the second clock signal provided by the second clock terminal CK2, and the potential of the third clock signal provided by the third clock terminal CK3 are all high. This allows the first transistor T1 to be turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to be turned off. Furthermore, since the potential of the first power signal provided by the first power terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the first power terminal VGL can be connected to the first sub-node N1-1, and the first sub-node N1-1 can be connected to the second sub-node N1-2, while the input terminal GSTV can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the third node N3, and the first power terminal VGL can be disconnected from the second node N2. Furthermore, the low-potential first power signal provided by the first power supply terminal VGL can be transmitted to the first child node N1-1 via the turned-on first transistor T1, and then further transmitted to the second child node N1-2 via the turned-on tenth transistor T10. This also enables the seventh transistor T7 to be turned on. Correspondingly, the second power supply terminal VGH can be connected to the second node N2, allowing the high-potential second power signal provided by the second power supply terminal VGH to be transmitted to the second node N2 via the turned-on seventh transistor T7. This also enables the third transistor T3 to be turned off, ensuring a reliable disconnection between the second power supply terminal VGH and the first child node N1-1.

[0143] That is, in stage T01, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be low, and the potential of the second node N2 can be controlled to be high. Based on this, the eighth transistor T8 can be turned on, and the ninth transistor T9 can be turned off. Correspondingly, the third clock terminal CK3 can be turned on with the output terminal GOUT, and the second power supply terminal VGH can be disconnected from the output terminal GOUT. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT through the turned-on eighth transistor T8. Since the potential of the third clock signal is high in this stage T01, it can be known that the potential of the gate drive signal output through the output terminal GOUT is also high.

[0144] (2) In stage T02, the potential of the input signal provided by the input terminal GSTV and the potential of the second clock signal provided by the second clock terminal CK2 are both low, and the potentials of the first clock signal provided by the first clock terminal CK1 and the third clock signal provided by the third clock terminal CK3 are both high. This allows the second transistor T2 and the fifth transistor T5 to be turned on, and the first transistor T1 and the fourth transistor T4 to be turned off. Furthermore, since the potential of the first power signal provided by the first power supply terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the input terminal GSTV can be connected to the first sub-node N1-1, the second power supply terminal VGH can be connected to the third node N3, and the first sub-node N1-1 can be connected to the second sub-node N1-2. Conversely, the first power supply terminal VGL can be disconnected from the first sub-node N1-1, and the second power supply terminal VGH can be disconnected from the first sub-node N1-1. Furthermore, the high-potential second power signal provided by the second power supply terminal VGH can be transmitted to the third node N3 via the turned-on fifth transistor T5, and the low-potential input signal provided by the input terminal GSTV can first be transmitted to the first sub-node N1-1 via the turned-on second transistor T2, and then further transmitted to the second sub-node N1-2 via the turned-on tenth transistor T10. This also allows the sixth transistor T6 to be turned off and the seventh transistor T7 to be turned on. Correspondingly, the second power supply terminal VGH can be connected to the second node N2, allowing the high-potential second power signal provided by the second power supply terminal VGH to be transmitted to the second node N2 via the turned-on seventh transistor T7. This also allows the third transistor T3 to be turned off, ensuring a reliable disconnection between the second power supply terminal VGH and the first sub-node N1-1.

[0145] That is, in stage T02, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can continue to be controlled to be low, and the potential of the second node N2 can continue to be controlled to be high. Based on this, the eighth transistor T8 can be turned on, and the ninth transistor T9 can be turned off. Correspondingly, the third clock terminal CK3 can be turned on to the output terminal GOUT, and the second power supply terminal VGH can be disconnected from the output terminal GOUT. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT through the turned-on eighth transistor T8. Since the potential of the third clock signal is also high in this stage T02, it can be known that the potential of the gate drive signal output through the output terminal GOUT is also high at this time.

[0146] (3) In stage T03, the potential of the third clock signal provided by the third clock terminal CK3 is low, and the potential of the input signal provided by the input terminal GSTV, the potential of the first clock signal provided by the first clock terminal CK1, and the potential of the second clock signal provided by the second clock terminal CK2 are all high. This allows the fourth transistor T4 to be turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 to be turned off. Furthermore, since the potential of the first power signal provided by the first power supply terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the first power supply terminal VGL can be disconnected from the first sub-node N1-1, the input terminal GSTV can be disconnected from the first sub-node N1-1, the second power supply terminal VGH can be disconnected from the third node N3, and the first power supply terminal VGL can be disconnected from the second node N2. Under the coupling effect of the second capacitor C2, the potentials of the first sub-node N1-1 and the second sub-node N1-2 can be low. Furthermore, because the potential of the third clock signal jumps from high to low, the potential of the second sub-node N1-2 can be coupled to an even lower potential. This also allows the seventh transistor T7 to turn on. Correspondingly, the second power supply terminal VGH can be connected to the second node N2. Furthermore, the high-potential second power supply signal provided by the second power supply terminal VGH can be transmitted to the second node N2 via the turned-on seventh transistor T7. This also allows the third transistor T3 to turn off. Correspondingly, the second power supply terminal VGH can be disconnected from the first sub-node N1-1.

[0147] That is, in stage T03, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be even lower low potentials, and the potential of the second node N2 can continue to be controlled to be high potentials. Based on this, the eighth transistor T8 can be fully turned on, while the ninth transistor T9 can be turned off. Correspondingly, the third clock terminal CK3 can be turned on with the output terminal GOUT, while the second power supply terminal VGH can be disconnected from the output terminal GOUT. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT through the turned-on eighth transistor T8. Since the potential of the third clock signal is low in this stage T03, it can be known that the potential of the gate drive signal output through the output terminal GOUT is low at this time.

[0148] (4) In stage T04, the potential of the first clock signal provided by the first clock terminal CK1 is low, and the potential of the input signal provided by the input terminal GSTV, the potential of the second clock signal provided by the second clock terminal CK2, and the potential of the third clock signal provided by the third clock terminal CK3 are all high. This allows the first transistor T1 to be turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to be turned off. Furthermore, since the potential of the first power signal provided by the first power terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the first power terminal VGL can be connected to the first sub-node N1-1, and the first sub-node N1-1 can be connected to the second sub-node N1-2, while the input terminal GSTV can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the third node N3, and the first power terminal VGL can be disconnected from the second node N2. Furthermore, the low-potential first power signal provided by the first power supply terminal VGL can be transmitted to the first child node N1-1 via the turned-on first transistor T1, and then further transmitted to the second child node N1-2 via the turned-on tenth transistor T10. This also enables the seventh transistor T7 to be turned on. Correspondingly, the second power supply terminal VGH can be connected to the second node N2, allowing the high-potential second power signal provided by the second power supply terminal VGH to be transmitted to the second node N2 via the turned-on seventh transistor T7. This also enables the third transistor T3 to be turned off, ensuring a reliable disconnection between the second power supply terminal VGH and the first child node N1-1.

[0149] That is, in stage T04, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be low, and the potential of the second node N2 can be controlled to be high. Based on this, the eighth transistor T8 can be turned on, and the ninth transistor T9 can be turned off. Correspondingly, the third clock terminal CK3 can be turned on with the output terminal GOUT, and the second power supply terminal VGH can be disconnected from the output terminal GOUT. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT through the turned-on eighth transistor T8. Since the potential of the third clock signal is high in this stage T04, it can be known that the potential of the gate drive signal output through the output terminal GOUT is also high.

[0150] (5) In stage T05, the potential of the second clock signal provided by the second clock terminal CK2 is low, and the potential of the input signal provided by the input terminal GSTV, the potential of the first clock signal provided by the first clock terminal CK1, and the potential of the third clock signal provided by the third clock terminal CK3 are all high. This allows the second transistor T2 and the sixth transistor T6 to be turned on, and the first transistor T1, the fourth transistor T4, and the fifth transistor T5 to be turned off. Furthermore, since the potential of the first power signal provided by the first power supply terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the input terminal GSTV can be connected to the first sub-node N1-1, the first power supply terminal VGL can be connected to the second node N2, and the first sub-node N1-1 can be connected to the second sub-node N1-2. Conversely, the first power supply terminal VGL can be disconnected from the first sub-node N1-1, and the second power supply terminal VGH can be disconnected from the first sub-node N1-1 and the third node N3. Furthermore, the low-potential first power signal provided by the first power supply terminal VGL can be transmitted to the second node N2 via the turned-on sixth transistor T6, and the high-potential input signal provided by the input terminal GSTV can be transmitted first to the first sub-node N1-1 via the turned-on second transistor T2, and then further transmitted to the second sub-node N1-2 via the turned-on tenth transistor T10. This also allows the third transistor T3 to be turned on and the seventh transistor T7 to be turned off. Correspondingly, the second power supply terminal VGH can be disconnected from the second node N2.

[0151] That is, in stage T05, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be high, and the potential of the second node N2 can be controlled to be low. Based on this, the ninth transistor T9 can be turned on, and the eighth transistor T8 can be turned off. Correspondingly, the second power supply terminal VGH can be turned on with the output terminal GOUT, and the third clock terminal CK3 can be disconnected from the output terminal GOUT. Furthermore, the high-potential second power supply signal provided by the second power supply terminal VGH can be transmitted to the output terminal GOUT through the turned-on ninth transistor T9. That is, the potential of the gate drive signal output through the output terminal GOUT at this time is high.

[0152] (6) In stage T06, the potential of the third clock signal provided by the third clock terminal CK3 is low, and the potentials of the input signal provided by the input terminal GSTV, the first clock signal provided by the first clock terminal CK1, and the second clock signal provided by the second clock terminal CK2 are all high. This allows the fourth transistor T4 to be turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 to be turned off. Furthermore, since the potential of the first power signal provided by the first power supply terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the first power supply terminal VGL can be disconnected from the first sub-node N1-1, the input terminal GSTV can be disconnected from the first sub-node N1-1, the second power supply terminal VGH can be disconnected from the third node N3, and the first power supply terminal VGL can be disconnected from the second node N2. Under the action of the second capacitor C2, the potentials of the first sub-node N1-1 and the second sub-node N1-2 can be maintained at high potentials. This also allows the seventh transistor T7 to be turned off. Correspondingly, this disconnects the second power supply terminal VGH from the second node N2. Furthermore, under the influence of the third capacitor C3, the potential of the second node N2 remains low. This also allows the third transistor T3 to turn on. Consequently, this connects the second power supply terminal VGH to the first sub-node N1-1. Furthermore, the high-potential second power signal provided by the second power supply terminal VGH is first transmitted to the first sub-node N1-1 via the turned-on third transistor T3 and fourth transistor T4, and then to the second sub-node N1-2 via the turned-on tenth transistor T10, ensuring that the potentials of both the first sub-node N1-1 and the second sub-node N1-2 are high.

[0153] That is, in stage T06, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be high, and the potential of the second node N2 can be controlled to be low. Based on this, the ninth transistor T9 can be turned on, and the eighth transistor T8 can be turned off. Correspondingly, the second power supply terminal VGH can be turned on and the output terminal GOUT can be turned off, while the third clock terminal CK3 can be disconnected from the output terminal GOUT. Furthermore, the high-potential second power supply signal provided by the second power supply terminal VGH can be transmitted to the output terminal GOUT through the turned-on ninth transistor T9. That is, at this time, the potential of the gate drive signal output through the output terminal GOUT is high.

[0154] (7) In stage T07, the potential of the first clock signal provided by the first clock terminal CK1 is low, and the potential of the input signal provided by the input terminal GSTV, the potential of the second clock signal provided by the second clock terminal CK2, and the potential of the third clock signal provided by the third clock terminal CK3 are all high. This allows the first transistor T1 to be turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to be turned off. Furthermore, since the potential of the first power signal provided by the first power terminal VGL is low, the tenth transistor T10 can also be turned on. Correspondingly, the first power terminal VGL can be connected to the first sub-node N1-1, and the first sub-node N1-1 can be connected to the second sub-node N1-2, while the input terminal GSTV can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the first sub-node N1-1, the second power terminal VGH can be disconnected from the third node N3, and the first power terminal VGL can be disconnected from the second node N2. Furthermore, the low-potential first power signal provided by the first power supply terminal VGL can be transmitted to the first child node N1-1 via the turned-on first transistor T1, and then further transmitted to the second child node N1-2 via the turned-on tenth transistor T10. This also enables the seventh transistor T7 to be turned on. Correspondingly, the second power supply terminal VGH can be connected to the second node N2, allowing the high-potential second power signal provided by the second power supply terminal VGH to be transmitted to the second node N2 via the turned-on seventh transistor T7. This also enables the third transistor T3 to be turned off, ensuring a reliable disconnection between the second power supply terminal VGH and the first child node N1-1.

[0155] That is, similar to stage T04, in stage T07, the potentials of the two child nodes N1-1 and N1-2 included in the first node N1 can be controlled to be low, and the potential of the second node N2 can be controlled to be high. Based on this, the eighth transistor T8 can be turned on, and the ninth transistor T9 can be turned off. Correspondingly, the third clock terminal CK3 can be turned on to the output terminal GOUT, and the second power supply terminal VGH can be disconnected from the output terminal GOUT. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the output terminal GOUT via the turned-on eighth transistor T8. Since the potential of the third clock signal is high in stage T07, it can be known that the potential of the gate drive signal output through the output terminal GOUT is also high. Stage T07 can be considered a repetition of stage T04.

[0156] It is understandable that stages T02 and T03 correspond to the first stage shown in Figure 8, stage T04 corresponds to the second stage shown in Figure 8, stage T05 corresponds to the third stage shown in Figure 8, and stage T06 corresponds to the fourth stage shown in Figure 8. In actual operation, stages T04 through T06 can be repeatedly executed while in a holding state. For example, stage T07 is a repeated execution of stage T04.

[0157] Optionally, based on Figure 9, Figure 10 also schematically shows the corresponding timing simulation diagram. Combining Figures 9 and 10, it can be seen that in stage T03, the shift register unit can output a low-level (i.e., effective level) gate drive signal, and then continuously output a high-level (i.e., ineffective level) gate drive signal. Accordingly, the stage after T03 can be considered as the stage where the shift register unit is in a holding state. In some embodiments, because the eighth transistor T8 of the output circuit 03 is continuously off and the ninth transistor T9 is continuously on after stage T03, that is, the potential of the second node N2 will remain low for a long time, causing the third transistor T3 to remain in a strongly negative bias state, which in turn causes the first node N1 to be unable to reliably maintain a high potential, resulting in the eighth transistor T8 being falsely turned on, causing the shift register unit to output NG. In this embodiment of the application, as can be seen from Figure 9, after the T03 stage, under the control of three different clock signals, the potential of the first node N1 and the potential of the second node N2 can be controlled to alternately be high or low, so that the eighth transistor T8 and the ninth transistor T9 included in the output circuit 03 can be alternately turned on or off. Therefore, the third transistor T3 can be avoided from always being in a strong negative bias state, thereby avoiding the situation where the shift register unit outputs NG.

[0158] It is understood that the working principle and driving timing of the structure shown in Figure 7 are the same as those of the structure shown in Figure 6. That is, the driving timing diagram and timing simulation diagram of the structure shown in Figure 7 can be referenced in Figures 9 and 10, and will not be repeated. The difference lies in that when the fifth transistor T5 responds to a low-potential input signal, it controls the second node N2 and the third node N3 to conduct, rather than controlling the second power supply terminal VGH and the third node N3 to conduct. Furthermore, referring to the timing diagrams in Figures 9 and 10, it can be seen that the shift register unit provided in this embodiment is used to output gate drive signals to the P-type transistors in the pixel. Accordingly, the shift register unit can also be called a Pgate GOA unit.

[0159] It is understood that since the driving method of the shift register unit can have the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the driving method of the shift register unit will not be described again here for the sake of brevity.

[0160] This application also provides a gate driving circuit. As shown in FIG11, the gate driving circuit includes: a plurality of cascaded shift register units, i.e., GOA units, as shown in any one of FIG1 to FIG7. The figure schematically shows four cascaded GOA units, labeled as GOA(1) to GOA(4).

[0161] Optionally, the output terminal GOUT of the i-th stage GOA unit can be connected to the input terminal GIN of the (i+L)-th stage GOA unit, and the output terminal GOUT of the i-th stage GOA unit can also be connected to a pixel to transmit the required input signal to the input terminal GIN of the (i+L)-th stage GOA unit and the required gate drive signal to the pixel. Here, 1≤i≤ML, M is the total number of GOA units, M≥1, and L is a positive integer greater than or equal to 1. Of course, the input terminal GIN of the first stage GOA unit can be connected to the enable signal terminal GSTV to receive the enable signal provided by GSTV, realizing shift drive. For example, referring to Figure 11, L is shown as 1, meaning that in the gate drive circuit shown, every two adjacent GOA units are cascaded.

[0162] It is understood that since the gate drive circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the gate drive circuit will not be described again here for the sake of brevity.

[0163] This application also provides a display device. As shown in FIG12, the display device includes: a display panel 100, and a gate driving circuit 000 as shown in FIG11.

[0164] The display panel 100 includes multiple pixels (not shown in the figure). The gate drive circuit 000 is connected to the multiple pixels via the output terminal GOUT and is used to transmit gate drive signals to the multiple pixels to drive the multiple pixels to emit light.

[0165] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an OLED display device, an AMOLED display device, or a liquid crystal display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0166] It is understood that since the display device can have essentially the same technical effect as the gate drive circuit described in the previous embodiments, the technical effect of the display device will not be repeated here for the sake of brevity.

[0167] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the scope of this application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0168] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0169] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: The first input circuit is connected to the input terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is used to control the connection and disconnection between the input terminal and the first node, control the connection and disconnection between the first power supply terminal and the first node, and control the connection and disconnection between the second power supply terminal and the first node in response to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the potential of the second node. The second input circuit is connected to the input terminal, the second clock terminal, the first power terminal, the second power terminal, the first node, and the second node, respectively, and is used to control the on / off state of the first power terminal and the second node in response to the input signal provided by the input terminal, the second clock signal, and the potential of the first node; The output circuit is connected to the first node, the second node, the third clock terminal, the second power supply terminal, and the output terminal respectively, and is used to control the connection and disconnection of the third clock terminal and the output terminal in response to the potential of the first node and the potential of the second node, and to control the connection and disconnection of the second power supply terminal and the output terminal.

2. The shift register unit according to claim 1, wherein, The first input circuit includes: The first input sub-circuit is connected to the first clock terminal, the first power supply terminal, and the first node respectively, and is used to control the on / off state of the first power supply terminal and the first node in response to the first clock signal. The second input sub-circuit is connected to the second clock terminal, the input terminal, and the first node respectively, and is used to control the connection and disconnection between the input terminal and the first node in response to the second clock signal; The third input sub-circuit is connected to the second node, the third clock terminal, the second power supply terminal, and the first node, respectively, and is used to control the connection and disconnection between the second power supply terminal and the first node in response to the potential of the second node and the third clock signal.

3. The shift register unit according to claim 2, wherein, The first input sub-circuit includes: a first transistor; The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first node.

4. The shift register unit according to claim 2 or 3, wherein, The second input sub-circuit includes: a second transistor; The gate of the second transistor is connected to the second clock terminal, the first terminal of the second transistor is connected to the input terminal, and the second terminal of the second transistor is connected to the first node.

5. The shift register unit according to any one of claims 2 to 4, wherein, The third input sub-circuit includes: a third transistor and a fourth transistor; The gate of the third transistor is connected to the second node, the first terminal of the third transistor is connected to the second power supply terminal, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, the gate of the fourth transistor is connected to the third clock terminal, and the second terminal of the fourth transistor is connected to the first node.

6. The shift register unit according to any one of claims 1 to 5, wherein, The second input circuit includes: The fourth input sub-circuit is connected to the input terminal, the second clock terminal, the second power supply terminal, and the third node respectively, and is used to control the on / off state of the second power supply terminal and the third node or control the on / off state of the second node and the third node in response to the input signal, and is also used to adjust the potential of the third node in response to the second clock signal. The fifth input sub-circuit is connected to the third node, the first power supply terminal and the second node respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the potential of the third node. The sixth input sub-circuit is connected to the first node, the second power supply terminal, and the second node respectively, and is used to control the connection and disconnection between the second power supply terminal and the second node in response to the potential of the first node.

7. The shift register unit according to claim 6, wherein, The fourth input sub-circuit includes: a fifth transistor and a first capacitor; When the fourth input sub-circuit responds to the input signal and controls the switching between the second power supply terminal and the third node, the gate of the fifth transistor is connected to the input terminal, the first terminal of the fifth transistor is connected to the second power supply terminal, and the second terminal of the fifth transistor is connected to the third node; When the fourth input sub-circuit responds to the input signal and controls the switching on and off of the second node and the third node, the gate of the fifth transistor is connected to the input terminal, the first terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the third node; One end of the first capacitor is connected to the second clock terminal, and the other end of the first capacitor is connected to the third node.

8. The shift register unit according to claim 6 or 7, wherein, The fifth input sub-circuit includes: a sixth transistor; The gate of the sixth transistor is connected to the third node, the first terminal of the sixth transistor is connected to the first power supply terminal, and the second terminal of the sixth transistor is connected to the second node.

9. The shift register unit according to any one of claims 6 to 8, wherein, The sixth input sub-circuit includes: a seventh transistor; The gate of the seventh transistor is connected to the first node, the first terminal of the seventh transistor is connected to the second power supply terminal, and the second terminal of the seventh transistor is connected to the second node.

10. The shift register unit according to any one of claims 1 to 9, wherein, The output circuit includes: The first output sub-circuit is connected to the first node, the third clock terminal, and the output terminal respectively, and is used to control the on / off state of the third clock terminal and the output terminal in response to the potential of the first node, and is also used to adjust the potential of the first node based on the signal output through the output terminal. The second output sub-circuit is connected to the second node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the second node, and is also used to adjust the potential of the second node based on the second power supply signal provided by the second power supply terminal.

11. The shift register unit according to claim 10, wherein, The first output sub-circuit includes: an eighth transistor and a second capacitor; the second output sub-circuit includes: a ninth transistor and a third capacitor; The gate of the eighth transistor is connected to the first node, the first terminal of the eighth transistor is connected to the third clock terminal, and the second terminal of the eighth transistor is connected to the output terminal. One end of the second capacitor is connected to the output terminal, and the other end of the second capacitor is connected to the first node; The gate of the ninth transistor is connected to the second node, the first terminal of the ninth transistor is connected to the second power supply terminal, and the second terminal of the ninth transistor is connected to the output terminal. One end of the third capacitor is connected to the second power supply terminal, and the other end of the third capacitor is connected to the second node.

12. The shift register unit according to any one of claims 1 to 11, wherein, The first node includes: a first child node and a second child node; both the first input circuit and the second input circuit are connected to the first child node, and the output circuit is connected to the second child node; the shift register unit further includes: An isolation circuit is connected to the first power supply terminal, the first sub-node, and the second sub-node respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to the first power supply signal provided by the first power supply terminal.

13. The shift register unit according to claim 12, wherein, The isolation circuit includes: a tenth transistor; The gate of the tenth transistor is connected to the first power supply terminal, the first electrode of the tenth transistor is connected to the first sub-node, and the second electrode of the tenth transistor is connected to the second sub-node.

14. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 13; the method comprising: In the first stage, the first input circuit responds to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the third clock signal provided by the third clock terminal, and the potential of the second node, and controls the input terminal to be connected to the first node. The second input circuit responds to the input signal provided by the input terminal, the second clock signal, and the potential of the first node, and controls the second power supply terminal to be connected to the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to be connected to the output terminal. In the second stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the first power supply terminal to be connected to the first node; the second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the second power supply terminal to be connected to the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the third clock terminal to be connected to the output terminal. In the third stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the input terminal to be connected to the first node; the second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the first power supply terminal to be connected to the second node; the output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to be connected to the output terminal. In the fourth stage, the first input circuit responds to the first clock signal, the second clock signal, the third clock signal and the potential of the second node, and controls the second power supply terminal to be connected to the first node. The second input circuit responds to the input signal, the second clock signal and the potential of the first node, and controls the first power supply terminal to be connected to the second node. The output circuit responds to the potential of the first node and the potential of the second node, and controls the second power supply terminal to be connected to the output terminal.

15. A gate driving circuit, the gate driving circuit comprising: A series of cascaded shift register units as described in any one of claims 1 to 13.

16. A display device, the display device comprising: The display panel, and the gate driving circuit as described in claim 15; The display panel includes multiple pixels; The gate driving circuit is connected to the plurality of pixels via its output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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