Shift register and driving method therefor, and gate driving circuit and display panel

Abstract

Provided in the present disclosure are a shift register and a driving method therefor, and a gate driving circuit and a display panel. The shift register has an input phase, an output phase and a reset phase. The shift register comprises: an input sub-circuit, which is configured to, during the input phase, transmit an input signal to a first node in response to a first clock signal; an output sub-circuit, which is configured to, during the output phase, output a second clock signal by means of a signal output end in response to the potential of the first node, wherein within one operating cycle, a start moment of an active level of the second clock signal is not earlier than an end moment of an active level of the first clock signal; a first control sub-circuit, which is configured to, during the input phase and the reset phase, control the potential of a second node by means of a third clock signal in response to the input signal and the third clock signal; and a holding sub-circuit, which is configured to, during the reset phase, output a first inactive operating level signal by means of the signal output end in response to the potential of the second node.

Description

Shift registers and their driving methods, gate driving circuits and display panels Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register and its driving method, a gate driving circuit, and a display panel. Background Technology

[0002] Currently, AMOLED (Active-matrix organic light-emitting diode) flexible screen technology is becoming increasingly mature. Its characteristics, such as flexibility, light weight, high contrast, and low power consumption, make it a potential next-generation display technology to replace Liquid Crystal Display (LCD). AMOLED displays incorporate gate drive circuits that provide gate drive signals to pixel units. These gate drive circuits include multiple cascaded shift registers, each configured to provide a gate drive signal to one or more rows of pixel units. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art, and provides a shift register, including an input sub-circuit, an output sub-circuit, a first control sub-circuit, and a holding sub-circuit; wherein,

[0004] The input sub-circuit is configured to transmit an input signal to a first node in response to a first clock signal; the first node is the connection node between the input sub-circuit and the output sub-circuit.

[0005] The output sub-circuit is configured to output a second clock signal through a signal output terminal in response to the potential of the first node; the first control sub-circuit is configured to control the potential of the second node through the third clock signal in response to the input signal and the third clock signal; the second node is the connection node between the first control sub-circuit and the holding sub-circuit.

[0006] The holding sub-circuit is configured to output a first invalid operating level signal through the signal output terminal in response to the potential of the second node.

[0007] In some embodiments, the first control sub-circuit includes a second transistor, a third transistor, and a first capacitor;

[0008] The control electrode of the second transistor is connected to the signal input terminal, the first electrode is connected to the control electrode of the third transistor, and the second electrode is connected to the second invalid working level signal terminal; the second invalid working level signal is greater than or equal to the first invalid working level signal.

[0009] The control electrode of the third transistor is connected to the first electrode of the second transistor and the first electrode of the first capacitor. The first electrode is connected to the second electrode of the first capacitor and the third clock signal terminal. The second electrode is connected to the second node.

[0010] In some embodiments, the shift register further includes a first pull-up sub-circuit;

[0011] The first pull-up sub-circuit is configured to pull up the first node in response to the third clock signal and the potential of the second node by a second invalid operating level signal; the second invalid operating level signal is greater than or equal to the first invalid operating level signal.

[0012] In some embodiments, the first pull-up sub-circuit includes a sixth transistor and a seventh transistor;

[0013] The control electrode of the sixth transistor is connected to the second node, the first electrode is connected to the second invalid working level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the third clock signal terminal, and the second electrode is connected to the first node.

[0014] In some embodiments, the shift register further includes a second pull-up sub-circuit;

[0015] The second pull-up sub-circuit is configured to pull up the second node in response to the potential of the first node by a second invalid operating level signal; the second invalid operating level signal is greater than or equal to the first invalid operating level signal.

[0016] In some embodiments, the second pull-up sub-circuit includes a ninth transistor;

[0017] The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the second invalid working level signal terminal.

[0018] In some embodiments, the shift register further includes a protection sub-circuit;

[0019] The protection sub-circuit is configured to transmit a second invalid operating level signal to the first node in response to a protection level signal; the second invalid operating level signal is greater than or equal to the first invalid operating level signal.

[0020] In some embodiments, the protection sub-circuit includes a tenth transistor;

[0021] The control electrode of the tenth transistor is connected to the protection level signal terminal, the first electrode is connected to the first node, and the second electrode is connected to the second invalid working level signal terminal.

[0022] In some embodiments, the shift register further includes a voltage stabilization sub-circuit;

[0023] The voltage stabilizing sub-circuit is connected between the input sub-circuit and the output sub-circuit; the connection node between the voltage stabilizing sub-circuit and the input sub-circuit is the first sub-node, and the connection node between the voltage stabilizing sub-circuit and the output sub-circuit is the second sub-node;

[0024] The voltage stabilizing sub-circuit is configured to transmit the voltage of the first sub-node to the second sub-node in response to an operating level signal.

[0025] In some embodiments, the voltage stabilizing sub-circuit includes an eighth transistor;

[0026] The control electrode of the eighth transistor is connected to the working level signal terminal, the first electrode is connected to the first sub-node, and the second electrode is connected to the second sub-node.

[0027] In some embodiments, the input sub-circuit includes a first transistor;

[0028] The control electrode of the first transistor is connected to the first level signal terminal, the first electrode is connected to the signal input terminal, and the second electrode is connected to the first node.

[0029] In some embodiments, the output sub-circuit includes a fifth transistor and a second capacitor;

[0030] The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second clock signal terminal; the first electrode of the second capacitor is connected to the control electrode of the fifth transistor, and the second electrode is connected to the first electrode of the fifth transistor.

[0031] In some embodiments, the holding sub-circuit includes a fourth transistor and a third capacitor;

[0032] The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first invalid working level signal terminal, and the second electrode is connected to the signal output terminal; the first electrode of the third capacitor is connected to the control electrode of the fourth transistor, and the second electrode is connected to the first electrode of the fourth transistor.

[0033] This disclosure also provides a driving method for driving a shift register, wherein the driving method includes:

[0034] During the input phase, a first clock signal, an input signal, and a third clock signal are provided to the shift register. The input signal is transmitted to the first node through the input sub-circuit, and the third clock signal controls the potential of the second node to be at an invalid level. The first node is the connection node between the input sub-circuit and the output sub-circuit, and the second node is the connection node between the first control sub-circuit and the holding sub-circuit.

[0035] During the output phase, a second clock signal is provided to the shift register, and the second clock signal is transmitted to the signal output terminal through the output sub-circuit.

[0036] During the reset phase, a third clock signal and a first invalid working level signal are provided to the shift register. The third clock signal controls the potential of the second node to be at an active level, and the first invalid working level signal is transmitted to the signal output terminal through the holding sub-circuit.

[0037] In some embodiments, within a working cycle, the start time of the effective level of the second clock signal is not earlier than the end time of the effective level of the first clock signal.

[0038] This disclosure also provides a gate drive circuit including a plurality of cascaded shift registers;

[0039] For the gate drive circuit, the i-th shift register and the (i+4)-th shift register are connected to the same clock signal line; i is a positive integer.

[0040] In some embodiments, the gate driving circuit is connected to four clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line; the start times of the effective levels of the four clock signals on the four clock signal lines are sequentially 1H apart, where H is the unit scan time;

[0041] The shift register is configured with a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal that respectively receive the first clock signal, the second clock signal, and the third clock signal; the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the shift register are respectively connected to three different clock signal lines;

[0042] The shift registers are cascaded in groups of four. For each group of shift registers, the first clock signal terminal of the first-stage shift register is connected to the first clock signal line, the second clock signal terminal is connected to the second clock signal line, and the third clock signal terminal is connected to the third clock signal line; the first clock signal terminal of the second-stage shift register is connected to the second clock signal line, the second clock signal terminal is connected to the third clock signal line, and the third clock signal terminal is connected to the fourth clock signal line; the first clock signal terminal of the fourth-stage shift register is connected to the fourth clock signal line, the second clock signal terminal is connected to the first clock signal line, and the third clock signal terminal is connected to the second clock signal line.

[0043] This disclosure also provides a display panel divided into a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of pixel units arranged in an array, and the peripheral area is provided with the aforementioned gate driving circuit; each of the shift registers in the gate driving circuit is configured to provide a gate driving signal to a row of pixel units. Attached Figure Description

[0044] Figure 1a is a block diagram of an existing shift register.

[0045] Figure 1b is a circuit diagram of the shift register in Figure 1a.

[0046] Figure 1c is the timing diagram of the shift register in Figure 1b.

[0047] Figure 2a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0048] Figure 2b is a circuit diagram of the shift register in Figure 2a.

[0049] Figure 3a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0050] Figure 3b is a circuit diagram of the shift register in Figure 3a.

[0051] Figure 4a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0052] Figure 4b is a circuit diagram of the shift register in Figure 4a.

[0053] Figure 5a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0054] Figure 5b is a circuit diagram of the shift register in Figure 5a.

[0055] Figure 6a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0056] Figure 6b is a circuit diagram of the shift register in Figure 6a.

[0057] Figure 7a is a structural block diagram of a shift register provided in an embodiment of this disclosure.

[0058] Figure 7b is a circuit diagram of the shift register in Figure 7a.

[0059] Figure 8 is the timing diagram of the shift register in Figure 7b.

[0060] Figure 9 is a circuit cascade diagram of a gate drive circuit provided in an embodiment of this disclosure.

[0061] Figure 10 is a timing diagram of the gate drive circuit in Figure 9.

[0062] Figure 11 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0063] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0065] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0066] The transistors used in this embodiment can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In this embodiment, to distinguish the source and drain of the transistor, one is called the first terminal, the other the second terminal, and the gate is called the control terminal. Furthermore, the transistors in this embodiment are all P-type transistors. The control terminal is the gate of the P-type transistor, the first terminal is the source of the P-type transistor, and the second terminal is the drain of the P-type transistor. When a low-level signal is input to the gate, the P-type transistor is turned on. Therefore, for a P-type transistor, both the working level signal and the effective level signal are low-level signals, while both the invalid working level signal and the invalid level signal are high-level signals. Here, the difference between an invalid working level signal and an invalid level signal is that an invalid working level signal refers to a high-level signal with a constant level, such as VGH1, VGH2, etc. An invalid level signal refers to a high level in a signal with a changing level; for example, a high level in the CLK signal is an invalid level signal, and a low level is an effective level signal. The magnitudes of the invalid operating level signal and the invalid level signal can be equal or unequal. Alternatively, all transistors in this disclosure can be N-type transistors, in which case both the operating level signal and the active level signal are high-level signals, and both the invalid operating level signal and the invalid level signal are low-level signals. This disclosure does not impose any limitations on this; the following description uses only P-type transistors as an example to illustrate the shift register of this disclosure.

[0067] Figure 1a is a circuit diagram of a conventional shift register. Referring to Figure 1a, the shift register includes an input sub-circuit 01, an output sub-circuit 02, a first control sub-circuit 03, and a holding sub-circuit 04. The connection node between the input sub-circuit 01, the output sub-circuit 02, and the first control sub-circuit 03 is the first node P1, and the connection node between the first control sub-circuit 03 and the holding sub-circuit 04 is the second node P2.

[0068] Specifically, referring to Figure 1b, the input sub-circuit 01 includes a first transistor T1, whose gate is connected to the first clock signal terminal CK, its source is connected to the input signal terminal STV, and its drain is connected to the first node P1. When the first clock signal is low, the first transistor T1 is turned on, and the input signal is transmitted to the first node P1 through the first transistor. The output sub-circuit 02 includes a second transistor T2 and a capacitor C1. The gate of the second transistor T2 is connected to the first node P1, its source is used as the signal output terminal OUT, and its drain is connected to the second clock signal terminal CB. The two terminals of the first capacitor C1 are connected to the gate and source of the second transistor T2, respectively. When the potential of the first node P1 is low, the second transistor T2 is turned on, and the second clock signal is transmitted to the signal output terminal OUT through the second transistor T2. The first capacitor C1 can act as an energy storage element, controlling the potential of the first node P1 through capacitive coupling. The first control sub-circuit 03 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a second capacitor C2. The gates of both the third transistor T3 and the fourth transistor T4 are connected to the first node P1, and their drains are both connected to the invalid operating level signal terminal VGH. The source of the third transistor T3 is connected to the gate of the fifth transistor T5, and the source of the fourth transistor T4 is connected to the second node P2. The source of the fifth transistor T5 is connected to the second clock signal terminal CB, and its drain is connected to the second node P2. The two terminals of the second capacitor C2 are connected to the gate and source of the fifth transistor T5, respectively. When the potential of the first node P1 is low, both the third transistor T3 and the fourth transistor T4 are turned on. The invalid operating level signal turns off the fifth transistor T5 through the third transistor T3 and pulls the second node P2 high through the fourth transistor T4. When the potential of the first node P1 is high, both the third transistor T3 and the fourth transistor T4 are turned off. If the second clock signal is low at this time, the low-level signal can turn on the fifth transistor T5 and transmit the signal to the second node P2 through the fifth transistor T5. The holding sub-circuit 04 includes a sixth transistor T6 and a third capacitor C3. The gate of the sixth transistor T6 is connected to the second node P2, the source is connected to the invalid working level signal terminal VGH, and the drain is connected to the source of the second transistor T2, serving as the signal output terminal OUT. The third capacitor C3 can act as an energy storage element, controlling the potential of the second node P2 through capacitive coupling. When the potential of the second node P2 is a low level signal, the sixth transistor T6 is turned on, and the invalid working level signal is output to the signal output terminal OUT through the sixth transistor T6.

[0069] It should be noted that the first clock signal and the second clock signal in the above circuit are inverted signals. Figure 1c is the timing diagram of the above shift register. Referring to Figure 1c, the above shift register can include the following four operating stages.

[0070] In the first stage (S1), a low-level signal is written to the input signal terminal STV, a low-level signal is written to the first clock signal terminal CK, and a high-level signal is written to the second clock signal terminal CB. The first transistor T1 is turned on, and the input signal is transmitted to the first node P1 through T1, pulling the potential of the first node P1 low. The second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on. The invalid operating level signal VGH is turned off by the third transistor T3, and the potential of the fifth transistor T5 is pulled high by the fourth transistor T4. The high-level signal written to the second clock signal terminal CB is transmitted to the signal output terminal OUT through the second transistor T2 for output.

[0071] In the second stage S2, a high-level signal is written to the input signal terminal STV, a high-level signal is written to the first clock signal terminal CK, and a low-level signal is written to the second clock signal terminal CB. The first transistor T1 is turned off, and the first node P1 continues to maintain a low-level signal due to the coupling effect of the first capacitor C1. The second transistor T2, the third transistor T3, and the fourth transistor T4 remain on. The low-level signal written to the second clock signal terminal CB is transmitted to the signal output terminal OUT through the second transistor T2 for output.

[0072] In the third stage, a high-level signal is written to the input signal terminal STV, a low-level signal is written to the first clock signal terminal CK, and a high-level signal is written to the second clock signal terminal CB. The first transistor T1 is turned on, and the high-level signal written to the input signal terminal STV is transmitted to the first node P1 through the first transistor T1, raising the potential of the first node P1. The second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off. The fifth transistor T5 is turned on by the low-level signal written to the first clock signal terminal CK. This low-level signal is transmitted to the second node P2 through the fifth transistor T5, lowering the potential of the second node P2. The sixth transistor T6 is turned on, and the high-level signal written to the invalid working level signal terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6 for output.

[0073] In the fourth stage, a high-level signal is written to the input signal terminal STV, a high-level signal is written to the first clock signal terminal CK, and a low-level signal is written to the second clock signal terminal CB. The first transistor T1 remains off, and the potential of the first node P1 continues to be high due to the coupling effect of the first capacitor C1. The second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off. The high-level signal written to the first clock signal terminal CK turns off the third transistor T3. The potential of the second node P2 continues to be low due to the coupling effect of the third capacitor C3. The sixth transistor T6 remains on, and the high-level signal written to the invalid working level signal terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6.

[0074] In the third stage (S3) and the fourth stage (S4) described above, the potential of the first node P1 is a high-level signal. Because the second transistor T2 has a large aspect ratio, its gate-drain capacitance Cgs and Miller capacitance Cgd are also large. When the signal written to the second clock signal terminal CB changes from high to low, the low-level signal will couple and pull the first node P1 low, causing the third transistor T3 and the fourth transistor T4 to partially turn on, further interfering with the potential of the second node P2 and affecting the output.

[0075] Based on the above problems, this disclosure provides a shift register. Figure 2a is a schematic diagram of the shift register structure, and Figure 8 is a timing diagram of the shift register operation. Referring to Figures 2a and 8, the shift register has three operating stages: input stage T1, output stage T2, and reset stage T3. Specifically, referring to Figure 2a, the shift register includes an input sub-circuit 1, an output sub-circuit 2, a first control sub-circuit 3, and a holding sub-circuit 4. The connection node between the input sub-circuit 1 and the output sub-circuit 2 is the first node N1, and the connection node between the first control sub-circuit 3 and the holding sub-circuit 4 is the second node N2. The input sub-circuit 1 is configured to transmit an input signal to the first node N1 in response to a first clock signal during the input stage T1. The output sub-circuit 2 is configured to output a second clock signal through the signal output terminal OUT in response to the potential of the first node N1 during the output stage T2. The first control sub-circuit 3 is configured to control the potential of the second node N2 in response to the input signal and the third clock signal during the input stage T1 and the reset stage T3, using the third clock signal. The holding sub-circuit 4 is configured to output a first invalid operating level signal through the signal output terminal OUT in response to the potential of the second node N2 during the reset phase T3. It should be noted that within one operating cycle of the shift register (i.e., the input, output, and reset phases), the start time of the effective level of the second clock signal is no earlier than the end time of the effective level of the first clock signal. In other words, the effective levels of the second and first clock signals do not overlap. Therefore, when the second clock signal is low, pulling down the potential of the first node N1, since the first clock signal is high at this time, the first transistor T1 will not be turned on, and the pulled-down potential of the first node N1 will not affect the potential of the second node N2. Therefore, the shift register disclosed herein has high reliability, and its application in AMOLED display panels can effectively improve product yield.

[0076] Figure 2b is a detailed circuit diagram of the shift register in Figure 2a. Referring to Figure 2b, the input sub-circuit 1 includes a first transistor T1, wherein the gate of the first transistor T1 is connected to the first clock signal terminal CK1, the source is connected to the input signal terminal INPUT, and the drain is connected to the first node N1. For example, the input signal written to the input signal terminal INPUT can be an STV signal. The output sub-circuit 2 includes a fifth transistor T5 and a second capacitor C2, wherein the gate of the fifth transistor T5 is connected to the first node N1, the source is connected to the signal output terminal OUT, and the drain is connected to the second clock signal terminal CB. The two terminals of the second capacitor C2 are connected to the gate and source of the fifth transistor T5, respectively. The first control sub-circuit 3 includes a second transistor T2, a third transistor T3, and a second capacitor C2. The gate of the second transistor T2 is connected to the input signal terminal INPUT, its source is connected to the gate of the third transistor T3, and its drain is connected to the second invalid operating level signal terminal VGH2. The source of the third transistor T3 is connected to the third clock signal terminal CK3, and its drain is connected to the second node N2. The two terminals of the first capacitor C1 are connected to the gate and source of the third transistor T3, respectively. The holding sub-circuit 4 includes a fourth transistor T4 and a third capacitor C3. The gate of the fourth transistor T4 is connected to the second node N2, its source is connected to the first invalid operating level signal terminal VGH1, and its drain is connected to the signal output terminal OUT. The two terminals of the third capacitor C3 are connected to the gate and source of the fourth transistor T4, respectively. The first invalid operating level signal is less than or equal to the second invalid operating level signal.

[0077] Referring again to Figure 2b, in the input phase T1, the first transistor T1 is turned on by the first clock signal, and the input signal is transmitted to the first node N1 through the first transistor T1, pulling down the potential of the first node N1. Then, in the output phase T2, the fifth transistor T5 is turned on by the low potential of the first node N1, and the second clock signal is transmitted to the signal output terminal OUT through the fifth transistor T5. In the input phase T1, the second transistor T2 is turned on by the input signal, and the second invalid operating level signal is transmitted to the gate of the third transistor T3 through the second transistor T2, turning off the third transistor T3. In the reset phase T3, the second transistor T2 is turned off by the input signal. At this time, the third transistor T3 is turned on by the third clock signal, and the third clock signal is transmitted to the second node N2 through the third transistor T3, pulling down the potential of the second node N2. Then, in the reset phase T3, the fourth transistor T4 is turned on by the low potential of the second node N2, and the first invalid operating level signal is output through the fourth transistor T4.

[0078] In some examples, referring to Figure 3a, the shift register of this disclosure further includes a first pull-up sub-circuit 5, which is configured to pull up the first node N1 via a second invalid working level signal in response to the third clock signal and the potential of the second node N2 during the reset phase T3. It should be noted that within one operating cycle, the start time of the effective level of the third clock signal is not earlier than the end time of the effective level of the second clock signal. This ensures that when the output sub-circuit 2 outputs the effective level of the second clock signal, the third clock signal becoming effective will not interfere with the potentials of the second node N2 and the first node N1, further affecting the output. Specifically, referring to Figure 3b, the first pull-up sub-circuit 5 includes a sixth transistor T6 and a seventh transistor T7. The gate of the sixth transistor T6 is connected to the second node N2, the source is connected to the second invalid working level signal terminal VGH2, and the drain is connected to the source of the seventh transistor T7. The gate of the seventh transistor T7 is connected to the third clock signal terminal, and the drain is connected to the first node N1. During the reset phase T3, the sixth transistor T6 is turned on by the low potential of the second node N2, and the seventh transistor T7 is turned on by the effective level of the third clock signal. The second invalid working level signal is transmitted to the first node N1 through the sixth transistor T6 and the seventh transistor T7, pulling up the potential of the first node N1 and controlling the output sub-circuit 4 to stop outputting the second clock signal.

[0079] In some examples, referring to FIG4a, the shift register of this disclosure further includes a second pull-up circuit 6, which is configured to pull up the second node N2 in response to the potential of the first node N1 during input phase T1 and output phase T2 via a second invalid operating level signal. The second invalid operating level signal is greater than or equal to the first invalid operating level signal. Specifically, referring to FIG4b, the second pull-up circuit 6 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the second invalid operating level signal terminal VGH2. During input phase T1 and output phase T2, the potential of the first node N1 remains low. The ninth transistor T9 is turned on by the low level of the first node N1, and the second invalid operating level signal is transmitted to the second node N2 through the ninth transistor T9, pulling up the potential of the second node N2 to prevent the first node N1 and the second node N2 from simultaneously being at low potentials, thus affecting the output. Here, the second invalid operating level signal is transmitted to the second node N2, and further transmitted to the gate of the fourth transistor T4. Since the gate voltage of the fourth transistor T4 (i.e. the second invalid operating level signal) is greater than or equal to the source voltage of the fourth transistor T4 (i.e. the first invalid operating level signal), the fourth transistor T4 can be guaranteed to be absolutely turned off, thereby ensuring that the output of the output sub-circuit 4 is not affected.

[0080] In some examples, referring to FIG5a, the shift register of this disclosure further includes a voltage stabilizing sub-circuit 7 connected between the input sub-circuit 1 and the output sub-circuit 2. The connection node between the voltage stabilizing sub-circuit 7 and the input sub-circuit 1 is the first sub-node N1-1, and the connection node between the voltage stabilizing sub-circuit 7 and the output sub-circuit 2 is the second sub-node N1-2. The voltage stabilizing sub-circuit 7 is configured to transfer the voltage of the first sub-node N1-1 to the second sub-node N1-2 in response to an operating level signal. Specifically, referring to FIG5b, the voltage stabilizing sub-circuit 7 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the operating level signal terminal VGL, the source is connected to the first sub-node N1-1, and the drain is connected to the second sub-node N1-2. The eighth transistor T8 is normally open throughout the entire operating cycle of the shift register. By setting the eighth transistor T8, leakage current through the first transistor T1 to the second sub-node N1-2 can be avoided, thereby controlling the voltage of the second sub-node N1-2 to be in a stable state, and further controlling the fifth transistor T5 to be in a stable on or off state.

[0081] In some examples, referring to FIG6a, the shift register of this disclosure further includes a protection sub-circuit 8, which is configured to transmit a second invalid working level signal to the first node N1 in response to a working level signal during the input phase T1. Specifically, referring to FIG6b, the protection sub-circuit 8 includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the working level signal terminal VEL, the source is connected to the first node N1, and the drain is connected to the second invalid working level signal terminal VGH2. Before the input phase T1, that is, at the moment of power-on of the display panel, the second invalid working level signal is transmitted to the first node N1 through the tenth transistor T10, pulling up the potential of the first node N1, ensuring that the fifth transistor T5 is in the off state, thereby ensuring that the signal output at the signal output terminal OUT is a high-level signal and avoiding power-on screen flickering.

[0082] To describe the shift register of this disclosure in more detail, a specific embodiment is given below. Referring to FIG7a, the shift register includes an input sub-circuit 1, an output sub-circuit 2, a first control sub-circuit 3, a holding sub-circuit 4, a first pull-up sub-circuit 5, a second pull-up sub-circuit 6, a voltage stabilization sub-circuit 7, and a protection sub-circuit 8. The connection node of the input sub-circuit 1, the first pull-up sub-circuit 5, the second pull-up sub-circuit 6, the voltage stabilization sub-circuit 7, and the protection sub-circuit 8 is the first sub-node N1-1; the connection node of the output sub-circuit 2 and the protection sub-circuit 8 is the second sub-node N1-2; and the connection node of the first control sub-circuit 3, the first pull-up sub-circuit 5, the second pull-up sub-circuit 6, and the holding sub-circuit 4 is the second node N2.

[0083] Specifically, referring to Figure 7b, the input sub-circuit 1 includes a first transistor T1, whose gate is connected to the first clock signal terminal CK1, its source is connected to the input signal terminal INPUT, and its drain is connected to the first sub-node N1-1. The output sub-circuit 2 includes a fifth transistor T5 and a second capacitor C2. The gate of the fifth transistor T5 is connected to the second sub-node N1-2, its source is connected to the signal output terminal OUT, and its drain is connected to the second clock signal terminal CK2. The two terminals of the second capacitor C2 are connected to the gate and source of the fifth transistor T5, respectively. The first control sub-circuit 3 includes a second transistor T2, a third transistor T3, and a first capacitor C1. The gate of the second transistor T2 is connected to the input signal terminal INPUT, its source is connected to the gate of the third transistor T3, and its drain is connected to the second invalid working level signal terminal VGH2. The source of the third transistor T3 is connected to the third clock signal terminal CK3, and its drain is connected to the second node N2. The two terminals of the first capacitor C1 are connected to the gate and source of the third transistor T3, respectively. The holding sub-circuit 4 includes a fourth transistor T4 and a third capacitor C3. The gate of the fourth transistor T4 is connected to the second node N2, the source is connected to the first invalid working level signal terminal VGH1, and the drain is connected to the signal output terminal OUT. The two terminals of the third capacitor C3 are connected to the source and gate of the fourth transistor T4, respectively. The first pull-up sub-circuit 5 includes a sixth transistor T6 and a seventh transistor T7. The gate of the sixth transistor T6 is connected to the second node N2, the source is connected to the second invalid working level signal terminal VGH2, and the drain is connected to the source of the seventh transistor T7. The gate of the seventh transistor T7 is connected to the third clock signal terminal CK3, and the drain is connected to the first sub-node N1-1. The second pull-up sub-circuit 6 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the first sub-node N1-1, the source is connected to the second node N2, and the drain is connected to the second invalid working level signal terminal VGH2. The voltage stabilizing sub-circuit 7 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the working level signal terminal VGL, the source is connected to the first sub-node N1-1, and the drain is connected to the second sub-node N1-2. The protection sub-circuit includes the tenth transistor T10. The gate of the tenth transistor T10 is connected to the protection level signal terminal VEL, the source is connected to the first sub-node N1-1, and the drain is connected to the second invalid working level signal terminal VGH2.

[0084] Figure 8 shows the circuit timing diagram corresponding to the shift register in Figure 7b. Referring to Figure 8, the working stages of the shift register include: input stage T1, output stage T2, and reset stage T3. It should be noted that before the shift register starts working, i.e., before input stage T1, that is, at the instant the display panel is powered on, a low-level signal is written to the protection level signal terminal VEL to turn on the tenth transistor. The second invalid working level signal is transmitted to the first sub-node N1-1 through the tenth transistor T10, pulling up the potential of the first sub-node N1-1 and the second sub-node N1-2, ensuring that the fifth transistor T5 is in the off state. This ensures that the signal output terminal OUT is a high-level signal, i.e., an invalid working level signal, avoiding power-on screen flickering. The working process of each stage of the shift register is as follows:

[0085] During input phase T1, a low-level signal is written to the input signal terminal INPUT, a low-level signal is written to the first clock signal terminal CK1, a high-level signal is written to the second clock signal terminal CK2, and a high-level signal is written to the third clock signal terminal CK3. The first transistor T1 and the second transistor T2 are turned on. The low-level signal written to the input signal terminal INPUT is transmitted to the first sub-node N1-1 through the first transistor T1, pulling down the potentials of the first sub-node N1-1 and the second sub-node N1-2. The fifth transistor T5 is turned on, and the high-level signal written to the second clock signal terminal CK2 is transmitted to the signal output terminal OUT through the fifth transistor T5 for output. Simultaneously, a second invalid working level signal is transmitted to the gate of the third transistor T3 through the second transistor T2, turning off the third transistor T3. Since the first sub-node N1-1 is a low-level signal, the ninth transistor T9 is turned on. The second invalid working level signal is transmitted to the second node N2 through the ninth transistor T9, pulling up the potential of the second node N2 and turning off the fourth transistor T4.

[0086] In output phase T2, a high-level signal is written to the input signal terminal INPUT, a high-level signal is written to the first clock signal terminal CK1, a low-level signal is written to the second clock signal terminal CK2, and a high-level signal is written to the third clock signal terminal CK3. The first transistor T1 and the second transistor T2 are turned off by the high-level signal written to the input signal terminal INPUT, and the third transistor T3 is turned off by the low-level signal written to the third clock signal terminal CK3. That is, there is no signal input to the shift register in output phase T2. Due to the coupling effect of the second capacitor C2 and the third capacitor C3, the first sub-node N1-1 and the second sub-node N1-2 remain at a low potential, while the second node N2 remains at a high potential. The high potential of the second sub-node N1-2 turns on the fifth transistor T5, and the low-level signal written to the second clock signal terminal CK2 is transmitted to the signal output terminal OUT through the fifth transistor T5.

[0087] During the reset phase T3, a high-level signal is written to the input signal terminal INPUT, a high-level signal is written to the first clock signal terminal CK1, a high-level signal is written to the second clock signal terminal CK2, and a low-level signal is written to the third clock signal terminal CK3. The first transistor T1 and the second transistor T2 remain off. The third transistor T3 is turned on by the low-level signal written to the third clock signal terminal CK3, and the third clock signal is transmitted to the second node N2 through the third transistor T3, pulling down the potential of the second node N2. The fourth transistor T4 and the sixth transistor T6 are both turned on by the low potential of the second node N2, and the first invalid working level signal VGH1 is transmitted to the signal output terminal OUT through the fourth transistor T4. Simultaneously, the low-level signal written to the third clock signal terminal CK3 turns on the seventh transistor T7. Therefore, the second invalid working level signal VGH2 is transmitted sequentially to the first sub-node N1-1 through the sixth transistor T6 and the seventh transistor T7, pulling up the potentials of the first sub-node N1-1 and the second sub-node N1-2, turning off the fifth transistor T5, and preparing for the next working phase.

[0088] Specifically, the start time of the effective level of the second clock signal is no earlier than the end time of the effective level of the first clock signal, and the start time of the effective level of the third clock signal is no earlier than the end time of the effective level of the second clock signal. In other words, the durations of the effective levels of the first, second, and third clock signals do not overlap. This avoids the possibility of transistors turning on erroneously during operation, thereby improving the reliability of the circuit.

[0089] This disclosure also provides a method for driving the above-mentioned pixel driving circuit, the driving method including the following steps S1-S3.

[0090] Step S1: In the input stage T1, a first clock signal is provided to the first clock signal terminal CK1 of the shift register, an input signal STV is provided to the input signal terminal INPUT, and a third clock signal is provided to the third clock signal terminal CK3. The input signal STV is transmitted to the first node N1 through the input sub-circuit 1. The third clock signal controls the potential of the second node N2 to be invalid and turns off the holding sub-circuit 4.

[0091] In some embodiments, the pixel driving circuit includes a voltage stabilizing sub-circuit 7. The first node N1 is divided into a first sub-node N1-1 and a second sub-node N1-2. The first sub-node N1-1 is the connection node between the input sub-circuit and the voltage holding sub-circuit 7, and the second sub-node N1-2 is the connection node between the voltage holding sub-circuit 7 and the output sub-circuit 2. At this time, the input signal STV is transmitted sequentially to the first sub-node N1-1 and the second sub-node N1-2 through the input sub-circuit 1.

[0092] Step S2: In the output stage T2, a second clock signal is provided to the second clock signal terminal CK2 of the shift register. The second clock signal is transmitted to the signal output terminal OUT through the output sub-circuit 2.

[0093] Step S3: During the reset phase T3, a third clock signal is provided to the third clock signal terminal CK3 of the shift register, and a first invalid working level signal is provided to the first invalid working level signal terminal VGH1. The third clock signal controls the potential of the second node N2 to be at an effective level, and the first invalid working level signal is transmitted to the signal output terminal OUT through the holding sub-circuit 4.

[0094] In some examples, the driving method also includes providing a protection level signal to the protection level signal terminal VEL of the shift register and a second invalid working level signal to the second invalid working level signal terminal VGH2 before the input stage T1, so as to ensure that the signal output terminal OUT outputs an invalid level signal and avoids power-on screen flickering.

[0095] This disclosure also provides a gate driving circuit, which includes multiple cascaded shift registers from any of the above embodiments. A schematic diagram of the gate driving circuit is shown in Figure 9. For the i-th shift register, its signal output terminal OUT is connected to the input signal terminal INPUT of the (i+1)-th shift register, where i is a positive integer.

[0096] Referring to Figure 9-10, the gate drive circuit is connected to four clock signal lines: the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4. The clock signals transmitted on these four lines are square wave signals with the same period and duty cycle, and the duty cycle of the square wave signal is less than 25%. Within one cycle of the square wave, the start times (falling edges) of the four clock signals differ sequentially by 1H, where H is the unit scan time.

[0097] Referring again to Figure 9, for the multiple cascaded shift registers in the gate drive circuit, each shift register is configured with a first clock signal terminal CK1 for receiving the first clock signal, a second clock signal terminal CK2 for receiving the second clock signal, and a third clock signal terminal CK3 for receiving the third clock signal. The first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 are each connected to three different clock signal lines. That is, each shift register is connected to three of the four clock signal lines: the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4. For the gate drive circuit, the i-th shift register is connected to the same three clock signal lines as the (i+4)-th shift register, where i is a positive integer. For example, the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 of the first shift register are connected to the first clock signal line CLK1, the second clock signal line CLK2, and the third clock signal line CLK3, respectively. The first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 of the fifth shift register, the ninth shift register, the thirteenth shift register, and the (4a+1)th shift register are also connected to the first clock signal line CLK1, the second clock signal line CLK2, and the third clock signal line CLK3, respectively; a is an integer greater than or equal to 0.

[0098] Optionally, each cascaded group of four shift registers is formed, and the four shift registers in the same group are connected to three different clock signal lines. Specifically, referring to Figure 9, taking the first to fourth stage shift registers GOA1-GOA4 as an example, the first clock signal terminal CK1 of the first stage shift register GOA1 is connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the first stage shift register GOA1 is connected to the second clock signal line CLK2, and the third clock signal terminal CK3 of the first stage shift register GOA1 is connected to the third clock signal line CLK3; the first clock signal terminal CK1 of the second stage shift register GOA2 is connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the second stage shift register GOA2 is connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the second stage shift register GOA2 is connected to the third clock signal line CLK3. CK3 is connected to the fourth clock signal line CLK4; the first clock signal terminal CK1 of the third-stage shift register GOA3 is connected to the third clock signal line CLK3, the second clock signal terminal CK2 of the third-stage shift register GOA3 is connected to the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the third-stage shift register GOA3 is connected to the first clock signal line CLK1; the first clock signal terminal CK1 of the fourth-stage shift register GOA4 is connected to the fourth clock signal line CLK4, the second clock signal terminal CK2 of the fourth-stage shift register GOA4 is connected to the first clock signal line CLK1, and the third clock signal terminal CK3 of the fourth-stage shift register GOA4 is connected to the second clock signal line CLK2. Thus, the four cascaded shift registers sequentially output the first gate drive signal, the second gate drive signal, the third gate drive signal, and the fourth gate drive signal, with the start times of the effective levels of the four gate drive signals differing by 1H sequentially. After the first-stage shift register GOA1 outputs the first gate drive signal, this signal is used not only to drive the corresponding row of pixel units to emit light, but also as the input signal for the second-stage shift register GOA2, driving GOA2 to output its own signal; and so on. Each shift register operates sequentially, outputting gate drive signals to drive the corresponding pixel units to emit light and to activate the next-stage shift register.

[0099] This disclosure also provides a display panel. Referring to FIG11, the display panel is divided into a display area and a peripheral area surrounding the display area. Multiple pixel units P arranged in an array are disposed in the display area. The peripheral area is disposed of a gate driving circuit GOA and a source driving circuit IC for driving the pixel units P to emit light, as well as a timing controller Tcon that provides a clock signal CLK to the gate driving circuit GOA. The gate driving circuit GOA provides a gate driving signal to the pixel units P through a gate line (Gate), and the source driving circuit IC provides a data signal to the pixel units through a data line (Date). The pixel unit P includes a pixel driving circuit and a light-emitting device. After receiving the gate driving signal and the data signal, the pixel driving circuit starts working and drives the light-emitting device to emit light. The gate driving circuit includes multiple cascaded shift registers as described in the above embodiments, each shift register being configured to provide a gate driving signal to a row of pixel units.

[0100] In some examples, the display panel may include any product or component with a display function, such as a flexible wearable device, mobile phone, tablet computer, television set, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display are as would be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0101] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising an input sub-circuit, an output sub-circuit, a first control sub-circuit, and a holding sub-circuit; wherein, The input sub-circuit is configured to transmit an input signal to a first node in response to a first clock signal; the first node is the connection node between the input sub-circuit and the output sub-circuit. The output sub-circuit is configured to output a second clock signal through a signal output terminal in response to the potential of the first node; The first control sub-circuit is configured to control the potential of the second node in response to the input signal and the third clock signal; The second node is the connection node between the first control sub-circuit and the holding sub-circuit; The holding sub-circuit is configured to output a first invalid operating level signal through the signal output terminal in response to the potential of the second node.

2. The shift register of claim 1, wherein, The first control sub-circuit includes a second transistor, a third transistor, and a first capacitor; The control electrode of the second transistor is connected to the signal input terminal, the first electrode is connected to the control electrode of the third transistor, and the second electrode is connected to the second invalid working level signal terminal. The second invalid operating level signal is greater than or equal to the first invalid operating level signal; The control electrode of the third transistor is connected to the first electrode of the second transistor and the first electrode of the first capacitor. The first electrode is connected to the second electrode of the first capacitor and the third clock signal terminal. The second electrode is connected to the second node.

3. The shift register of claim 1, wherein, The shift register also includes a first pull-up sub-circuit; The first pull-up sub-circuit is configured to pull up the first node via a second invalid operating level signal in response to the third clock signal and the potential of the second node; The second invalid operating level signal is greater than or equal to the first invalid operating level signal.

4. The shift register of claim 3, wherein, The first pull-up sub-circuit includes a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is connected to the second node, the first electrode is connected to the second invalid working level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the third clock signal terminal, and the second electrode is connected to the first node.

5. The shift register of claim 1, wherein, The shift register also includes a second pull-up sub-circuit; The second pull-up sub-circuit is configured to pull up the second node via a second invalid operating level signal in response to the potential of the first node; The second invalid operating level signal is greater than or equal to the first invalid operating level signal.

6. The shift register of claim 5, wherein, The second pull-up circuit includes a ninth transistor; The control electrode of the ninth transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the second invalid working level signal terminal.

7. The shift register of claim 1, wherein, The shift register also includes a protection sub-circuit; The protection sub-circuit is configured to transmit a second invalid operating level signal to the first node in response to a protection level signal; The second invalid operating level signal is greater than or equal to the first invalid operating level signal.

8. The shift register according to claim 7, wherein, The protection sub-circuit includes a tenth transistor; The control electrode of the tenth transistor is connected to the protection level signal terminal, the first electrode is connected to the first node, and the second electrode is connected to the second invalid working level signal terminal.

9. The shift register of claim 1, wherein, The shift register also includes a voltage stabilization sub-circuit; The voltage stabilizing sub-circuit is connected between the input sub-circuit and the output sub-circuit; the connection node between the voltage stabilizing sub-circuit and the input sub-circuit is the first sub-node, and the connection node between the voltage stabilizing sub-circuit and the output sub-circuit is the second sub-node; The voltage stabilizing sub-circuit is configured to transmit the voltage of the first sub-node to the second sub-node in response to an operating level signal.

10. The shift register of claim 9, wherein, The voltage stabilizing sub-circuit includes an eighth transistor; The control electrode of the eighth transistor is connected to the working level signal terminal, the first electrode is connected to the first sub-node, and the second electrode is connected to the second sub-node.

11. The shift register according to claim 1, wherein, The input sub-circuit includes a first transistor; The control electrode of the first transistor is connected to the first level signal terminal, the first electrode is connected to the signal input terminal, and the second electrode is connected to the first node.

12. The shift register of claim 1, wherein, The output sub-circuit includes a fifth transistor and a second capacitor; The control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second clock signal terminal. The first terminal of the second capacitor is connected to the control terminal of the fifth transistor, and the second terminal is connected to the first terminal of the fifth transistor.

13. The shift register of claim 1, wherein, The holding sub-circuit includes a fourth transistor and a third capacitor; The control electrode of the fourth transistor is connected to the second node, the first electrode is connected to the first invalid working level signal terminal, and the second electrode is connected to the signal output terminal; the first electrode of the third capacitor is connected to the control electrode of the fourth transistor, and the second electrode is connected to the first electrode of the fourth transistor.

14. A driving method for the shift register driver as claimed in any one of claims 1 to 13, wherein The driving method includes: During the input phase, a first clock signal, an input signal, and a third clock signal are provided to the shift register. The input signal is transmitted to the first node through the input sub-circuit, and the third clock signal controls the potential of the second node to be at an invalid level. The first node is the connection node between the input sub-circuit and the output sub-circuit, and the second node is the connection node between the first control sub-circuit and the holding sub-circuit. During the output phase, a second clock signal is provided to the shift register, and the second clock signal is transmitted to the signal output terminal through the output sub-circuit. During the reset phase, a third clock signal and a first invalid working level signal are provided to the shift register. The third clock signal controls the potential of the second node to be at an active level, and the first invalid working level signal is transmitted to the signal output terminal through the holding sub-circuit.

15. The driving method according to claim 14, wherein Within one working cycle, the start time of the effective level of the second clock signal is not earlier than the end time of the effective level of the first clock signal.

16. A gate drive circuit comprising a plurality of cascaded shift registers as described in any one of claims 1-13; For the gate drive circuit, the i-th shift register and the (i+4)-th shift register are connected to the same clock signal line; i is a positive integer.

17. The gate drive circuit of claim 16, wherein, The gate drive circuit is connected to four clock signal lines, namely the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line; the start times of the effective levels of the four clock signals on the four clock signal lines are successively 1H apart, where H is the unit scan time; The shift register is configured with a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal that respectively receive the first clock signal, the second clock signal, and the third clock signal; the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the shift register are respectively connected to three different clock signal lines; Each group consists of four cascaded shift registers. For each group of shift registers, the first clock signal terminal of the first-stage shift register is connected to the first clock signal line, the second clock signal terminal is connected to the second clock signal line, and the third clock signal terminal is connected to the third clock signal line. The first clock signal terminal of the second-stage shift register is connected to the second clock signal line, the second clock signal terminal is connected to the third clock signal line, and the third clock signal terminal is connected to the fourth clock signal line. The first clock signal terminal of the third-stage shift register is connected to the third clock signal line, the second clock signal terminal is connected to the fourth clock signal line, and the third clock signal terminal is connected to the first clock signal line. The first clock signal terminal of the fourth-stage shift register is connected to the fourth clock signal line, the second clock signal terminal is connected to the first clock signal line, and the third clock signal terminal is connected to the second clock signal line.

18. A display panel divided into a display area and a peripheral area surrounding the display area; the display area having a plurality of pixel units arranged in an array, and the peripheral area having a gate driving circuit as described in claim 16 or 17; each of the shift registers in the gate driving circuit being configured to provide a gate driving signal to a row of the pixel units.

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