Display panel and display apparatus

Abstract

The present disclosure provides a display panel and a display apparatus. The display panel comprises a base substrate and a plurality of sub-pixels disposed on the base substrate, each sub-pixel comprising a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit comprising a first conductive connection portion, a driving transistor, a sensing transistor, and a storage capacitor. A first electrode plate of the storage capacitor is coupled to a gate of the driving transistor, and a second electrode plate of the storage capacitor is located on the side of the first electrode plate of the storage capacitor facing away from the base substrate. At least a part of the first conductive connection portion is located on the side of the second electrode plate facing away from the base substrate, and the first conductive connection portion is separately coupled to the second electrode plate and a second electrode of the driving transistor by means of a via structure. At least a part of a second electrode of the sensing transistor is located on the side of the first conductive connection portion facing away from the base substrate, and the second electrode of the sensing transistor is coupled to the first conductive connection portion.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411730298.1, filed in China on November 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] With the widespread adoption of AR / VR technology, high PPI display products have become a crucial technology to overcome. However, display products based on glass and PI (polyimide) substrates using thin-film transistor devices can currently only achieve 500-600 PPI, which cannot meet the demands of VR near-eye displays exceeding 1800 PPI. For example, existing display products using LTPS (low-temperature polycrystalline silicon) or LTPO (low-temperature polycrystalline oxide) technology generally employ a 7T1C or 8T1C internal compensation pixel circuit structure. Due to the large number of thin-film transistor devices required, the resolution of this structure is limited to 600 PPI.

[0005] Therefore, how to achieve higher resolution display products has become an urgent technical problem to be solved. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display panel and a display device.

[0007] To achieve the above objectives, this disclosure provides the following technical solution:

[0008] A first aspect of this disclosure provides a display panel, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, wherein each sub-pixel includes a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit includes a first conductive connection portion, a driving transistor, a sensing transistor and a storage capacitor;

[0009] The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is located on the side of the storage capacitor opposite to the substrate.

[0010] At least a portion of the first conductive connection is located on the side of the second electrode plate facing away from the substrate, and the first conductive connection is coupled to the second electrode plate and the second electrode of the driving transistor respectively through a via structure;

[0011] At least a portion of the second electrode of the sensing transistor is located on the side of the first conductive connection that faces away from the substrate, and the second electrode of the sensing transistor is coupled to the first conductive connection.

[0012] Optionally, the second electrode of the driving transistor is located on the side of the driving transistor whose gate faces the substrate, and at least a portion of the orthographic projection of the second electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate.

[0013] The via structure includes a first via and a second via that are connected. The first conductive connection portion is coupled to the second electrode plate through the second via. The first conductive connection portion is coupled to the second electrode of the driving transistor through the second via and the first via.

[0014] Optionally, the first conductive connection includes a first conductive portion and a second conductive portion coupled together. The first conductive portion is located inside the via structure and is coupled to the second electrode and the second electrode of the driving transistor, respectively. The second conductive portion is located outside the via structure and is coupled to the second electrode of the sensing transistor.

[0015] Optionally, the sub-pixel driving circuit further includes a first planarization layer, which is located within the via structure and on the side of the first conductive portion facing away from the substrate.

[0016] The sub-pixel driving circuit further includes a second conductive connection portion, which covers the first planarization layer and is in contact with the second conductive portion;

[0017] At least a portion of the second electrode of the sensing transistor is located on the side of the second conductive connection that faces away from the substrate and is coupled to the second conductive connection.

[0018] Optionally, the orthographic projection of the second conductive portion on the substrate surrounds the orthographic projection of the first conductive portion on the substrate.

[0019] The orthographic projection of the second conductive portion on the substrate is located inside the orthographic projection of the second conductive connection portion on the substrate.

[0020] Optionally, at least a portion of the second electrode of the sensing transistor is in contact with the side of the second conductive connection and the side of the second conductive portion.

[0021] Optionally, the sub-pixel driving circuit further includes a third conductive connection portion, at least a portion of which is located on the side of the second electrode of the sensing transistor facing away from the substrate. The third conductive connection portion is coupled to the second conductive connection portion, the second electrode of the sensing transistor, and the anode of the light-emitting element.

[0022] Optionally, the sub-pixel driving circuit further includes a third conductive connection portion, at least a portion of which is located on the side of the second electrode of the sensing transistor facing away from the substrate. The third conductive connection portion is coupled to the second conductive portion, the second electrode of the sensing transistor, and the anode of the light-emitting element.

[0023] Optionally, the sub-pixel driving circuit further includes a compensation electrode layer and a data writing transistor. The compensation electrode layer is located on the side of the data writing transistor facing away from the substrate. The compensation electrode layer is coupled to the second electrode of the data writing transistor through a third via. The compensation electrode layer is also coupled to the gate of the driving transistor. The orthographic projection of the compensation electrode layer on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate.

[0024] Optionally, at least a portion of the compensation electrode layer is located on the side of the driving transistor facing away from the substrate, and the compensation electrode layer is directly connected to the gate of the driving transistor.

[0025] Optionally, the display panel includes a first gate metal layer and a second gate metal layer sequentially stacked along a direction away from the substrate.

[0026] The gate of the driving transistor is disposed in the same layer and with the same material as the first gate metal layer, the second electrode is disposed in the same layer and with the same material as the second gate metal layer, and at least a portion of the compensation electrode layer is located between the first gate metal layer and the second gate metal layer.

[0027] Optionally, the compensation electrode layer includes an indium tin oxide layer or a metal layer.

[0028] Optionally, the sub-pixel driving circuit further includes a fourth conductive connection portion and a data writing transistor, wherein the fourth conductive connection portion is coupled to the gate of the driving transistor and the second electrode of the data writing transistor, respectively; the fourth conductive connection portion is disposed in the same layer and with the same material as the first conductive connection portion.

[0029] Optionally, the sub-pixel driving circuit further includes a data writing transistor, the gate of which is coupled to the corresponding scan line, the first electrode of which is coupled to the corresponding data line, and the second electrode of which is coupled to the gate of the driving transistor.

[0030] The gate of the sensing transistor is coupled to the corresponding scan line, and the first electrode of the sensing transistor is coupled to the sensing line;

[0031] The first terminal of the driving transistor is coupled to the corresponding power line, and the second terminal of the driving transistor is also coupled to the anode of the light-emitting element.

[0032] The data writing transistor and the driving transistor are low-temperature polycrystalline silicon transistors, and the sensing transistor is an oxide transistor.

[0033] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0035] Figure 1 is a circuit schematic diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0036] Figure 2 is a timing diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0037] Figure 3 is a first cross-sectional schematic diagram of the display panel provided in an embodiment of this disclosure;

[0038] Figure 4 is a second cross-sectional schematic diagram of the display panel provided in an embodiment of this disclosure;

[0039] Figure 5 is a third cross-sectional schematic diagram of the display panel provided in an embodiment of this disclosure;

[0040] Figure 6 is a fourth cross-sectional schematic diagram of the display panel provided in an embodiment of this disclosure;

[0041] Figure 7 is a schematic diagram of the layout of the bottom gate metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0042] Figure 8 is a schematic diagram of the layout of the second source / drain metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0043] Figure 9 is a schematic diagram of the layout of the stacked configuration shown in Figures 7 and 8;

[0044] Figure 10 is a schematic diagram of the layout of the first active layer in the 2*6 array sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0045] Figure 11 is a layout diagram with Figure 10 superimposed on Figure 9;

[0046] Figure 12 is a schematic diagram of the via layout in the first gate insulating layer of the sub-pixel driving circuit distributed in a 2*6 array in the display panel provided in the embodiment of this disclosure;

[0047] Figure 13 is a schematic diagram of the layout of the first gate metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0048] Figure 14 is a layout diagram with Figures 12 and 13 superimposed on Figure 11;

[0049] Figure 15 is a schematic diagram of the layout of the compensation metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0050] Figure 16 is a layout diagram of Figure 15 superimposed on Figure 14;

[0051] Figure 17 is a schematic diagram of the via layout in the second gate insulating layer of the sub-pixel driving circuit distributed in a 2*6 array in the display panel provided in the embodiment of this disclosure;

[0052] Figure 18 is a schematic diagram of the layout of the second gate metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0053] Figure 19 is a layout diagram that overlays Figures 17 and 18 on top of Figure 16;

[0054] Figure 20 is a schematic diagram of the via structure layout in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0055] Figure 21 is a schematic diagram of the layout of the first conductive connection part in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0056] Figure 22 is a schematic diagram of the layout of the first active layer to the first conductive connection portion in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure.

[0057] Figure 23 is a schematic diagram of the layout of the first flattening layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0058] Figure 24 is a schematic diagram of the layout of the second conductive connection portion in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0059] Figure 25 is a layout diagram with Figures 23 and 24 superimposed on Figure 22;

[0060] Figure 26 is a schematic diagram of the layout of the second active layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0061] Figure 27 is a schematic diagram of the layout of the via structure, the first conductive connection part, the first planarization layer, the second conductive connection part and the second active layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of the present disclosure.

[0062] Figure 28 is a schematic diagram of the layout of the third gate metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0063] Figure 29 is a layout diagram with Figure 28 superimposed on Figure 27;

[0064] Figure 30 is a schematic diagram of the layout of the deep hole penetrating the insulating layer between the first source / drain metal layer and the first active layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0065] Figure 31 is a schematic diagram of the layout of shallow holes penetrating the insulating layer between the first source / drain metal layer and the second active layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure.

[0066] Figure 32 is a schematic diagram of the layout of the first source / drain metal layer in the 2*6 array sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0067] Figure 33 is a schematic diagram of the layout of the first active layer to the first source / drain metal layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0068] Figure 34 is a schematic diagram of the layout of the eighth via in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0069] Figure 35 is a schematic diagram of the layout of the third source / drain metal layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0070] Figure 36 is a schematic diagram of the layout of the second active layer to the third source-drain metal layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0071] Figure 37 is a schematic diagram of the layout of vias penetrating the second planarization layer in the sub-pixel driving circuit of a 2*6 array distributed in the display panel provided in the embodiment of this disclosure;

[0072] Figure 38 is a schematic diagram of the layout of vias penetrating the second passivation layer in the sub-pixel driving circuit of a 2*6 array distributed in the display panel provided in the embodiment of this disclosure;

[0073] Figure 39 is a schematic diagram of the layout of the anode layer in the sub-pixel driving circuit of the 2*6 array distribution in the display panel provided in the embodiment of this disclosure;

[0074] Figure 40 is a schematic diagram of the layout of the first source / drain metal layer to the anode layer in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure;

[0075] Figure 41 is a schematic diagram of the layout of the pixel opening area defined by the pixel demarcation layer in the sub-pixel driving circuit of the 2*6 array distributed in the display panel provided in the embodiment of the present disclosure;

[0076] Figure 42 is a schematic diagram of the layout of the first source / drain metal layer to the pixel opening area in the 2*6 array distribution sub-pixel driving circuit of the display panel provided in the embodiment of this disclosure. Detailed Implementation

[0077] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0078] Please refer to Figures 1, 5, 6, 7 to 22. This disclosure provides a display panel, including: a substrate and a plurality of sub-pixels disposed on the substrate. Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a first conductive connection portion 11, a driving transistor M3, a sensing transistor M2 and a storage capacitor Cst.

[0079] The first plate Cst1 of the storage capacitor Cst is coupled to the gate M3-g of the driving transistor M3, and the second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 of the storage capacitor Cst that is away from the substrate.

[0080] At least a portion of the first conductive connection portion 11 is located on the side of the second electrode plate Cst2 facing away from the substrate. The first conductive connection portion 11 is coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through the via structure 20.

[0081] At least a portion of the second electrode M2-2 of the sensing transistor M2 is located on the side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 is coupled to the first conductive connection portion 11.

[0082] It should be noted that the area enclosed by the rectangular boxes in Figures 7 to 42 is the layout area corresponding to a sub-pixel driving circuit.

[0083] For example, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0084] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode (Ano) of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0085] For example, as shown in Figure 1, the sub-pixel driving circuit adopts a 3T1C (i.e., 3 transistors and 1 capacitor) circuit structure. The sub-pixel driving circuit specifically includes a driving transistor M3, a sensing transistor M2, a data writing transistor M1, and a storage capacitor Cst.

[0086] The gate of the data writing transistor M1 is coupled to the corresponding scan line GL, the first terminal M1-1 of the data writing transistor M1 is coupled to the corresponding data line DL, and the second terminal M1-2 of the data writing transistor M1 is coupled to the gate M3-g of the driving transistor M3. As shown in FIG3, the fifth conductive connection portion 15 is coupled to the first terminal M1-1 of the data writing transistor M1 and the corresponding data line DL through the seventh via Via7.

[0087] The gate of the sensing transistor M2 is coupled to the corresponding scan line GL, the first terminal M2-1 of the sensing transistor M2 is coupled to the corresponding sensing line SL, and the second terminal M2-2 of the sensing transistor M2 is coupled to the second terminal M3-2 of the driving transistor M3. As shown in Figure 3, the first terminal M2-1 of the sensing transistor M2 is coupled to the corresponding sensing line SL through the eighth via Via8.

[0088] The first plate Cst1 of the storage capacitor Cst is coupled to the gate M3-g of the driving transistor M3, and the second plate Cst2 of the storage capacitor Cst is coupled to the second terminal M3-2 of the driving transistor M3. The first terminal M3-1 of the driving transistor M3 is coupled to the corresponding power line VDD, and the second terminal M3-2 of the driving transistor M3 is coupled to the anode Ano of the light-emitting element in its sub-pixel. The cathode of the light-emitting element receives the VSS signal. As shown in Figure 3, the first terminal M3-1 of the driving transistor M3 is coupled to the corresponding power line VDD through the ninth via Via9.

[0089] For example, the sensing line SL is coupled to the reference signal line VREF via a first switch S_REF. By controlling the first switch S_REF to close or open, the electrical connection between the sensing line SL and the reference signal line VREF can be controlled. The sensing line SL is also coupled to the sensing signal line SENS via a second switch S_SAMP. By controlling the second switch S_SAMP to close or open, the electrical connection between the sensing line SL and the sensing signal line SENS can be controlled.

[0090] For example, the data writing transistor M1 and the driving transistor M3 are low-temperature polysilicon transistors, such as LTPS NMOS transistors; the sensing transistor M2 is an oxide transistor, such as an Oxide TG NMOS transistor.

[0091] Figure 2 illustrates the driving timing diagram of the sub-pixel driving circuit. The operating timing of the sub-pixel driving circuit includes a display stage and a sensing stage. The display stage specifically includes a reset stage (not shown in the figure), a data writing stage, and a light emission stage; the sensing stage specifically includes a reset stage, a Vth compensation stage, and an extraction stage.

[0092] During the display phase:

[0093] During the reset phase, the scan signal transmitted by the scan line GL controls the sensing transistor M2 to turn on, while the first switch S_REF closes, the second switch S_SAMP opens, and the reference signal transmitted by the reference signal line VREF resets the potential of node N2.

[0094] During the data writing phase, the scan signal transmitted by the scan line GL controls the data writing transistor M1 to turn on, writing the data signal to node N1.

[0095] During the light-emitting stage, the driving transistor M3 is turned on, controlling the light-emitting element to emit light.

[0096] During the sensing phase:

[0097] During the reset phase, the scan signal transmitted by the scan line GL controls the sensing transistor M2 to turn on, while the first switch S_REF closes, the second switch S_SAMP opens, and the reference signal transmitted by the reference signal line VREF resets the potential of node N2.

[0098] During the Vth compensation phase, the sensing transistor M2 remains on to compensate the threshold voltage of the N2 node coupled to the driving transistor M3.

[0099] During the extraction phase, the sensing transistor M2 remains on, while the first switch S_REF is off and the second switch S_SAMP is closed. The driver chip extracts the threshold voltage of the N2 node coupled to the sensing driving transistor M3 in the current time period.

[0100] After Vth is extracted, an algorithm is used to compensate the data signal with the Vth compensation value during the data writing stage to achieve external compensation of Vth.

[0101] For example, the first plate Cst1 of the storage capacitor Cst is formed as an integral structure with the gate M3-g of the driving transistor M3. The second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 of the storage capacitor Cst that is opposite to the substrate, and the orthographic projection of the second plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the first plate Cst1 on the substrate.

[0102] For example, at least a portion of the first conductive connection portion 11 is located on the side of the second electrode plate Cst2 facing away from the substrate. The orthographic projection of the first conductive connection portion 11 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate Cst2 on the substrate. The orthographic projection of the first conductive connection portion 11 on the substrate at least partially overlaps with the orthographic projection of the second electrode M3-2 of the driving transistor M3 on the substrate. The first conductive connection portion 11 is coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 respectively through the via structure 20.

[0103] For example, at least a portion of the second electrode M2-2 of the sensing transistor M2 is located on the side of the first conductive connection portion 11 facing away from the substrate. The second electrode M2-2 of the sensing transistor M2 can be directly connected to the first conductive connection portion 11, but is not limited thereto.

[0104] As can be seen from the specific structure of the display panel described above, the display panel provided in this embodiment includes a first conductive connection portion 11. This first conductive connection portion 11 can be coupled to both the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through a via structure 20. Simultaneously, the second electrode M2-2 of the sensing transistor M2 is disposed on the side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 is coupled to the first conductive connection portion 11. When the display panel adopts the above structure, the first conductive connection portion 11 couples the second electrode plate Cst2 of the storage capacitor Cst, the second electrode M3-2 of the driving transistor M3, and the second electrode M2-2 of the sensing transistor M2 together through a via structure 20. Compared to the prior art, which requires at least two via structures 20 to achieve the above connection relationship, the technical solution of this disclosure effectively reduces the overall layout space occupied by the sub-pixel driving circuit, which is beneficial for the display panel to achieve a higher PPI. The technical solution of this disclosure can achieve a display panel with a PPI of 1500 or higher.

[0105] Please refer to Figures 1, 5, 6, 7 to 22. In some embodiments, the second electrode M3-2 of the driving transistor M3 is located on the side of the gate M3-g of the driving transistor M3 facing the substrate, and at least a portion of the orthographic projection of the second electrode M3-2 of the driving transistor M3 on the substrate does not overlap with the orthographic projection of the second electrode Cst2 on the substrate.

[0106] The via structure 20 includes a first via Via1 and a second via Via2 that are connected to each other. The first conductive connection part 11 is coupled to the second electrode Cst2 through the second via Via2. The first conductive connection part 11 is coupled to the second electrode M3-2 of the driving transistor M3 through the second via Via2 and the first via Via1.

[0107] For example, the first via Via1 is located between the second via Via2 and the substrate, and the diameter of the first via Via1 is smaller than the diameter of the second via Via2.

[0108] The via structure 20 described above includes the first via Via1 and the second via Via2, which helps to simplify the overall layout space occupied by the via structure 20, thereby reducing the layout area of ​​the first conductive connection part 11 and achieving a higher PPI for the display panel.

[0109] Please refer to Figures 1, 5, 6, 7 to 22. In some embodiments, the first conductive connection portion 11 includes a first conductive portion 111 and a second conductive portion 112 coupled together. The first conductive portion 111 is located inside the via structure 20 and is coupled to the second electrode Cst2 and the second electrode M3-2 of the driving transistor M3, respectively. The second conductive portion 112 is located outside the via structure 20 and is coupled to the second electrode M2-2 of the sensing transistor M2.

[0110] For example, the first conductive portion 111 and the second conductive portion 112 are formed as an integral structure.

[0111] For example, the second electrode M2-2 of the sensing transistor M2 can be directly connected to the second conductive portion 112, or it can be electrically connected to the second conductive portion 112 through other conductive connection parts without forming a via.

[0112] The above configuration allows the second electrode M2-2 of the sensing transistor M2 to be coupled to the portion of the first conductive connection 11 located outside the via structure 20, which is beneficial to improving the connection yield between the second electrode M2-2 of the sensing transistor M2 and the first conductive connection 11.

[0113] As shown in Figures 3, 4, and 10 to 29, in some embodiments, the sub-pixel driving circuit further includes a first planarization layer PLN1, which is located within the via structure 20 and on the side of the first conductive portion 111 facing away from the substrate. The sub-pixel driving circuit also includes a second conductive connection portion 12, which covers the first planarization layer PLN1 and is in contact with the second conductive portion 112. At least a portion of the second electrode M2-2 of the sensing transistor M2 is located on the side of the second conductive connection portion 12 facing away from the substrate and is coupled to the second conductive connection portion 12.

[0114] For example, after the first conductive connection portion 11 is fabricated in the via structure 20, a first planarization layer PLN1 is filled in the via structure 20. The first planarization layer PLN1 fills the via structure 20 flat, and the first planarization layer PLN1 does not cover the second conductive portion 112. The surface of the first planarization layer PLN1 facing away from the substrate is flat.

[0115] For example, after the first planarization layer PLN1 is fabricated, a second conductive connection portion 12 is fabricated. The second conductive connection portion 12 completely covers the first planarization layer PLN1 and contacts the second conductive portion 112, thereby achieving an electrical connection between the second conductive connection portion 12 and the second conductive portion 112. For example, the second conductive connection portion 12 includes an indium tin oxide layer or a metal layer, but is not limited to these.

[0116] For example, after the second conductive connection portion 12 is fabricated, the second electrode M2-2 of the sensing transistor M2 is fabricated. The second electrode M2-2 of the sensing transistor M2 is electrically connected to the second conductive connection portion 12, and is electrically connected to the first conductive connection portion 11 through the second conductive connection portion 12.

[0117] As shown in Figures 3, 4, and 3 to 42, exemplarily, the sub-pixel driving circuit further includes a third conductive connection portion 13. At least a portion of the third conductive connection portion 13 is located on the side of the second electrode M2-2 of the sensing transistor M2 facing away from the substrate. The third conductive connection portion 13 is coupled to the second conductive connection portion 12, the second electrode M2-2 of the sensing transistor M2, and the anode Ano of the light-emitting element. For example, the third conductive connection portion 13 is disposed in the same layer and with the same material as the first source / drain metal layer in the display panel. The third conductive connection portion 13 is coupled to the second conductive connection portion 12 and the second electrode M2-2 of the sensing transistor M2 through a fourth via Via4, and the third conductive connection portion 13 is coupled to the anode Ano of the light-emitting element through a fifth via Via5.

[0118] It is worth noting that the fifth via Via5 includes a first sub-via Via51 and a second sub-via Via52 that are connected. The first sub-via Via51 is a via that penetrates the second planarization layer, and the second sub-via Via52 is a via that penetrates the second passivation layer PVX2. Figure 41 illustrates the pixel opening region K1 defined by the pixel defining layer PDL.

[0119] It should be noted that as the PPI of the display panel continues to increase, such as above 1500 PPI, due to the limitation of layout space, the via structure 20 and the fourth via Via4 will overlap in the longitudinal direction perpendicular to the substrate. In this case, if the first planarization layer PLN1 is not provided, there is a risk of open circuit.

[0120] In the display panel provided in the above embodiment, the first planarization layer PLN1 is provided to fill the via structure 20, and the second conductive connection portion 12 is provided to cover the first planarization layer PLN1 and electrically connect to the second conductive portion 112 of the first conductive connection portion 11. This realizes the electrical connection between the second conductive connection portion 12 and the second electrode M3-2 and the second plate Cst2 of the driving transistor M3. Then, the second electrode M2-2 of the sensing transistor M2 is attached to the surface of the second conductive connection portion 12. The third conductive connection portion 13 is coupled to the second conductive connection portion 12 and the second electrode M2-2 of the sensing transistor M2 through the fourth via Via4. This realizes the electrical connection between the third conductive connection portion 13 and the second electrode M3-2 of the driving transistor M3, the second plate Cst2 of the storage capacitor Cst, and the second electrode M2-2 of the sensing transistor M2. When this configuration is adopted, even if the via structure 20 and the fourth via Via4 overlap in the longitudinal direction perpendicular to the substrate, the risk of open circuit will not increase. Moreover, the PPI of the display panel can be further improved by further increasing the overlap area of ​​the via structure 20 and the fourth via Via4 in the longitudinal direction perpendicular to the substrate.

[0121] As shown in Figures 21 to 25, in some embodiments, the orthographic projection of the second conductive portion 112 on the substrate surrounds the orthographic projection of the first conductive portion 111 on the substrate; the orthographic projection of the second conductive portion 112 on the substrate is located inside the orthographic projection of the second conductive connection portion 12 on the substrate.

[0122] The above-described configuration arranges the orthographic projection of the second conductive portion 112 on the substrate to surround the orthographic projection of the first conductive portion 111 on the substrate, allowing the second conductive portion 112 to be distributed around the via structure 20, thus enabling the second conductive portion 112 to have a larger area outside the via structure 20. Simultaneously, the orthographic projection of the second conductive portion 112 on the substrate is positioned inside the orthographic projection of the second conductive connection portion 12 on the substrate, ensuring that all second conductive portions 112 around the via structure 20 can contact the second conductive connection portion 12. This effectively improves the connection performance between the second conductive connection portion 12 and the second conductive portion 112, enhancing the reliability of the electrical connection.

[0123] As shown in Figures 3 and 4, in some embodiments, at least a portion of the second electrode M2-2 of the sensing transistor M2 is configured to contact the side of the second conductive connection portion 12 and the side of the second conductive portion 112.

[0124] The above configuration effectively improves the connection performance between the second electrode M2-2 of the sensing transistor M2 and the second conductive portion 112 and the second conductive connection portion 12, thereby enhancing the reliability of the electrical connection.

[0125] As shown in Figures 5 and 6, in some embodiments, the sub-pixel driving circuit further includes a third conductive connection portion 13. At least a portion of the third conductive connection portion 13 is located on the side of the second electrode M2-2 of the sensing transistor M2 facing away from the substrate. The third conductive connection portion 13 is coupled to the second conductive portion 112, the second electrode M2-2 of the sensing transistor M2, and the anode Ano of the light-emitting element.

[0126] For example, the third conductive connection portion 13 is coupled to the second conductive portion 112 and the second electrode M2-2 of the sensing transistor M2 through the fourth via Via4 respectively. The orthographic projection of the fourth via Via4 on the substrate does not overlap with the orthographic projection of the via structure 20 on the substrate.

[0127] When the first planarization layer PLN1 and the second conductive connection portion 12 are not included in the display panel, the third conductive connection portion 13 and the fourth via Via4 are arranged in the manner described above, which can reduce the risk of open circuit.

[0128] As shown in Figures 3, 5, and 11 to 19, in some embodiments, the sub-pixel driving circuit further includes a compensation electrode layer 30 and a data writing transistor M1. The compensation electrode layer 30 is located on the side of the second electrode M1-2 of the data writing transistor M1 facing away from the substrate. The compensation electrode layer 30 is coupled to the second electrode M1-2 of the data writing transistor M1 through a third via Via3. The compensation electrode layer 30 is also coupled to the gate M3-g of the driving transistor M3. The orthographic projection of the compensation electrode layer 30 on the substrate at least partially overlaps with the orthographic projection of the second electrode Cst2 on the substrate.

[0129] For example, at least a portion of the compensation electrode layer 30 is located on the side of the gate M3-g of the driving transistor M3 facing away from the substrate, and the compensation electrode layer 30 is directly connected to the gate M3-g of the driving transistor M3.

[0130] For example, the display panel includes a first gate metal layer and a second gate metal layer stacked sequentially along a direction away from the substrate; the gate M3-g of the driving transistor M3 is disposed in the same layer and with the same material as the first gate metal layer, the second electrode Cst2 is disposed in the same layer and with the same material as the second gate metal layer, and at least a portion of the compensation electrode layer 30 is located between the first gate metal layer and the second gate metal layer.

[0131] It should be noted that when manufacturing the display panel with the above structure, since the compensation electrode layer 30 is added, a conductive film layer needs to be added. In actual manufacturing, the compensation electrode layer 30 can be formed before or after the first gate metal layer. If it is formed before the first gate metal layer, the conductive film layer is used to form the gate of each transistor. The conductive film layer can only be made of metal material. In this case, the first gate metal layer is used to form the compensation electrode layer 30. If it is formed after the first gate metal layer, the conductive film layer is used to form the compensation electrode layer 30. The conductive film layer can be made of metal material or indium tin oxide material. In this case, the first gate metal layer is used to form the gate of each transistor.

[0132] For example, the layer closest to the substrate among the first gate metal layer and the conductive film layer is used as a dopping barrier layer to dope the active layer of the transistor, forming the source and drain of the transistor. The compensation electrode layer 30 serves as a signal transfer layer between the second electrode M1-2 of the data writing transistor M1 and the gate M3-g of the driving transistor M3, and also serves as a compensation electrode for the storage capacitor Cst.

[0133] For example, the compensation electrode layer 30 includes an indium tin oxide layer or a metal layer, but is not limited to this.

[0134] In the display panel provided in the above embodiment, by adding a compensation electrode layer 30 to electrically connect the second electrode M1-2 of the data writing transistor M1 and the gate M3-g of the driving transistor M3 together, the function of the gate M3-g of the driving transistor M3 being connected downward to the second electrode M1-2 of the data writing transistor M1 is realized. This allows the layout position of the first plate Cst1 of the storage capacitor Cst (i.e., the gate M3-g of the driving transistor M3) to no longer be limited by the via and the position of the active layer of the data writing transistor M1. Furthermore, the compensation electrode layer 30 can be further expanded in the horizontal and vertical space of the pixels, increasing the electrode area. This effectively increases the capacitance value of the storage capacitor Cst formed between the compensation electrode layer 30 and the second plate Cst2, improving the potential stability of the gate M3-g of the driving transistor M3 and the stability of the driving current. At the same time, since the gate M3-g of the driving transistor M3 has good potential stability, abnormal jumps can be better avoided, ensuring that the display panel can achieve various grayscale displays. Taking a 1500PPI display panel as an example, by adding a compensation electrode layer 30, the capacitance of the storage capacitor Cst can be increased from 4.2fF to 11.9fF, which is 2.8 times higher.

[0135] Moreover, the addition of the aforementioned compensation electrode layer 30 helps to stabilize the gate voltage of the driving transistor M3, reduce the influence of parasitic capacitance, and reduce flicker problems.

[0136] As shown in Figures 4 and 6, in some embodiments, the sub-pixel driving circuit further includes a fourth conductive connection portion 14 and a data writing transistor M1. The fourth conductive connection portion 14 is coupled to the gate M3-g of the driving transistor M3 and the second terminal M1-2 of the data writing transistor M1, respectively. The fourth conductive connection portion 14 is disposed in the same layer and with the same material as the first conductive connection portion 11.

[0137] For example, the fourth conductive connection portion 14 is coupled to the gate M3-g of the driving transistor M3 and the second terminal M1-2 of the data writing transistor M1 through the sixth via Via6.

[0138] The above-mentioned arrangement of the fourth conductive connection portion 14 and the first conductive connection portion 11 in the same layer and with the same material allows the fourth conductive connection portion 14 to be formed simultaneously with the first conductive connection portion 11 in the same patterning process, which helps to simplify the manufacturing process of the display panel and reduce manufacturing costs.

[0139] The process flow corresponding to each embodiment is described in detail below:

[0140] Under the structure shown in Figure 3, the specific manufacturing process of the display panel is as follows:

[0141] A bottom gate metal material layer is fabricated using Mo on the base buffer layer BUF0, and the bottom gate metal material layer is patterned (Mask1) to form the bottom gate metal layer. This bottom gate metal layer can be used as the bottom gate bg of the driving transistor M3.

[0142] Using SiO x Create the first buffer layer BUF-L.

[0143] A second source / drain metal material layer is fabricated using Mo, and the second source / drain metal material layer is patterned (Mask2) to form the second source / drain metal layer.

[0144] Using SiO x / SiN x Create the insulating layer GI0.

[0145] A first active base layer is formed using P-Si material, and the first active base layer is patterned (Mask3) to form the first active layer.

[0146] Using SiO x / SiN xA first gate insulating layer GI1 is fabricated, and the first gate insulating layer is patterned (Mask4) to form a third via Via3.

[0147] A first gate metal material layer is fabricated using Mo, and the first gate metal material layer is patterned (Mask5) to form the first gate metal layer.

[0148] LDD Mask (Mask6) is performed using the first gate metal layer as a mask, and Doping is performed on the first active layer.

[0149] A compensation metal material layer is fabricated using Mo or ITO, and the compensation metal material layer is patterned (Mask7) to form a compensation electrode layer.

[0150] Using SiN x A second gate insulating layer GI2 is fabricated, and the second gate insulating layer is patterned (Mask8) to form a seventh via Via7.

[0151] A second gate metal material layer is fabricated using Mo, and the second gate metal material layer is patterned (Mask9) to form the second gate metal layer.

[0152] Using SiO x Create a second buffer layer, BUF-O.

[0153] Mask10 is applied to form via structure 20.

[0154] A first conductive material layer is fabricated using Mo, and the first conductive material layer is patterned (Mask 11) to form a first conductive connection portion 11.

[0155] An organic film layer is formed using organic materials, and the first organic film layer is patterned (Mask12) to form a first planarization layer PLN1.

[0156] A second conductive material layer is fabricated using ITO, and the second conductive material layer is patterned (Mask 13) to form a second conductive connection portion 12.

[0157] A second active base layer is fabricated using IGZO, and then patterned (Mask14) to form the second active layer.

[0158] Using SiO x Fabricate the third gate insulating layer GI3.

[0159] A third gate metal material layer is fabricated using Mo, and the third gate metal material layer is patterned (Mask15) to form the third gate metal layer.

[0160] Using SiO / SiN x Fabricate the interlayer insulation layer (ILD).

[0161] Perform CNT-L via process (Mask16).

[0162] Perform CNT-O via process (Mask17).

[0163] A first source / drain metal material layer of Ti / Al / Ti stacked structure is fabricated, and the first source / drain metal material layer is patterned (Mask18) to form the first source / drain metal layer.

[0164] Using SiO x / SiN x A first passivation material layer is fabricated, and the first passivation material layer is patterned (Mask19) to form a first passivation layer PVX1.

[0165] A third source / drain metal material layer with a Ti / Al / Ti stacked structure is fabricated, and the third source / drain metal material layer is patterned (Mask20) to form the third source / drain metal layer.

[0166] A second organic film layer is formed using organic materials, and the second organic film layer is patterned (Mask21) to form a second planarization layer PLN2.

[0167] Using SiO x / SiN x A second passivation material layer is fabricated, and the second passivation material layer is patterned (Mask22) to form the second passivation layer PVX2.

[0168] Perform Mask23 to create the anode Ano.

[0169] An inorganic material is used to fabricate a pixel defining material layer, which is then patterned (Mask24) to form a pixel opening region K1.

[0170] In the structure shown in Figure 4, the specific process flow of the display panel reduces Mask 4 and Mask 7 compared to the structure in Figure 3. That is, the structure shown in Figure 4 requires 22 Mask processes.

[0171] In the structure shown in Figure 5, the specific process flow of the display panel reduces Mask 12 and Mask 13 compared to the structure in Figure 3. That is, the structure shown in Figure 5 requires 22 Mask processes.

[0172] In the structure shown in Figure 6, the specific process flow of the display panel is reduced by Mask4, Mask7, Mask12, and Mask13 compared to the structure in Figure 3. That is, the structure shown in Figure 6 requires 20 Mask processes.

[0173] It should be noted that the solutions in the above embodiments are not limited to the 3T1C circuit structure, but can also be applied to other internally compensated or externally compensated pixel circuits, and are equally applicable to LTPS PMOS process or Oxide NMOS process.

[0174] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0175] For example, the display device includes Micro-LED devices, Mini-LED devices, OLED devices, etc., but is not limited to these. The display device can be applied to the field of AR-VR ultra-high PPI displays.

[0176] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0177] The display panel provided in the above embodiment includes a first conductive connection portion 11, which can be coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through a via structure 20. At the same time, the second electrode M2-2 of the sensing transistor M2 is disposed on the side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 is coupled to the first conductive connection portion 11. When the display panel adopts the above structure, the first conductive connection portion 11 can couple the second electrode plate Cst2 of the storage capacitor Cst, the second electrode M3-2 of the driving transistor M3, and the second electrode M2-2 of the sensing transistor M2 together through a via structure 20. Compared with the prior art, which requires at least two via structures 20 to achieve the above connection relationship, the above technical solution effectively reduces the overall layout space occupied by the sub-pixel driving circuit, which is conducive to the display panel achieving a higher PPI.

[0178] The display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0179] It should be noted that "the structure extends in a certain direction" means that the structure includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0180] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0181] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0182] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0183] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0184] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0185] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0186] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixel comprising a sub-pixel driving circuit and a light emitting element, the sub-pixel driving circuit comprising a first conductive connection, a driving transistor, a sensing transistor and a storage capacitor; A first plate of the storage capacitor is coupled with a gate of the driving transistor, and a second plate of the storage capacitor is located on a side of the first plate of the storage capacitor away from the substrate; At least part of the first conductive connection is located on a side of the second plate away from the substrate, and the first conductive connection is coupled with the second plate and a second electrode of the driving transistor through a via structure respectively; At least part of the second electrode of the sensing transistor is located on a side of the first conductive connection away from the substrate, and the second electrode of the sensing transistor is coupled with the first conductive connection.

2. The display panel of claim 1, wherein, The second electrode of the driving transistor is located on a side of the gate of the driving transistor toward the substrate, and at least part of the orthographic projection of the second electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second plate on the substrate; The via structure comprises a first via and a second via in communication, the first conductive connection is coupled with the second plate through the second via, and the first conductive connection is coupled with the second electrode of the driving transistor through the second via and the first via.

3. The display panel of claim 1, wherein, The first conductive connection comprises a first conductive part and a second conductive part coupled with each other, the first conductive part is located in the via structure, the first conductive part is coupled with the second plate and the second electrode of the driving transistor respectively, and the second conductive part is located outside the via structure, and the second conductive part is coupled with the second electrode of the sensing transistor.

4. The display panel of claim 3, wherein, The sub-pixel driving circuit further comprises a first planar layer, the first planar layer is located in the via structure and on a side of the first conductive part away from the substrate; The sub-pixel driving circuit further comprises a second conductive connection, the second conductive connection covers the first planar layer and is in contact with the second conductive part; At least part of the second electrode of the sensing transistor is located on a side of the second conductive connection away from the substrate and is coupled with the second conductive connection.

5. The display panel of claim 4, wherein, The orthographic projection of the second conductive part on the substrate surrounds the orthographic projection of the first conductive part on the substrate; The orthographic projection of the second conductive part on the substrate is located inside the orthographic projection of the second conductive connection on the substrate.

6. The display panel of claim 4, wherein, At least part of the second electrode of the sensing transistor is in contact with the side surface of the second conductive connection and the side surface of the second conductive part.

7. The display panel of claim 4, wherein, The sub-pixel driving circuit further comprises a third conductive connection, at least part of the third conductive connection is located on a side of the second electrode of the sensing transistor away from the substrate, and the third conductive connection is coupled with the second conductive connection, the second electrode of the sensing transistor and the anode of the light emitting element respectively.

8. The display panel of claim 3, wherein, The sub-pixel driving circuit further comprises a third conductive connection part, at least part of the third conductive connection part is located on the side of the second electrode of the sensing transistor away from the substrate, and the third conductive connection part is coupled with the second conductive part, the second electrode of the sensing transistor, and the anode of the light emitting element respectively.

9. The display panel according to any one of claims 1 to 8, wherein The sub-pixel driving circuit further comprises a compensation electrode layer and a data writing transistor, the compensation electrode layer is located on the side of the second electrode of the data writing transistor away from the substrate, and the compensation electrode layer is coupled with the second electrode of the data writing transistor through a third via hole; the compensation electrode layer is also coupled with the gate of the driving transistor; the orthographic projection of the compensation electrode layer on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate.

10. The display panel of claim 9, wherein, At least part of the compensation electrode layer is located on the side of the gate of the driving transistor away from the substrate, and the compensation electrode layer is directly overlapped with the gate of the driving transistor.

11. The display panel of claim 9, wherein, The display panel comprises a first gate metal layer and a second gate metal layer which are sequentially stacked in the direction away from the substrate; The gate of the driving transistor is provided in the same layer and with the same material as the first gate metal layer, and the second electrode plate is provided in the same layer and with the same material as the second gate metal layer, and at least part of the compensation electrode layer is located between the first gate metal layer and the second gate metal layer.

12. The display panel of claim 9, wherein, The compensation electrode layer comprises an indium tin oxide layer or a metal layer.

13. The display panel according to any one of claims 1 to 8, wherein, The sub-pixel driving circuit further comprises a fourth conductive connection part and a data writing transistor, the fourth conductive connection part is coupled with the gate of the driving transistor and the second electrode of the data writing transistor respectively; and the fourth conductive connection part is provided in the same layer and with the same material as the first conductive connection part.

14. The display panel according to any one of claims 1 to 8, wherein, The sub-pixel driving circuit further comprises a data writing transistor, the gate of the data writing transistor is coupled with a corresponding scan line, the first electrode of the data writing transistor is coupled with a corresponding data line, and the second electrode of the data writing transistor is coupled with the gate of the driving transistor; The gate of the sensing transistor is coupled with a corresponding scan line, and the first electrode of the sensing transistor is coupled with a sensing line; The first electrode of the driving transistor is coupled with a corresponding power supply line, and the second electrode of the driving transistor is also coupled with the anode of the light emitting element; The data writing transistor and the driving transistor are low-temperature polysilicon transistors, and the sensing transistor is an oxide transistor.

15. A display device comprising the display panel according to any one of claims 1 to 14.

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