Solar cell and photovoltaic module

Abstract

The present application relates to the field of solar cells, and in particular to a solar cell and a photovoltaic module. The solar cell comprises: a substrate; a passivation layer arranged on the surface of the substrate, the passivation layer comprising an intrinsic amorphous silicon layer; an intrinsic silicon oxide layer, wherein the intrinsic silicon oxide layer is arranged on the surface of the passivation layer facing away from the substrate, the content range of high-valence state silicon oxide in the intrinsic silicon oxide layer is greater than 50% and less than or equal to 95%, and the valence state of silicon element in the high-valence state silicon oxide is greater than or equal to +2; a doped layer, wherein the doped layer comprises a doped microcrystalline silicon layer, and the doped microcrystalline silicon layer is arranged on the surface of the intrinsic silicon oxide layer facing away from the passivation layer; a transparent conductive layer, wherein the transparent conductive layer is arranged on the surface of the doped layer facing away from the intrinsic silicon oxide layer; and an electrode, arranged on the transparent conductive layer. The solar cell can solve the problem of performance limitations between the passivation layer and the doped layer caused by the presence of an incubation layer.

Description

Solar cells and photovoltaic modules

[0001] This application claims priority to Chinese invention patent application number "202411720251.7", filed on "November 27, 2024", entitled "Solar Cell and Photovoltaic Module". Technical Field

[0002] This application relates to the field of solar cells, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0003] In heterojunction solar cells, using a doped microcrystalline silicon layer is a better choice than using a doped amorphous silicon layer. However, when a doped microcrystalline silicon layer is placed on the passivation layer of a heterojunction solar cell, there is a mutual constraint and influence between the performance of the doped microcrystalline silicon layer and the performance of the passivation layer, making it difficult to take full advantage of using the doped microcrystalline silicon layer and limiting further improvement of the heterojunction solar cell performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses a solar cell and a photovoltaic module.

[0005] In a first aspect, this application provides a solar cell, the solar cell comprising:

[0006] Base;

[0007] A passivation layer is disposed on the surface of the substrate, and the passivation layer includes an intrinsic amorphous silicon layer;

[0008] The intrinsic silicon oxide layer is located on the side of the passivation layer that is away from the substrate. The content of high-valence silicon oxide in the intrinsic silicon oxide layer is greater than 50% and less than or equal to 95%, and the valence of silicon in the high-valence silicon oxide is greater than or equal to +2.

[0009] The doped layer includes a doped microcrystalline silicon layer, which is disposed on the side of the intrinsic silicon oxide layer opposite to the passivation layer.

[0010] A transparent conductive layer is disposed on the side of the doped layer that faces away from the intrinsic silicon oxide layer.

[0011] The electrode is disposed on the transparent conductive layer.

[0012] In some embodiments, the intrinsic silicon oxide layer is a non-hydrogenated intrinsic silicon oxide layer.

[0013] In some embodiments, the pore size of the intrinsic silicon oxide layer is 2 nm to 8 nm.

[0014] In some embodiments, the doped layer is a hydrogenated doped layer, where oxygen atoms in the intrinsic silicon oxide layer and hydrogen atoms in the doped layer form a dipole moment.

[0015] In some embodiments, the passivation layer is a hydrogenated intrinsic amorphous silicon layer.

[0016] In some embodiments, the thickness of the passivation layer is 6 nm to 8 nm; and / or,

[0017] When the doped layer is an N-type doped layer, the thickness of the doped layer is 23 nm to 26 nm; and / or,

[0018] When the doped layer is a p-type doped layer, the thickness of the doped layer is 28 nm to 32 nm; and / or,

[0019] The thickness of the intrinsic silicon oxide layer is 0.4 nm to 3 nm.

[0020] In some embodiments, when the doped layer is an N-type doped layer, the doping concentration of the dopant element in the doped layer is 5% to 7%; and / or,

[0021] When the doped layer is an N-type doped layer, the doping concentration of the dopant element in the doped layer is 0.3% to 1%.

[0022] In some embodiments, the passivation layer, the intrinsic silicon oxide layer, the doped layer, the transparent conductive layer, and the electrode are symmetrically disposed on the light-receiving surface and the back-lighting surface of the substrate, respectively.

[0023] The substrate and the doped layer on the light-receiving side of the substrate have the same conductivity type, while the substrate and the doped layer on the back-light-receiving side of the substrate have opposite conductivity types.

[0024] In some embodiments, the substrate is an N-type silicon substrate or a P-type silicon substrate; and / or,

[0025] The transparent conductive layer includes one or more layers selected from indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, or transparent conductive aluminum-fluorine co-doped zinc oxide; and / or,

[0026] The electrodes are silver electrodes, copper electrodes, aluminum electrodes, or silver-aluminum electrodes.

[0027] Secondly, this application provides a photovoltaic module, which includes a solar cell as described in the first aspect, or a solar cell prepared by the method described in the second aspect.

[0028] Compared with the prior art, this application has at least the following beneficial effects:

[0029] The solar cell of this application utilizes an intrinsic silicon oxide layer. An intrinsic silicon oxide layer with a high valence state silicon oxide content of greater than 50% and less than or equal to 95% is added between the passivation layer and the doped layer with doped microcrystalline silicon. The density of this intrinsic silicon oxide layer can promote the rapid nucleation of the microcrystalline silicon layer, thereby reducing the thickness of the incubation layer and solving the problem of performance constraints of the passivation layer and doped layer caused by the presence of the incubation layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 is a schematic diagram of the structure of a solar cell according to an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Passivation layer; 3. Intrinsic silicon oxide layer; 4. Doped layer; 41. N-type doped layer; 42. P-type doped layer; 5. Transparent conductive layer; 6. Electrode. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0034] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0035] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0036] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0037] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (the specific types and structures may be the same or different), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0038] Heterojunction solar cells typically include a substrate and a passivation layer and a doped layer sequentially disposed on the substrate. When selecting materials for the doped layer, doped microcrystalline silicon is a better choice than doped amorphous silicon due to its higher doping efficiency and other advantages.

[0039] However, the formation process of doped microcrystalline silicon layers typically includes stages such as incubation, nucleation, and crystal growth. During this process, an incubation layer of a certain thickness inevitably forms on the side of the doped layer near the passivation layer as a transition region. The inevitable existence of this incubation layer is detrimental to the passivation layer and the doped microcrystalline silicon layer each performing their respective functions.

[0040] Taking the deposition of a doped microcrystalline silicon layer using PECVD process as an example, the formation process of the doped microcrystalline silicon layer includes: firstly, an amorphous incubation layer is formed on the passivation layer. This incubation layer serves as a transition region with a certain thickness, which forms the basis for the subsequent incubation to form crystalline silicon. As deposition proceeds, nucleation points for microcrystalline silicon begin to form in the incubation layer, serving as the starting point for crystal growth. Then, the crystals gradually grow to form microcrystalline silicon particles. These microcrystalline silicon particles expand through an island-like growth pattern and eventually connect with each other to form a continuous microcrystalline silicon layer.

[0041] Because the amorphous incubation layer in doped microcrystalline silicon layers is often thick and has many defects and a small band gap, it can have various negative effects, such as hindering carrier transport and affecting the uniformity of the longitudinal structure of the doped microcrystalline silicon layer. Therefore, it is necessary to make the incubation layer thinner to alleviate these problems. However, a thinner incubation layer means faster nucleation and crystal growth in the microcrystalline silicon layer. Dopants in the microcrystalline silicon layer can more easily pass through grain boundaries and the incubation layer to enter the passivation layer and even reach the substrate interface, leading to the depassivation of the passivation layer and the substrate interface. In other words, a thicker incubation layer will have a significant adverse impact on the performance of the doped microcrystalline silicon layer. It is evident that there is always a mutually restrictive relationship between the performance of the doped microcrystalline silicon layer and the passivation layer. This restriction means that the application of doped microcrystalline silicon layers in heterojunction solar cells cannot demonstrate significant technological advantages, limiting the performance improvement of heterojunction solar cells with this type of structure.

[0042] Based on in-depth analysis and research of the above-mentioned technical problems, this application provides a solar cell and photovoltaic module. By setting an intrinsic silicon oxide layer between the passivation layer and the doped microcrystalline silicon layer, the mutual constraints between the passivation layer and the doped microcrystalline silicon layer are effectively eliminated, allowing both the passivation layer and the doped microcrystalline silicon layer to better perform their respective functions, thereby further improving the performance of the solar cell.

[0043] In the first aspect, as shown in Figure 1, this application provides a solar cell, comprising:

[0044] Base 1;

[0045] Passivation layer 2 is disposed on the surface of substrate 1, and passivation layer 2 includes an intrinsic amorphous silicon layer;

[0046] Intrinsic silicon oxide layer 3 is disposed on the side of passivation layer 2 facing away from substrate 1; the content of high-valence silicon oxide in intrinsic silicon oxide layer 3 is greater than 50% and less than or equal to 95%, and the valence state of silicon element in high-valence silicon oxide is greater than or equal to positive divalent.

[0047] Doped layer 4, which includes a doped microcrystalline silicon layer, is disposed on the side of intrinsic silicon oxide layer 3 facing away from passivation layer 2.

[0048] A transparent conductive layer 5 is disposed on the side of the doped layer 4 that is opposite to the intrinsic silicon oxide layer 3.

[0049] Electrode 6 is disposed on the transparent conductive layer 5.

[0050] The intrinsic silicon oxide layer 3 contains high-valence silicon oxide with a content greater than 50% and less than or equal to 95%, including any value within this range. For example, the content of high-valence silicon oxide in the intrinsic silicon oxide layer 3 can be 51%, 55%, 58%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, or 95%. The range of high-valence silicon oxide content refers to the mass percentage of high-valence silicon oxide in the intrinsic silicon oxide layer 3. Furthermore, high-valence silicon oxide is silicon oxide with a silicon valence greater than or equal to +2, such as silicon oxide with a +2, +3, or +4 valence, and mixtures of silicon oxides corresponding to these valence states. The aforementioned high-valence silicon oxide is oxygen-rich silicon oxide; a higher proportion of oxygen-rich silicon oxide in this layer indicates better silicon oxide density. Besides the above valence states, silicon oxide in the silicon oxide layer can also exist in a +1 valence state, such as Si₂O (Si₂O₃). 1+ This type does not belong to high-valence silicon oxide.

[0051] Furthermore, the "intrinsic" in intrinsic silicon oxide layer 3 refers to the fact that no specific doping operation is performed during the fabrication of this layer, therefore, this layer does not contain any doped elements after fabrication. However, it is understandable that when a doped layer 4 is subsequently fabricated on this layer (especially to achieve a high doping concentration in doped layer 4), the doped elements in doped layer 4 may diffuse into intrinsic silicon oxide layer 3, resulting in trace amounts of doped elements in intrinsic silicon oxide layer 3. However, since the concentration of doped elements is insufficient to provide normal conductivity, this application allows the intrinsic silicon oxide layer 3 to contain trace amounts of doped elements, but its overall properties remain those of the intrinsic layer, not those of doped layer 4. The intrinsic nature of intrinsic amorphous silicon layers is similar, and will not be elaborated further below.

[0052] Among them, substrate 1 is either an N-type silicon substrate 1 or a P-type silicon substrate 1.

[0053] The passivation layer 2 includes an intrinsic amorphous silicon layer, meaning that the passivation layer 2 can be only an intrinsic amorphous silicon layer, or it can include an intrinsic amorphous silicon layer and other films that can play a passivation role.

[0054] The doped layer 4 includes a doped microcrystalline silicon layer disposed on the side of the intrinsic silicon oxide layer 3 facing away from the passivation layer 2. That is, the doped layer 4 can be simply a doped microcrystalline silicon layer disposed on the intrinsic silicon oxide layer 3, or it can include a doped microcrystalline silicon layer disposed close to the intrinsic silicon oxide layer 3 and other doped layers 4 disposed away from the intrinsic silicon oxide layer 3. These other doped layers 4 may be, for example, doped amorphous silicon layers. Since the doped layer 4 uses a doped microcrystalline silicon layer, an incubation layer of a certain thickness inevitably exists on the side of the doped layer 4 close to the intrinsic silicon oxide layer 3. Therefore, in this embodiment, an intrinsic silicon oxide layer 3 is added between the passivation layer 2 and the doped layer 4 to mitigate a series of problems caused by the presence of the incubation layer.

[0055] The transparent conductive layer 5 includes one or more layers of indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), or indium-doped zinc oxide (IZO).

[0056] Among them, electrode 6 can be a silver electrode, copper electrode, aluminum electrode or silver-aluminum electrode.

[0057] The solar cell provided in this application embodiment utilizes an intrinsic silicon oxide layer 3 with a high proportion of high-valence silicon oxide, added between the passivation layer 2 and the doped layer 4 with a doped microcrystalline silicon layer. This reduces the thickness of the incubation layer, thereby solving the performance limitation problem of the passivation layer 2 and the doped layer 4 caused by the presence of the incubation layer. Specifically, the intrinsic silicon oxide layer 3 with a high-valence silicon oxide content greater than 50% and less than or equal to 95% has better film density. It can effectively prevent dopants in the doped layer 4 from entering the passivation layer 2, promote rapid nucleation of the microcrystalline silicon layer, and achieve the goal of reducing the thickness of the incubation layer without affecting the passivation performance of the passivation layer 2. This is beneficial for reducing the obstacle to longitudinal carrier transport, increasing the open-circuit voltage, and improving the carrier transport capability of the doped layer 4. When the content of high-valence silicon oxide is less than or equal to 50%, the density of the intrinsic silicon oxide layer 3 is insufficient to effectively block the doping elements in the doped layer 4. When the content of high-valence silicon oxide reaches 95%, the intrinsic silicon oxide layer 3 has both high density to block the doping elements and avoids the increase in process difficulty, making the intrinsic silicon oxide layer 3 easier to meet mass production requirements.

[0058] The intrinsic silicon oxide layer 3 of the solar cell in the embodiments of this application will be further described below.

[0059] In some embodiments, the intrinsic silicon oxide layer 3 is a non-hydrogenated intrinsic silicon oxide layer. The embodiments of this application employ a non-hydrogenated intrinsic silicon oxide layer 3. Compared to a hydrogenated intrinsic silicon oxide layer, the non-hydrogenated intrinsic silicon oxide layer 3 has more Si-Si bonds and fewer Si-H bonds, resulting in a denser film. This is more effective in blocking dopants that cannot be intercepted by the incubation layer, ensuring that the passivation performance of the passivation layer 2 is not affected by the thinning of the incubation layer.

[0060] The non-hydrogenated nature of the intrinsic silicon oxide layer 3 means that no specific hydrogen doping operation is performed during its fabrication, resulting in a layer without a high hydrogen doping concentration. However, it is understandable that if a doped layer 4 is subsequently fabricated on top of this layer (especially a hydrogenated doped layer 4), hydrogen from the doped layer 4 may diffuse into the intrinsic silicon oxide layer 3, resulting in trace amounts of hydrogen. However, the concentration of these trace amounts of hydrogen is insufficient to achieve the properties of a hydrogenated layer; therefore, the overall properties of the intrinsic silicon oxide layer 3 remain those of a non-hydrogenated layer.

[0061] In some embodiments, the pore size of the intrinsic silicon oxide layer 3 is 2 nm to 8 nm. The pore size of the intrinsic silicon oxide layer 3 is 2 nm to 8 nm, including any value within this range. For example, the pore size of the intrinsic silicon oxide layer 3 is 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, or 8 nm. Controlling the pore size of the intrinsic silicon oxide layer 3 within the above range is beneficial for better balancing the compactness and carrier transport capacity of the film. The pore size of the intrinsic silicon oxide layer can be obtained, for example, by scanning electron microscopy (SEM) imaging and measurement.

[0062] In some embodiments, the thickness of the intrinsic silicon oxide layer 3 is 0.4 nm to 3 nm. The thickness of the intrinsic silicon oxide layer 3 is 0.4 nm to 3 nm, including any value within this range. For example, the thickness of the intrinsic silicon oxide layer 3 is 0.4 nm, 0.8 nm, 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, or 3.0 nm. Controlling the thickness of the intrinsic silicon oxide layer 3 within the above range is beneficial for better balancing carrier transport capacity and efficient crystal nucleation of the doped microcrystalline silicon layer, reducing the impact of excessively thick film on carrier transport and the negative impact of excessively thin film on efficient crystal nucleation on the film.

[0063] In some embodiments, the doped layer 4 is a hydrogenated doped layer, and oxygen atoms in the intrinsic silicon oxide layer 3 and hydrogen atoms in the doped layer 4 form a dipole moment. The dipole moment generated by the longitudinal distribution of oxygen and hydrogen atoms (i.e., the distribution perpendicular to the thickness direction of the doped layer 4) between the intrinsic silicon oxide layer 3 and the doped layer 4 helps to reduce the hole hopping distance, thereby reducing the recombination of holes and electrons.

[0064] The passivation layer 2 of the solar cell in the embodiments of this application will be further described below.

[0065] In some embodiments, the passivation layer 2 is a hydrogenated intrinsic amorphous silicon layer. Through the combined action of the hydrogenated intrinsic amorphous silicon layer, the intrinsic silicon oxide layer 3, and the doped layer 4, chemical passivation and field passivation effects are better utilized, providing superior passivation performance for solar cells.

[0066] In some embodiments, the thickness of the passivation layer 2 is 6 nm to 8 nm. The thickness of the passivation layer 2 is 6 nm to 8 nm, including any value within this range. For example, the thickness of the passivation layer 2 is 6 nm, 6.2 nm, 6.5 nm, 6.8 nm, 7 nm, 7.2 nm, 7.5 nm, 7.8 nm, or 8 nm. Controlling the thickness of the passivation layer 2 within the above range helps to better balance the impact on the solar cell's on-state voltage and series resistance.

[0067] The doped layer 4 of the solar cell in the embodiment of this application will be further described below.

[0068] In this embodiment, the doped layer 4 can be a P-type doped layer 42 and / or an N-type doped layer 41.

[0069] When the doped layer 4 is an N-type doped layer 41, the doping element in the N-type doped layer 41 includes phosphorus, arsenic, antimony, or bismuth. For example, the N-type doped layer 41 is a phosphorus-doped microcrystalline silicon layer. The thickness of the N-type doped layer 41 is 23 nm to 26 nm, and the doping concentration of the N-type doping element in the N-type doped layer 41 is 5% to 7%. The thickness of the N-type doped layer 41 is 23 nm to 26 nm, including any value within the above range. For example, the thickness of the N-type doped layer 41 is 23 nm, 24 nm, 24.5 nm, 25 nm, or 26 nm. The doping concentration of the N-type doping element in the N-type doped layer 41 is 5% to 7%, including any value within the above range. For example, the doping concentration of the N-type doping element in the N-type doped layer 41 is 5%, 5.5%, 6%, 6.5%, or 7%.

[0070] When the doped layer 4 is a P-type doped layer 42, the doping element in the P-type doped layer 42 includes boron, gallium, or indium. For example, the P-type doped layer 42 is a boron-doped microcrystalline silicon layer. The thickness of the P-type doped layer 42 is 28 nm to 32 nm, and the doping concentration of the P-type doping element in the P-type doped layer 42 is 0.3% to 1%. The thickness of the P-type doped layer 42 is 28 nm to 32 nm, including any value within the above range. For example, the thickness of the P-type doped layer 42 is 28 nm, 29 nm, 30 nm, 31 nm, or 32 nm. The doping concentration of the P-type doping element in the P-type doped layer 42 is 0.3% to 1%, including any value within the above range. For example, the doping concentration of the P-type doping element in the P-type doped layer 42 is 0.3%, 0.5%, 0.6%, 0.8%, or 1%.

[0071] By controlling the thickness and dopant concentration of the doped layer 4, the thickness of the doped layer 4 can be reduced while ensuring good carrier transport capability, thereby reducing series resistance.

[0072] The solar cell in this embodiment is a heterojunction solar cell, and its structure will be further described below.

[0073] In this embodiment, the passivation layer 2, the intrinsic silicon oxide layer 3, the doped layer 4, the transparent conductive layer 5, and the electrode 6 are symmetrically disposed on the light-receiving surface and the backlight surface of the substrate 1, respectively.

[0074] The substrate 1 and the doped layer 4 located on the light-receiving side of the substrate 1 have the same conductivity type, while the substrate 1 and the doped layer 4 located on the backlight side of the substrate 1 have opposite conductivity types.

[0075] In one optional embodiment, the substrate 1 is an N-type silicon substrate 1. A passivation layer 2, an N-type doped layer 41, a transparent conductive layer 5, and a light-receiving electrode 6 are sequentially disposed on the light-receiving surface of the silicon substrate 1. A passivation layer 2, a P-type doped layer 42, a transparent conductive layer 5, and a backlight electrode 6 are sequentially disposed on the backlight-receiving surface of the silicon substrate 1. An intrinsic silicon oxide layer 3 is disposed between the passivation layer 2 and the N-type doped layer 41, and also between the passivation layer 2 and the P-type doped layer 42. It is understood that the intrinsic silicon oxide layer 3 may also be disposed only on one side of the substrate 1, for example, only between the passivation layer 2 and the doped layer 41.

[0076] In the structure described above, which uses an N-type silicon substrate 1 and a PN junction formed on the side where the P-type doped layer 42 is located, the bandgap matching between the P-type doped layer 42 and the passivation layer 2 is poor when the intrinsic silicon oxide layer 3 is not provided. However, after adding the intrinsic silicon oxide layer 3 between these two layers, the bandgap of the intrinsic silicon oxide layer 3 is wider, which can reduce the bandgap shift at the interface between the P-type doped layer 42 and the passivation layer 2, thereby improving the transport and collection efficiency of hole carriers.

[0077] In another optional embodiment, the substrate 1 is a P-type silicon substrate 1, and the arrangement of other film layers is similar to that in the above embodiment. The positional relationship between the N-type doped layer 41 and the P-type doped layer 42 can be adjusted according to actual needs. For example, it is also possible to set the P-type doped layer 42 on the light-receiving side and the N-type doped layer 41 on the backlight side.

[0078] This application also provides a method for preparing the above-mentioned solar cell, including the following steps:

[0079] Preparation of intrinsic silicon oxide layer: A gas mixture of silane, hydrogen, and oxygen source gas is introduced into the solar cell semi-finished product using the PECVD process to deposit a non-hydrogenated intrinsic silicon oxide layer on the semi-finished product. The solar cell semi-finished product includes a substrate and a passivation layer disposed on the substrate, and the oxygen source gas includes carbon dioxide and / or nitrous oxide. By controlling the deposition conditions (e.g., by adjusting the deposition time, deposition temperature, and mass concentration of the introduced oxygen source gas), the content range of high-valence silicon oxide in the intrinsic silicon oxide layer can be satisfied, and an intrinsic silicon oxide layer with better film thickness and film quality can be obtained.

[0080] A hydrogenated doped layer is deposited on the intrinsic silicon oxide layer by a PECVD process. Although the doped layer includes a doped microcrystalline silicon layer, an incubation layer inevitably forms on the side of the doped microcrystalline silicon layer obtained by the PECVD process, near the amorphous silicon oxide layer. Nevertheless, since the intrinsic silicon oxide layer is prepared first in this application, the thickness of the incubation layer can be reduced when preparing the doped layer.

[0081] A transparent conductive layer and an electrode are fabricated on the doped layer.

[0082] It is understood that the solar cells described in the embodiments of this application can also be prepared by other preparation methods in the prior art, and this application does not limit the preparation methods.

[0083] Secondly, embodiments of this application provide a photovoltaic module, which includes solar cells as described in the first aspect. In this photovoltaic module, a plurality of the aforementioned solar cells are connected in series and / or in parallel, and then encapsulated using a film, cover plate, or the like to obtain the photovoltaic module.

[0084] The technical solutions disclosed in the embodiments of this application have been described in detail above. Specific examples have been used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: Base; A passivation layer is disposed on the surface of the substrate, and the passivation layer includes an intrinsic amorphous silicon layer; An intrinsic silicon oxide layer is disposed on the side of the passivation layer opposite to the substrate; the content of high-valence silicon oxide in the intrinsic silicon oxide layer is greater than 50% and less than or equal to 95%, and the valence state of silicon in the high-valence silicon oxide is greater than or equal to +2. The doped layer includes a doped microcrystalline silicon layer disposed on the side of the intrinsic silicon oxide layer opposite to the passivation layer. A transparent conductive layer is disposed on the side of the doped layer opposite to the intrinsic silicon oxide layer; The electrode is disposed on the transparent conductive layer.

2. The solar cell according to claim 1, characterized in that, The intrinsic silicon oxide layer is a non-hydrogenated intrinsic silicon oxide layer.

3. The solar cell according to claim 1, characterized in that, The intrinsic silicon oxide layer has a pore size of 2 nm to 8 nm.

4. The solar cell according to claim 1, characterized in that, The doped layer is a hydrogenated doped layer, and the oxygen atoms in the intrinsic silicon oxide layer form a dipole moment with the hydrogen atoms in the doped layer.

5. The solar cell according to claim 1, characterized in that, The passivation layer is a hydrogenated intrinsic amorphous silicon layer.

6. The solar cell according to claim 1, characterized in that, The passivation layer has a thickness of 6 nm to 8 nm; and / or, When the doped layer is an N-type doped layer, the thickness of the doped layer is 23 nm to 26 nm; and / or, When the doped layer is a P-type doped layer, the thickness of the doped layer is 28 nm to 32 nm; and / or, The thickness of the intrinsic silicon oxide layer is 0.4 nm to 3 nm.

7. The solar cell according to claim 6, characterized in that, When the doped layer is an N-type doped layer, the doping concentration of the dopant element in the doped layer is 5% to 7%; and / or, When the doped layer is an N-type doped layer, the doping concentration of the doping element in the doped layer is 0.3% to 1%.

8. The solar cell according to any one of claims 1 to 7, characterized in that, The passivation layer, the intrinsic silicon oxide layer, the doped layer, the transparent conductive layer, and the electrode are symmetrically disposed on the light-receiving surface and the back-lighting surface of the substrate, respectively. The substrate and the doped layer located on the light-receiving side of the substrate have the same conductivity type, while the substrate and the doped layer located on the backlight side of the substrate have opposite conductivity types.

9. The solar cell according to any one of claims 1 to 7, characterized in that, The substrate is an N-type silicon substrate or a P-type silicon substrate; and / or, The transparent conductive layer comprises one or more layers selected from indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, or transparent conductive aluminum-fluorine co-doped zinc oxide; and / or, The electrode is a silver electrode, a copper electrode, an aluminum electrode, or a silver-aluminum electrode.

10. A photovoltaic module, characterized in that, The photovoltaic module includes a solar cell as described in any one of claims 1 to 9.

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