Power amplifier and device comprising power amplifier

Abstract

Provided in the present application is a power amplifier. The power amplifier comprises a driver unit and a power unit, wherein the driver unit comprises N first transistors, a driver input matching network that matches input ends of the N first transistors, and a driver output matching network that matches output ends of the N first transistors; and the power unit comprises M second transistors, a power input matching network that matches input ends of the M second transistors, and a power output matching network that matches output ends of the M second transistors, wherein an output end of the driver output matching network is connected to an input end of the power input matching network, and the first transistors and the second transistors are heterogeneous. On the basis of the power amplifier, when the power of a signal is amplified, nonlinear distortion can be reduced, and the efficiency during power back-off can also be improved.

Description

A power amplifier and a device including the power amplifier.

[0001] This application claims priority to Chinese Patent Application No. 202411745303.6, filed on November 28, 2024, entitled “A Power Amplifier and a Device Including a Power Amplifier”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a power amplifier and a device including the power amplifier. Background Technology

[0003] When communication devices in a communication system communicate with each other, the transmitting end usually amplifies the generated signal through a power amplifier (PA) to meet the communication transmission requirements over a certain distance, thereby enabling communication with the other party.

[0004] However, power amplification via a power amplifier (PA) introduces nonlinear distortion. Therefore, solving the problem of nonlinear distortion has become an urgent technical challenge. Summary of the Invention

[0005] This application provides a power amplifier and an apparatus including the power amplifier. Based on the power amplifier provided by this application, when amplifying the power of a signal, it can reduce the nonlinear distortion of the signal and improve the efficiency during power back-off.

[0006] In a first aspect, this application provides a power amplifier, including a driving unit and a power unit;

[0007] The driving unit includes N first transistors, a driving input matching network that matches the input terminals of the N first transistors, and a driving output matching network that matches the output terminals of the N first transistors.

[0008] The power unit includes M second transistors, a power input matching network that matches the input terminals of the M second transistors, and a power output matching network that matches the output terminals of the M second transistors.

[0009] The input terminal of the driving input matching network is used to receive the first signal of the first power, and the output terminal is connected to the input terminal of N first transistors respectively. The output terminal of N first transistors is connected to the input terminal of the driving output matching network respectively.

[0010] The output terminal of the drive output matching network is connected to the input terminal of the power input matching network, and the output terminal of the power input matching network is connected to the input terminals of M second transistors respectively. The output terminals of the M second transistors are connected to the input terminals of the power output matching network respectively. The output terminal of the power output matching network is used to output the first signal of the second power.

[0011] The first transistor and the second transistor are heterogeneous.

[0012] Optionally, the second power is higher than the first power.

[0013] The power amplifier provided in this application can be considered to include two stages of amplifiers. The driving unit can be considered as the first stage amplifier, and the power unit can be considered as the second stage amplifier. In this way, the gain of the power unit can be compensated by gain expansion through the driving unit, thereby bringing the 1 dB compression point of the power unit closer to the power saturation point of the power unit. This reduces the nonlinear distortion of the first signal output after the first signal passes through the two stages of amplifiers, while also improving the efficiency during power back-off.

[0014] In one possible design, the first transistor is a GaAs pseudomorphic high electron mobility transistor (GaAs pHEMT), and the second transistor is a GaN high electron mobility transistor (GaN HEMT).

[0015] In one possible design, N and M are equal. That is, the number of first transistors in the driving unit is the same as the number of second transistors in the power unit.

[0016] In one possible design, the number of connection points between the drive output matching network and the power input matching network is one or more.

[0017] In one possible design, the drive unit and the power unit are bonded together or eutectic welded, and the drive output matching network and the power input matching network are connected by gold wire bond.

[0018] In one possible design, the drive unit and the power unit are integrated on the same chip.

[0019] Secondly, this application provides a radio frequency device, including the power amplifier and antenna described in the first aspect or any possible implementation thereof; wherein:

[0020] The power amplifier is used to receive a first signal with a first power and output a first signal with a second power, and to send the first signal with the second power to the antenna.

[0021] The antenna is used to transmit a first signal with a second power.

[0022] Thirdly, this application provides a network device including the radio frequency device as described in the second aspect.

[0023] Fourthly, this application provides a terminal including the radio frequency device as described in the second aspect.

[0024] Fifthly, this application provides a communication system, including a network device as described in the third aspect or a terminal as described in the fourth aspect. Attached Figure Description

[0025] Figure 1 shows a schematic diagram of the power amplification of the PA;

[0026] Figure 2 is a schematic diagram of a communication system to which the technical solution of this application can be applied;

[0027] Figure 3 illustrates a fully digital beamforming architecture;

[0028] Figure 4 illustrates a schematic diagram of reducing the distortion level of the PA output signal based on digital predistortion (DPD);

[0029] Figure 5 illustrates a schematic diagram of reducing the distortion of the PA output signal based on DPD in an all-digital beamforming architecture;

[0030] Figure 6 shows a schematic diagram of a fully connected beamforming architecture;

[0031] Figure 7 illustrates a schematic diagram of reducing the distortion of the PA output signal based on analog predistortion (APD).

[0032] Figure 8 shows another schematic diagram for reducing the nonlinear distortion of the signal at the PA output;

[0033] Figure 9 shows a schematic diagram of the power amplifier provided in this application;

[0034] Figure 10 shows a schematic diagram of the gain curve of a power amplifier based on a drive unit and a power unit;

[0035] Figure 11 is a schematic diagram of the drive unit and power unit connected by gold wires according to this application;

[0036] Figures 12 and 13 are circuit diagrams of the power amplifier provided in this application;

[0037] Figure 14 shows schematic diagrams of the input-output curves, gain curves, and efficiency curves for a single power unit and the power amplifier provided in this application, respectively.

[0038] Figure 15 shows schematic diagrams of the AM-PM curves for a single power unit and the power amplifier provided in this application, respectively;

[0039] Figure 16 shows a schematic diagram of another input-output curve, gain curve, and efficiency curve corresponding to a separate power unit and the power amplifier provided in this application, respectively;

[0040] Figure 17 shows a schematic diagram of an RF front-end module;

[0041] Figure 18 shows a schematic diagram of a doherty power amplifier based on a driver unit compensation. Detailed Implementation

[0042] To facilitate understanding, some concepts involved in PA will be explained below.

[0043] 1. PA

[0044] A power amplifier (PA) is a functional module that amplifies the power of an input signal. In many applications, it is necessary to use a PA to boost the input signal to an appropriate level to meet specific requirements.

[0045] Figure 1 shows a schematic diagram of a power amplifier (PA). It can be seen that a PA has a linear region, a nonlinear region, and a saturation region. When the PA operates in the linear region, the output power and input power maintain a linear relationship. When the input power of the PA exceeds the linear region and enters the nonlinear region, the output power and input power have a nonlinear relationship. When the input power reaches the saturation region of the PA, the output power no longer increases with increasing input power.

[0046] 2. PA efficiency

[0047] PA efficiency refers to the PA's ability to convert input power into output power, usually expressed as a percentage. The calculation formula is: PA efficiency equals (output power / input power) × 100%. PA efficiency can also be understood as energy conversion efficiency; high efficiency means less power is lost during power amplification.

[0048] 3. Gain of PA

[0049] The gain of a power amplifier (PA) measures how much it amplifies the input power. It is usually expressed in decibels (dB). The higher the gain, the greater the output power of the amplifier.

[0050] 4. Output power 1dB compression point

[0051] As shown in Figure 1, when the PA operates in the linear region, its output power increases linearly with the input power, and the PA's gain is a constant, called the linear gain. As the input power continues to increase, the PA enters the nonlinear region, and the gain begins to decrease after the output power reaches a certain value. The output power corresponding to a gain that drops 1dB below the linear gain is usually called the 1dB compression point of the output power, and the corresponding input power is called the 1dB compression point of the input power. The 1dB compression point is generally considered an abbreviation for the 1dB compression point of the output power. The 1dB compression point is also commonly referred to as the P-1dB compression point.

[0052] 5. Power back-off of PA

[0053] Power back-off of a PA refers to the process in PA design where, in order to maintain the linearity of the output signal, the PA's output power is reduced by a few decibels from the P-1dB compression point, making the PA's operating point much smaller than the P-1dB compression point.

[0054] 6. AM-AM distortion

[0055] AM-AM distortion refers to the distortion in amplitude between the output signal and the input signal.

[0056] 7. AM-PM distortion

[0057] AM-PM distortion refers to the change in phase difference between the output signal and the input signal caused by the change in the amplitude of the input signal of the nonlinear power amplifier (PA).

[0058] The technical solution of this application will now be described with reference to the accompanying drawings.

[0059] The technical solutions provided in this application can be applied to various communication systems, such as: 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, wireless local area network (WLAN) systems, etc.

[0060] The technical solutions provided in this application can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems.

[0061] The technical solutions provided in this application can also be applied to future communication systems, such as the sixth generation (6G).

[0062] As an example, Figure 2 illustrates an application scenario of the technical solution provided in this application. It is understood that the system architecture described in the embodiments of this application is for the purpose of more clearly illustrating the technical solutions of the embodiments of this application and does not constitute a limitation on the technical solutions provided in the embodiments of this application.

[0063] As shown in Figure 2, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 2, collectively referred to as 110) and at least one terminal (120a-120j in Figure 2, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment (not shown in Figure 2). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0064] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0065] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 2 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 2 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0066] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 2, 110a), a micro base station or indoor station (as shown in Figure 2, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0067] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0068] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0069] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0070] When two communication devices in a communication system communicate, the transmitting end needs to amplify the transmitted signal through a power amplifier (PA) to meet the communication transmission requirements over a certain distance.

[0071] For example, as shown in Figure 3, the baseband signal, after being processed by a digital-to-analog converter (DAC), is superimposed with the signal generated by a local oscillator (LO). This superposition is then amplified by a power amplifier (PA) before being fed to the antenna for radiation. The architecture shown in Figure 3 is also known as an all-digital beamforming architecture. It can be seen that in an all-digital beamforming architecture, one PA corresponds to one DAC, or one PA corresponds to one digital channel.

[0072] When a power amplifier (PA) is used to amplify a signal, nonlinear distortion occurs when the PA operates in the nonlinear region. This degrades the signal's performance, such as causing a decrease in the error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR).

[0073] To reduce the impact of nonlinearity, digital predistortion (DPD) is introduced. DPD is an effective means of improving the linearity of the power amplifier (PA). Its basic principle is to digitally preprocess the signal before it is amplified by the PA, thereby improving the linearity of the transmitted signal. Theoretically, the function output by the DPD should be the inverse function of the function output by the PA. Referring to Figure 4, before the signal is input to the PA, it is digitally preprocessed by the DPD. The signal output by the DPD is also called the digitally predistorted signal. Then, the digitally predistorted signal is amplified by the PA to reduce the impact of the PA's nonlinearity.

[0074] For example, for the all-digital beamforming architecture shown in Figure 3, the nonlinear distortion of the PA output signal can be reduced based on the DPD. As shown in Figure 5, each digital channel signal can correspond to a DPD to reduce the nonlinear distortion of the PA output signal after the signal on each digital channel passes through the PA.

[0075] Figure 6 shows a schematic diagram of a fully connected beamforming architecture. As shown in Figure 6, in a fully connected beamforming architecture, each PA is connected to all digital channels, making it impossible to use a DPD to solve the nonlinear distortion of the PA output signal, also known as DPD failure.

[0076] To address the issue of DPD malfunction, two implementation methods have been proposed to reduce the nonlinear distortion of the PA output signal. These two methods are described below.

[0077] Implementation Method 1:

[0078] As shown in Figure 7, before the signal is input to the PA, the transmitter first preprocesses the signal through analog predistortion (APD). The signal output after the signal passes through the APD is called the analog predistortion signal. Then, the analog predistortion signal is amplified by the PA to reduce the influence of the PA's nonlinearity.

[0079] APDs can be implemented in different ways.

[0080] For example, in one implementation, the function of the APD can be achieved using a series diode predistorter, which includes a Schottky diode and a capacitor connected in parallel with the Schottky diode. This structure can achieve a positive amplitude and a negative phase under low voltage bias. The function of the APD is accomplished by adjusting the bias voltage and the capacitor, thereby making the nonlinearity of the APD completely opposite to that of the PA.

[0081] In another implementation, the APD can be implemented using a parallel diode predistorter.

[0082] In another implementation, the APD can be implemented using a varactor diode. This method primarily improves the nonlinear distortion of the PA output signal through two functional regions. The varactor diode is used to compensate for the AM-PM effect, and second-order harmonic control technology is introduced to compensate for the AM-AM effect of the PA. For example, an APD based on a varactor diode can be applied to a GaAs FET power amplifier. The varactor diode can provide capacitive compensation at the GaAs FET input to eliminate the AM-PM effect of the power amplifier. Second-order harmonic injection technology is used to compensate for the AM-AM nonlinearity of the power amplifier. This effectively eliminates AM-PM and AM-AM distortion, thereby improving the linearity of the power amplifier.

[0083] Implementation Method 2: Calibrate the signal output by PA based on the circuit shown in Figure 8.

[0084] As shown in Figure 8, the RF signal requiring power amplification is input into this circuit and splits into two paths: one goes to the main PA and the other to delay device 1. The signal output from the main PA goes to combiner 1 on one side and delay device 2 on the other. The signal output from delay device 1 enters combiner 1. After receiving the signals from delay device 1 and the main PA, combiner 1 outputs a signal that enters the auxiliary PA. The signals from the auxiliary PA and delay device 2 simultaneously enter combiner 2, which outputs the final power-amplified RF signal.

[0085] In addition to the main frequency signal that needs to be amplified, the output of the main power amplifier (PA) also contains third-order intermodulation interference. The output of delay device 1 and the output of the main PA, after passing through synthesizer 1, can cancel out the main carrier frequency signal included in the main PA output signal. Thus, the signal output by synthesizer 1 only contains the inverted third-order intermodulation component. This third-order intermodulation component, after being amplified by the auxiliary PA, interacts with the intermodulation component output by delay device 2, which cancels out the nonlinearity of the main amplifier, thereby improving the linearity of the final power amplifier.

[0086] However, when improving the linearity of the amplified signal using the two methods described above, the insertion loss of the analog predistorter is relatively large in method one, affecting system efficiency. Method two has high cancellation requirements, necessitating matching of signal amplitude, phase, and time delay, making implementation complex. Furthermore, since the output calibration involves a high power level, the calibration signal needs to be amplified to a high power level, requiring an additional auxiliary amplifier. Moreover, this auxiliary amplifier must have distortion characteristics exceeding the specifications of the feedforward system.

[0087] In view of this, this application provides a power amplifier that, when amplifying the power of a signal, can reduce the nonlinear distortion of the signal while improving the efficiency during power back-off.

[0088] Referring to Figure 9, which is a schematic diagram of a power amplifier provided in this application, the power amplifier 900 includes a drive unit 901 and a power unit 902.

[0089] The driving unit 901 includes N first transistors (Figure 9 only shows 3 as an example), an input matching network 9011 that matches the input terminals of the N first transistors, and an output matching network 9012 that matches the output terminals of the N first transistors.

[0090] In this application, the input matching network that matches the input terminals of the N first transistors is also called the driving input matching network, and the output matching network that matches the output terminals of the N first transistors is also called the driving output matching network. The driving input matching network 9011 can match the input of the first transistor to a first impedance. For example, the first impedance is 50 ohms. The driving output matching network 9012 can match the output of the first transistor to a second impedance, which can be any impedance.

[0091] The power unit 902 includes M second transistors (only 3 are shown in the figure), an input matching network 9021 that matches the input terminals of the M second transistors, and an output matching network 9022 that matches the output terminals of the M second transistors.

[0092] In this application, the input matching network that matches the input terminals of the M second transistors is also called the power input matching network, and the output matching network that matches the output terminals of the M second transistors is also called the power output matching network. The power input matching network 9021 can match the input of the second transistors to the same impedance as the output of the drive output matching network 9012, i.e., the second impedance. The power output matching network 9022 can match the impedance corresponding to the output terminal of the second transistors to the aforementioned first impedance.

[0093] In this application, the first transistor and the second transistor are heterogeneous, which can also be understood as the first transistor and the second transistor being made of different materials. That is, the first transistor and the second transistor are made of different semiconductor materials. Optionally, the first transistor is a GaAs PHEMT and the second device is a GaN HEMT.

[0094] As shown in Figure 9, the input terminal of the drive input matching network 9011 is used to receive the first signal with the first power, and the output terminal of the drive input matching network 9011 is connected to the input terminals of N first transistors. Alternatively, it can be understood that the drive input matching network 9011 can receive the first signal with the first power, and the N first transistors can receive the signal output by the drive input matching network 9011.

[0095] The outputs of the N first transistors are each connected to the input of the output matching network 9012. This can also be understood as the output matching network 9012 receiving signals from the N first transistors.

[0096] The output of the drive output matching network 9012 is connected to the input of the power input matching network 9021. This can also be understood as the power input matching network 9021 receiving the signal output from the drive output matching network 9012.

[0097] The output of the power input matching network 9021 is connected to the input of each of the M second transistors. This can also be understood as the M second transistors receiving the signal output from the power input matching network 9021.

[0098] The outputs of the M second transistors are each connected to the input of the power output matching network 9022. That is, the power output matching network 9022 can receive the signals output by the M second transistors.

[0099] The output of the power output matching network 9022 is used to output the first signal of the second power.

[0100] Understandably, from the perspective of the flow of the first signal, when the power amplifier 900 shown in Figure 9 receives the first signal of the first power, the first signal will sequentially pass through the drive input matching network 9011, N first transistors, drive output matching network 9012, power input matching network 9021, M second transistors, and power output matching network 9022, and finally output the first signal of the second power.

[0101] Alternatively, it can be understood that after the first signal is input to the power amplifier 900, the drive input matching network 9011 processes the first signal and outputs a signal. The signal output by the drive input matching network 9011 enters N first transistors and is output by N first transistors. The signal output by the N first transistors enters the drive output matching network 9012 and is output by the drive output matching network 9012. The signal output by the drive output matching network 9012 enters the power input matching network 9021 and is output by the power input matching network 9021. The signal output by the power input matching network 9021 enters M second transistors and is output by the M second transistors. The signal output by the M second transistors enters the power output matching network 9022 and is output by the power output matching network 9022, which then outputs the final second power first signal.

[0102] Optionally, the second power is greater than the first power.

[0103] Optionally, the first transistor and the second transistor can be used for signal power amplification. Therefore, in this application, the driving unit including the first transistor is also referred to as the first-stage PA, and the power unit including the second transistor is also referred to as the second-stage PA. That is to say, the power amplifier 900 provided in this application can be considered to include a first-stage PA (i.e., driving unit) composed of the first transistor and a second-stage PA (i.e., power unit) composed of the second transistor.

[0104] The power amplifier 900 provided in this application, when the power unit exhibits a slow compression characteristic (the output power of the power unit slowly reaches saturation as the input power increases), can, in practice, achieve a gain expansion characteristic (the gain of the drive unit increases as the input power increases) through the drive unit. This gain expansion of the drive unit compensates for the slow compression characteristic of the power unit, bringing the P-1dB point of the power unit closer to its power saturation point. This allows for reduced nonlinear distortion and improved efficiency during power back-off when amplifying signal power. Alternatively, it can be understood as designing the first-stage PA with a power distortion response opposite to that of the second-stage PA to compensate for the nonlinear characteristics of the second-stage PA, without introducing additional losses and resulting in a simple structure.

[0105] Referring to Figure 10, which shows the gain curves of the driving unit, the power unit, and the overall PA (Power Amplifier) ​​including both the driving unit and the power unit, it can be seen that the gain expansion achieved by the driving unit compensates for the slow compression characteristics of the power unit. This is equivalent to bringing the P-1dB point of the power unit closer to its power saturation point, thereby reducing nonlinear distortion and improving efficiency during power back-off when amplifying signal power.

[0106] This application does not limit the number of connection points between the power unit and the drive unit, that is, it does not limit the number of connection points between the drive output matching network 9012 and the power input matching network 9021. For example, there may be one connection point or multiple connection points. That is, the number of connection points between the power unit and the drive unit is K, where K can be equal to 1 or a positive integer greater than 1.

[0107] In one implementation, the drive unit and power unit are bonded or eutectic soldered to a carrier plate, for example, by bonding or eutectic soldering the power unit together. The drive unit and power unit are connected by gold wire bonding. Figure 11 shows a schematic diagram of the connection between the drive output matching network and the power input matching network via gold wire bonding.

[0108] In another implementation, advanced substrate transfer and growth techniques are employed to integrate the drive unit and power unit with the wafer growth process. For example, a diamond substrate can be used. Specifically, the process is as follows: 1. A SiN protective film is grown on the surface of the fabricated GaAs and GaN wafers using in-situ growth techniques or low-pressure chemical vapor deposition (LPCVD) to protect the active region of the wafer; 2. A temporary Si substrate is bonded to the outside of the protective film using surface activated bonding (SAB); 3. The original GaAs or SiC substrate is thinned, and the temporary Si substrate is debonded using hydrofluoric acid; 4. A nanometer-thick Si bonding layer is deposited on the diamond substrate using rapid Ar atom bombardment; 5. Oxides and contaminants on the wafer surface are removed using surface activation techniques; 6. The GaAs and GaN wafers are pressure-bonded onto the diamond substrate; 7. Passive circuits and interconnect metals are fabricated using semiconductor back-end processes.

[0109] It should be noted that Figure 9 is only an example with N=3 and M=3, but it does not constitute a limitation of this application.

[0110] For example, N and M can be the same.

[0111] For example, N and M can also be different.

[0112] For example, N can be a positive integer less than 3 or a positive integer greater than 3.

[0113] For example, M can be a positive integer less than 3 or a positive integer greater than 3.

[0114] The following, referring to Figure 12, describes a circuit of an overall PA including a driving unit and a power unit, taking as an example that the driving unit includes two first transistors, the first transistors being GaAs pHEM, and the power unit includes two second transistors, the second transistors being GaN HEMT.

[0115] As shown in Figure 12, the drive unit includes input port 11; output ports 12 and 13; transmission lines TL11, TL12, and TL13; capacitors C11, C12, C13, C14, C15, C16, C17, C18, C19, C10, and C20; resistors R11, R12, R13, and R14; inductors L11, L12, L13, and L14; and two GaAs pHEMs. Among these:

[0116] The first end of transmission line TL11 and the first end of capacitor C11 are both connected to input port 11. Input port 11 can receive a first signal of first power. The second end of transmission line TL11 is grounded. The second end of capacitor C11 is connected to the first ends of capacitor C12 and capacitor C13.

[0117] The second terminal of capacitor C12 and the first terminal of resistor R12 are both connected to the first terminal of resistor R11. The second terminal of resistor R11 is connected to the first terminal of inductor L11. The second terminal of inductor L11 and the first terminal of capacitor C14 are both connected to the power supply, and the second terminal of capacitor C14 is grounded. The second terminal of resistor R12 is connected to the gate of the GaAs PHEMT. The drain of the GaAs PHEMT and the first terminal of capacitor C16 are both connected to the first terminal of inductor L12. The second terminal of inductor L12 and the first terminal of capacitor C15 are both connected to the power supply, and the other terminal of capacitor C15 is grounded. The second terminal of capacitor C16 is connected to the first terminal of transmission line TL12. The second terminal of transmission line TL12 and the first terminal of capacitor C17 are both connected to output port 12, and the second terminal of capacitor C17 is grounded.

[0118] The second terminal of capacitor C13 and the first terminal of resistor R14 are both connected to the first terminal of resistor R13. The second terminal of resistor R13 is connected to the first terminal of inductor L13. The second terminal of inductor L13 and the first terminal of capacitor C18 are both connected to the power supply, and the second terminal of capacitor C18 is grounded. The second terminal of resistor R14 is connected to the gate of GaAs PHEMT. The drain of GaAs PHEMT and the first terminal of capacitor C10 are both connected to the first terminal of inductor L14. The second terminal of inductor L14 and the first terminal of capacitor C19 are both connected to the power supply, and the other terminal of capacitor C19 is grounded. The second terminal of capacitor C10 is connected to the first terminal of transmission line R13. The second terminal of transmission line R13 and the first terminal of capacitor C20 are both connected to output port 13, and the second terminal of capacitor C20 is grounded.

[0119] The sources of GaAs PHEMTs are all grounded.

[0120] The power unit includes: input port 21, input port 22; output port 23; transmission lines TL21, TL22, TL23, TL24, TL25, TL26, TL27, TL28, TL29, TL30, and TL31; capacitors C21, C22, C23, C24, C25, C26, C27, and C28; resistors R21, RL22, R23, and R24; two GaN HEMTs; and output port 23.

[0121] As shown in Figure 12, for the power unit:

[0122] The first end of transmission line TL21 and the first end of capacitor C21 are both connected to input port 21, and the second end of transmission line TL21 is grounded. The second end of capacitor C21 is connected to the first end of transmission line TL22 and the first end of capacitor C22; the second end of capacitor C22 is grounded. The second end of transmission line TL22 is connected to the first end of resistor R21 and the first end of resistor R22. The second end of resistor R21 is connected to the first end of transmission line TL23. The second end of transmission line TL23 and the first end of capacitor C23 are both connected to the power supply; the second end of resistor R22 is connected to the gate of GaN HEMT; the drain of GaN HEMT1 is connected to the first end of transmission line TL24.

[0123] The first end of transmission line TL25 and the first end of capacitor C24 are both connected to input port 22, and the second end of transmission line TL25 is grounded. The second end of capacitor C24 is connected to the first end of transmission line TL26 and the first end of capacitor C25; the second end of capacitor C25 is grounded. The second end of transmission line TL26 is connected to the first end of resistor R23 and the first end of resistor R24. The second end of resistor R23 is connected to the first end of transmission line TL27. The second end of transmission line TL27 and the first end of capacitor C26 are both connected to the power supply; the second end of resistor R24 ​​is connected to the gate of the GaN HEMT; the drain of GaN HEMT1 is connected to the first end of transmission line TL28.

[0124] The sources of GaN HEMTs are all grounded.

[0125] The second end of transmission line TL24, the second end of transmission line TL28, the first end of transmission line TL29, and the first end of transmission line TL30 are all connected to the first end of capacitor C28. The second end of transmission line TL29 and the first end of capacitor C27 are both connected to the power supply, and the second end of capacitor C27 is grounded. The second end of capacitor C28 and the first end of transmission line TL31 are both connected to output port 23, and the second end of transmission line TL31 is grounded. Output port 23 can output the first signal of the second power.

[0126] Understandably, the circuit located before the GaAs PHEMT in the driving unit of Figure 12 can be considered as the driving input matching network in this application, and the circuit located after the GaAs PHEMT can be considered as the driving output matching network in this application; the circuit located before the GaN HEMT in the power unit can be considered as the power input matching network in this application, and the circuit located after the GaN HEMT can be considered as the power output matching network in this application.

[0127] For example, in the example of Figure 12, the input matching network of the GaAs pHEMT is used to match the impedance corresponding to the input of the GaAs pHEMT to 50 ohms, and the output matching network of the GaAs pHEMT is used to match the impedance corresponding to the output of the GaAs pHEMT to a second impedance, which can be any impedance; the input matching network of the GaN HEMT is used to match the impedance corresponding to the input of the GaN HEMT to a second impedance, and the output matching network of the GaN HEMT is used to match the impedance corresponding to the output of the GaN HEMT to a first impedance.

[0128] It should be noted that Figure 12 is merely an example illustrating one circuit of a power amplifier (PA) including a driving unit comprising one GaAs pHEM and a power unit comprising one GaN HEMT. However, it is understood that the above example does not constitute a limitation of this application.

[0129] For example, the driving unit may include a GaAs pHEM, a driving input matching network that matches the input of the GaAs pHEM, and a driving output matching network that matches the output of the GaAs pHEM.

[0130] For example, a power unit may include a GaN HEMT, a power input matching network that matches the input of the GaN HEMT, and a power output matching network that matches the output of the GaN HEMT.

[0131] For example, the driving unit may include more than two GaAs pHEMs, a driving input matching network that matches the inputs of the more than two GaAs pHEMs, and a driving output matching network that matches the outputs of the more than two GaAs pHEMs.

[0132] For example, a power unit may include more than two GaN HEMTs, a power input matching network that matches the inputs of the more than two GaN HEMTs, and a power output matching network that matches the outputs of the more than two GaN HEMTs.

[0133] For example, referring to Figure 13, taking the driving unit as an example including a GaAs pHEM and the power unit as an example including a GaN HEMT, a circuit of an overall PA including the driving unit and the power unit is described.

[0134] As shown in Figure 13, the drive unit includes an input port 11; an output port 12; transmission lines TL11 and TL12; capacitors C12, C14, C15, C16, and C17; resistors R11 and R12; inductors L11 and L12; and one GaAs pHEM.

[0135] in:

[0136] The first end of transmission line TL11 and the first end of capacitor C12 are both connected to input port 11. The input port can receive a first signal with first power. The second end of transmission line TL11 is grounded.

[0137] The second terminal of capacitor C12 and the first terminal of resistor R12 are both connected to the first terminal of resistor R11. The second terminal of resistor R11 is connected to the first terminal of inductor L11. The second terminal of inductor L11 and the first terminal of capacitor C14 are both connected to the power supply, and the second terminal of capacitor C14 is grounded. The second terminal of resistor R12 is connected to the gate of GaAs PHEMT. The drain of GaAs PHEMT and the first terminal of capacitor C16 are both connected to the first terminal of inductor L12. The second terminal of inductor L12 and the first terminal of capacitor C15 are both connected to the power supply, and the other terminal of capacitor C15 is grounded. The second terminal of capacitor C16 is connected to the first terminal of transmission line TL 12. The second terminal of transmission line TL 12 and the first terminal of capacitor C17 are both connected to output port 12, and the second terminal of capacitor C17 is grounded.

[0138] The power unit includes: input port 21; output port 23; resistor 21, transmission line TL22, transmission line TL23, transmission line TL24, transmission line TL29, transmission line TL31; capacitors C21, C22, C23, C27, and C28; resistors R21 and R22; and one GaN HEMT.

[0139] As shown in Figure 13, for the power unit:

[0140] The first end of transmission line TL21 and the first end of capacitor C21 are both connected to input port 21, and the second end of transmission line TL21 is grounded. The second end of capacitor C21 is connected to the first end of transmission line TL22 and the first end of capacitor C22; the second end of capacitor C22 is grounded. The second end of transmission line TL22 is connected to the first end of resistor R21 and the first end of resistor R22. The second end of resistor R21 is connected to the first end of transmission line TL23. The second end of transmission line TL23 and the first end of capacitor C23 are both connected to the power supply; the second end of resistor R22 is connected to the gate of GaN HEMT; the drain of GaN HEMT1 is connected to the first end of transmission line TL24, and the source of GaN HEMT1 is grounded.

[0141] The second end of transmission line TL24 and the first end of transmission line TL29 are both connected to the first end of capacitor C28. The second end of transmission line TL29 and the first end of capacitor C27 are both connected to the power supply. The second end of capacitor C27 is grounded. The second end of capacitor C28 and the first end of transmission line TL31 are both connected to output port 23. The second end of transmission line TL31 is grounded. Output port 23 can output the first signal of the second power.

[0142] Referring to Figure 14, Figure 14(a) shows a circuit based on the power amplifier shown in Figure 12, and a schematic diagram of the power unit's power curve, efficiency curve, and gain curve when the power unit (second stage PA) is not compensated by the driving unit (first stage PA). Figure 14(b) shows a schematic diagram of the power amplifier's power curve, efficiency curve, and gain curve based on the power amplifier provided in this application where the power unit (second stage PA) is compensated by the driving unit (first stage PA).

[0143] As shown in Figure 14(a), for a power unit that does not compensate for the power unit (second stage PA) through the drive unit (first stage PA), when the input power is 0.500, the gain is approximately between 14.200 and 14.833, the output power is approximately between 13.700 and 14.333, and the efficiency is approximately between 2.666 and 3.008; when the input power is 12.000, the gain is approximately between 13.913 and 14.364, the output power is approximately between 25.913 and 26.364, and the efficiency is approximately between 18.329 and 18.548; when the input power is 20.000, the gain is approximately between 13.245 and 13.567, the output power is approximately between 33.245 and 33.567, and the efficiency is approximately between 43.641 and 45.344.

[0144] As shown in Figure 14(b), based on the power amplifier 900 provided in this application that compensates the power unit (second stage PA) through the driving unit (first stage PA), the gain is approximately between 22.971 and 23.665, the output power is approximately between 18.971 and 19.683, and the efficiency is approximately between 4.289 and 4.851 when the input power is -4.000; the gain is approximately between 22.469 and 23.626 when the input power is 7.500, the output power is approximately between 29.969 and 31.126, and the efficiency is approximately between 21.140 and 24.271; and the gain is approximately between 21.915 and 22.555 when the input power is 15.500, the output power is approximately between 37.415 and 38.055, and the efficiency is approximately between 49.646 and 54.011.

[0145] It can be seen that, based on the compensation of the power unit (second stage PA) by the drive unit (first stage PA), the P-1dB compression point is increased from 33.5 dBm to 37.8 dBm, and the efficiency of the P-1dB compression point back to the operating point by 8dB is increased from 18% to 21-24%.

[0146] Figure 15 shows a schematic diagram of the AM-PM curve of the power unit when the power unit (second stage PA) is not compensated by the drive unit (first stage PA). Figure 15(b) shows a schematic diagram of the AM-PM curve of the power amplifier 900 after the power unit (second stage PA) is compensated by the drive unit (first stage PA) according to the present application.

[0147] As shown in Figure 15(a), when the input power is -8.500 (m6 position in Figure 15(a)), the AM-PM distortion of the output signal is approximately 132.140; when the input power is 22.500 (m5 position in Figure 15(a)), the AM-PM distortion of the output signal is approximately 144.437.

[0148] As shown in Figure 15(b), when the input power is -12.000 (m7 position in Figure 15(b)), the AM-PM distortion of the output signal is approximately -75.619; when the input power is 20.000 (m6 position in Figure 15(b)), the AM-PM distortion of the output signal is approximately -75.789.

[0149] It can be seen that after the power unit (second-stage PA) is compensated by the drive unit (first-stage PA), the AM-PM distortion of the second-stage PA is also improved. Before compensation, the distortion value is about 12° (144.437-132.140), and after compensation, it does not exceed 3°. The distortion value can be considered as the difference between the phase of the output voltage under high input power and the phase of the output voltage under low input power.

[0150] Referring to Figure 16, Figure 16 shows a schematic diagram of the power, efficiency, and gain curves of the power amplifier circuit based on the power amplifier shown in Figure 13, the corresponding drive unit (first stage PA), the power unit (second stage PA), and the power amplifier (the overall PA composed of the first stage PA and the second stage PA) formed by the drive unit and the power unit.

[0151] As shown in Figure 16, for the second-stage PA using GaN HEMT, the gain is 13.498, the output power is 15.498, and the efficiency is 2.164 when the input power is 2.0000; the gain is 13.123 when the input power is 13.0000, the output power is 26.123, and the efficiency is 16.813; and the gain is 12.416 when the input power is 21.0000, the output power is 33.416, and the efficiency is 43.779. It can be seen that the power unit (i.e., the second-stage PA) using GaN HEMT has high efficiency characteristics, but the distance between the P-1dB point and the power saturation point (also known as the Psat point) is more than 8dB. This means that when the power drops back 8dB from the P-1dB point to the operating point (represented by the Pavg point), the amplification efficiency of the second-stage PA will drop significantly if there is no driving unit. As shown in Figure 16, the amplification efficiency of the second-stage PA drops from 43.7979 to 16.813.

[0152] However, after adding the first-stage PA, as shown in Figure 16, the first-stage PA is designed with gain expansion characteristics (the characteristic that the amplifier gain increases with the increase of input power). As shown in Figure 16, for the first-stage PA using GaAs pHEMT, at an input power of -7.0000, the gain is 11.327, the output power is 4.327, and the efficiency is 4.751; at an input power of 8.0000, the gain is 13.410, the output power is 21.410, and the efficiency is 44.475. It can be seen that when the output power of the first-stage PA is 21dB, the gain expands by 2dB to compensate for the soft compression characteristic of the second-stage PA (the characteristic that the output power slowly reaches saturation with the increase of input power). As shown in Figure 16, after compensating the second-stage PA with the first-stage PA, the P-1dB of the entire power amplifier, including both the first and second-stage PAs, is 34.726. Compared to the P-1dB of 33.4 without the first-stage PA compensation, the P-1dB point has advanced by 1.5dB, bringing it closer to the Psat point. This embodiment reduces the PA's nonlinearity while also improving efficiency during power back-off.

[0153] This application also provides a radio frequency device, which includes the power amplifier 900 and antenna provided above; wherein, the power amplifier 900 is used to receive a first signal with a first power and output a first signal with a second power and transmit the first signal with the second power to the antenna; the antenna is used to transmit the first signal with the second power.

[0154] For example, Figure 17 shows a schematic diagram of a radio frequency (RF) device provided in this application. As shown in Figure 17, the RF device is connected to a mixer and an amplifier circuit. The RF device includes a silicon-based phased array chip, a power amplifier (PA), a low-noise amplifier (LNA), an antenna, etc. In practice, the power amplifier 900 provided in the above embodiments of this application can be used for the PA in Figure 17.

[0155] Optionally, the aforementioned power unit is a Doherty amplifier. That is, by connecting a driver unit before the Doherty amplifier to compensate for the Doherty amplifier, the linearity of the signal output from the Doherty amplifier after passing through the driver unit and the Doherty amplifier is improved. Thus, when amplifying the signal power, the nonlinear distortion of the signal can be reduced while the efficiency of power back-off is improved.

[0156] For example, Figure 18 shows a schematic diagram of a Doherty amplifier provided in this application. As shown in Figure 18, it includes a main connector (IMN_main), an auxiliary connector (IMN_Aux); resistors L181 and L182; inductors L181, L182, L183, and L184; a DC block; and an output match network (OMN). The connection relationship of each device is shown in Figure 18 and will not be described in detail. In the figure, Vgm is the main gate bias, Vga is the auxiliary gate bias, and Vd is the drain bias.

[0157] As shown in Figure 18, a driving unit, such as a driving unit including a GaAs pHEM device, can be connected before the Doherty amplifier to improve the nonlinear distortion of the signal output through the Doherty amplifier and at the same time improve the efficiency during back-off.

[0158] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0159] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power amplifier, characterized in that, The device includes a driving unit and a power unit. The driving unit includes N first transistors, a driving input matching network that matches the input terminals of the N first transistors, and a driving output matching network that matches the output terminals of the N first transistors. The power unit includes M second transistors, a power input matching network that matches the input terminals of the M second transistors, and a power output matching network that matches the output terminals of the M second transistors. The input terminal of the driving input matching network is used to receive a first signal of a first power, and the output terminal is connected to the input terminal of the N first transistors respectively. The output terminal of the N first transistors is connected to the input terminal of the driving output matching network respectively. The output terminal of the drive output matching network is connected to the input terminal of the power input matching network, and the output terminal of the power input matching network is connected to the input terminals of the M second transistors respectively. The output terminals of the M second transistors are connected to the input terminals of the power output matching network respectively. The output terminal of the power output matching network is used to output the first signal of the second power. The first transistor and the second transistor are heterogeneous.

2. The power amplifier according to claim 1, characterized in that, The first transistor is a gallium arsenide pseudo-matched high electron mobility transistor (GaAs pHEMT), and the second transistor is a gallium nitride high electron mobility transistor (GaN HEMT).

3. The power amplifier according to claim 1 or 2, characterized in that, N is equal to M.

4. The power amplifier according to any one of claims 1 to 3, characterized in that, The number of connection points between the drive output matching network and the power input matching network is one or more.

5. The power amplifier according to claim 4, characterized in that, The drive unit and the power unit are bonded together or eutectic welded together, and the drive output matching network and the power input matching network are connected by gold wire bond.

6. The power amplifier according to any one of claims 1 to 4, characterized in that, The driving unit and the power unit are integrated on the same chip.

7. A radio frequency device, characterized in that, Including the power amplifier and antenna as described in any one of claims 1 to 6; The power amplifier is used to receive a first signal with a first power and output a first signal with a second power, and to send the first signal with the second power to the antenna. The antenna is used to transmit a first signal with the second power.

8. A network device, characterized in that, Includes the radio frequency device as described in claim 7.

9. A terminal, characterized in that, Includes the radio frequency device as described in claim 7.

10. A communication system, characterized in that, This includes the network device as described in claim 8 or the terminal as described in claim 9.

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