Hybrid analog-to-digital conversion device and method, and sensor signal processing device comprising same

Abstract

A hybrid analog-to-digital conversion device and method, and a sensor signal processing device comprising same are disclosed. The hybrid analog-to-digital conversion device for generating a digital output of N (N is a natural number greater than or equal to 1) bits, according to one embodiment of the present invention, comprises a control-logic circuit, n (n is a natural number greater than or equal to 1) comparators, and a reference voltage generation circuit, wherein the control-logic circuit controls the reference voltage generation circuit according to comparison outputs of the comparators so as to adjust a reference voltage or an input signal voltage to be applied to one comparator or at least one of a plurality of comparators.

Description

Hybrid analog-to-digital converter, method, and sensor signal processing device including the same

[0001] The present invention relates to an analog-to-digital converter (ADC) for converting an analog voltage into a digital signal, and more specifically, to a new hybrid ADC technology that overcomes the high-resolution implementation limitations of existing high-speed flash ADCs and enables conversion and processing in a single step, like a flash ADC, without the need for multiple steps such as the Successive Approximation Register (SAR) method.

[0002] Analog-to-digital converters (ADCs) are widely used to digitize analog signals generated by sensors or measurement targets at a constant resolution. Generally, ADCs process continuous physical quantities, such as voltage or current, by sampling them at regular time intervals and quantizing them into digital values. This ADC technology has played a core role in various electronic systems, and various architectures have been developed to meet the required resolution and speed.

[0003] Conventional ADC structures are broadly classified into Flash ADC and Successive Approximation Register (SAR) ADC methods. Flash ADCs are widely used in fields requiring ultra-high-speed computation, such as communications and image processing, due to the advantage of acquiring digital signals very quickly with a single sampling by arranging multiple comparators in parallel. However, as the resolution increases, 2 N Since it requires one or more comparators, for example, 1,023 comparators must be used to implement 10-bit resolution. This causes a sharp increase in chip area and power consumption, and also increases the complexity of the reference voltage generation circuit. In particular, when a high number of bits is required, circuit design becomes even more challenging because reference voltages must be generated down to very small units.

[0004] In contrast, a SAR ADC uses a single comparator to adjust the reference voltage stepwise and compare it with the input signal. While this method is advantageous for miniaturization and low power consumption due to the small number of comparators, its conversion speed is relatively lower compared to Flash ADCs because each bit must be determined sequentially. Furthermore, when implementing high-resolution ADCs, the reference voltage must be generated and controlled with high fineness and precision, which increases circuit complexity and limits the conversion speed.

[0005] As such, since Flash ADCs and SAR ADCs each have limitations in the simultaneous implementation of high speed and high resolution, research on hybrid ADCs has been conducted to combine the advantages of both methods. However, most previously proposed hybrid ADCs still suffered from drawbacks such as high hardware complexity and high power consumption, often involving multiple sequential steps or the inclusion of complex internal ADC modules. Particularly in high-resolution domains exceeding 12 bits, accurately generating and stably comparing extremely small reference voltage units has been a challenging task for Flash ADCs, SAR ADCs, and simple hybrid structures alike. For example, the reference voltage V REF In the case of a 24-bit ADC with a voltage of 1V, the least significant bit must accurately detect a very small voltage of 1 / 16,777,216 V, so it is susceptible to noise and requires extremely strict control during the manufacturing process.

[0006] For this reason, there has been a persistent need for new ADC structures capable of achieving higher resolution while using a smaller number of comparators and simultaneously supporting high-speed processing. There is a demand for hybrid ADC design methods that simultaneously satisfy high-speed and high-resolution conversion with low power consumption and small area by actively controlling the reference voltage or input signal voltage according to each comparison stage while maintaining the advantages of a parallel structure. In fact, research is underway on new architectures that can drastically reduce the number of comparators and power consumption compared to conventional flash ADCs, alleviate speed limitations of SAR ADCs, and lower design difficulty even at high resolutions.

[0007] Meanwhile, there is also a need for improvement in the digital conversion of sensor signals. Conventional sensor signal processing devices primarily use a method of converting the change in the sensor's resistance or capacitance into a pulse width form and counting the time corresponding to that pulse width to obtain a digital value. However, this pulse width-measurement method has limitations in that the overall conversion speed is slow and inefficient because it requires a time delay to generate the pulse width and a counter operation. Accordingly, there is a growing need for an ADC structure that can rapidly digitize analog signals obtained from sensors without additional complex calculations.

[0008] The aforementioned background technology is technical information that the inventor possessed for the derivation of the present invention or acquired during the process of deriving the present invention, and it cannot be considered as prior art disclosed to the general public prior to the filing of the present invention.

[0009] One objective of an embodiment of the present invention is to provide a hybrid ADC device and method capable of achieving low power consumption, miniaturization, and design simplification by significantly reducing the number of comparators and combining the stepwise comparison and control-logic methods of a SAR ADC in parallel or serial and parallel, while securing a fast conversion speed at the level of a Flash ADC.

[0010] One objective of an embodiment of the present invention is to provide a hybrid ADC device and method of ultra-high resolution that is difficult to implement with a general SAR method, by controlling the input signal voltage or reference voltage by dividing it into multiple groups or by modifying and repeatedly comparing the input signal voltage itself, in order to enable stable reference voltage generation even at high resolution.

[0011] One objective of an embodiment of the present invention is to provide a sensor signal processing device capable of directly converting an analog signal obtained from a change in the resistance or capacitance of a sensor into a high-speed digital signal without additional time delay by simplifying the sensor interface.

[0012] The purpose of the embodiments of the present invention is not limited to the problems mentioned above, and other unmentioned purposes and advantages of the present invention may be understood from the following description and will be more clearly understood by the embodiments of the present invention. Furthermore, it will be understood that the purposes and advantages of the present invention can be realized by the means and combinations thereof set forth in the claims.

[0013] A hybrid analog-to-digital converter device according to one embodiment of the present invention is a hybrid analog-to-digital converter device that generates a digital output of N bits (N≥1, natural number), comprising: a control logic circuit; and n comparators (n≥1, natural number), wherein the comparators are input signal voltages (V A ) and a reference voltage are compared to generate a comparison output; the reference voltage generating circuit includes a circuit that provides a reference voltage preset to the comparator, and the control-logic circuit controls the reference voltage generating circuit according to the comparison output of the comparator, so as to provide the reference voltage or the input signal voltage (V) that is applied to one comparator or at least one of a plurality of comparators. A ) can be adjusted.

[0014] In addition to this, other methods for implementing the present invention, other systems, and computer-readable recording media storing a computer program for executing said methods may be further provided.

[0015] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention.

[0016] According to an embodiment of the present invention, the hybrid ADC has the effect of achieving high resolution by drastically reducing the massive number of comparators required in the flash structure while maintaining the fast conversion speed of the existing flash ADC. For example, in a conventional flash ADC based on 10 bits, 1,023 comparators were required, but in the present invention, 10-bit conversion is possible with only 10 comparators, so chip area and power consumption can be significantly reduced. Accordingly, by combining the high speed of flash with the power and area efficiency of SAR, and achieving the precision and noise averaging aspects provided by the double-integration method within a single architecture, the constraint of having to select different ADCs for each application is alleviated, and a wide range of requirements can be covered with a single hybrid ADC.

[0017] Furthermore, the hybrid ADC according to the present invention has the effect of enabling stable and practical voltage comparison even in ultra-high resolution regions of 24 bits or more by applying a parallel group method or an input signal voltage transformation method. In other words, by controlling the input signal or reference voltage by dividing it into multiple stages, ADC operation can be implemented even in ultra-high resolutions that are difficult to achieve with a general SAR structure. In particular, according to the present invention, the reference voltage can be efficiently subdivided and generated, thereby mitigating the noise sensitivity problem caused by reference voltage subdivision at high resolutions. This implies that it can be practically applied even in precision measurement regions where the conventional dual-slope method was mainly used.

[0018] In addition, the hybrid ADC according to the present invention provides various hybrid structures (parallel, serial, mixed parallel-serial, circular, etc.) that combine the advantages of flash and SAR, thereby enabling flexible design optimization according to the required resolution (number of bits), speed, power consumption, etc. For example, the interface between the comparator and the control-logic circuit is simplified, which can significantly reduce complex reference voltage division and noise issues that were problematic in conventional high-resolution ADC designs. Furthermore, circuit resources are saved and design difficulty is eased due to the reduction in the number of comparators, allowing for stable performance even when implementing high bit counts.

[0019] Furthermore, conventionally, individual designs had to be performed by selecting one of Flash, SAR, or double integral depending on the requirements of application services (speed, resolution, power, noise immunity), but the present invention can accommodate different level requirements with a single ADC platform by selecting parallel operation, circular operation, or mixed serial and parallel operation. This allows for not only a reduction in chip area and power consumption due to a decrease in the number of comparators, but also the management of reference voltage distribution and noise vulnerability issues during high-resolution implementation within a consistent structure.

[0020] The hybrid ADC according to the present invention can satisfy the requirements of fields requiring both high resolution and high speed simultaneously, such as high-speed signal processing, AI computation, and image sensors. Even in systems requiring complex computations or deep neural network processing, the ADC of the present invention provides high-performance analog-to-digital conversion with low power consumption and a small footprint, thereby offering the effect of being easily integrated into the system.

[0021] Furthermore, according to the sensor interface combination form of the present invention, the sensor output signal can be directly digitally converted without a separate time delay, thereby improving the sensor signal processing speed. Compared to conventional indirect conversion methods such as pulse width measurement, the present invention has the advantage of enabling near real-time sensor data acquisition because it directly inputs the voltage acquired from the sensor into an ADC for processing.

[0022] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0023] Figure 1 is a schematic diagram showing the basic operation structure of a Flash ADC and a SAR ADC.

[0024] FIG. 2 is a diagram showing the overall configuration of a parallel hybrid ADC that combines the advantages of a flash ADC and a SAR ADC according to one embodiment of the present invention.

[0025] FIGS. 3 to 5 illustrate three reference voltage generation methods that can be used when implementing the parallel hybrid ADC of FIG. 2, where FIG. 3 illustrates a current source-based method, FIG. 4 illustrates a resistor voltage divider method, and FIG. 5 illustrates a capacitor-based method.

[0026] FIGS. 6 to 8 illustrate a method of designing reference voltages in steps from MSB to LSB using an 8-bit ADC as an example, utilizing the reference voltage generation method of FIG. 2, where FIG. 6 illustrates the upper 4-bit generation unit, FIG. 7 illustrates the middle 2-bit generation unit, and FIG. 8 illustrates the lower 2-bit generation unit.

[0027] FIG. 9 is a diagram showing the process of simultaneously comparing the reference voltages from MSB to LSB and the input signal voltage according to FIGS. 6 to 8 on the time axis. It illustrates an exemplary operation flow in which each comparison result is immediately reflected in the determination of the reference voltage for the next comparison.

[0028] FIG. 10 is a diagram briefly illustrating examples of circuits that generate a reference voltage in FIG. 9, wherein (a) shows a current-based resistance control circuit, (b) shows a resistance-based current control circuit, and (c) shows a capacitor-based current control circuit.

[0029] Figure 11 shows the process of Figures 6 to 8 in the form of a flowchart, illustrating the process in which the parallel hybrid ADC proceeds step by step from MSB comparison to LSB comparison, and each comparison result is immediately reflected in the next step of comparison.

[0030] Figure 12 is a diagram showing a parallel-group hybrid ADC configuration for realizing high resolution by dividing the parallel hybrid ADC structure into several groups.

[0031] FIGS. 13 and FIGS. 14 are exemplary drawings illustrating a method for comparing input signal voltage (VA) by modifying it for high resolution (Fig. 13) and an input signal voltage generation circuit for implementing ultra-high resolution (Fig. 14).

[0032] FIG. 15 is a conceptual diagram of a series-circulating hybrid ADC, wherein the reference voltage is 1 / 2 V REF This is a diagram showing an operation that fixes the input signal voltage and performs a comparison at each step while gradually changing the input signal voltage.

[0033] FIG. 16 illustrates how the input voltage is transformed step by step for an example of an actual input signal voltage (e.g., 0.46 V, 0.94 V, etc.) for the cyclic hybrid ADC of FIG. 15. FIG. 16(a) and FIG. 16(b) respectively illustrate the process of generating and comparing the next step input voltage according to the transformation formula.

[0034] Figure 17 is a diagram illustrating the step-by-step voltage transformation process in a different form for an example of an actual input signal voltage in the cyclic hybrid ADC of Figure 15. Figures 16 and 17 complementarily explain the operating principle of the cyclic ADC.

[0035] FIG. 18 is a diagram showing examples of circuits that generate input signal voltages within the parallel hybrid ADC of FIG. 2 and the cyclic hybrid ADC of FIG. 15. Examples of circuit implementations that generate input signals in different ADC structures are compared.

[0036] FIG. 19 is a diagram showing a parallel-circular hybrid ADC configuration that combines the parallel hybrid ADC method of FIG. 2 and the circular hybrid ADC method of FIG. 15.

[0037] FIGS. 20 to 23 illustrate examples of circuits for applying the input signal voltage generation method of FIG. 14 to a group-hybrid ADC. FIG. 20 illustrates an example utilizing an instrumentational amplifier, FIG. 21 illustrates an example utilizing an OP amp buffer and a differential amplifier, FIG. 22 illustrates an example utilizing an OTA (Operational Transconductance Amplifier) ​​and a current mirror, and FIG. 23 illustrates an example circuit utilizing a dual OTA and a current mirror.

[0038] FIGS. 24 and FIGS. 25 show other implementation examples of a circuit that generates an input signal voltage in the cyclic hybrid ADC of FIG. 17. FIG. 24 is an example applying a cyclic sample-and-hold circuit, and FIG. 25 is an example of an input voltage generation circuit including a sample-and-hold (S&H), respectively.

[0039] FIGS. 26 to 31 illustrate various implementation examples of the input signal voltage generation circuit of FIG. 18. FIG. 26 illustrates an example utilizing two OTA amplifiers, FIGS. 27 and 28 illustrate examples utilizing two OTAs and a current mirror, FIG. 29 illustrates an example utilizing one OTA, a current mirror, and an OTA-resistor combination, FIG. 30 illustrates an example utilizing an OP amp-based instrumentation amplifier, and FIG. 31 illustrates an example utilizing an OP amp buffer and a differential amplifier.

[0040] FIG. 32 is a block diagram showing a sensor signal processing configuration in which one resistive sensor and a hybrid ADC are connected.

[0041] Figure 33 specifically illustrates the block configuration of Figure 32 at the circuit level.

[0042] FIG. 34 is a block diagram showing a sensor signal processing configuration in which one capacitor sensor and a hybrid ADC are connected.

[0043] FIG. 35 is a detailed circuit-level representation of the configuration illustrated in FIG. 34.

[0044] FIG. 36 is a block diagram showing a sensor signal processing configuration connected to a hybrid ADC using multiple resistive sensors and a differential amplifier.

[0045] FIG. 37 is a block diagram showing a sensor signal processing configuration connected to a hybrid ADC using multiple capacitor sensors and a differential amplifier.

[0046] FIG. 38 is a circuit diagram showing a specific example of generating an input signal voltage using an OTA and a fixed resistor in the configuration of FIG. 36.

[0047] FIG. 39 is a configuration diagram showing a specific example of generating an input signal voltage using an OTA and a fixed capacitor in the configuration of FIG. 36.

[0048] FIG. 40 is a configuration diagram showing a specific example of generating an input signal voltage using an OTA and a fixed resistor in the configuration of FIG. 37.

[0049] FIG. 41 is a configuration diagram showing a specific example of generating an input signal voltage using an OTA and a fixed capacitor in the configuration of FIG. 37.

[0050] Figure 42 shows a detailed circuit diagram of the configuration of Figure 38.

[0051] Figure 43 shows a detailed circuit diagram of the configuration of Figure 39.

[0052] Figure 44 shows a detailed circuit diagram of the configuration of Figure 40.

[0053] Figure 45 shows a detailed circuit diagram of the configuration of Figure 41.

[0054] Preferred embodiments of the present invention will be described below with reference to the attached drawings. The drawings are merely illustrative for the purpose of facilitating understanding and the invention is not limited thereto; some components may be exaggerated to clarify the gist of the invention.

[0055] Technical and scientific terms in this specification are used in their ordinary sense unless otherwise specifically defined, and detailed descriptions of known functions and configurations are omitted to the extent that they do not detract from the essence. Furthermore, while the described background technology may include technical information acquired during the process of deriving the invention, it is not necessarily interpreted as prior art prior to the filing. Where necessary, known structures are omitted or illustrated with block diagrams focusing on core functions to aid understanding.

[0056] In this specification, terms such as 'comprising' are open expressions that do not exclude elements, materials, and processes not enumerated, and singular expressions include the plural depending on the context.

[0057] The present invention relates to an Analog-to-Digital Converter (ADC) and proposes a hybrid structure that combines the high speed of a Flash ADC with the efficiency of a Successive Approximation Register (SAR) ADC. Although a Flash ADC is high-speed, when implementing high resolution, the comparator is 2 N-1 The number of comparators required (e.g., 1,023 for 10 bits) increases area and power consumption, and the generation of a very small reference voltage increases design complexity and noise issues. In contrast, the present invention reduces the number of comparators to the N level (e.g., 10 for 10 bits) at the same resolution while aiming for flash-level speed, thereby reducing area and power consumption.

[0058] SAR ADCs are low-power but provide precise step-by-step reference voltages (2 n It requires a scale. The present invention utilizes SAR control logic but compensates for this limitation by selectively controlling not only the reference voltage but also the input signal voltage itself. As a result, through various hybrid configurations such as parallel or mixed series-parallel types of Flash and SAR, high speed and high resolution are secured simultaneously while simplifying the circuit and achieving low power consumption.

[0059] The proposed structure comprises (i) a method of fixing the input voltage and generating a reference voltage in steps, and (ii) fixing the reference voltage (e.g., 1 / 2 V). REF It encompasses methods that modify the input voltage and perform iterative comparison. Through this, the degradation in accuracy caused by the miniaturization of the reference voltage can be mitigated by linking with control logic, even at high resolutions of 12 bits or more, and even 24 bits or more. In addition, by utilizing the stepwise comparison principle of SAR in parallel while maintaining the fast conversion characteristics of flash, it can be flexibly applied from 10 bits to 24 bits or more.

[0060] The reference voltage generator (DAC) of the present invention offers high design flexibility and scalability as it can be selected and applied from various methods, such as current-based resistors and capacitors, to suit process and system requirements. Since stable comparison is possible even at ultra-high resolution through superposition and iterative control techniques, it facilitates the realization of ADCs of 24 bits or higher, which were previously difficult to implement. Consequently, it provides area and power advantages in applications such as portable devices, high-speed signal processing, and large-scale parallel computing.

[0061] In addition, the hybrid ADC of the present invention is easily applied to sensor signal processing circuits that directly digitize changes in the resistance or capacitance of a sensor. While conventional pulse width conversion and counter methods have large response delays, the present invention enables high-speed response by immediately converting to a hybrid ADC simply by forming a voltage signal (VIN) through sample-and-hold (S / H). That is, by generating an input voltage VIN and applying it to the ADC of the present invention, a digital output can be obtained quickly without an additional conversion process.

[0062] Figure 1 is a schematic diagram showing the basic operation structure of a Flash ADC and a SAR ADC.

[0063] Figure 1 illustrates a comparison of the structures of a Flash ADC and a SAR ADC. A Flash ADC obtains a digital output in a single cycle by arranging multiple comparators in parallel to simultaneously compare an input analog signal with multiple reference voltages. On the other hand, a SAR ADC determines bits sequentially from a single comparator symbol MSB (Most Significant Bit) to LSB (Least Significant Bit), and changes over multiple cycles by adjusting the reference voltage of the DAC according to the previous comparison result. The present invention proposes a new structure that effectively combines the two methods.

[0064] FIG. 2 illustrates a hybrid ADC (100) structure of one embodiment. This structure performs rapid signal processing from MSB to LSB and can flexibly implement resolutions from, for example, 4 bits to 24 bits. Operation is performed using an input voltage (V A ) and 1 / 2 V REF The process proceeds by determining the MSB through comparison and, based on the result, the control logic generates the reference voltage for the next stage (MSB-1). Subsequently, the entire N-bit range is executed sequentially by continuously setting the reference voltage for the next stage by reflecting the comparison results of each stage, and the overall conversion delay can be reduced through asynchronous control.

[0065] A hybrid ADC may consist of control logic (such as SAR Logic), a comparator array, a reference voltage generation circuit, and a sample and hold (S / H) circuit. In some examples, the comparator is L1 to L n It includes multiple comparators, and the reference voltage generation circuit may include a step-by-step reference voltage generation unit.

[0066] The control logic receives the output of each comparator and immediately determines the reference voltage for the next stage. The comparators are arranged in parallel, each with an applied reference voltage and V A It compares to output "1" or "0". The reference voltage generation circuit is implemented using resistors, capacitors, a DAC structure utilizing a current source, etc., and the step generation section provides a reference voltage suitable for the corresponding step comparator. The reference voltage is V REF It is based on fractional values ​​(e.g., 1 / 2 V REF , 1 / 4 V REF , 3 / 4 V REF ), according to the binary search principle V REF ×(integer / 2 nIt uses the form ). If necessary, an offset can be added to correct comparator error or DAC imbalance.

[0067] S / H is V at the start of conversion A By sampling and maintaining it until the conversion is complete, errors caused by input fluctuations are suppressed, and all comparators are made to make stable judgments based on the same input.

[0068] In summary, V in this embodiment A and 1 / 2 V REF Starting with a comparison, the next reference voltage is set by reflecting the results of each step in real-time, and the corresponding reference voltage and V A The digital output from MSB to LSB is determined by repeating the comparison procedure N times. By combining this stepwise reference voltage setting with a parallel comparator structure, high resolution and fast conversion speed can be achieved simultaneously while suppressing the number of comparators.

[0069] FIGS. 3 to 5 illustrate three reference voltage generation methods that can be used when implementing the parallel hybrid ADC of FIG. 2, where FIG. 3 illustrates a current source-based method, FIG. 4 illustrates a resistor voltage divider method, and FIG. 5 illustrates a capacitor-based method.

[0070] Figure 3 forms a reference voltage by generating a reference current based on a current source and applying it to a resistor. Figure 4 obtains a reference voltage by selecting or switching the node voltages of a resistor voltage divider network. Figure 5 forms a reference voltage by pre-charging or discharging a capacitor or by capacitor division. In all three methods, the input voltage (V A A step reference voltage is generated and supplied to the comparator for comparison with ), and the circuit configuration, precision, and power characteristics may vary depending on the implementation selection.

[0071] FIGS. 6 to 8 illustrate a method of designing reference voltages in steps from MSB to LSB using an 8-bit ADC as an example, utilizing the reference voltage generation method of FIG. 2, where FIG. 6 illustrates the upper 4-bit generation unit, FIG. 7 illustrates the middle 2-bit generation unit, and FIG. 8 illustrates the lower 2-bit generation unit.

[0072] In this example, the MSB determination criterion is 1 / 2 V REF is. Input voltage V A If the MSB is determined by comparison, the reference voltage for the next step is 1 / 4 V according to the MSB result. REF or 1 / 2 V REF + 1 / 4 V REF It is selected as. Subsequent steps are also V according to the binary search principle. REF × (integer / 2 k Select one of the candidates and V A When compared with, even if there are branching cases, there is only one reference voltage actually used at each stage. For example, V A < 1 / 2 V REF In this case, the MSB becomes 0 and the next reference voltage is 1 / 4 V REF This becomes the case, and MSB-1 is determined as a result of this comparison. Each comparison result is passed to the control logic, and the reference voltage generation circuit immediately generates the next stage reference voltage.

[0073] Consequently, this parallel hybrid ADC combines the stepwise comparison of SAR with the multiple comparison structure of Flash, rapidly generating different reference voltages while keeping the input voltage fixed and supplying them to the comparator, thereby simplifying the circuit while simultaneously securing high conversion speed and resolution.

[0074] FIG. 9 shows the reference voltages from MSB to LSB and the input signal voltage (V) according to the procedure of FIG. 6 to 8. AThe process of comparing ) on the time axis is illustrated. The comparison result of each step is immediately transmitted to the control logic to set the reference voltage for the next step, and then the next comparison proceeds asynchronously. The operation is V A and 1 / 2 V REF Starting with a comparison, the MSB is determined, and the reference voltage of MSB-1 is set according to the result. As this procedure proceeds sequentially step by step, the next step begins as soon as each step is completed, and the final N-bit digital output is quickly determined.

[0075] FIG. 10 illustrates an example of a reference voltage generation circuit used in FIG. 9. It can be implemented using (a) current-based resistance control, (b) resistance-based current control, (c) capacitor-based current control, etc., and these circuits rapidly generate the reference voltage required as a DAC. For example, the resistance voltage divider is 1 / 2 V through switching. REF It forms a current, and the current control method obtains the target voltage solely by adjusting the current magnitude. A reference voltage can also be implemented using a combination of a current source and a resistor or capacitor; however, the capacitor method requires a reset to ensure accuracy in the next stage once the comparison is complete after charging. Through these various combinations of components, the reference voltage required for the comparator at each stage can be provided quickly and accurately.

[0076] FIG. 11 illustrates the process of FIG. 6 to 8 in the form of a flowchart, showing the flowchart of a parallel hybrid ADC. Input voltage (V A ) is maintained and only the reference voltage is adjusted step by step, and the MSB comparison result is immediately reflected in the next step setting and sequentially determined up to the LSB. Since the result of each step is reflected in real time and the comparison and reference voltage setting proceed continuously, the entire N bit is converted quickly.

[0077] FIG. 12 illustrates a parallel-group hybrid ADC configuration in which the comparator is divided into multiple groups to achieve high resolution. FIG. 13 illustrates the input voltage (V) for high resolution. A A method for comparing by modifying ), Fig. 14 shows an example of the input voltage generation circuit. The method of Fig. 2 has the advantages of high speed, small area, and low power, but for 12 bits or more, V REF / 2 N There are limitations because it requires the generation of a very small reference voltage at the level. For example, V REF =1 V, the LSB of 24 bits is about 1 / 16,777,216 V, which is a noise level, making practical implementation difficult.

[0078] Accordingly, the entire bit set is divided into multiple groups, and within each group, the same reference voltage range is repeated. For example, if 24 bits are divided into three groups of 8 bits each, the minimum reference voltage for each group is 1 / 256 V. REF It is realistic at (approx. 3.9 mV). The group size can be selected from 2 to 8 bits and extends to 12, 16, and 32 bits using the same principle. If the input voltage is not fixed, V during conversion is used via sample-and-hold. A Maintains.

[0079] In addition, the result of the upper group is used to scale the residual signal and use it as the input for the next group. After the upper group transformation, the reference voltage V of the least significant bit of that group is applied. J ul V A Subtract from and 2 K (Group bit count) Expand by a factor of 1 / 2 to the next group input V B Set to.

[0080] (V A - V J ) × 2 K = V B

[0081] Likewise, (V B - V M ) × 2 K = VC , (V C - V P ) × 2 K = V D High resolution is achieved by proceeding sequentially through subgroups as shown above, and this method can be extended up to 32 bits.

[0082] FIGS. 13 and 14 illustrate an input voltage transformation method. Based on the step-by-step comparison result, the corresponding reference voltage is subtracted from the input voltage, and 2 K The value magnified by a factor of 1 is used as the input for the next stage. Since this method only requires precise control of a limited voltage range in each group, it is stably expanded to high resolution. In addition, the structures of FIGS. 2 to 14 operate asynchronously without an external clock to produce output bits, making them suitable for high-speed and high-resolution implementation.

[0083] Figure 15 shows a conceptual diagram of a series-circulating hybrid ADC, with a reference voltage of 1 / 2 V REF It is a structure that sequentially determines N bits by repeatedly comparing the input voltage, which is modified step by step, with the fixed state. Although the conversion time is longer compared to the parallel method of FIG. 2, it is suitable for high-resolution implementation because it has low power consumption and is easy to reduce the circuit size. Input voltage modification can be realized using the current source, resistor, and capacitor-based circuits of FIGs. 3 to 5.

[0084] The operation is initial input V A 1 / 2 V REF After determining the MSB by comparison with, at each step k, the result of the previous comparison b k Input V according to {k+1} = (V k - b k × V REF / 2) Update to 2 and the same 1 / 2 V REF Compare with again. Here, b kis 0 or 1 depending on the comparison result of the corresponding step, and this process is repeated N times to sequentially determine up to the LSB. Since the comparison threshold is constant at every step, the comparator requirements are simplified, and there is no need to directly generate a reference voltage of very small resolution, which lowers the complexity and sensitivity of the DAC.

[0085] For implementation, sample-and-hold or integral-type hold nodes are used to stably transfer voltage between stages, and in capacitor-based implementations, residual charge is removed through an appropriate reset after the end of each stage. Current-controlled or resistor voltage divider circuits can implement step subtraction and gain multiplication via switching, and comparator offset and DAC imbalance can be compensated for using correction signals in the control logic.

[0086] Consequently, this cyclic structure significantly reduces the burden on the DAC by fixing the reference voltage and updating only the input, while providing low-power, high-resolution conversion with minimal hardware.

[0087] Figure 16 shows the step-by-step update of the input voltage in a cyclic hybrid ADC with example values ​​(e.g., 0.46 V, 0.94 V, V REF It is illustrated as = 1 V). Figures 16(a) and 16(b) show V at each step. (k+1) = {V (k) - b (k) × V REF Generate the next step input according to the / 2} Х 2 rule and the same reference voltage (1 / 2 V REF It shows a procedure for comparing with ). FIG. 17 presents the same operation in a different representation and indicates that the above operation can be implemented using a current source, a resistor, a capacitor, and switching. The operation is initial V A and 1 / 2 V REF After determining MSB through comparison, the comparison result b (k) Subtraction and scaling are repeated based on the value to sequentially determine up to the LSB. This configuration reliably achieves high-resolution conversion without the direct generation of a very small reference voltage.

[0088] FIG. 18 illustrates a comparison of circuit examples for generating input signal voltages in the parallel hybrid ADC of FIG. 2 and the circular hybrid ADC of FIG. 15. Additionally, a parallel-circular hybrid ADC configuration integrating the two methods is presented, thereby simultaneously securing the advantages of high speed of the parallel structure and low power consumption and high resolution of the circular structure. This configuration alleviates the difficulty of comparing minute voltages during high-speed conversion, improves upon the issues pointed out in FIG. 1, and simplifies the circuit to reduce power consumption and implementation difficulty. Furthermore, depending on the required specifications, the design can be flexibly expanded from low resolution of 2 bits or more to high resolution of 24 bits or more.

[0089] FIG. 19 illustrates a parallel-circular hybrid ADC configuration diagram combining the parallel hybrid ADC of FIG. 2 and the circular hybrid ADC of FIG. 15. This structure combines a parallel processing section and a circular processing section to reduce the number of comparators and reference voltage generation circuits while maintaining high-speed operation, thereby lowering circuit area and power consumption. Accordingly, high speed and high resolution can be secured simultaneously while reducing overall complexity.

[0090] FIGS. 20 to 23 illustrate examples of circuits applying the input voltage generation method of FIG. 14 to a group hybrid ADC. FIG. 20 is based on an instrumentation amplifier, FIG. 21 is based on an OP amp buffer and differential amplifier, FIG. 22 is based on an OTA and current mirror, and FIG. 23 is based on a dual OTA and current mirror configuration. FIG. 20 can be implemented with an OP amp or an OTA, and the application of an OTA is advantageous in terms of implementation simplicity and ease.

[0091] FIGS. 24 and 25 illustrate a simplified sample-and-hold (S / H) implementation example generating the input voltage in the cyclic hybrid ADC of FIG. 17. In step 1, the external input V A Apply it to the comparator as is, SW1 on, SW 11 Off, SW 12and SW 13 V in ON state REF Determine MSB by comparing with / 2.

[0092] After step 2, the result b from the previous step k V depending on (0 or 1) {k+1} = V k - b k × V REF Update to / 2 and apply a scale (e.g., 2x) if necessary, then turn off SW1, SW 11 On, SW 12 Back to off state V REF Compare with / 2. When the comparison is finished, SW 12 On, SW 13 The off voltage is stored in capacitor C1 and passed to the next stage input, and the same sequence is repeated to sequentially convert up to the LSB.

[0093] FIGS. 26 to 31 illustrate implementation examples of the input voltage generation circuit of FIG. 18. FIG. 26 shows two OTAs, FIGS. 27 and 28 show two OTAs and a current mirror, FIG. 29 shows one OTA, a current mirror, and a resistor combination, FIG. 30 shows an OP amp-based instrumentation amplifier, and FIG. 31 shows an example of an OP amp buffer and a differential amplifier, respectively. These circuits can be implemented with OP amps or OTAs, and the design difficulty is relatively lower with the OTA method.

[0094] The switch operation is V at the input when SW1 is ON and SW2 is OFF. REF Subtract / 2, and apply 0V when SW1 is off and SW2 is on. Then, double the resulting voltage to form the input for the next stage.

[0095] By combining the above voltage generation block with n comparators and control logic, a parallel hybrid ADC can be implemented, and it can also be extended to group parallel, circular, and parallel-circular combined structures. The reference voltage is controlled in real-time by a current source-resistance or capacitor-based DAC, and the input variation is (V A - V J) × 2 K or (V An - V REF By repeatedly applying / 2 × (0 or 1)) × 2, the generation of ultra-small reference voltage is avoided.

[0096] FIG. 19 is a configuration diagram combining the parallel hybrid ADC of FIG. 2 and the circular hybrid ADC of FIG. 15. By combining the parallel section and the circular section, high-speed operation, low power consumption, and a small area are achieved simultaneously. Furthermore, by reducing the number of comparators and reference voltage generation circuits, circuit complexity is lowered while ensuring high speed and high resolution.

[0097] When the above structure is applied, the present invention achieves a higher speed than the SAR method and the same level of resolution with fewer comparators than the flash method. Internal operation proceeds asynchronously, enabling operation without an external clock, and parallel, circular, or combined structures can be selected depending on the required resolution, power, and speed conditions in communication, sensor data processing, artificial intelligence computation, etc.

[0098] It also includes a parallel group hybrid configuration that divides the comparator into multiple groups (see FIG. 12). The entire N bits are divided into several groups, and a parallel hybrid conversion is performed in each group. By amplifying the residual signal of the upper group and supplying it as the input to the lower group, ultra-high resolution is realized. FIG. 8 is an example of implementing 8 bits into three groups of 4 bits, 2 bits, and 2 bits, and FIGs. 20 to 23 show examples of OP amps, OTAs, and current mirror-based circuits for converting the upper group results into lower group inputs.

[0099] In a cyclic implementation, the reference voltage is set to 1 / 2 V using one or a few comparators. REF Each bit is determined sequentially by updating the input voltage in steps while keeping it fixed (see Fig. 15). After determining the MSB, V at the input REFThe procedure of creating the next stage input by subtracting a value equivalent to half of and applying a scaling factor is repeated. FIGS. 16 and 17 illustrate the step-by-step voltage update process for an example input. The cyclic structure enables high-resolution conversion while minimizing hardware resources, but the conversion time may be longer than that of the parallel structure, and a structure that compromises between parallel and cyclic can also be selected as needed (see FIG. 19).

[0100] Reference voltage generation circuits can be implemented using current-based, resistor voltage divider, or capacitor methods (see FIGS. 3 to 5). The current-based method is advantageous for continuous control, the resistor voltage divider method has a simple structure, and the capacitor method offers high accuracy. Depending on the application, they can be used individually or in combination.

[0101] When the number of comparators is set to N, it operates in a parallel hybrid mode as shown in FIG. 2; when the number of comparators is reduced and input updates are repeated, it operates in a serial mode; and when groups are set, it operates in a parallel group mode. The flowchart in FIG. 11 shows a control flow in which each comparison result is immediately reflected in the next step setting in the parallel hybrid mode.

[0102] The sensor signal processing device of the present invention includes the hybrid ADC to convert the analog output of a sensor into a high-speed and high-precision digital code. Since the voltage formed at the sensor interface is directly applied to the ADC, pulse conversion and measurement steps are unnecessary, thereby minimizing delay. By including a reference current source and a sample-and-hold circuit, it suppresses current and input fluctuations caused by environmental changes and provides a stable voltage. The device is composed of a sensor element, a reference current source, a sample-and-hold circuit, and a hybrid ADC including multiple comparators and control logic. Based on the comparison result, the reference voltage is adjusted in real time or the input is updated, and the conversion is completed in bit or bit group units. Accordingly, real-time high-speed conversion is possible even under low-power conditions in various applications such as industrial, medical, and Internet of Things.

[0103] Below, a sensor signal processing device integrating a sensor and an ADC is described with reference to FIGS. 32 to 45.

[0104] FIG. 32 is a basic block diagram showing a resistive sensor and a hybrid ADC connected. The resistance of the resistive sensor changes according to physical quantities such as pressure, strain, and temperature, and a stable reference current I REF Apply voltage V IN Creates. I REF It is maintained to minimize the effects of temperature, power fluctuations, and noise, becoming the core of conversion precision. The generated V IN It is input to a sample-and-hold circuit operated by a switch control signal, where it charges a capacitor during the sample interval and is maintained during the hold interval. The maintained voltage is transmitted to a hybrid ADC and converted into a digital code. This configuration stabilizes the input voltage right up until conversion, thereby reducing errors.

[0105] FIG. 33 is a circuit-level embodiment of the block configuration of FIG. 32. The circuit of this embodiment is a resistive sensor (R sensor )-Reference Current Source (IREF)-Buffer-Sample and Hold (S&H) Capacitor (C Fixed It can be configured so that the signal is transmitted in the order of )-switch (SW2)-hybrid ADC. The Gm (operational transconductance amplifier) ​​on the left is reference voltage V Fixed Drives the low-current mirror, and the mirror output to the sensor top node is I, which is insensitive to temperature and power fluctuations REF It supplies. Since the bottom of the sensor is fixed to ground, the top node voltage is ideally V in ≒I REF × R sensor It becomes, and this voltage is the sensor output V in am.

[0106] The sensor output passes through a buffer with a voltage gain of 1 and is electrically isolated from the S&H stage. Accordingly, kickback, sampling glitches, and load fluctuations occurring during downstream switching and ADC sampling can be suppressed from being fed back to the sensor.

[0107] Switching is controlled by a non-overlap clock. During the sample interval, SW1 is turned on and SW2 is turned off to control the buffer output C Fixed Charge to, and C Fixed The voltage is V in It tracks. An auxiliary switch with bootstrap and clamp functions is placed in the SW1 path to minimize changes in on-resistance and suppress charge injection and clock feedthrough. In the hold-transfer section, SW1 is turned off first to C Fixed After conserving the voltage, switch SW2 to ON and apply it to the hybrid ADC input. After the conversion is finished, turn SW2 OFF, and switch SW1 back ON in the next cycle.

[0108] I during design REF is stabilized with mirror matching and Gm bias, and V in R to operate within this current source compliance range sensor Determine the range and power supply voltage. C Fixed is selected such that the kT / C noise is smaller than the target LSB, and the sample time T s τ = R so that it is sufficiently charged during out_buf × C Fixed Determine the buffer bandwidth and switch-on resistance by considering the above.

[0109] Through the above configuration and sequence, the circuit of Fig. 33 can stably sample the resistive sensor signal and precisely transmit it to the hybrid ADC.

[0110] FIG. 34 is a sensor signal processing block diagram composed of one capacitor-type sensor and a hybrid ADC. This configuration includes a reference current source (I REF ), Sample and Hold (S&H), Capacitive Sensor (C Sensor It includes a switch control unit and a hybrid ADC. The sensor's capacitance varies depending on changes in pressure, humidity, and displacement, and I REF The voltage V across the sensor terminals is applied by in This is formed. V inAfter being maintained as S&H for a certain period of time, it is applied to the ADC according to the switch control signal and converted into digital.

[0111] FIG. 35 shows the configuration of FIG. 34 in detail at the circuit level. The circuit consists of Gm (operational transconductance amplifier) ​​- current mirror - sensor capacitor (C Sensor )-Switches SW1, SW2, SW3-Hybrid ADC are configured so that signals are formed and transmitted in that order. Gm is the reference voltage V Fixed A reference current I that is biased to drive the current mirror and is insensitive to temperature and power fluctuations REF It stably outputs.

[0112] The operation proceeds in three stages according to non-overlapping switch control. In the sample stage (SW1=ON, SW2=OFF, SW3=OFF), I REF is injected into the sensor node and C Sensor is charged, and the sensor node voltage V in This is formed. Charging time is T s Ideally, if fixed as V in =( I REF × T s ) / C Sensor ... becomes. The diode-type device at the SW2 input stage acts as a clamp / bootstrap to suppress reverse charge inflow during sampling. In the hold and transfer stage (SW1=OFF, SW2=ON, SW3=OFF), C Sensor V stored in in While maintaining this state, it is transmitted to the hybrid ADC input via SW2; at this time, the sensor node is isolated from the driver, preventing ADC kickback feedback. In the reset phase, SW2 is turned OFF followed by SW3 is turned ON to discharge the sensor node to ground for initialization, preventing residual charge and ghost samples. The diode symbol at the SW2 input indicates a clamp / bootstrap element that suppresses the inflow of reverse charge into the sensor node during sampling. Additionally, accumulated charge and ghost samples are prevented by isolating the reset path.

[0113] I during design REF V within the scope of compliance in Set the Gm bias and current mirror matching so that this is formed, and T s and switch on-resistance and C Sensor Considering this, ensure that kT / C noise and settling time at the target resolution satisfy the standards. Through the above procedure, C Sensor Stable voltage V for capacitance change in It can be converted into and accurately applied to a hybrid ADC.

[0114] FIG. 36 illustrates a sensor signal processing configuration connected to a hybrid ADC using multiple resistive sensors and a differential amplifier. This configuration includes two resistive sensors (R+△R, R-△R) and a reference current source (I) that applies a DC reference current to each. REF1 , I REF2 It consists of a differential amplifier, a sample-and-hold (S&H) circuit, and a hybrid ADC. The bottom of each sensor is fixed to ground, and the top is connected in series with a corresponding reference current source. The reference current source is implemented as a current mirror or a Gm-based circuit, resulting in an I that is insensitive to process, temperature, and power supply variations. REF It provides.

[0115] At this time, the upper node voltage is V P =I REF1 ×(R+△R), V N =I REF2 It is defined as ×(R-△R). The differential amplifier consists of two nodes (V P , V N Amplifying the differential voltage of ) to produce a single-ended output V OUT It generates, and V with respect to gain G OUT =G×(V P -V N It is set to ). The amplifier's common mode voltage is biased to match the downstream interface and may include input protection and offset trimming if necessary. The S&H circuit V in the sample phase according to the switch control signal.OUT hold capacitor (C H Charge to ), and C in the hold phase H voltage V IN Maintain it as such and apply it to the hybrid ADC input.

[0116] If necessary, C immediately before sampling H It includes a reset path that discharges to the reference voltage or ground. The hybrid ADC retains V during the hold interval. IN It receives as input and performs a conversion in a manner selected from the parallel hybrid, group hybrid, or cyclic hybrid modes of this specification. In summary, I REF1 and I REF2 Authorization V P and V N This is formed, and V is used as a differential amplifier OUT After creating, V in S&H IN Sample and retain, and then conversion is performed in the ADC. The same function can be implemented by an equivalent circuit by a person skilled in the art.

[0117] FIG. 37 illustrates a configuration connected to a hybrid ADC using multiple capacitor sensors and a differential amplifier. This configuration consists of two capacitor sensors (C+△C, C-△C), two reference current sources supplying a constant current to each channel, dual S / H capable of simultaneous sampling, a differential amplifier, and a hybrid ADC. Each sensor has one terminal connected to ground and the other terminal connected to the S / H input node, with an independent I at each input node. REF is authorized.

[0118] In the sample phase, both channels become sampled simultaneously, and I REF is injected into the sensor node and the sensor capacitor at time T S The charge is accumulated during this period. At this time, V P = I REF ×T S / (C+△C), V N = I REF ×T SIt is formed by / (C-△C), and the two voltages are held by the S / H capacitor (C H +, C H Sampled in -). In the hold and forward phases, the sample switch is blocked to C H +, C H - of V P , V N It maintains and applies this to the differential amplifier. Under common-mode bias, the amplifier amplifies the two voltage differences to gain G, and the single-ended V OUT Outputting V OUT = G×(V P -V N ) is. V OUT is V IN As such, it is input to the hybrid ADC. If necessary, a reset phase is introduced between the sensor node and C H It discharges to the reference potential, and all timing is controlled non-superposition.

[0119] Two I REF It is supplied to each input node of the S / H and returns to ground through the sensor. The two holding nodes of the S / H are directly connected to both inputs of the differential amplifier, and the amplifier output is V without a buffer as needed. IN It can be connected. The reference current source is implemented as a current mirror or a Gm-based circuit, and the I of the two channels REF Set to the same value.

[0120] In summary, the voltages formed at two sensors over the same period are simultaneously sampled, converted into single-ended voltages using differential amplification, and then digitally converted using a hybrid ADC.

[0121] FIG. 38 illustrates an example of generating an input signal voltage using OTA and a fixed resistor in the configuration of FIG. 36. The same reference current I is applied to the tops of the two resistive sensors (R+△R, R-△R). REF Apply and connect the bottom to ground. Accordingly, V P = I REF × (R+△R), V N = IREF × (R-△R) is formed, and the two node voltages are applied to the ± inputs of the OTA. For the OTA, △V = V P - V N = 2 × I REF Current I proportional to × △R OUT = gm × △V outputs, and this current is fixed resistor R Fixed While flowing V O = I OUT × R Fixed = gm × △V × R Fixed It becomes. V O is transmitted as the S / H input, and the S / H output is the ADC's V IN It is directly connected to.

[0122] The operation proceeds with sample, hold, and reset using non-overlapping timing. By turning on the S / H switch during the sample phase, V O It charges the hold capacitor, and the two sensor I REF by V P and V N Maintain and OTA is I according to △V OUT It continues to provide. In the hold phase, the S / H input switch is turned off to set the stored voltage to V. IN Maintain it and the ADC performs the conversion. If necessary, reset paths are placed in the S / H and OTA output nodes to reset the reference potential for the next cycle.

[0123] Two I when designing REF It generates currents that ensure identical current using current mirrors, etc., and suppresses common-mode errors by symmetricalizing wiring and input leakage. OTA is implemented with a differential input and single-ended output structure, and adds an output buffer as needed. R Fixed gm is selected to satisfy the ADC input range and bandwidth conditions. Consequently, the signal path is defined in the order of sensor (dual current driven) → differential VI conversion (OTA) → IV conversion through resistor → S / H → hybrid ADC.

[0124] FIG. 39 illustrates an example of generating an input signal voltage using an OTA and a fixed capacitor in the configuration of FIG. 36. The same reference current I is applied to the tops of the two resistive sensors (R+△R, R-△R). REF Apply and connect the bottom to ground. Accordingly, V P = I REF × (R+△R), V N = I REF × (R-△R) is formed, and the two node voltages are applied to the differential input of the OTA. For the OTA, △V = V P - V N = 2 × I REF Current I proportional to ×△R OUT = output gm × △V, and the output node is a fixed capacitor C connected to ground. Fixed It is directly connected to.

[0125] I OUT This integral time T INT During C Fixed By charging or discharging V O (t0+T INT ) = V0(t0) + (I OUT / C Fixed ) × T INT It becomes, and the reset switch Φ is necessary. R As V0(t0) is 0 V or common mode V CM Initialize to. V O It is connected to the sample-and-hold (S / H) input, and the integral / sample phase (Φ) according to non-overlapping switch control S In ), V O Tracks and stores in the internal capacitor, and the hold / transform phase (Φ H In ), the storage voltage is V IN Maintain as and transmit to the hybrid ADC. Optionally, Φ R C in phase Fixed Discharge the internal capacitor of S / H to prepare for the next cycle.

[0126] Two I when designing REFis a common reference current mirror to ensure the same current, and C Fixed , T INT gm is selected to satisfy the ADC input range and bandwidth. If necessary, ringing can be suppressed by inserting a buffer between the OTA output and S / H or by connecting a damping element in parallel to the integration node. Consequently, the signal path is defined as Sensor (Dual Current Driven) → Differential VI Conversion (OTA) → Voltage Generation via Capacitor Integration → S / H → Hybrid ADC.

[0127] FIG. 40 illustrates an example of generating an input signal voltage using an OTA and a fixed resistor in the configuration of FIG. 37. The bottoms of the two capacitor sensors (C+△C, C-△C) are connected to common ground, and the top nodes are connected to the S&H input, with the same reference current I to each top. REF It is injected. The two outputs of S&H are applied to the (+) and (-) inputs of the OTA, and the single output of the OTA is connected to a fixed resistor R to ground. Fixed It is connected to. The voltage at this resistor node is V IN This is then transferred to the hybrid ADC.

[0128] The operation consists of three stages based on non-overlapping switch control.

[0129] First, reset (Φ R In the ) step, the S&H hold capacitor is in common mode V CM Initialize to, and V the sensor node if necessary. CM Or precharge to GND.

[0130] Second, filling and sample (Φ S In the ) step, I to the top of each sensor REF time T CHG Injected during V P = V CM + ( I REF / (C+△C)) × T CHG , V N = V CM + ( I REF / (C-△C)) × TCHG This is formed, and the two voltages are sampled across the S&H hold capacitor. In the small-signal approximation, △V = V P - V N ≒ (2 × I REF × T CHG It is expressed as × △C) / C².

[0131] Third, amplification and voltage conversion (Φ H V maintained by S&H in the ) stage P , V N Applied to this OTA, and OTA output current I OUT = gm × △V is R Fixed Converted into voltage through V IN = R Fixed × I OUT This becomes. V if necessary. IN By adding a buffer to the node, the effect of changes in ADC input impedance can be blocked.

[0132] In short, the signal path is differential capacitor sensor (dual current injection) → S&H simultaneous sampling → differential VI conversion by OTA → R Fixed Single voltage generation at → V IN → It is a hybrid ADC, and Φ R- Φ S- Φ H Stable V while suppressing residual charge and charge injection through timing IN forms.

[0133] FIG. 41 shows the OTA, rear S&H2, and fixed capacitor C in the differential capacitor type sensor interface of FIG. 37. Fixed By adding to convert the differential voltage into current and integrating, the single-ended input voltage V IN An embodiment forming is illustrated. The bottoms of the two sensors (C+△C, C-△C) are connected to a common ground, and the tops are connected to the same reference current I REFis injected. The sensor's top node is connected to the front-end S&H, and the two node voltages are sampled and maintained. The two outputs of the front-end S&H are applied as inputs to the OTA, and the OTA output is connected to the switch of S&H2 and C Fixed is connected to the juxtaposed node. When the switch is on, I OUT This C Fixed A voltage is formed by integration, and it retains that voltage when turned off. This node voltage is V IN It is transmitted to a hybrid ADC. Switch control is driven by a non-overlapping clock.

[0134] The operation sequence is as follows.

[0135] (1) Reset and Precharge: The hold capacitor of the preceding S&H is in common mode V CM Initialize to, and if necessary, turn the top of the sensor to V CM Or precharge to GND. At the same time, C through S&H2 Fixed Discharges.

[0136] (2) Sensor charging and sample: I REF time T CHG Inject during V P = V CM + ( I REF / (C+△C)) × T CHG , V N = V CM + ( I REF / (C-△C)) × T CHG It forms, and the shear S&H samples and maintains it. In the small-signal approximation, △V = V P - V N ≒ (2 × I REF × T CHG × △C) / C 2 .

[0137] (3) VI Transformation and Integration: OTA is I in a state where shear S&H is maintained OUT = Generates gm × △V. Turn on the S&H2 switch to C Fixed Integrating from V IN (t) = (1 / C Fixed) ∫I OUT dt, integration time is T INT and when the starting voltage is reset to 0, V IN = (I OUT / C Fixed ) × T INT .

[0138] (4) Hold and apply ADC: After integration is finished, turn off S&H2 to hold the voltage, and V IN Apply to the ADC. V if necessary IN Insert a buffer into the node to block the load effect on the integration node.

[0139] In summary, the signal path is the differential capacitor sensor (dual I REF Injection) → Pre-shear S&H simultaneous sample → VI conversion by OTA → C in S&H2 Fixed Integration and retention → V IN → Defined as a hybrid ADC, it operates the front-end and rear-end S&H separately to suppress charge injection and glitches while stabilizing V IN forms.

[0140] Figure 42 is an example of the path of Figure 38 (differential resistance sensor → current-voltage conversion → S&H → hybrid ADC) realized at the circuit level. The left OTA (Gm1) is the reference voltage V. Fixed It is biased to drive the current mirror, and a reference current I of the same magnitude REF Two paths are created to supply power to each sensor branch. The bottoms of the two resistance sensors (R+△R, R-△R) are connected to common ground, and the tops are connected to I REF V is injected P = I REF ×(R+△R), V N = I REF ×(R-△R) is formed, and the differential voltage is △V = V P -V N = 2×I REF It is ×△R.

[0141] The two top nodes are connected to the input of the second OTA (Gm2), and Gm2 is IOUT = Output gm2×△V. I OUT is a fixed resistor R connected to ground. Fixed voltage V through O = I OUT ×R Fixed = gm2×△V×R Fixed It is converted to. The following buffer is V O The nodes are isolated with high impedance to prevent the downstream switching load from affecting the upstream end.

[0142] The buffer output is input to S&H. SW1 (Sample Switch) and C Fixed It consists of a (hold capacitor) and SW2 (transfer switch), and in the sample phase, SW1 is turned on to C Fixed ul V O Charge and keep SW2 off. During the hold / transfer phase, switch SW1 off and SW2 on with a non-overlapping clock to set the hold voltage to the single-ended input V. IN Apply to the ADC. If necessary, C for the next conversion. Fixed A precharge interval is provided to reset it.

[0143] I REF The two paths are injected into the top of the sensor with the same size and polarity, and the bottom of the sensor is fixed to a common ground. The output node of Gm2 is R Fixed It is connected only to the S&H input (via buffer), so current-voltage conversion and sampling operations are clearly defined. Switch control is set to non-overlapping timing so that SW1 and SW2 do not conduct simultaneously and match the ADC sample timing.

[0144] FIG. 43 is a circuit diagram detailing the configuration of FIG. 39 at a near-transistor level, wherein a minute change (±△R) of a differential resistance sensor is processed through Gm (OTA), a current mirror, and a current-integrating S&H to obtain a single-ended input voltage V IN An example is illustrated in which it is generated and provided to a hybrid ADC. Gm on the left is the reference voltage V. FixedIt is biased to drive the current mirror, and a reference current I of the same magnitude REF Two paths are created to supply power to each sensor branch. The bottoms of the two resistance sensors (R+△R, R-△R) are connected to common ground, and the tops are connected to I REF V is injected P = I REF × (R+△R), V N = I REF × (R-△R) is formed, and the differential voltage is △V = 2 × I REF It is defined as × △R.

[0145] The two top nodes are connected to the input of the second Gm (differential input, single current output), and Gm is I OUT = outputs gm × △V. This current is the integration node V of S&H. in Fixed capacitor C, which flows into and is connected to ground. Fixed It is integrated into. S&H consists of three switches SW1 (integration), SW2 (transfer), and SW3 (reset), and operates as non-overlapping switch control. Reset step (Φ RST In ), SW3 is ON, and SW1 and SW2 are OFF, so C Fixed Discharge V in Initialize to 0.

[0146] Sample / Integration Step (Φ S In ), SW1 is ON, and SW2 and SW3 are OFF. OUT Set time T int During C Fixed Flowing in V in (t) = (1 / C Fixed ) ∫I OUT dt ≈ (I OUT × T int ) / C Fixed It becomes (constant current approx.). Retention / transfer stage (Φ H In ), turn SW1 off non-overlapping and then switch SW2 on to C Fixed V stored in in 1 single end V INOutputs to, and the hybrid ADC performs the conversion. After conversion, SW2 is turned off and returns to reset for the next cycle.

[0147] V in The diode indication between the node and SW2 signifies an optional clamp (or bootstrap) element for switch charge injection and kickback suppression. The two outputs of the current mirror are connected to the upper nodes of R+△R and R-△R, respectively, and the lower ends of both sensors are fixed to common ground. The single current output of the second Gm is connected only to the SW1 input of S&H, and C Fixed is necessarily V in It is placed between GND. The input of the hybrid ADC is V after SW2. IN It is connected to the node via a single end (when using a differential ADC, the complement terminal can be fixed to the reference potential or an equivalent implementation can be achieved using a separate buffer). With the above configuration, FIG. 43 shows a stable V proportional to △R using a current-integrating S&H and non-overlapping switching. IN Initiates a procedure to form and accurately apply it to a hybrid ADC.

[0148] FIG. 44 is an example of the block configuration of FIG. 40 realized at the circuit level, wherein the capacitance change (±△C) of a differential capacitor sensor is processed in the order of constant current charging, sample and hold, differential current conversion, and resistance voltage conversion to obtain the hybrid ADC input voltage V IN Illustrates the process of generating.

[0149] The left transconductance amplifier (Gm) is reference voltage V Fixed It is biased to drive the current mirror, and a reference current I of the same magnitude REF Provides two paths. Each I REF It is applied to the upper nodes of sensor capacitors C+△C and C-△C through the upper switch SW1, and the lower ends are connected to a common ground. A discharge switch SW3 is placed at each upper node and is clamped to ground upon reset.

[0150] In the sample interval, SW1=ON, SW2=OFF, and SW3=OFF are set so that I on the two capacitors REF a constant time T CH Allow it to flow during. At this time, V P = (I REF × T CH ) / (C+△C), V N = (I REF × T CH ) / (C-△C) is formed, and the differential voltage is △V = V P - V N ≒ (2 × I REF × T CH It is approximated as ÷ C²) × △C (|△C|≪ assumption). The switch control unit is driven with non-overlapping timing. When the sample ends, SW1 is turned OFF non-overlapping to hold the charge, and if necessary, a clamp or bootstrap element is placed before SW2 to suppress charge injection.

[0151] In the transmission section, V is set to SW2=ON P , V N Connect to the input of differential Gm and keep SW3 OFF. Differential Gm is an output current I proportional to △V. OUT It generates = gm × △V, and this current is connected to a fixed resistor R connected to ground. Fixed It is voltaged through V in = gm × R Fixed × becomes △V. V in is the single-ended input V of the hybrid ADC IN It is directly authorized.

[0152] After conversion, disconnect by setting SW2=OFF. During the reset phase, discharge the two sensor nodes by setting SW3=ON, then start the next cycle in the order of SW3=OFF, SW1=ON. The two outputs of the current mirror are respectively connected to the two upper nodes after SW1, and the two upper nodes are connected to the input of the differential Gm through SW2. The single current output of Gm is R Fixed It is directly connected to and its contact point is V inAll switches operate non-overlappingly, and SW3 conducts only upon reset.

[0153] In short, FIG. 44 shows △C sampled to V through a constant current rechargeable sample-and-hold, and then differential Gm and R Fixed Single end V IN A circuit and operation procedure are disclosed that form and stably transmit to a hybrid ADC.

[0154] FIG. 45 illustrates a circuit-level specification of the block configuration of FIG. 41, showing a two-stage sampling structure leading from a differential capacitor sensor → first sample and hold (S&H1) → voltage-current converter (OTA, hereinafter Gm) → second sample and hold (S&H2) → hybrid ADC.

[0155] The left Gm is the reference voltage V Fixed It is biased to drive the current mirror, and the same reference current I REF Provides two paths. Each I REF It is applied to the upper nodes of sensor capacitors C+△C and C-△C via upper switch SW1, and the lower ends are connected to common ground. A reset switch SW3 is placed at each upper node. The two sensor nodes are respectively connected to the input of differential Gm via transfer switch SW2. The single current output of differential Gm is transferred to S&H2, and S&H2 is connected to SW4-C Fixed - Consists of SW6 and ADC input V through SW5 IN It is connected to. All switches are driven with non-overlapping timing.

[0156] During the reset phase, S&H1 discharges the sensor node with SW3=ON, SW1=OFF, and SW2=OFF. S&H2 discharges C with SW6=ON, SW4=OFF, and SW5=OFF. Fixed Discharges.

[0157] In the S&H1 sample interval, SW1 is set to ON, SW3 to OFF, and SW2 to form the voltage at the top nodes of the two sensors during the charging time Tch1. VP =( I REF ×Tch1) / (C+△C), V N =( I REF ×Tch1) / (C-△C), differential voltage △V=V P -V N This sensor is proportional to △C.

[0158] In the S&H1 hold and transmission section, turn SW1 OFF non-overlapping, then switch SW2 to ON to V P , V N Apply to differential Gm. Differential Gm is an output current I proportional to △V. OUT1 = Generate gm1×△V.

[0159] In the S&H2 sample (cumulative) section, SW4=ON, SW6=OFF, SW5=OFF. OUT1 ul C Fixed Integrating into V BUF =( I OUT1 ХTch2) / C Fixed Forms and holds SW4=OFF.

[0160] During the ADC application period, SW5 is set to ON, and V BUF ul V IN It applies to perform conversion. At this time, S&H1 and S&H2 are maintained in a hold state so that the ADC kickback does not affect the preceding stage. After conversion, SW5=OFF, SW6=ON, and SW3=ON are set to C respectively. Fixed After discharging the sensor nodes, prepare for the next cycle. SW1↔SW2 and SW4↔SW5 must be switched to non-superposition mode. S&H1 operates as a differential voltage sampler, and S&H2 operates as a single-ended voltage holder. The two current mirrors are matched to have the same I REF It provides, and SW3 conducts only upon reset.

[0161] The sensor signal processing device above is I stabilized by a Gm / current mirror. REF Generates, and V formed in the sensor via buffer and S&H INAfter isolating and holding the voltage, it is directly supplied to a hybrid ADC (including control logic, comparator array, and resistor / current / capacitor-based DAC) to convert the voltage into digital. The switch is driven by non-overlapping timing and a dedicated reset path to suppress charge injection and kickback. Resistive, capacitor, and differential sensors can be processed within the same framework, and direct conversion is possible without pulse width conversion or external counters. This hybrid ADC can select or combine parallel, group split, and cyclic modes to simultaneously satisfy high-speed, high-resolution, and low-power requirements, while ensuring immunity to temperature and power changes as well as noise through reference current stabilization and S&H isolation.

[0162] In this specification (particularly in the claims), the above or similar descriptive terms may include both singular and plural forms depending on the context. Where numerical ranges are described, they may be interpreted to include each individual value within that range unless otherwise specified. The steps of the method may be performed in an appropriate order unless explicitly prescribed and may not be limited to the order described. The described embodiments are merely illustrative examples and should not be interpreted as limiting the scope of rights defined by the claims. Those skilled in the art may make various modifications, combinations, and substitutions, and such variations may be included within the scope of the claims and their equivalents.

[0163] Therefore, the scope of the present invention may be determined by the claims and equivalents set forth below.

Claims

1. A hybrid analog-to-digital converter device that generates an N-bit (N≥1, natural number) digital output, Control-logic circuit; n comparators (n≥1, natural number), wherein the comparators are input signal voltages (V A Generates a comparison output by comparing ) with the reference voltage; As a reference voltage generating circuit, it includes a circuit that provides a reference voltage preset to the comparator, and The control-logic circuit controls the reference voltage generation circuit according to the comparison output of the comparator, thereby generating the reference voltage or the input signal voltage (V) applied to one comparator or applied to at least one of a plurality of comparators. A A hybrid analog-to-digital converter device characterized by adjusting ).

2. In Paragraph 1, The above n comparators range from the first comparator (L1) that generates a comparison output by comparing the input signal voltage (VA) and the reference voltage to the nth comparator (L n Consists of, The above control-logic circuit controls the reference voltage of the lower bit comparator according to the comparison output of the higher bit, and A hybrid analog-to-digital converter device characterized in that the number of n comparators is set to be equal to the number of output bits N.

3. In Paragraph 1, At least one of the above comparators has a maximum reference voltage (V REF A hybrid analog-to-digital converter device characterized by providing a reference voltage of half the value of ), wherein the input signal voltage is transformed stepwise and repeatedly compared over a plurality of comparison stages.

4. In Paragraph 3, The above control-logic circuit determines the most significant bit (MSB) by using the input signal voltage as the maximum reference voltage (V REF Comparing with 1 / 2 value of ), and based on the MSB determination result, the 1 / 2 V at the input signal voltage REF A hybrid analog-to-digital converter device characterized by subtracting a portion of and expanding the remainder value by a predetermined ratio to generate the input signal voltage of the next stage.

5. In Paragraph 1, The above reference voltage generation circuit is a digital-to-analog conversion (DAC) circuit comprising at least one of a resistor element and a capacitor element based on current; A circuit that generates a reference voltage using a reference current source and a variable resistor; A circuit that generates a plurality of reference voltages using resistive voltage divider elements; and A hybrid analog-to-digital converter device characterized by including one of a circuit that generates a reference voltage using the charging or discharging of a capacitor.

6. In Paragraph 1, A hybrid analog-to-digital converter device characterized by the above comparators being composed of a plurality of groups, each group corresponding to some bits of the N-bit output, and the control-logic circuit determining the analog input signal voltage of a second group based on the comparison result of a first group and determining the analog input signal voltage of a third group based on the comparison result of a second group, thereby controlling sequential conversion for the plurality of groups, wherein the input signal voltage of a second group is generated by multiplying the difference obtained by subtracting the lowest bit reference voltage value of a first group from the input signal voltage of a first group by a constant multiplier determined according to the comparison result of a first group.

7. A hybrid analog-to-digital conversion method for obtaining an N-bit (N≥1, natural number) digital output, A step of generating at least one comparison result by comparing an analog input signal voltage with at least one reference voltage using n comparators (n≥1, natural number); A step of adjusting the reference voltage or the analog input signal voltage through a control-logic circuit according to the above comparison result; and A hybrid analog-to-digital conversion method characterized by including a step of generating the above comparison result and a step of determining each bit of the N-bit output by repeating the above adjustment step over a plurality of conversion steps for determining the output bit, or repeating the above adjustment step in a conversion group unit that processes a plurality of bits by grouping them into one group.

8. In Paragraph 7, The method further includes the step of processing the analog input signal by dividing it into a plurality of sets of bits and adjusting the analog input signal of the lower group according to the conversion result of the upper group, One of the reference voltages used in the step of generating the above comparison result is the maximum reference voltage (V REF Fix it at 1 / 2 of ), and A hybrid analog-to-digital conversion method characterized by changing the analog input signal voltage at each comparison step during the adjustment step to produce the N-bit digital output.

9. In Paragraph 7, A hybrid analog-to-digital conversion method characterized by further including the step of sampling and maintaining an analog signal proportional to the output of a sensor element prior to the step of generating the comparison result, and providing it as the analog input signal voltage.

10. A sensor element whose electrical characteristics change according to a physical quantity; A reference current source that applies a reference current to the sensor element to generate an analog input signal voltage corresponding to the output of the sensor element; A sample-and-hold circuit that samples and maintains the above analog input signal voltage; and A sensor signal processing device characterized by including a hybrid analog-to-digital converter (ADC) that generates an N-bit (N≥1, natural number) digital output by repeatedly comparing the analog input signal voltage using n comparators (n≥1, natural number) and a control-logic circuit.

11. In Paragraph 10, A sensor signal processing device characterized in that the sensor element is a resistance sensor or a capacitor sensor, and the reference current source applies a reference current to the sensor element that is not affected by changes in electrical characteristics due to changes in environmental conditions to generate the analog input signal voltage.

12. In Paragraph 10, The sensor element above includes a differentially connected first sensor and a second sensor, and The sensor signal processing device forms two analog voltages by applying a reference current to the first sensor and the second sensor, respectively, through a first current source and a second current source, and generates the analog input signal voltage by amplifying the differential signal between the two voltages using a differential amplifier, wherein the reference current source is implemented with an Operational Transconductance Amplifier (OTA) and a reference resistor, and the sample-and-hold circuit suppresses voltage fluctuations and noise during the conversion process to maintain the analog input signal voltage within a reference error range.

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