Method of transferring redistribution layers from carrier substrate to cavity of glass substrate to improve uniformity of redistribution layers

Abstract

Embodiments of a method of preparing an electro-optical chip package are provided. In the method, a plurality of redistribution layers (RDL) is provided onto a first major surface of a carrier substrate. The plurality of RDL is positioned over a glass substrate in which the glass substrate includes a third major surface, a fourth major surface, and a border surface. The glass substrate has a first thickness between the fourth major surface and the third major surface and a second thickness between the fourth major surface and the border surface. The first thickness is less than the second thickness such that the third major surface defines at least in part a cavity in the glass substrate. The plurality of RDL is transferred from the carrier substrate to the cavity of the glass substrate.

Description

METHOD OF TRANSFERRING REDISTRIBUTION LAYERS FROM CARRIER SUBSTRATE TO CAVITY OF GEASS SUBSTRATE TO IMPROVE UNIFORMITY OF REDISTRIBUTION LAYERSCROSS-REFERENCE TO REEATED APPLICATIONS

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application No. 63 / 725,227 filed November 26, 2024, the content of which is incorporated herein by reference in its entirety.BACKGROUND

[0002] The disclosure relates to integrated circuit packages having glass substrates and integrated chips coupled thereto.

[0003] High data transmission rates are desired for high performance computing and data center applications. Conventional optical interconnects that provide high data transmission rates may incur undesired expense due to the addition of components, may consume substantial power, and may be difficult to manufacture. Accordingly, integrated circuit packages that incorporate electrical and optical connectivity may be desired.SUMMARY

[0004] According to an aspect, embodiments of the disclosure relate to a method of preparing an electro-optical chip package. In the method, a plurality of redistribution layers (RDL) is provided onto a first major surface of a carrier substrate. The plurality of RDL is positioned over a glass substrate in which the glass substrate comprises a third major surface, a fourth major surface, and a border surface. The glass substrate comprises a first thickness between the fourth major surface and the third major surface and a second thickness between the fourth major surface and the border surface. The first thickness is less than the second thickness such that the third major surface defines at least in part a cavity in the glass substrate. The plurality of RDL is transferred from the carrier substrate to the cavity of the glass substrate.

[0005] According to another aspect, embodiments of the disclosure relate to an electro-optical chip package. The electro-optical chip package comprises a glass substrate comprising a first major surface, a second major surface, and a border surface. The border surface surrounds the first major surface, and the glass substrate comprises a first thickness as measured between the second major surface and the first major surface and a second thickness as measured between the second major surface and the border surface. The first thickness is less than the secondthickness so that the first major surface defines at least in part a cavity in the glass substrate. At least one via extends from the first major surface to the second major surface, and each of the at least one via has a wall coated with a conductive metal. A plurality of redistribution layers (RDL) is disposed in the cavity and in electrical communication with the conductive metal in the at least one via. An electronic component is mounted to the plurality of RDL.

[0006] According to still another aspect, embodiments of the disclosure relate to an electro- optical chip package. The electro-optical chip package comprises a glass substrate comprising a first major surface, a second major surface, and a border surface. The border surface surrounds the first maj or surface, and the glass substrate comprises a first thickness as measured between the second major surface and the first major surface and a second thickness as measured between the second major surface and the border surface. The first thickness is less than the second thickness so that the first major surface defines at least in part a cavity in the glass substrate. At least one via extends from the first maj or surface to the second maj or surface, and each of the at least one via has a wall coated with a conductive metal. A plurality of redistribution layers (RDL) is disposed in the cavity and in electrical communication with the conductive metal in the at least one via. Each RDL of the plurality of RDL comprises a thickness variation of 1 pm or less between a highest point of a surface of the RDL and a lowest point of the surface of the RDL as measured across the surface of each RDL.

[0007] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.

[0008] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understanding the nature and character of the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment s), and together with the description serve to explain principles and operation of the various embodiments. In the drawings:

[0010] FIG. 1 depicts an electro-optical chip package, according to an exemplary embodiment of the present disclosure;

[0011] FIG. 2 depicts a glass substrate having redistribution layers transferred into a cavity of a glass substrate, according to an exemplary embodiment of the present disclosure;

[0012] FIG. 3 schematically depicts a method of etching of a glass substrate and carrier substrate using masks formed from the same mask pattern, according to an exemplary embodiment of the present disclosure;

[0013] FIG. 4 depicts a carrier substrate having redistribution layers formed on a convex extension, according to an exemplary embodiment of the present disclosure;

[0014] FIG. 5 schematically depicts a method of forming redistribution layers on the carrier substrate after planarizing the carrier substrate, according to an exemplary embodiment of the present disclosure;

[0015] FIG. 6 depicts the through glass vias of the glass substrate coated with a conductive metal, according to an exemplary embodiment of the present disclosure; and

[0016] FIG. 7 schematically depicts a method of transferring a plurality of redistribution layers from the carrier substrate into the cavity of the glass substrate, according to an exemplary embodiment of the present disclosure.DETAILED DESCRIPTION

[0017] Reference will now be made in detail to various embodiments of an electro-optical chip package and a method of fabricating such an electro-optical chip package, examples of which are illustrated in the accompanying drawings. In an electro-optical chip package, optical signals are translated to electrical signals, and vice versa, for controlling the operation of an electronic component. As will be discussed more fully below, the electro-optical chip package includes redistribution layers (RDL) disposed within a cavity of a glass substrate, and according to the present disclosure, the RDL are fabricated on a separate flat substrate and transferred to the cavity of the glass substrate. In this way, warpage and thickness variation of the RDL is substantially reduced or eliminated. Accordingly, a photonic integrated circuit that translates the optical and electrical signals can be properly mounted to the RDL and glass substrate to efficiently receive / send electrical signals through the RDL and receive / send optical signals through the glass substrate. These and other aspects and advantages of the disclosed electro-optical chip package and method of making same will be described in relation to the embodiments provided below and in the drawings. These embodiments are presented by way of example and not by way of limitation.

[0018] Electro-optical chip packages for high-performance systems like data-center network switches and artificial intelligence (Al) and machine learning (ML) computer clusters have increasingly employed glass as a packaging and optical interconnect substrate. Electrical links with data rates of 100 Gbit and above have high propagation loss and require a significant amount of power for signal processing and re-timing. For that reason, there is a desire to move optics deeper into the system to minimize the electrical line length. Optical transceivers are assembled on a common substrate together with the electrical chips to reduce the electrical line length to a few millimeters instead of tens of centimeters, which provides significant power savings by eliminating digital signal processing and re-timing electrical circuits. FIG. 1 demonstrates an example packaging concept for a glass substrate in an electro-optical chip package.

[0019] FIG. 1 depicts an embodiment of an electro-optical chip package 10. In the embodiment depicted in FIG. 1, the electro-optical chip package 10 is mounted to a printed circuit board (PCB) 12. In particular, a first ball grid array (BGA) 14 provides electrical connection between the electro-optical chip package 10 and the PCB 12. The electro-optical chip package 10 comprises a glass substrate 15 on which one or more photonic integrated circuits (PIC) 16 and one or more electronic components 18 are mounted. In one or more embodiments, the electronic component 18 may be a single chip or combination of multiple chiplets that can comprise memory, central processing unit (CPU), a graphics processing unit (GPU), or / and application specific integrated circuit (ASIC), among other possibilities. Advantageously, the electro-optical chip package 10 may be a heterogeneously integrated chip package in which one or more chips or chiplets are assembled closely together (e.g., with spacings of tens of micrometers) to reduce electrical line length. In this way, the electro-optical chip package 10 provides a “system-in-package” with the same or improved functionality as compared to a “system-on-chip” but with reduced complexity and cost and increased yield. In the electro- optical chip package 10, the PIC 16 translates optical signals into electrical signals that are communicated to the electronic component 18 or translates electrical signals communicated from the electronic component 18 to optical signals.

[0020] The PIC 16 comprises a PIC waveguide 20 for receiving or transmitting optical signals into or out of the PIC 16. The glass substrate 15 has a glass waveguide 21 formed therein, and at an optical interface 22, the optical signals from the PIC waveguide 20 are exchanged with the glass waveguide 21. The glass waveguide 21 carries the optical signals to / from an optical connector 23, which is connected to an optical fiber 24. In this way, the optical fiber 24 maycarry optical signals to the electro-optical chip package 10 that are translated by the PIC 16 into electrical signals, which may be used in the operation of the electronic component 18. Additionally, electrical signals may be forwarded by the electronic component 18 to the PIC 16, which translates the electrical signals into optical signals to be carried off of the electro- optical chip package 10 by the optical fiber 24.

[0021] In addition, the PIC 16 and the electronic component 18 may send and receive electrical signals through the glass substrate 15 to the PCB 12. To route the electrical signals, the electro- optical chip package 10 comprises a first plurality of redistribution layers (RDL) 26 and a second plurality of RDL 28 connected by through glass vias (TGV) 30. As can be seen in FIG. 1, the first plurality of RDL 26 and the second plurality of RDL 28 are disposed on opposite sides of the glass substrate 15. The first plurality of RDL 26 is disposed between the glass substrate 15 and the PIC 16 and electronic component 18, and the second plurality of RDL 28 is disposed between the PCB 12 and the glass substrate 15. The first and second plurality of RDL 26, 28 may each comprise two or more layers of electrically conductive paths disposed within a dielectric material. The TGV 30 electrically connect the first plurality of RDL 26 and the second plurality of RDL 28 through the thickness of the glass substrate 15. The first plurality of RDL 26 is electrically connected to the PIC 16 and the electronic component 18 through electrical micro-bumps 32 on which the PIC 16 and electrical component 18 are mounted. Similarly, the second plurality of RDL 28 is electrically connected to the PCB 12 through the first BGA 14.

[0022] The present disclosure relates to the manner in which the first plurality of RDL 26 (hereinafter referred to as “RDL 26”) are attached to the glass substrate 15. As will be discussed more fully below in accordance with embodiments of the present disclosure, the RDL 26 are formed on a separate substrate to enhance the flatness and uniformity of the RDL layer thickness, and the RDL 26 are transferred from the separate substrate onto the glass substrate 15.

[0023] FIG. 2 depicts an embodiment of the glass substrate 15 before incorporation into the electro-optical chip package 10. As can be seen, the glass substrate 15 comprises a first major 50 surface, a second major surface 52, and a border surface 54. The border surface 54 surrounds the first major surface 50. The glass substrate 15 comprises a first thickness T1 as measured between the second major surface 52 and the first major surface 50 and a second thickness T2 as measured between the second major surface 52 and the border surface 54. Thefirst thickness T1 is less than the second thickness T2 so that the first major surface 50 defines at least in part a cavity 56 in the glass substrate 15. The RDL 26 is disposed in the cavity 56.

[0024] Further, as can be seen from FIG. 2, the TGV 30 extend from the first major surface 50 to the second major surface 52. Each of the TGV 30 has a wall 58 that is coated or coated and filled with a conductive metal 60.

[0025] As mentioned above, each layer of the RDL 26 comprises a plurality of conductive metal paths 62 surrounded by dielectric material 64. The RDL 26 are formed by various layer- by-layer fabrication techniques, and forming such layers within the cavity 56 (as is conventionally done) is difficult and prone to create non-uniform layers. Specifically, because the layers of the RDL 26 are individually and collectively smaller in thickness than the depth of the cavity 56, traditional planarization techniques, such as chemical-mechanical polishing (CMP), cannot be used to prevent warpage of the RDL 26 over successive layer depositions when the RDL 26 is built up within the cavity 56. Ultimately, small thickness deviations in each layer of the RDL 26 will create large thickness deviations in the overall RDL 26 structure. Such thickness deviations affect the ability of the PIC 16 (as shown in FIG. 1) to be properly placed on the glass substrate 15 to efficiently translate electrical and optical signals between the waveguide of the glass substrate 15 and the RDL 26. In particular, for certain glass substrate 15 configurations, the PIC 16 needs both optical and electrical interfaces to be bonded on the same level, and warpage of the RDL 26 from successive buildup of thickness deviations in each layer of the RDL 26 may prevent the PIC from level bonding.

[0026] Thus, as will be discussed more fully below, the RDL 26 are prepared on a flat substrate outside of the cavity 56 and transferred to the glass substrate 15. In one or more embodiments, the RDL 26 transferred to the cavity 56 are bonded to the glass substrate 15. In one or more embodiments, the first major surface 50 has been treated (e.g., using plasma or by application of a coating) to increase wettability of the RDL 26 on the first major surface 50 of the glass substrate. In one or more other embodiments, an adhesive layer is at least partially disposed between the RDL 26 and the first major surface 50. That is, the adhesive layer may only cover a continuous or discontinuous portion of the first major surface 50 to facilitate transfer of the RDL 26 into the cavity 56 of the glass substrate 15, leaving openings or pathways for electrical communication between the conductive metal paths 62 and the TGV 30, for example.

[0027] The RDL 26 can be bonded to the glass substrate 15 in a variety of different ways. For example, in one or more embodiments, the RDL 26 are bonded to the conductive metal 60 of the TGV 30 as shown in FIG. 2, e.g., using a technique such as laser bonding. In one or more other embodiments, the RDL 26 are bonded to bonding pads on the glass substrate 15 next tothe TGV 30. Still further, in one or more embodiments, the RDL 26 are adhered to the glass substrate 15, e.g., conductive adhesives. Additionally, in one or more embodiments, the RDL 26 are bonded to the glass substrate 15 using fusion bonding, solder bonding, or thermocompression bonding, amongst other possibilities. As mentioned, the RDL 26 are bonded to the glass substrate 15 in such a manner that electrical communication is provided between the conductive metal paths 62 of the RDL 26 and the conductive metal 60 of the TGV 30

[0028] As can be seen in FIG. 2, the RDL 26 comprises an outermost RDL defining a first RDL surface 66. The RDL surface 66 is spaced a furthest distance of the RDL 26 from the first major surface 50. In one or more embodiments, the RDL surface 66 is disposed between the border surface 54 and the first major surface 50 such that the RDL surface 66 is recessed relative to the border surface 54.

[0029] Having described the electro-optical chip package 10 and glass substrate 15, embodiments of methods for forming the RDL 26 and transferring the RDL 26 to the glass substrate 15 are now described.

[0030] FIG. 3 depicts a method 100 of preparing the glass substrate 15 and a carrier substrate 70 configured for transfer of the RDL 26. In the method 100, a first step 101 is the preparation of a mask pattern 72. As can be seen, the mask pattern 72 includes a first mask 74 for the carrier substrate 70 and a second mask 76 for the glass substrate 15. As shown in FIG. 3, a second step 102 is the application of the first mask 74 to the carrier substrate 70 and the second mask to the glass substrate 15. As will be discussed more fully below, in one or more embodiments, the shape of the carrier substrate 70 complements the cavity 56 of the glass substrate 15 such that both masks 72, 74 can be made from a single pattern 72. In a third step 103, the glass substrate 15 and the carrier substrate 70 are etched using an acid. The masks 72, 74 prevent etching of the respective substrates 15, 70 in the areas where the masks 72, 74 are located. For the glass substrate 15, the etching produces the cavity 56. FIG. 3 also shows the TGV 30 formed in the glass substrate 15 during or after etching of the cavity 56 using techniques known in the art. For the carrier substrate 70, the etching removes a peripheral region to define a convex extension 76. In one or more embodiments, the carrier substrate 70 is formed from glass, such as the same glass material as the glass substrate 15. In this way, the same etchant process can be used to etch both the glass substrate 15 and the carrier substrate 70.

[0031] FIG. 4 depicts the carrier substrate 70 with the RDL 26 deposited on the convex extension 76. As can be seen in the embodiment of FIG. 4, the carrier substrate 70 includes a third major surface 78 on which the RDL 26 is positioned. A fourth major surface 80 isopposite to the third major surface 78. In one or more embodiments, the second border surface 82 surrounds the third major surface 78, although the second border surface 82 is not necessarily required. The carrier substrate 70 comprises a third thickness T3 as measured between the fourth major surface 80 and the third major surface 78 and a fourth thickness T4 as measured between the second major surface 80 and the second border surface 82 (where included). The third thickness T3 is greater than the fourth thickness T4 so as to define at least in part the convex extension 76.

[0032] In one or more embodiments, the RDL 26 is formed on the third major surface 78 using layer-by-layer deposition techniques known in the art, typically involving iterative steps of conductive seed layer sputtering, application of a photoresist, photoresist layer photolithography, electrolytic plating of a conductive metal, planarization, stripping of the photoresist layer, conductive seed layer sputtering, and so on. In one or more embodiments, the RDL 26 includes layers of conductive metal paths 62 having a thickness in a range of 0.5 pm to 10 pm, in particular in a range of 1 pm to 5 pm. In one or more embodiments, the RDL 26 includes layers of dielectric material 64 having a thickness in a range of 1 pm to 15 pm, in particular in a range from 5 pm to 15 pm. Using the RDL 26 transfer process described herein, the variation in thickness across each combined layer (conductive metal paths 62 and dielectric material 64) of the RDL 26 is 1 pm or less. That is, a highest point measured across the surface of the combined layer of the RDL is less than 1 pm greater than a lowest point measured across the surface of the combined layer of the RDL as measured using various surface metrology techniques known in the art, such as by using a profilometer, interferometry, or digital holography, for example.

[0033] In one or more embodiments in which the carrier substrate 70 includes a second border surface 82, such as shown in FIG. 5, the carrier substrate 70 can be provided with a planarization layer 84 before providing the RDL 26 on the third major surface 78. In particular, certain processing equipment for depositing the RDL 26 may only work with flat substrates, and the planarization layer 84 may be used to make the carrier substrate 70 flat for deposition of the RDL 26. Thus, as shown in the method 200 of FIG. 5, in a first step 201, the carrier substrate 70 is provided with a planarization layer 84 over the second border surface 82. In this way, the surface of the planarization layer 84 is flush with the third major surface 78. In a second step 202, the RDL 26 are deposited on the third major surface 78, and finally in a third step 203, the planarization layer 84 is removed, leaving the carrier substrate 70 with the RDL 26 disposed thereon. In one or more embodiments, the planarization layer 84 is formed froma thermoplastic polymer such that the planarization layer 84 can be applied in a molten state, solidified, and removed after RDL deposition by heating the thermoplastic polymer.

[0034] FIG. 6 depicts the glass substrate 15 after the etching as shown in FIG. 3. In particular, in FIG. 6, the glass substrate 15 after etching includes the TGV 30, and the walls 58 of the TGV 30 are coated or coated and filled with a conductive metal 60. In one or more embodiments, the conductive metal 60 is coated onto the walls 58 using such metallization processes as providing an adhesion / seed layer through physical vapor deposition (PVD), chemical vapor deposition (CVD), or wet-chemical coating, for example; electroless plating may be used to form a conductive seed layer at the center of the TGV 30; and electrolytic plating may be used to fill the TGV 30 with the conductive metal. In one or more embodiments, the conductive metal used to coat and fill the TGV 30 is copper, gold, silver, or aluminum, amongst other possibilities. As can be seen in FIG. 6, the conductive metal 60 deposited in the TGV 30 extends around the periphery of the TGV 30 on the first major surface 50 and on the second major surface 52. The conductive metal 60 on the first major surface 50 and the second major surface 52 provides bonding area for connection of the first RDL 26 and the second RDL 28.

[0035] Referring now to FIG. 7, an exemplary embodiment of a method 300 of transferring the RDL 26 from the carrier substrate 70 to the cavity 56 of the glass substrate 15 is schematically depicted. In a first step 301 of the method 300, the carrier substrate 70 is positioned over the glass substrate 15 such that the convex extension 76 is positioned for insertion into the cavity 56 of the glass substrate 15. As can be seen, the RDL 26 is positioned such that it is disposed between the carrier substrate 70 and the glass substrate 15.

[0036] In a second step 302 of the method 300, the carrier substrate 70 is inserted into the cavity 56 of the glass substrate 15 such that the RDL 26 contacts the first major surface 50 of the glass substrate 15. As discussed above, in one or more embodiments, the masks for etching the glass substrate 15 and the carrier substrate 70 are formed from the same mask pattern, promoting a close fit and alignment between the cavity 56 of the glass substrate 15 and the convex extension 76 of the carrier substrate 70. Further, conventional wafer-bonding equipment and techniques can be adopted for precisely aligning the carrier substrate 70 and the glass substrate 15, in particular aligning electrodes of the RDL 26 and the TGV 30 for connection.

[0037] Thereafter, in a third step 303 of the method 300, the RDL 26 is transferred from the carrier substrate 70 to the glass substrate 15. The transfer between the carrier substrate 70 and the glass substrate 15 can be facilitated in a variety of ways. For example, various selectivelayer transfer techniques may be utilized, including laser bonding / debonding or UV treatment. In such embodiments, a laser is utilized to disrupt / join or deactivate / activate bonding between the RDL 26 and the carrier substrate 70 and the RDL 26 and the glass substrate 15, respectively. Further, in one or more embodiments, a polymer release layer may be provided between the carrier substrate 70 and the RDL 26. In this way, thermal energy applied to the carrier substrate 70 may cause release of the RDL 26 from the carrier substrate 70 while the RDL 26 is within the cavity 56 of the glass substrate 15.

[0038] Additionally, in one or more preferred embodiments, transfer of the RDL 26 is controlled by tuning the wettability of the RDL 26 with the respective carrier substrate 70 and glass substrate 15. In particular, the carrier substrate 70 can be treated to be more hydrophobic relative to the RDL 26, and the first major surface 50 defining the bottom of the cavity 56 of the glass substrate 15 can be made more hydrophilic. In this way, the RDL 26 will be more strongly attracted to the glass substrate 15 than the carrier substrate 70 such that, when the carrier substrate 70 is lifted away from the glass substrate 15, the RDL 26 transfer to the glass substrate 15. Modification of the hydrophilicity and hydrophobicity can be attained through various methods. For example, to make a hydrophilic surface, the first major surface 50 defining the bottom of the cavity 56 can be treated with O2 plasma to create a coating of SiCh, and the level of hydrophilicity can be configured by changing the O2 plasma conditions or the SiC>2 layer thickness. To create a more hydrophobic surface, fluoride-containing material coatings may be used. The level of hydrophobicity can be controlled by adjusting the number of fluorides substituted in a chemical or on an alkyl chain length of coating material. Increasing the amount of fluoride that is present in the coating will increase the hydrophobicity.

[0039] Still further, in addition to or in the alternative to the foregoing methods, the transfer of the RDL 26 can be facilitated by pre-heating the carrier substrate 70 and glass substrate 15 and pressing the carrier substrate 70 onto the glass substrate 15. In one or more embodiments, one or both of the substrates 15, 70 is pre-heated to a temperature in a range from 50 °C to 200 °C.

[0040] In a fourth step 304 of the method 300, the carrier substrate 70 is lifted free of the glass substrate 15, leaving the RDL 26 transferred to the cavity 56 of the glass substrate 15. In one or more embodiments, the carrier substrate 70 may be re-used in a subsequent process to transfer RDL 26 into another glass substrate 15.

[0041] While FIG. 7 depicts a carrier substrate 70 having a second border surface 82 surrounding the third major surface 78 to define a convex extension 76, the carrier substrate 70 does not need to include such a border surface 82, and the size and shape of the carrier substrate 70 may provide a third major surface 78 that is able to fit into the cavity 56 of the glass substrate15. That is, the length and width of the carrier substrate 70 may be less than the length and width of the first major surface 50 of the glass substrate 15 such that the carrier substrate 70 is insertable into the cavity 56. Still further, the carrier substrate 70 need not be the same substrate on which the RDL 26 is formed. That is, the RDL 26 can be formed on a separate flat substrate and then transferred to the carrier substate 70. Thereafter, the carrier substrate 70 can be used to transfer the RDL 26 to the glass substrate 15. In one or more such embodiments, the carrier substrate 70 is essentially a transfer tool between the substrate on which the RDL 26 is formed and the cavity 56 of the glass substrate 15.

[0042] Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is in no way intended that any particular order be inferred. In addition, as used herein, the article "a" is intended to include one or more than one component or element, and is not intended to be construed as meaning only one.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the disclosed embodiments. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the embodiments may occur to persons skilled in the art, the disclosed embodiments should be construed to include everything within the scope of the appended claims and their equivalents.

Claims

What is claimed is:

1. A method of preparing an electro-optical chip package, comprising: providing a plurality of redistribution layers (RDL) onto a first major surface of a carrier substrate; positioning the plurality of RDL over a glass substrate, the glass substrate comprising a third major surface, a fourth major surface, and a border surface, wherein the glass substrate comprises a first thickness between the fourth major surface and the third major surface and a second thickness between the fourth major surface and the border surface, the first thickness being less than the second thickness such that the third major surface defines at least in part a cavity in the glass substrate; and transferring the plurality of RDL from the carrier substrate to the cavity of the glass substrate.

2. The method of claim 1, wherein prior to the positioning, forming at least one through glass via in the glass substrate, each of the at least one through glass via extending from the third major surface to the fourth major surface.

3. The method of claim 2, further comprising metallizing the at least one through glass via with at least one conductive metal.

4. The method of claim 3, wherein metallizing comprises at least one of chemical vapor deposition, physical vapor deposition, wet chemical coating, electroless plating, or electrolytic plating of the conductive metal onto a wall of each of the at least one through glass via.

5. The method of any of claims 1-4, further comprising etching the glass substrate to remove glass material within the border surface to create the third major surface.

6. The method of any of claims 1-5, wherein the providing further comprises depositing the plurality of RDL on the first major surface.

7. The method of any of claims 1-5, wherein the providing further comprises forming the plurality of RDL on a flat substrate and transferring the plurality of RDL to the carrier substrate.

8. The method of any of claims 1-7, wherein the carrier substrate comprises a glass material.

9. The method of claim 8, further comprising etching the carrier substrate to remove the glass material outside the first major surface to create a second border surface surrounding the first major surface; and wherein the carrier substrate comprises a second major surface opposite to the first major surface, a third thickness measured between the second major surface and the first major surface, and a fourth thickness measured between the second major surface and the second border surface, the fourth thickness less than the third thickness such that the second border surface is disposed between the first major surface and the second major surface.

10. The method of claims 9, wherein, prior to the providing the plurality of RDL, the method further comprises: applying a planarization layer over the first border surface such that the planarization layer defines a surface level with the first major surface; depositing the plurality of RDL on the first major surface; and removing the planarization layer to uncover the first border surface.

11. The method of any of claims 1-10, wherein the transferring the plurality of RDL from the carrier substrate to the cavity of the glass substrate further comprises laser debonding the plurality of RDL from the carrier substrate and laser bonding the plurality of RDL to the glass substrate.

12. The method of any of claims 1-10, wherein the transferring the plurality of RDL from the carrier substrate to the cavity of the glass substrate further comprises UV treating a coating between the plurality of RDL and the third major surface of the carrier substrate to release the plurality of RDL from the third major surface.

13. The method of any of claims 1-10, further comprising preheating the carrier substrate and the glass substrate prior to the transferring the plurality of RDL from the carrier substrate to the cavity of the glass substrate.

14. The method of any of claims 1-10, further comprising plasma treating at least one of the first major surface or the third major surface to affect the wettability of the plurality of RDL with respect to the first major surface or the third major surface.

15. The method of any of claims 1-14, further comprising mounting an electronic component to the plurality of RDL.

16. An electro-optical chip package, comprising: a glass substrate comprising a first major surface, a second major surface, and a border surface surrounding the first major surface, the glass substrate comprising a first thickness measured between the second major surface and the first major surface and a second thickness measured between the second major surface and the border surface, the first thickness less than the second thickness such that the first major surface defines at least in part a cavity in the glass substrate; at least one via extending from the first major surface to the second major surface, the at least one via comprising a wall coated with a conductive metal;a plurality of redistribution layers (RDL) disposed in the cavity and in electrical communication with the conductive metal in the at least one via; and an electronic component mounted to the plurality of RDL.

17. The electro-optical chip package of claim 16, wherein the plurality of RDL is laser bonded to the first major surface.

18. The electro-optical chip package of claim 16, wherein the first major surface has been plasma-treated to increase wettability of the plurality of RDL on the first major surface.

19. The electro-optical chip package of any of claims 16-18, wherein the plurality of RDL comprises an outermost RDL spaced a farthest distance from the first major surface and disposed between the border surface and the first major surface such that the outermost RDL is recessed relative to the border surface.

20. The electro-optical chip package of any of claims 16-19, wherein each RDL of the plurality of RDL comprises a layer including a plurality of conductive metal paths surrounded by dielectric material.

21. An electro-optical chip package, comprising: a glass substrate comprising a first major surface, a second major surface, and a border surface surrounding the first major surface, the glass substrate comprising a first thickness measured between the second major surface and the first major surface and a second thickness measured between the second major surface and the border surface, the first thickness less than the second thickness such that the first major surface defines at least in part a cavity in the glass substrate; at least one via extending from the first major surface to the second major surface, the at least one via comprising a wall coated with a conductive metal; anda plurality of redistribution layers (RDL) disposed in the cavity and in electrical communication with the conductive metal in the at least one via; and wherein each RDL of the plurality of RDL comprises a thickness variation of 1 pm or less between a highest point of a surface of the RDL and a lowest point of the surface of the RDL as measured across the surface of each RDL.

22. The electro-optical chip package of claim 21, wherein each RDL of the plurality of RDL comprises a plurality of conductive metal paths surrounded by dielectric material.

23. The electro-optical chip package of claim 22, wherein the conductive metal paths comprise a thickness in a range of 0.5 pm to 10 pm.

24. The electro-optical chip package of claim 22 or claim 23, wherein the dielectric material comprises a thickness in a range firmo 1 pm to 15 pm.

25. The electro-optical chip package of any of claims 21-24, further comprising an electronic component mounted to the plurality of RDL.

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