Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a plurality of repeating units, each of which comprises a first sub-pixel and a second sub-pixel, wherein a pixel drive circuit in the first sub-pixel at least comprises an eleventh N-type transistor (N11) and an eleventh P-type transistor (P11), a pixel drive circuit in the second sub-pixel at least comprises a twenty-first N-type transistor (N21) and a twenty-first P-type transistor (P21), a gate electrode of the eleventh N-type transistor (N11) and a gate electrode of the twenty-first N-type transistor (N21) are connected to a first scan signal line (31), and a gate electrode of the eleventh P-type transistor (P11) and a gate electrode of the twenty-first P-type transistor (P21) are connected to a second scan signal line (32); and in at least one repeating unit, the ratio of an extension length of the first scan signal line (31) to an extension length of the second scan signal line (32) ranges from 0.95 to 1.05.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve weight reduction. Silicon-based OLEDs offer advantages such as small size, high resolution, and high refresh rate, and are widely used in near-eye displays for virtual reality and augmented reality. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of repeating units, each repeating unit including a first sub-pixel and a second sub-pixel. Both the first and second sub-pixels include pixel driving circuits. The pixel driving circuit in the first sub-pixel includes at least an eleventh N-type transistor and an eleventh P-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a twelfth P-type transistor forming transmission gates. The pixel driving circuit in the second sub-pixel includes at least a twenty-first N-type transistor and a twenty-first P-type transistor, a twenty-second N-type transistor, a twenty-third N-type transistor, and a twenty-second P-type transistor forming transmission gates. The gate electrodes of the eleventh N-type transistor and the twenty-first N-type transistor are connected to a first scan signal line. The gate electrodes of the eleventh P-type transistor and the twenty-first P-type transistor are connected to a second scan signal line. The first terminals of the eleventh N-type transistor and the eleventh P-type transistor are interconnected and connected to a first data signal line. The second terminals of the eleventh N-type transistor and the eleventh P-type transistor are connected to each other. The second terminals of the transistors are interconnected and connected to the gate electrode of the twelfth N-type transistor. The second terminal of the twelfth N-type transistor is connected to the second terminal of the thirteenth N-type transistor and the first terminal of the twelfth P-type transistor. The first terminals of the twentieth N-type transistor and the twentieth P-type transistor are interconnected and connected to the second data signal line. The second terminals of the twentieth N-type transistor and the twentieth P-type transistor are interconnected and connected to the gate electrode of the twentieth N-type transistor. The second terminal of the twentieth N-type transistor is connected to the second terminal of the twentieth N-type transistor and the first terminal of the twentieth P-type transistor. The first scan signal line and the second scan signal line are zigzag lines whose main body extends along a first direction. The first scan signal line is disposed on one side of the second scan signal line in a second direction. The first direction and the second direction intersect. In at least one repeating unit, the ratio of the extension length of the first scan signal line to the extension length of the second scan signal line is 0.95 to 1.05.

[0005] In an exemplary embodiment, in at least one repeating unit, both the first scan signal line and the second scan signal line include a plurality of horizontal sub-lines and a plurality of vertical sub-lines. The horizontal sub-lines are straight lines extending along the first direction, and the vertical sub-lines are straight lines extending along the second direction. The number of horizontal sub-lines in the first scan signal line is equal to the number of horizontal sub-lines in the second scan signal line, and the number of vertical sub-lines in the first scan signal line is equal to the number of vertical sub-lines in the second scan signal line.

[0006] In an exemplary embodiment, the first electrode of the twelfth N-type transistor and the first electrode of the second twelfth N-type transistor are both connected to the first power supply line. The first data signal line, the second data signal line, and the first power supply line are in the shape of a straight line or a broken line whose main body extends along the second direction. In at least one repeating unit, the first power supply line is disposed between the first data signal line and the second data signal line.

[0007] In an exemplary embodiment, the gate electrode of the thirteenth N-type transistor and the gate electrode of the twenty-third N-type transistor are connected to the third scan signal line; at least one repeating unit further includes a forty-fourth connection electrode connected to the third scan signal line; in the first direction, the forty-fourth connection electrode is disposed between the first data signal line and the first power supply line.

[0008] In an exemplary embodiment, at least one repeating unit further includes a thirty-first connecting electrode having the potential of a first node in the first sub-pixel, the thirty-first connecting electrode being disposed between the first power line and the forty-fourth connecting electrode; a shielding strip and a shielding frame are connected to the forty-fourth connecting electrode, the shielding strip being disposed on one side of the third-first connecting electrode in the second direction, and the shielding frame being disposed on one side of the third-first connecting electrode in the second direction, the forty-fourth connecting electrode, the shielding strip, and the shielding frame forming a structure that semi-encloses the thirty-first connecting electrode.

[0009] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuit of the first sub-pixel further includes a first storage capacitor, the first storage capacitor including at least an eleventh capacitor and a twelfth capacitor connected in parallel; the pixel driving circuit of the second sub-pixel further includes a second storage capacitor, the second storage capacitor including at least a twenty-first capacitor and a twenty-second capacitor connected in parallel; in at least one repeating unit, the eleventh capacitor and the twenty-first capacitor are disposed in the middle region of the repeating unit in the first direction, the eleventh capacitor and the twenty-first capacitor are sequentially disposed along the second direction, and the twenty-first capacitor is disposed on one side of the eleventh capacitor in the second direction; the twelfth N-type transistor and the twenty-twelfth N-type transistor are disposed in the edge regions on both sides of the eleventh capacitor and the twenty-first P-type transistor in the first direction, the eleventh N-type transistor and the eleventh P-type transistor are disposed between the eleventh capacitor and the twelfth N-type transistor, and the twenty-first N-type transistor and the twenty-first P-type transistor are disposed between the twenty-first capacitor and the twenty-first N-type transistor in the first sub-pixel.

[0010] In an exemplary embodiment, in at least one repeating unit, the eleventh N-type transistor is disposed on the side of the twelfth N-type transistor near the eleventh capacitor, and the eleventh P-type transistor is disposed on the side of the eleventh N-type transistor near the eleventh capacitor; the twenty-first N-type transistor is disposed on the side of the twelfth N-type transistor near the twenty-first capacitor, and the twenty-first P-type transistor is disposed on the side of the twenty-first N-type transistor near the twenty-first capacitor. The twenty-first N-type transistor is disposed on one side of the eleventh N-type transistor in the second direction, and the twenty-first P-type transistor is disposed on one side of the eleventh P-type transistor in the second direction.

[0011] In an exemplary embodiment, in at least one repeating unit, the twelfth P-type transistor is disposed between the twelfth N-type transistor and the eleventh N-type transistor, the thirteenth N-type transistor is disposed between the twelfth N-type transistor and the eleventh N-type transistor, the twelfth P-type transistor is disposed between the twelfth N-type transistor and the eleventh capacitor, the thirteenth N-type transistor is disposed on one side of the twelfth P-type transistor in the second direction, and the thirteenth N-type transistor is disposed on one side of the twelfth P-type transistor in the second direction.

[0012] In an exemplary embodiment, the eleventh capacitor includes an eleventh and a twelfth electrode stacked together, the orthographic projection of the twelfth electrode on the display substrate plane at least partially overlapping the orthographic projection of the eleventh electrode on the display substrate plane; the second eleventh capacitor includes a second eleventh and a second twelfth electrode stacked together, the orthographic projection of the second twelfth electrode on the display substrate plane at least partially overlapping the orthographic projection of the second eleventh electrode on the display substrate plane; the orthographic projection of the first scan signal line on the display substrate plane at least partially overlaps the gate electrode of the second eleventh N-type transistor, the gate electrode of the second eleventh P-type transistor, and the orthographic projection of the second twelfth electrode on the display substrate plane; at least one repeating unit further includes a first compensation electrode, the first compensation electrode being connected to the first scan signal line, the orthographic projection of the first compensation electrode on the display substrate plane at least partially overlapping the gate electrode of the eleventh N-type transistor, the gate electrode of the eleventh P-type transistor, and the orthographic projection of the twelfth electrode on the display substrate plane.

[0013] In an exemplary embodiment, the eleventh capacitor includes a stacked eleventh plate and a twelfth plate, the orthographic projection of the twelfth plate on the display substrate plane at least partially overlapping the orthographic projection of the eleventh plate on the display substrate plane; the second eleventh capacitor includes a stacked twenty-first plate and a twenty-second plate, the orthographic projection of the twenty-second plate on the display substrate plane at least partially overlapping the orthographic projection of the twenty-first plate on the display substrate plane; the orthographic projection of the second scan signal line on the display substrate plane at least partially overlaps the gate electrode of the eleventh N-type transistor, the gate electrode of the eleventh P-type transistor, and the orthographic projection of the twelfth plate on the display substrate plane; at least one repeating unit further includes a second compensation electrode, the second compensation electrode being connected to the second scan signal line, the orthographic projection of the second compensation electrode on the display substrate plane at least partially overlapping the gate electrode of the twenty-first N-type transistor, the gate electrode of the twenty-first P-type transistor, and the orthographic projection of the twenty-second plate on the display substrate plane.

[0014] In an exemplary embodiment, a capacitor compensation block is connected to the second scanning signal line, and the orthographic projection of the capacitor compensation block on the display substrate plane at least partially overlaps with the orthographic projection of the twelfth electrode plate on the display substrate plane.

[0015] In an exemplary embodiment, the twelfth N-type transistor includes at least a twelfth N-type active region, the thirteenth N-type transistor includes at least a thirteenth N-type active region, the twelfth P-type transistor includes at least a twelfth P-type active region, the twelfth N-type transistor includes at least a twenty-twelfth N-type active region, the thirteenth N-type transistor includes at least a twenty-thirteenth N-type active region, and the twelfth P-type transistor includes at least a twenty-twelfth P-type active region; a first spacing exists between the twelfth N-type active region and the twelfth P-type active region, or a first spacing exists between the twelfth N-type active region and the thirteenth N-type active region; a second spacing exists between the twelfth N-type active region and the thirteenth N-type active region, or a second spacing exists between the twelfth N-type active region and the thirteenth N-type active region; the first spacing is greater than the second spacing, and the first spacing and the second spacing are dimensions in the first direction.

[0016] In an exemplary embodiment, the eleventh-N type transistor includes at least an eleventh-N type active region, the thirteenth-N type transistor includes at least a thirteenth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, and the twelfth-P type transistor includes at least a twelfth-P type active region; a third spacing is provided between the eleventh-N type active region and the twelfth-P type active region, and a fourth spacing is provided between the thirteenth-N type active region and the twenty-first-N type active region, wherein the third spacing is greater than the fourth spacing, and the third spacing and the fourth spacing are dimensions in the first direction.

[0017] In an exemplary embodiment, the eleventh-N type transistor includes at least an eleventh-N type active region, the eleventh-P type transistor includes at least an eleventh-P type active region, the twelfth-N type transistor includes at least a twelfth-N type active region, the thirteenth-N type transistor includes at least a thirteenth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, the twenty-second-N type transistor includes at least a twenty-second-N type active region, and the twenty-third-N type transistor includes at least a twenty-third-N type active region; a second spacing exists between the twelfth-N type active region and the thirteenth-N type active region, or a second spacing exists between the twenty-second-N type active region and the twenty-third-N type active region; a fourth spacing exists between the thirteenth-N type active region and the twenty-first-N type active region, and a fifth spacing exists between the eleventh-N type active region and the eleventh-P type active region, the fifth spacing being greater than the second spacing and the fifth spacing being greater than the fourth spacing, wherein the second spacing, the fourth spacing, and the fifth spacing are dimensions in the first direction.

[0018] In an exemplary embodiment, the twelfth N-type transistor includes at least a twelfth N-type active region, the thirteenth N-type transistor includes at least a thirteenth N-type active region, the twentieth N-type transistor includes at least a twenty-first N-type active region, the twentieth N-type transistor includes at least a twenty-second N-type active region, the thirteenth N-type transistor includes at least a twenty-third N-type active region, and the twentieth P-type transistor includes at least a twenty-first P-type active region; a second spacing exists between the twelfth N-type active region and the thirteenth N-type active region, or a second spacing exists between the twentieth N-type active region and the thirteenth N-type active region; a fourth spacing exists between the thirteenth N-type active region and the twentieth N-type active region, and a sixth spacing exists between the twentieth N-type active region and the twentieth P-type active region, the sixth spacing being greater than the second spacing and the sixth spacing being greater than the fourth spacing, wherein the second spacing, the fourth spacing, and the sixth spacing are dimensions in the first direction.

[0019] In an exemplary embodiment, the eleventh-N type transistor includes at least an eleventh-N type active region, the thirteenth-N type transistor includes at least a thirteenth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, the eleventh-P type transistor includes at least an eleventh-P type active region, the twelfth-P type transistor includes at least a twelfth-P type active region, and the twenty-first-P type transistor includes at least a twenty-first-P type active region; a seventh spacing is provided between the twelfth-P type active region and the thirteenth-N type active region, an eighth spacing is provided between the eleventh-N type active region and the twenty-first-N type active region, and a ninth spacing is provided between the eleventh-P type active region and the twenty-first-P type active region; the seventh spacing is greater than the eighth spacing, the seventh spacing is greater than the ninth spacing, and the seventh spacing, the eighth spacing, and the ninth spacing are dimensions in the second direction.

[0020] In an exemplary embodiment, the eleventh-N type transistor includes at least an eleventh-N type active region, the twelfth-N type transistor includes at least a twelfth-N type active region, the twentieth-first-N type transistor includes at least a twentieth-first-N type active region, the twentieth-second-N type transistor includes at least a twentieth-second-N type active region, the eleventh-P type transistor includes at least an eleventh-P type active region, the twelfth-P type transistor includes at least a twelfth-P type active region, the twentieth-first-P type transistor includes at least a twentieth-first-P type active region, and the twentieth-second-P type transistor includes at least a twentieth-second-P type active region; the active length of the eleventh-P type active region 111P is less than the active length of the eleventh-N type active region 111N, the active length of the twelfth-P type active region is less than the active length of the twelfth-N type active region, the active length of the twelfth-P type active region is less than the active length of the twelfth-first-N type active region, and the active length of the twentieth-second-P type active region is less than the active length of the twentieth-second-N type active region.

[0021] In an exemplary embodiment, the second electrode of the eleventh N-type transistor and the second electrode of the eleventh P-type transistor are interconnected by a first connection electrode having a potential of the first node in the first sub-pixel; at least one repeating unit further includes a power connection line having a potential of a second power signal and a shielding block, the power connection line being a straight line or a broken line extending along the first direction, the shielding block being a strip extending along the second direction and connected to the power connection line; the shielding block is disposed on one side of the first connection electrode in the opposite direction to the first direction, the power connection line is disposed on one side of the first connection electrode in the second direction, and the power connection line and the shielding block form a structure that semi-encloses the first connection electrode.

[0022] In an exemplary embodiment, at least one repeating unit further includes a second eleventh connecting electrode having a potential of a first node in the first sub-pixel, a power connection line having a potential of a second power signal, and a shielding block. The second eleventh connecting electrode is connected to the gate electrode of the twelfth N-type transistor. The shape of the power connection line is a straight line or a broken line extending along the first direction. The shape of the shielding block is a strip extending along the second direction and is connected to the power connection line. The shielding block is disposed on one side of the second eleventh connecting electrode in the first direction, and the power connection line is disposed on one side of the second eleventh connecting electrode in the second direction. The power connection line and the shielding block form a structure that semi-encloses the second eleventh connecting electrode.

[0023] In an exemplary embodiment, the second electrode of the 21st N-type transistor and the second electrode of the 21st P-type transistor are interconnected via an 11th connection electrode having a potential of the first node in the second sub-pixel; at least one repeating unit further includes a 25th connection electrode having a potential of a second power signal and an electrode compensation block, the 25th connection electrode being in the shape of a straight line or a broken line extending along the first direction, the electrode compensation block being in the shape of a block and connected to the 25th connection electrode; the electrode compensation block is disposed on one side of the 11th connection electrode in the first direction, the 25th connection electrode is disposed on one side of the 11th connection electrode in the second direction, and the 25th connection electrode and the electrode compensation block form a structure that semi-encloses the 11th connection electrode.

[0024] In an exemplary embodiment, at least one repeating unit further includes a second thirteenth connecting electrode having a potential of a first node in the second sub-pixel, and a ninth connecting electrode, a twenty-fifth connecting electrode, and an electrode connecting strip having a potential of a second power signal. The second thirteenth connecting electrode is connected to the gate electrode of the second twelfth N-type transistor. The electrode connecting strip is disposed on one side of the second thirteenth connecting electrode in the opposite direction to the first direction. The ninth connecting electrode and the twenty-fifth connecting electrode are respectively disposed on both sides of the second thirteenth connecting electrode in the second direction, and the ninth connecting electrode is connected to the twenty-fifth connecting electrode through the electrode connecting strip. The ninth connecting electrode, the twenty-fifth connecting electrode, and the electrode connecting strip form a structure that semi-encloses the second thirteenth connecting electrode.

[0025] In an exemplary embodiment, at least one repeating unit further includes a thirty-fifth connecting electrode having the potential of the first node in the second sub-pixel, a second power line, and a third vertical power line. The second power line and the third vertical power line are in the shape of a straight line or a broken line extending along the second direction. The third vertical power line is disposed on the side opposite to the first direction of the second power line and is connected to the second power line through a plurality of fifth power connecting blocks. The thirty-fifth connecting electrode is disposed within the annular structure formed by the second power line, the third vertical power line, and the fifth power line.

[0026] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0029] Figure 1 is a schematic diagram of a silicon-based OLED display device;

[0030] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0031] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device;

[0032] Figure 4A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0033] Figure 4B is a driving timing diagram of the pixel driving circuit shown in Figure 4A;

[0034] Figure 5 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram showing the N-well region and P-well region patterns formed according to the embodiments of this disclosure;

[0036] Figure 7 is a schematic diagram of the active region pattern formed according to the embodiments of this disclosure;

[0037] Figures 8A and 8B are schematic diagrams of the gate conductive layer pattern formed according to an embodiment of the present disclosure;

[0038] Figures 9A and 9B are schematic diagrams of the P-type doped region pattern formed according to the embodiments of this disclosure;

[0039] Figures 10A and 10B are schematic diagrams of the N-type doped region pattern formed according to the embodiments of this disclosure;

[0040] Figure 11 is a schematic diagram of the second insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0041] Figures 12A and 12B are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure;

[0042] Figure 13 is a schematic diagram of the third insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0043] Figures 14A and 14B are schematic diagrams of the second conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0044] Figure 15 is a schematic diagram of the fourth insulating layer pattern formed according to an embodiment of the present disclosure;

[0045] Figures 16A and 16B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0046] Figure 17 is a schematic diagram of the fifth insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0047] Figures 18A and 18B are schematic diagrams of the fourth conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0048] Figures 19A and 19B are schematic diagrams showing the formation of the sixth insulating layer and the fifth conductive layer according to an embodiment of the present disclosure;

[0049] Figure 20 is a schematic diagram of the seventh insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0050] Figures 21A and 21B are schematic diagrams of the formation of the sixth conductive layer pattern according to an embodiment of the present disclosure;

[0051] Figure 22 is a schematic diagram of the formation of the eighth insulating layer pattern according to an embodiment of the present disclosure;

[0052] Figure 23 is a schematic diagram of the structure of the storage capacitor in an embodiment of this disclosure. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0055] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0058] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0060] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0061] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0063] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0064] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0065] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0066] Figure 1 is a schematic diagram of a silicon-based OLED display device. As shown in Figure 1, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is connected to the i-th scan signal line and the j-th data signal line, respectively. i and j can be natural numbers. The non-display area may include at least a gate driver (GD) and a source driver (SD). The gate driver is connected to multiple scan signal lines in the display area and is configured to provide the necessary timing signals to the connected pixel driving circuits to achieve progressive scan functionality. The source driver is connected to multiple data signal lines in the display area and is configured to provide the necessary data signals to the connected pixel driving circuits to achieve switching and control of the display screen.

[0067] In one exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture, integrating gate driving devices, data driving devices, clock control circuits, image processing units, and memory units onto the same chip. The one-chip architecture chip includes both digital and analog parts, belonging to mixed-signal chips.

[0068] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture, in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control circuit, the image processing unit, the mobile industry processor interface (MIPI), and the memory unit are integrated in one chip, which is bonded to the display substrate through a COC process.

[0069] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device. As shown in Figure 2, on a plane parallel to the display device, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0070] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0071] In exemplary embodiments, the shape of a sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular pattern, etc., and this disclosure does not limit the arrangement. In other possible embodiments, a pixel unit may include four sub-pixels, and this disclosure does not limit the arrangement.

[0072] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device, illustrating a structure that achieves full color using a white light + color filter approach. As shown in Figure 3, in the direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited herein.

[0073] In an exemplary embodiment, the silicon substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be fabricated on the silicon substrate 101 using silicon semiconductor processes. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor can include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, source electrode S, and drain electrode D can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0074] In an exemplary embodiment, the light-emitting structure layer 103 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode D of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0075] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can employ thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is located in the red sub-pixel and filters the white light emitted by the light-emitting device into red light. The blue filter unit is located in the blue sub-pixel and filters the white light emitted by the light-emitting device into blue light. The green filter unit is located in the green sub-pixel and filters the white light emitted by the light-emitting device into green light. The cover plate layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0076] Currently, silicon-based OLED displays are increasingly being applied in near-eye display fields such as Virtual Reality (VR), Augmented Reality (AR), Extended Reality (XR), and Mixed Reality (MR), allowing users to experience realistic sensations in the virtual reality world. These displays offer powerful simulation systems and enable human-computer interaction. Research shows that when screen resolution is high enough, the human retina cannot distinguish individual pixels. Resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display substrate can display images at a higher density, resulting in richer image details. Therefore, significantly increasing PPI has become a key research focus for manufacturers to improve display quality.

[0077] An exemplary embodiment of this disclosure provides a display substrate including a plurality of repeating units, each repeating unit including a first sub-pixel and a second sub-pixel. Both the first and second sub-pixels include pixel driving circuits. The pixel driving circuit in the first sub-pixel includes at least an eleventh N-type transistor and an eleventh P-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a twelfth P-type transistor forming transmission gates. The pixel driving circuit in the second sub-pixel includes at least a twenty-first N-type transistor and a twenty-first P-type transistor, a twenty-second N-type transistor, a twenty-third N-type transistor, and a twenty-second P-type transistor forming transmission gates. The gate electrodes of the eleventh N-type transistor and the twenty-first N-type transistor are connected to a first scan signal line. The gate electrodes of the eleventh P-type transistor and the twenty-first P-type transistor are connected to a second scan signal line. The first terminals of the eleventh N-type transistor and the eleventh P-type transistor are interconnected and connected to a first data signal line. The second terminal of the eleventh N-type transistor and the eleventh P-type transistor are connected to each other. The second terminals of the 21st N-type transistors are interconnected and connected to the gate electrode of the 12th N-type transistor. The second terminal of the 12th N-type transistor is connected to the second terminal of the 13th N-type transistor and the first terminal of the 12th P-type transistor. The first terminals of the 21st N-type transistor and the 21st P-type transistor are interconnected and connected to the second data signal line. The second terminals of the 21st N-type transistor and the 21st P-type transistor are interconnected and connected to the gate electrode of the 22nd N-type transistor. The second terminal of the 22nd N-type transistor is connected to the second terminal of the 23rd N-type transistor and the first terminal of the 22nd P-type transistor. The first scan signal line and the second scan signal line are zigzag lines whose main body extends along a first direction. The first scan signal line is disposed on one side of the second scan signal line in a second direction. The first direction and the second direction intersect. In at least one repeating unit, the ratio of the extension length of the first scan signal line to the extension length of the second scan signal line is 0.95 to 1.05.

[0078] The technical solution of the display substrate of this disclosure is described below through exemplary embodiments.

[0079] Figure 4A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4A, the pixel driving circuit of the present disclosure has a 5T1C structure, which may include 5 transistors (a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a first P-type transistor P1, and a second P-type transistor P2) and a storage capacitor C. The pixel driving circuit is coupled to 8 signal lines (a first scan signal line G1, a second scan signal line G2, a third scan signal line G3, a reference signal line REF, an initial signal line INIT, a data signal line DATA, a first power supply line VDD, and a second power supply line VSS).

[0080] In an exemplary embodiment, the pixel driving circuit may include a first node S1 and a second node S2. The first node S1 is coupled to the second terminal of a first N-type transistor N1, the second terminal of a first P-type transistor P1, the gate electrode of a second N-type transistor N2, and the first terminal of a storage capacitor C. The second node S2 is coupled to the second terminal of a second N-type transistor N2, the second terminal of a third N-type transistor N3, and the first terminal of a second P-type transistor P2.

[0081] In an exemplary embodiment, the gate electrode of the first N-type transistor N1 is coupled to the first scan signal line G1, the first electrode of the first N-type transistor N1 is coupled to the data signal line DATA, and the second electrode of the first transistor N1 is coupled to the first node S1.

[0082] In an exemplary embodiment, the gate electrode of the first P-type transistor P1 is coupled to the second scan signal line G2, the first electrode of the first P-type transistor P1 is coupled to the data signal line DATA, and the second electrode of the first P-type transistor P1 is coupled to the first node S1.

[0083] In an exemplary embodiment, the first N-type transistor N1 and the first P-type transistor P1 form a transmission gate with complementary characteristics, which can transmit data signals to the storage capacitor without voltage loss, thereby effectively improving the data range.

[0084] In an exemplary embodiment, the gate electrode of the second N-type transistor N2 is coupled to the first node S1, the first electrode of the second N-type transistor N2 is coupled to the first power line VDD, and the second electrode of the second N-type transistor N2 is coupled to the second node S2. The potential of the first node S1 can control the second N-type transistor N2. Through the source follower principle, the voltage change of the gate electrode of the second N-type transistor N2 can realize the control of the voltage of the first electrode of the light-emitting device EL. Corresponding to different grayscale data signals, the light-emitting device EL outputs the corresponding brightness.

[0085] In an exemplary embodiment, the gate electrode of the third N-type transistor N3 is coupled to the third scan signal line G3, the first electrode of the third N-type transistor N3 is coupled to the initial signal line INIT, and the second electrode of the third N-type transistor N3 is coupled to the second node S2.

[0086] In an exemplary embodiment, the gate electrode of the second P-type transistor P2 is coupled to the reference signal line REF, the first electrode of the second P-type transistor P2 is coupled to the second node S2, and the second electrode of the second P-type transistor P2 is coupled to the first electrode of the light-emitting device EL.

[0087] In an exemplary embodiment, the function of the second P-type transistor P2 is that when the data signal voltage is low, the gate-source voltage of the second P-type transistor P2 is less than the threshold voltage, which reduces the current flowing through the light-emitting device EL, resulting in lower brightness at low gray levels (especially 0 gray level) and achieving higher contrast. Furthermore, when the first and second terminals of the light-emitting device EL are short-circuited, the parasitic PN junction of the second P-type transistor P2 is reverse-biased. The second P-type transistor P2, being in an open state, prevents the negative voltage of the common voltage line VCOM from being transmitted to the second node S2, thus preventing latch-up of the second N-type transistor N2 and effectively avoiding defects in the entire display area caused by a short circuit in the light-emitting device EL.

[0088] In an exemplary embodiment, the first end of the storage capacitor C is coupled to the first node S1, and the second end of the storage capacitor C is coupled to the second power line VSS.

[0089] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. The first electrode of the light-emitting device EL is connected to the second node S2, and the second electrode of the light-emitting device EL is connected to the common voltage line VCOM.

[0090] In an exemplary embodiment, the signal of the first power line VDD can be a continuously supplied first power signal (high-level signal), the signal of the second power line VSS can be a continuously supplied second power signal (low-level signal), the voltage of the first power signal is greater than the voltage of the second power signal, and the signal of the common voltage line VCOM can be a continuously supplied low-level signal.

[0091] Figure 4B is a timing diagram of one possible driving mechanism for the pixel driving circuit shown in Figure 4A. As shown in Figure 4B, the operation of the pixel driving circuit may include:

[0092] The first stage, A1, can be called the initialization stage. The signal on the first scan signal line G1 is low, while the signals on the second scan signal line G2 and the third scan signal line G3 are high. The transmission gate formed by the first N-type transistor N1 and the first P-type transistor P1 is open, and the third N-type transistor N3 is turned on. The open transmission gate makes the first node S1 float, and the turned-on third N-type transistor N3 causes the initial signal output from the initial signal line INIT to be sent to the second node S2, initializing the second node S2.

[0093] The second stage, A2, can be called the data writing stage. The signal on the first scan signal line G1 is high, while the signals on the second scan signal line G2 and the third scan signal line G3 are low. The transmission gate composed of the first N-type transistor N1 and the first P-type transistor P1 is turned on, and the third N-type transistor N3 is turned off. The turn-on transmission gate causes the data signal output from the data signal line DATA to be written to the first node S1 and continuously charge the storage capacitor C. The potential of the first node S1 (the gate electrode of the second N-type transistor N2) is the voltage of the data signal. The turn-off of the third N-type transistor N3 causes the second node S2 to float.

[0094] The third stage, A3, can be called the light-emitting stage. The signal on the second scan signal line G2 is high, while the signals on the first scan signal line G1 and the third scan signal line G3 are low. The transmission gate formed by the first N-type transistor N1 and the first P-type transistor P1 is open, and the third N-type transistor N3 is also open. The first power signal output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting device EL through the second N-type transistor N2 in source follower mode, driving the light-emitting device EL to emit light.

[0095] An exemplary embodiment of this disclosure provides a display substrate, which may include a plurality of repeating units on a plane parallel to the display substrate. The repeating units are basic units constituting the display substrate. The display substrate can be constructed by repeatedly and continuously arranging repeating units along a first direction X and along a second direction Y, where the first direction X intersects the second direction Y.

[0096] In an exemplary embodiment, multiple repeating units arranged sequentially along the first direction X can form a unit row, and multiple repeating units arranged sequentially along the second direction Y can form a unit column. The multiple unit rows and multiple unit columns constitute an array of repeating units arranged in an array.

[0097] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a pixel driving circuit structure of 6 repeating units (12 sub-pixels) in 3 unit rows and 2 unit columns. At least one repeating unit may include a first sub-pixel and a second sub-pixel. The second sub-pixel may be disposed on one side of the first sub-pixel in the first direction X. Both the first sub-pixel and the second sub-pixel may include a pixel driving circuit, which is connected to a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a first power line 41, a second power line 42, a data signal line 43, a reference signal line 44, and an initial signal line 45, respectively.

[0098] In an exemplary embodiment, the first scan signal line 31, the second scan signal line 32, and the third scan signal line 33 are configured to provide a first scan signal, a second scan signal, and a third scan signal to the pixel driving circuit, respectively. The first power supply line 41 and the second power supply line 42 are configured to provide a first power supply signal and a second power supply signal to the pixel driving circuit, respectively. The voltage of the first power supply signal can be greater than the voltage of the second power supply signal. The reference signal line 44 and the initial signal line 45 are configured to provide a reference signal and an initial signal to the pixel driving circuit, respectively. The multiple signal lines connected to the pixel driving circuit can be located within corresponding repeating units.

[0099] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, and the third scan signal line 33 can be zigzag lines extending along the first direction X of the main body, and the shapes of the first power line 41, the second power line 42, the data signal line 43, the reference signal line 44, and the initial signal line 45 can be straight lines or zigzag lines extending along the second direction Y of the main body, and the first direction X and the second direction Y can be perpendicular to each other.

[0100] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0101] In an exemplary embodiment, the pixel driving circuit in the first sub-pixel may include: a first storage capacitor as storage capacitor C in FIG4, an eleventh N-type transistor N11 as the first N-type transistor N1 in FIG4, a twelfth N-type transistor N12 as the second N-type transistor N2 in FIG4, a thirteenth N-type transistor N13 as the third N-type transistor N3 in FIG4, an eleventh P-type transistor P11 as the first P-type transistor P1 in FIG4, and a twelfth P-type transistor P12 as the second P-type transistor P2 in FIG4. The pixel driving circuit in the second sub-pixel may include: a second storage capacitor as storage capacitor C in FIG4, a twenty-first N-type transistor N21 as the first N-type transistor N1 in FIG4, a twenty-second N-type transistor N22 as the second N-type transistor N2 in FIG4, a twenty-third N-type transistor N23 as the third N-type transistor N3 in FIG4, a twenty-first P-type transistor P21 as the first P-type transistor P1 in FIG4, and a twenty-second P-type transistor P22 as the second P-type transistor P2 in FIG4. Among them, the eleventh N-type transistor N11 and the eleventh P-type transistor P11 form the transmission gate of the first sub-pixel, the twenty-first N-type transistor N21 and the twenty-first P-type transistor P21 form the transmission gate of the second sub-pixel, the twelfth N-type transistor N12 serves as the driving transistor of the first sub-pixel, and the twenty-second N-type transistor N22 serves as the driving transistor of the second sub-pixel.

[0102] In an exemplary embodiment, the first storage capacitor may include an eleventh capacitor 11C and a twelfth capacitor (not shown) connected in parallel. The eleventh capacitor 11C may be a MOS capacitor, and the twelfth capacitor may be a MIM capacitor. The second storage capacitor may include a twenty-first capacitor 21C and a twenty-second capacitor (not shown) connected in parallel. The twenty-first capacitor 21C may be a MOS capacitor, and the twenty-second capacitor may be a MIM capacitor.

[0103] In at least one repeating unit, in the first direction X, the eleventh capacitor 11C and the second eleventh capacitor 21C can be disposed in the middle region of the repeating unit in the first direction X, and in the second direction Y, the eleventh capacitor 11C and the second eleventh capacitor 21C can be disposed sequentially along the second direction Y, and the second eleventh capacitor 21C can be disposed on one side of the eleventh capacitor 11C in the second direction Y.

[0104] In an exemplary embodiment, the eleventh capacitor 11C may include a stacked eleventh electrode 11 and a twelfth electrode 12, wherein the orthographic projection of the twelfth electrode 12 onto the silicon substrate at least partially overlaps with the orthographic projection of the eleventh electrode 11 onto the silicon substrate. The twenty-first capacitor 21C may include a stacked twenty-first electrode 21 and a twenty-second electrode 22, wherein the orthographic projection of the twenty-second electrode 22 onto the silicon substrate at least partially overlaps with the orthographic projection of the twenty-first electrode 21 onto the silicon substrate.

[0105] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a silicon substrate and a plurality of conductive layers disposed on the silicon substrate. The eleventh electrode plate 11 and the second eleventh electrode plate 21 may be disposed on the silicon substrate and are an integral structure interconnected with each other. The twelfth electrode plate 12 and the second twelfth electrode plate 22 may be disposed in the same conductive layer.

[0106] In an exemplary embodiment, the twelfth capacitor may be disposed on the side of the eleventh capacitor 11C away from the silicon substrate, and the twenty-second capacitor may be disposed on the side of the twenty-first capacitor 21C away from the silicon substrate. The twelfth capacitor may include a stacked thirteenth and fourteenth electrode plates, the orthographic projection of the fourteenth electrode plate on the display substrate plane at least partially overlapping with the orthographic projection of the thirteenth electrode plate on the display substrate plane. The twenty-second capacitor may include a stacked twenty-third and twenty-fourth electrode plates, the orthographic projection of the twenty-fourth electrode plate on the display substrate plane at least partially overlapping with the orthographic projection of the twenty-third electrode plate on the display substrate plane. The thirteenth and twenty-third electrode plates may be disposed in the same conductive layer and are an integral structure interconnected with each other, and the fourteenth and twenty-fourth electrode plates may also be disposed in the same conductive layer.

[0107] In an exemplary embodiment, in at least one repeating unit, the twelfth N-type transistor N12 can be disposed in the edge region on the opposite side of the first direction X of the repeating unit, and the twenty-second N-type transistor N22 can be disposed in the edge region on the first direction X side of the repeating unit, that is, the twelfth N-type transistor N12 and the twenty-second N-type transistor N22 are disposed in the edge regions on both sides of the eleventh capacitor 11C and the eleventh capacitor 21C in the first direction X. The eleventh N-type transistor N11, the eleventh P-type transistor P11, and the twelfth P-type transistor P12 can be disposed between the twelfth N-type transistor N12 and the eleventh capacitor 11C, the thirteenth N-type transistor N13, the twenty-first N-type transistor N21, and the twenty-first P-type transistor P21 can be disposed between the twelfth N-type transistor N12 and the twenty-first capacitor 21C, the twenty-second P-type transistor P22 can be disposed between the twenty-second N-type transistor N22 and the eleventh capacitor 11C, and the twenty-third N-type transistor N23 can be disposed between the twenty-second N-type transistor N22 and the twenty-first capacitor 21C.

[0108] In an exemplary embodiment, in at least one repeating unit, the twelfth P-type transistor P12 may be disposed on the side of the twelfth N-type transistor N12 near the eleventh capacitor 11C, the eleventh N-type transistor N11 may be disposed on the side of the twelfth P-type transistor P12 near the eleventh capacitor 11C, and the eleventh P-type transistor P11 may be disposed on the side of the eleventh N-type transistor N11 near the eleventh capacitor 11C. The thirteenth N-type transistor N13 may be disposed on the side of the twelfth N-type transistor N12 near the twenty-first capacitor 21C, the twenty-first N-type transistor N21 may be disposed on the side of the thirteenth N-type transistor N13 near the twenty-first capacitor 21C, and the twenty-first P-type transistor P21 may be disposed on the side of the twenty-first N-type transistor N21 near the twenty-first capacitor 21C.

[0109] In an exemplary embodiment, in at least one repeating unit, the thirteenth N-type transistor N13 may be disposed on one side of the twelfth P-type transistor P12 in the second direction Y, the twenty-first N-type transistor N21 may be disposed on one side of the eleventh N-type transistor N11 in the second direction Y, the twenty-first P-type transistor P21 may be disposed on one side of the eleventh P-type transistor P11 in the second direction Y, and the twenty-third N-type transistor N23 may be disposed on one side of the twenty-second P-type transistor P22 in the second direction Y.

[0110] In an exemplary embodiment, in at least one repeating unit, the data signal line 43 may include a first data signal line 43-1 and a second data signal line 43-2, the reference signal line 44 may include a first reference signal line 44-1 and a second reference signal line 44-2, and the initial signal line 45 may include a first initial signal line 45-1 and a second initial signal line 45-2.

[0111] In an exemplary embodiment, in the first sub-pixel of at least one repeating unit, the gate electrode of the eleventh N-type transistor N11 is connected to the first scan signal line 31, the gate electrode of the eleventh P-type transistor P11 is connected to the second scan signal line 32, the first electrode of the eleventh N-type transistor N11 and the first electrode of the eleventh P-type transistor P11 are connected to each other and to the first data signal line 43-1, the second electrode of the eleventh N-type transistor N11 and the second electrode of the eleventh P-type transistor P11 are connected to each other and to the gate electrode of the twelfth N-type transistor N12 and the twelfth plate 12, respectively. The gate electrode of the thirteenth N-type transistor N13 is connected to the third scan signal line 33. The gate electrode of the twelfth P-type transistor P12 is connected to the first reference signal line 44-1. The first terminal of the twelfth N-type transistor N12 is connected to the first power supply line 41. The first terminal of the thirteenth N-type transistor N13 is connected to the first initial signal line 45-1. The second terminal of the thirteenth N-type transistor N13 is connected to the second terminal of the twelfth N-type transistor N12 and the first terminal of the twelfth P-type transistor P12, respectively.

[0112] In an exemplary embodiment, in the second sub-pixel of at least one repeating unit, the gate electrode of the twenty-first N-type transistor N21 is connected to the first scan signal line 31, the gate electrode of the twenty-first P-type transistor P21 is connected to the second scan signal line 32, the first electrode of the twenty-first N-type transistor N21 and the first electrode of the twenty-first P-type transistor P21 are interconnected and connected to the second data signal line 43-2, the second electrode of the twenty-first N-type transistor N21 and the second electrode of the twenty-first P-type transistor P21 are interconnected and connected to the twenty-second N-type transistor N22 and the twenty-second electrode plate 22, respectively. The gate electrode of the twenty-third N-type transistor N23 is connected to the third scan signal line 33, the gate electrode of the twenty-second P-type transistor P22 is connected to the second reference signal line 44-2, the first electrode of the twenty-second N-type transistor N22 is connected to the first power supply line 41, the first electrode of the twenty-third N-type transistor N23 is connected to the second initial signal line 45-2, and the second electrode of the twenty-third N-type transistor N23 is connected to the second electrode of the twenty-second N-type transistor N22 and the first electrode of the twenty-second P-type transistor P22, respectively.

[0113] In an exemplary embodiment, in at least one repeating unit, the ratio of the extension length of the first scan signal line 31 to the extension length of the second scan signal line 32 can be approximately 0.95 to 1.05.

[0114] In an exemplary embodiment, in at least one repeating unit, the extension length of the first scan signal line 31 and the extension length of the second scan signal line 32 can be substantially equal, so that the first scan signal line 31 and the second scan signal line 32 form complementary traces of equal length.

[0115] In an exemplary embodiment, in at least one repeating unit, both the zigzag-shaped first scan signal line 31 and the second scan signal line 32 include multiple horizontal sub-lines and multiple vertical sub-lines. The horizontal sub-lines can be straight lines extending along a first direction X, and the vertical sub-lines can be straight lines extending along a second direction Y. The number of horizontal sub-lines in the first scan signal line 31 and the number of horizontal sub-lines in the second scan signal line 32 can be equal, and the number of vertical sub-lines in the first scan signal line 31 and the number of vertical sub-lines in the second scan signal line 32 can be equal.

[0116] In an exemplary embodiment, the first scan signal line 31 may include at least the eleventh sub-line 311, the twelfth sub-line 312, the thirteenth sub-line 313, the fourteenth sub-line 314, the fifteenth sub-line 315, the sixteenth sub-line 316, and the seventeenth sub-line 317 connected in sequence, and the second scan signal line 32 may include at least the twenty-first sub-line 321, the twenty-second sub-line 322, the twenty-third sub-line 323, the twenty-fourth sub-line 324, the twenty-fifth sub-line 325, the twenty-sixth sub-line 326, and the twenty-seventh sub-line 327 connected in sequence. The ratio of the extension length of the eleventh sub-line 311 to the extension length of the twenty-first sub-line 321 can be approximately 0.95 to 1.05; the ratio of the extension length of the twelfth sub-line 312 to the extension length of the twenty-second sub-line 322 can be approximately 0.95 to 1.05; the ratio of the extension length of the thirteenth sub-line 313 to the extension length of the twenty-third sub-line 323 can be approximately 0.95 to 1.05; the ratio of the extension length of the fourteenth sub-line 314 to the extension length of the twenty-fourth sub-line 324 can be approximately 0.95 to 1.05; the ratio of the extension length of the fifteenth sub-line 315 to the extension length of the twenty-fifth sub-line 325 can be approximately 0.95 to 1.05; the ratio of the extension length of the sixteenth sub-line 316 to the extension length of the twenty-sixth sub-line 326 can be approximately 0.95 to 1.05; and the ratio of the extension length of the seventeenth sub-line 317 to the extension length of the twenty-seventh sub-line 327 can be approximately 0.95 to 1.05.

[0117] In an exemplary embodiment, the eleventh sub-line 311, the thirteenth sub-line 313, the fifteenth sub-line 315, the seventeenth sub-line 317, the twenty-first sub-line 321, the twenty-third sub-line 323, the twenty-fifth sub-line 325, and the twenty-seventh sub-line 327 are straight lines extending along the first direction X.

[0118] In an exemplary embodiment, the twelfth sub-line 312 and the second twelfth sub-line 322 extend in opposite directions. The twelfth sub-line 312 extends in a direction away from the second scan signal line 32, and the second twelfth sub-line 322 extends in a direction away from the first scan signal line 31.

[0119] In an exemplary embodiment, the fourteenth sub-line 314 and the second fourteenth sub-line 324 extend in opposite directions, with the fourteenth sub-line 314 extending toward the direction closer to the second scan signal line 32 and the second fourteenth sub-line 324 extending toward the direction closer to the first scan signal line 31.

[0120] In an exemplary embodiment, the sixteenth sub-line 316 and the second sixteenth sub-line 326 extend in opposite directions, with the sixteenth sub-line 316 extending toward the direction closer to the second scan signal line 32 and the second sixteenth sub-line 326 extending toward the direction closer to the first scan signal line 31.

[0121] In an exemplary embodiment, a capacitance compensation block 32-1 may be provided on the 25th sub-line 325. The capacitance compensation block 32-1 may be block-shaped and may be located on the side of the 25th sub-line 325 away from the first scan signal line 31 and connected to the 25th sub-line 325. The orthographic projection of the capacitance compensation block 32-1 on the silicon substrate at least partially overlaps with the orthographic projection of the 12th electrode plate 12 on the silicon substrate. The capacitance compensation block 32-1 can adjust the parasitic capacitance of the second scan signal line 32 to avoid capacitance differences.

[0122] In an exemplary embodiment, at least one repeating unit may further include a nineteenth connecting electrode 119 as a first compensation electrode, which can be connected to the first scan signal line 31 via the connecting electrode.

[0123] The orthographic projection of the first scanning signal line 31 on the display substrate plane at least partially overlaps with the gate electrode of the twenty-first N-type transistor N21, the gate electrode of the twenty-first P-type transistor P21, and the orthographic projection of the twelfth electrode plate 22 on the display substrate plane. The orthographic projection of the nineteenth connecting electrode 119 on the display substrate plane at least partially overlaps with the gate electrode of the eleventh N-type transistor N11, the gate electrode of the eleventh P-type transistor P11, and the orthographic projection of the twelfth electrode plate 12 on the display substrate plane.

[0124] In an exemplary embodiment, at least one repeating unit may further include a twentieth connecting electrode 120 as a second compensation electrode, which can be connected to the second scan signal line 32 via the connecting electrode. The orthographic projection of the second scan signal line 32 on the display substrate plane at least partially overlaps with the orthographic projections of the gate electrode of the eleventh N-type transistor N11, the gate electrode of the eleventh P-type transistor P11, and the twelfth electrode plate 12 on the display substrate plane. The orthographic projection of the twentieth connecting electrode 120 on the display substrate plane at least partially overlaps with the orthographic projections of the gate electrode of the twenty-first N-type transistor N21, the gate electrode of the twenty-first P-type transistor P21, and the twentieth electrode plate 22 on the display substrate plane.

[0125] In an exemplary embodiment, in the first direction X, the first data signal line 43-1 of the first sub-pixel and the second data signal line 43-2 of the second sub-pixel can be disposed between the twelfth N-type transistor N12 and the eleventh capacitor 11C or the twenty-first capacitor 21C. The distance between the second data signal line 43-2 and the gate electrode of the twenty-second N-type transistor N22 can be greater than the distance between the first data signal line 43-1 and the gate electrode of the twelfth N-type transistor N12.

[0126] In an exemplary embodiment, in the first direction X, the first power line 41 may be disposed between the first data signal line 43-1 and the second data signal line 43-2.

[0127] In an exemplary embodiment, in the first direction X, the first reference signal line 44-1 and the first initial signal line 45-1 can be disposed between the twelfth N-type transistor N12 and the eleventh capacitor 11C or the twenty-first capacitor 21C. The first initial signal line 45-1 can be disposed on the side of the first data signal line 43-1 away from the first power supply line 41, and the first reference signal line 44-1 can be disposed on the side of the first initial signal line 45-1 away from the first power supply line 41.

[0128] In an exemplary embodiment, in the first direction X, the second reference signal line 44-2 and the second initial signal line 45-2 can be disposed between the 22nd N-type transistor N22 and the 11th capacitor 11C or the 21st capacitor 21C. The second initial signal line 45-2 can be disposed on the side of the 11th capacitor 11C or the 21st capacitor 21C away from the first power supply line 41. The second reference signal line 44-2 can be disposed on the side of the second initial signal line 45-2 away from the first power supply line 41.

[0129] The following is an illustrative description of the fabrication process of a display device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes coating the organic material, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition (CVD); coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0130] In an exemplary embodiment, taking three cell rows, each cell row including two repeating cells, and each repeating cell including a first sub-pixel and a second sub-pixel as an example, the fabrication process of the display substrate may include the following steps.

[0131] (1) The N-well region, P-well region, and active region pattern are formed sequentially. In an exemplary embodiment, forming the N-well region and P-well region pattern may include: providing a P-type silicon substrate; forming a photoresist pattern including an opening region by coating photoresist on the P-type silicon substrate, exposure, and development; removing the photoresist within the opening region to expose the surface of the P-type silicon substrate; implanting n-type dopant ions into the opening region by ion implantation; stripping away the remaining photoresist; forming an N-well (N-type well, abbreviated as NW) region on the P-type silicon substrate; and forming a P-well (P-type well, abbreviated as PW) region outside the N-well region, as shown in FIG6. Subsequently, the active region pattern is formed, as shown in FIG7.

[0132] In an exemplary embodiment, the N-well region is configured to form a P-type transistor and a P-type device, and the P-well region is configured to form an N-type transistor and an N-type device.

[0133] In an exemplary embodiment, in at least one repeating unit, the N-well region may include at least a first N-well region 10A1, a second N-well region 10A2, and a third N-well region 10A3. The shapes of the first N-well region 10A1, the second N-well region 10A2, and the third N-well region 10A3 may all be strip-shaped (such as a vertical long rectangle) extending along the second direction Y, and may be arranged sequentially along the first direction X. The first N-well region 10A1 is configured to form a twelfth P-type transistor P12, the second N-well region 10A2 is configured to form an eleventh P-type transistor P11, a twenty-first P-type transistor P21, and a P-type power supply region, and the third N-well region 10A3 is configured to form a twenty-second P-type transistor P22.

[0134] In an exemplary embodiment, the two second N-well regions 10A2 of adjacent cell rows can be an integral structure that is interconnected.

[0135] In an exemplary embodiment, the P-well region 10B may be located outside the N-well region, i.e., the N-well region and the P-well region are complementary patterns. The P-well region is configured to form an eleventh N-type transistor N11, a twelfth N-type transistor N12, a thirteenth N-type transistor N13, a twenty-first N-type transistor N21, a twenty-second N-type transistor N22, a twenty-third N-type transistor N23, a first N-type power supply region, and a second N-type power supply region, respectively.

[0136] In an exemplary embodiment, the n-type dopant ions can be phosphorus or arsenic plasma implanters, and the ion implantation depth and doping concentration can be achieved by controlling the implantation energy and dosage. The process for forming the N-well region may also include processes such as annealing, which allow the ion implanter to diffuse in the p-type silicon substrate, forming a stable N-well structure.

[0137] In some possible implementations, the silicon substrate may be an N-type silicon substrate, which may serve as the channel region of a P-type transistor, and this disclosure does not limit the scope of the invention.

[0138] In an exemplary embodiment, the active area (AA) pattern of each repeating unit in the display substrate may include at least: an eleventh electrode plate 11, a twenty-first electrode plate 21, an eleventh N-type active area 111N, a twelfth N-type active area 112N, a thirteenth N-type active area 113N, an eleventh P-type active area 111P, a twelfth P-type active area 112P, a twenty-first N-type active area 121N, a twenty-second N-type active area 122N, a twenty-third N-type active area 123N, a twenty-first P-type active area 121P, a twenty-second P-type active area 122P, a first N-type power supply area 114N, a second N-type power supply area 124N, and a P-type power supply area 113P.

[0139] In an exemplary embodiment, the eleventh electrode 11 and the second eleventh electrode 21 can be rectangular in shape. The eleventh electrode 11 can serve as the lower electrode of the eleventh capacitor in the first sub-pixel, and the second eleventh electrode 21 can serve as the lower electrode of the twenty-first capacitor in the second sub-pixel. In the first direction X, the eleventh electrode 11 and the second eleventh electrode 21 can be disposed in the middle region of the repeating unit, and in the second direction Y, the second eleventh electrode 21 can be disposed on one side of the eleventh electrode 11 in the second direction Y.

[0140] In an exemplary embodiment, in at least one repeating unit, the eleventh electrode plate 11 and the twenty-first electrode plate 21 can be an integral structure that is interconnected.

[0141] In an exemplary embodiment, in at least one unit column, a plurality of eleventh electrode plates 11 and a plurality of twenty-first electrode plates 21 can be an integral structure that is interconnected.

[0142] In an exemplary embodiment, the eleventh N-type active region 111N can serve as the active region of the eleventh N-type transistor N11 in the first sub-pixel, the twelfth N-type active region 112N can serve as the active region of the twelfth N-type transistor N12 in the first sub-pixel, the thirteenth N-type active region 113N can serve as the active region of the thirteenth N-type transistor N13 in the first sub-pixel, the eleventh P-type active region 111P can serve as the active region of the eleventh P-type transistor P11 in the first sub-pixel, and the twelfth P-type active region 112P can serve as the active region of the twelfth P-type transistor P12 in the first sub-pixel. The 21st N-type active region 121N can serve as the active region of the 21st N-type transistor N21 in the second sub-pixel; the 22nd N-type active region 122N can serve as the active region of the 22nd N-type transistor N22 in the second sub-pixel; the 23rd N-type active region 123N can serve as the active region of the 23rd N-type transistor N23 in the second sub-pixel; the 21st P-type active region 121P can serve as the active region of the 21st P-type transistor P21 in the second sub-pixel; and the 22nd P-type active region 122P can serve as the active region of the 22nd P-type transistor P22 in the second sub-pixel.

[0143] In an exemplary embodiment, the eleventh N-type active region 111N, the twelfth N-type active region 112N, the twenty-first N-type active region 121N, and the twenty-second N-type active region 122N can be strip-shaped extending along the second direction Y, and the thirteenth N-type active region 113N and the twenty-third N-type active region 123N can be strip-shaped extending along the first direction X. All of the above N-type active regions can be located within the region where the P-well region 10B is located.

[0144] In an exemplary embodiment, in the first direction X, the twelfth N-type active region 112N and the second twelfth N-type active region 122N can be respectively disposed on both sides of the repeating unit in the first direction X. The eleventh N-type active region 111N can be disposed between the twelfth N-type active region 112N and the eleventh electrode plate 11, the twenty-first N-type active region 121N can be disposed between the thirteenth N-type active region 113N and the second eleventh electrode plate 21, the thirteenth N-type active region 113N can be disposed between the twelfth N-type active region 112N and the second eleventh N-type active region 121N, and the twenty-third N-type active region 123N can be disposed between the twenty-second N-type active region 122N and the second eleventh electrode plate 21, and the thirteenth N-type active region 113N and the thirteenth N-type active region 123N can be located on the same straight line extending along the first direction X. In the second direction Y, the 21st N-type active region 121N can be located on one side of the 11th N-type active region 111N in the second direction Y, and the 11th N-type active region 111N and the 21st N-type active region 121N are on the same straight line extending along the second direction Y.

[0145] In an exemplary embodiment, the eleventh P-type active region 111P, the twelfth P-type active region 112P, the twenty-first P-type active region 121P, and the twenty-second P-type active region 122P can be strip-shaped extending along the second direction Y. The twelfth P-type active region 112P can be located within the region where the first N-well region 10A1 is located. The eleventh P-type active region 111P and the twenty-first P-type active region 121P can be located within the region where the second N-well region 10A2 is located. The twenty-second P-type active region 122P can be located within the region where the third N-well region 10A3 is located.

[0146] In an exemplary embodiment, in the first direction X, the eleventh P-type active region 111P can be disposed between the eleventh N-type active region 111N and the eleventh electrode plate 11, the twelfth P-type active region 112P can be disposed between the eleventh N-type active region 111N and the twelfth N-type active region 112N, the twenty-first P-type active region 121P can be disposed between the twenty-first N-type active region 121N and the eleventh electrode plate 21, and the twenty-second P-type active region 122P can be disposed between the twenty-second N-type active region 122N and the eleventh electrode plate 11. In the second direction Y, the twelfth P-type active region 112P can be located on the opposite side of the thirteenth N-type active region 113N in the second direction Y, the twenty-second P-type active region 122P can be located on the opposite side of the twenty-third N-type active region 123N in the second direction Y, and the twenty-first P-type active region 121P can be located on the same side of the eleventh P-type active region 111P in the second direction Y. Furthermore, the eleventh P-type active region 111P and the twenty-first P-type active region 121P can be located on the same straight line extending along the second direction Y.

[0147] In an exemplary embodiment, in at least one repeating unit, the eleventh N-type active region 111N may have a first N-type active width AN1, the eleventh P-type active region 111P may have a first P-type active width AP1, the first N-type active width AN1 and the first P-type active width AP1 may be substantially equal, and the first N-type active width AN1 and the first P-type active width AP1 may be dimensions in the first direction X.

[0148] In an exemplary embodiment, in at least one repeating unit, the twenty-first N-type active region 121N may have a second N-type active width AN2, and the twenty-first P-type active region 121P may have a second P-type active width AP2. The second N-type active width AN2 and the second P-type active width AP2 may be substantially equal, and the second N-type active width AN2 and the second P-type active width AP2 may be dimensions in the first direction X.

[0149] In an exemplary embodiment, the active length of the active region of a P-type transistor can be less than the active length of the active region of an N-type transistor, and the active length can be a dimension in the second direction Y. For example, the active length of the eleventh P-type active region 111P can be less than the active length of the eleventh N-type active region 111N, and the active length of the twenty-first P-type active region 121P can be less than the active length of the twenty-first N-type active region 121N. Similarly, the active length of the twelfth P-type active region 112P can be less than the active length of the twelfth N-type active region 112N, and the active length of the twenty-second P-type active region 122P can be less than the active length of the twenty-second N-type active region 122N.

[0150] In an exemplary embodiment, the first N-type power region 114N, the second N-type power region 124N, and the P-type power region 113P can be strip-shaped extending along the first direction X. The first N-type power region 114N and the second N-type power region 124N can be disposed within the region where the P-well region 10B is located, and the P-type power region 113P can be disposed within the region where the second N-well region 10A2 is located. By providing N-type power regions and P-type power regions, this disclosure can effectively prevent silicon substrate potential bias.

[0151] In an exemplary embodiment, in the first direction X, the first N-type power supply region 114N can be disposed between the twelfth N-type active region 112N and the twenty-first N-type active region 121N, and the second N-type power supply region 124N can be disposed between the twenty-second N-type active region 122N and the twenty-first electrode plate 21. The first N-type power supply region 114N and the second N-type power supply region 124N can be located on the same straight line extending along the first direction X. The P-type power supply region 113P can be disposed between the eleventh N-type active region 111N and the eleventh electrode plate 11. In the second direction Y, the first N-type power supply region 114N can be disposed on one side of the thirteenth N-type active region 113N in the second direction Y, the second N-type power supply region 124N can be disposed on one side of the twenty-third N-type active region 123N in the second direction Y, and the P-type power supply region 113P can be disposed on the opposite side of the eleventh P-type active region 111P in the second direction Y.

[0152] In an exemplary embodiment, the shapes and positions of the twelfth N-type active region 112N and the second twelfth N-type active region 122N can be symmetrically arranged with respect to the center line of the repeating unit, the shapes and positions of the thirteenth N-type active region 113N and the second thirteenth N-type active region 123N can be symmetrically arranged with respect to the center line of the repeating unit, the shapes and positions of the first N-type power region 114N and the second N-type power region 124N can be symmetrically arranged with respect to the center line of the repeating unit, and the shapes and positions of the twelfth P-type active region 112P and the second twelfth P-type active region 122P can be symmetrically arranged with respect to the center line of the repeating unit. The center line of the repeating unit can be a straight line that bisects the repeating unit in the first direction X and extends along the second direction Y.

[0153] In an exemplary embodiment, a first spacing L1 may be present between the twelfth N-type active region 112N and the twelfth P-type active region 112P, or a first spacing L1 may be present between the twentieth N-type active region 122N and the twentieth P-type active region 122P. A second spacing L2 may be present between the twelfth N-type active region 112N and the thirteenth N-type active region 113N, or a second spacing L2 may be present between the twentieth N-type active region 122N and the twentieth N-type active region 123N. The first spacing L1 may be greater than the second spacing L2, and both the first spacing L1 and the second spacing L2 may be dimensions in the first direction X.

[0154] In an exemplary embodiment, there may be a third spacing L3 between the eleventh N-type active region 111N and the twelfth P-type active region 112P, and there may be a fourth spacing L4 between the twenty-first N-type active region 121N and the thirteenth N-type active region 113N. The third spacing L3 may be greater than the fourth spacing L4, and the third spacing L3 and the fourth spacing L4 may be dimensions in the first direction X.

[0155] In an exemplary embodiment, there may be a fifth spacing L5 between the eleventh N-type active region 111N and the eleventh P-type active region 111P. The fifth spacing L5 may be greater than the second spacing L2 and the fourth spacing L4. The fifth spacing L5 may be a dimension in the first direction X.

[0156] In an exemplary embodiment, a sixth spacing L6 may be present between the twenty-first N-type active region 121N and the twenty-first P-type active region 121P. The sixth spacing L6 may be greater than the second spacing L2 and the fourth spacing L4. The sixth spacing L6 may be a dimension in the first direction X.

[0157] In an exemplary embodiment, a seventh spacing L7 may be present between the 12th P-type active region 112P and the 13th N-type active region 113N, an eighth spacing L8 may be present between the 11th N-type active region 111N and the 21st N-type active region 121N, and a ninth spacing L9 may be present between the 11th P-type active region 111P and the 21st P-type active region 121P. The seventh spacing L7 may be greater than the eighth spacing L8, and the seventh spacing L7 may be greater than the ninth spacing L9. The seventh spacing L7, the eighth spacing L8, and the ninth spacing L9 may be dimensions in the second direction Y.

[0158] By adjusting the spacing between the active regions, this disclosure not only allows the twelfth P-type transistor P12 to be as far away from the twelfth N-type transistor N12 as possible, but also maximizes the distance between the P-type transistor and the N-type transistor, effectively reducing the risk of latch-up and achieving better circuit reliability.

[0159] (2) Forming a gate conductive layer pattern. In an exemplary embodiment, forming a gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate on which the aforementioned pattern is formed; firstly, patterning the polysilicon film using a patterning process to form a first insulating layer covering the active region pattern and a polysilicon layer pattern disposed on the first insulating layer; and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in Figures 8A and 8B, where Figure 8B is a schematic diagram of the gate conductive layer in Figure 8A.

[0160] In an exemplary embodiment, the gate conductive layer pattern of each repeating unit in the display substrate may include at least: a twelfth electrode 12, a twenty-second electrode 22, an eleventh N-type gate electrode 211N, a twelfth N-type gate electrode 212N, a thirteenth N-type gate electrode 213N, an eleventh P-type gate electrode 211P, a twelfth P-type gate electrode 212P, a twenty-first N-type gate electrode 221N, a twenty-second N-type gate electrode 222N, a twenty-third N-type gate electrode 223N, a twenty-first P-type gate electrode 221P, and a twenty-second P-type gate electrode 222P.

[0161] In an exemplary embodiment, the twelfth electrode plate 12 may be rectangular in shape, and the orthographic projection of the twelfth electrode plate 12 on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh electrode plate 11 on the silicon substrate. The twelfth electrode plate 12 may serve as the upper electrode plate of the eleventh capacitor in the first sub-pixel, and the eleventh electrode plate 11 and the twelfth electrode plate 12 form the eleventh capacitor of the first sub-pixel.

[0162] In an exemplary embodiment, a twelfth connecting block 12-1 may be provided on the twelfth electrode plate 12. The twelfth connecting block 12-1 may be block-shaped (such as rectangular), and may be located at the corner of the side opposite to the first direction X of the twelfth electrode plate 12, and connected to the twelfth electrode plate 12. The edge of the twelfth electrode plate 12 away from the second twelfth electrode plate 22 and the edge of the twelfth connecting block 12-1 away from the second twelfth electrode plate 22 may be substantially flush.

[0163] In an exemplary embodiment, the shape of the 22nd electrode plate 22 can be rectangular. The orthographic projection of the 22nd electrode plate 22 on the silicon substrate at least partially overlaps with the orthographic projection of the 21st electrode plate 21 on the silicon substrate. The 22nd electrode plate 22 can serve as the upper electrode plate of the 21st capacitor in the second sub-pixel. The 21st electrode plate 21 and the 22nd electrode plate 22 form the 21st capacitor of the second sub-pixel.

[0164] In an exemplary embodiment, a second twelfth connecting block 22-1 may be provided on the second twelfth electrode plate 22. The shape of the second twelfth connecting block 22-1 may be block-shaped (such as rectangular), and it may be located at the corner of the side opposite to the first direction X of the second twelfth electrode plate 22 and connected to the second twelfth electrode plate 22. The edge of the second twelfth electrode plate 22 away from the twelfth electrode plate 12 and the edge of the second twelfth connecting block 22-1 away from the twelfth electrode plate 12 may be substantially flush.

[0165] In an exemplary embodiment, the twelfth electrode plate 12 and the second twelfth electrode plate 22 may be disposed in the middle region of the repeating unit in the first direction X, and the second twelfth electrode plate 22 may be disposed on one side of the twelfth electrode plate 12 in the second direction Y in the second direction Y.

[0166] In an exemplary embodiment, the twelfth N-type gate electrode 212N and the second twelfth N-type gate electrode 222N can be strip-shaped (such as a vertical long rectangle) extending along the second direction Y, and the eleventh N-type gate electrode 211N, the thirteenth N-type gate electrode 213N, the twenty-first N-type gate electrode 221N, the twenty-third N-type gate electrode 223N, the eleventh P-type gate electrode 211P, the twelfth P-type gate electrode 212P, the twenty-first P-type gate electrode 221P, and the second twelfth P-type gate electrode 222P can be block-shaped (such as rectangular).

[0167] In an exemplary embodiment, the twelfth N-type gate electrode 212N can be disposed in the side region on the opposite side of the first direction X of the repeating unit, and the second twelfth N-type gate electrode 222N can be disposed in the side region on the first direction X of the repeating unit. That is, the twelfth N-type gate electrode 212N and the second twelfth N-type gate electrode 222N are disposed in the side regions on both sides of the twelfth electrode plate 12 and the second twelfth electrode plate 22 in the first direction X.

[0168] In an exemplary embodiment, the twelfth P-type gate electrode 212P can be disposed on the side of the twelfth N-type gate electrode 212N near the twelfth electrode plate 12, the thirteenth N-type gate electrode 213N can be disposed on the side of the twelfth N-type gate electrode 212N near the twelfth electrode plate 22, the thirteenth N-type gate electrode 213N can be disposed on the side of the twelfth P-type gate electrode 212P in the second direction Y, and the twelfth P-type gate electrode 212P and the thirteenth N-type gate electrode 213N can be located on the same straight line extending along the second direction Y.

[0169] In an exemplary embodiment, the eleventh N-type gate electrode 211N can be disposed on the side of the twelfth P-type gate electrode 212P near the twelfth electrode plate 12, the twenty-first N-type gate electrode 221N can be disposed on the side of the thirteenth N-type gate electrode 213N near the twenty-second electrode plate 22, the twenty-first N-type gate electrode 221N can be disposed on the side of the eleventh N-type gate electrode 211N in the second direction Y, and the eleventh N-type gate electrode 211N and the twenty-first N-type gate electrode 221N can be located on the same straight line extending along the second direction Y.

[0170] In an exemplary embodiment, in at least one unit column, the eleventh N-type gate electrode 211N and the second eleventh N-type gate electrode 221N can be connected together by a connecting strip, that is, the eleventh N-type gate electrode 211N and the second eleventh N-type gate electrode 221N can be an integral structure that is interconnected.

[0171] In an exemplary embodiment, the eleventh P-type gate electrode 211P can be disposed between the eleventh N-type gate electrode 211N and the twelfth plate 12, the twenty-first P-type gate electrode 221P can be disposed between the twenty-first N-type gate electrode 221N and the twenty-second plate 22, the twenty-first P-type gate electrode 221P can be disposed on one side of the eleventh P-type gate electrode 211P in the second direction Y, and the eleventh P-type gate electrode 211P and the twenty-first P-type gate electrode 221P can be located on the same straight line extending along the second direction Y.

[0172] In an exemplary embodiment, in at least one unit column, the eleventh P-type gate electrode 211P and the second eleventh P-type gate electrode 221P can be connected together by a connecting strip, that is, the eleventh P-type gate electrode 211P and the second eleventh P-type gate electrode 221P can be an integral structure that is interconnected.

[0173] In an exemplary embodiment, the 22nd P-type gate electrode 222P can be disposed between the 22nd N-type gate electrode 222N and the 12th electrode plate 12, the 23rd N-type gate electrode 223N can be disposed between the 22nd N-type gate electrode 222N and the 12th electrode plate 22, the 23rd N-type gate electrode 223N can be disposed on one side of the 22nd P-type gate electrode 222P in the second direction Y, and the 22nd P-type gate electrode 222P and the 23rd N-type gate electrode 223N can be located on the same straight line extending along the second direction Y.

[0174] In an exemplary embodiment, the orthographic projection of the eleventh-N type gate electrode 211N on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh-N type active region 111N on the silicon substrate, and the eleventh-N type gate electrode 211N can serve as the gate electrode of the eleventh-N type transistor N11 in the first sub-pixel.

[0175] In an exemplary embodiment, the orthographic projection of the twelfth N-type gate electrode 212N on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth N-type active region 112N on the silicon substrate, and the twelfth N-type gate electrode 212N can serve as the gate electrode of the twelfth N-type transistor N12 in the first sub-pixel.

[0176] In an exemplary embodiment, a twelfth-N type gate connecting block 212N-1 may be provided on the twelfth-N type gate electrode 212N. The twelfth-N type gate connecting block 212N-1 may be block-shaped (e.g., rectangular) and may be located at the corner of the twelfth-N type gate electrode 212N on the first direction X side, and connected to the twelfth-N type gate electrode 212N. The edges of the twelfth-N type gate electrode 212N and the twelfth-N type gate connecting block 212N-1 on the opposite side of the second direction Y may be substantially flush.

[0177] In an exemplary embodiment, the orthographic projection of the thirteenth N-type gate electrode 213N on the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth N-type active region 113N on the silicon substrate, and the thirteenth N-type gate electrode 213N can serve as the gate electrode of the thirteenth N-type transistor N13 in the first sub-pixel.

[0178] In an exemplary embodiment, the orthographic projection of the 21N-type gate electrode 221N on the silicon substrate at least partially overlaps with the orthographic projection of the 21N-type active region 121N on the silicon substrate, and the 21N-type gate electrode 221N can serve as the gate electrode of the 21N-type transistor N21 in the second sub-pixel.

[0179] In an exemplary embodiment, the orthographic projection of the 222N gate electrode 222N on the silicon substrate at least partially overlaps with the orthographic projection of the 22N active region 122N on the silicon substrate, and the 222N gate electrode 222N can serve as the gate electrode of the 22N transistor N22 in the second sub-pixel.

[0180] In an exemplary embodiment, a second twelfth N-type gate connecting block 222N-1 may be provided on the second twelfth N-type gate electrode 222N. The shape of the second twelfth N-type gate connecting block 222N-1 may be block-shaped (such as rectangular), and it may be provided at the corner of the second twelfth N-type gate electrode 222N on the opposite side of the first direction X and the opposite side of the second direction Y, and connected to the second twelfth N-type gate electrode 222N.

[0181] In an exemplary embodiment, the orthographic projection of the 23rd N-type gate electrode 223N on the silicon substrate at least partially overlaps with the orthographic projection of the 23rd N-type active region 123N on the silicon substrate, and the 23rd N-type gate electrode 223N can serve as the gate electrode of the 23rd N-type transistor N23 in the second sub-pixel.

[0182] In an exemplary embodiment, the orthographic projection of the eleventh P-type gate electrode 211P on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh P-type active region 111P on the silicon substrate, and the eleventh P-type gate electrode 211P can serve as the gate electrode of the eleventh P-type transistor P11 in the first sub-pixel.

[0183] In an exemplary embodiment, the orthographic projection of the twelfth P-type gate electrode 212P on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth P-type active region 112P on the silicon substrate, and the twelfth P-type gate electrode 212P can serve as the gate electrode of the twelfth P-type transistor P12 in the first sub-pixel.

[0184] In an exemplary embodiment, a twelfth P-type gate connecting block 212P-1 may be provided on the twelfth P-type gate electrode 212P. The twelfth P-type gate connecting block 212P-1 may be block-shaped (such as rectangular), and may be provided at the corner of the twelfth P-type gate electrode 212P on one side of the first direction X and the opposite side of the second direction Y, and connected to the twelfth P-type gate electrode 212P.

[0185] In an exemplary embodiment, the orthographic projection of the 21st P-type gate electrode 221P on the silicon substrate at least partially overlaps with the orthographic projection of the 21st P-type active region 121P on the silicon substrate, and the 21st P-type gate electrode 221P can serve as the gate electrode of the 21st P-type transistor P21 in the second sub-pixel.

[0186] In an exemplary embodiment, the orthographic projection of the 222P gate electrode 222P on the silicon substrate at least partially overlaps with the orthographic projection of the 22P active region 122P on the silicon substrate, and the 22P gate electrode 222P can serve as the gate electrode of the 22P transistor P22 in the second sub-pixel.

[0187] In an exemplary embodiment, a second twelfth P-type gate connecting block 222P-1 may be provided on the second twelfth P-type gate electrode 222P. The shape of the second twelfth P-type gate connecting block 222P-1 may be block-shaped (such as rectangular), and it may be provided at the corner of the second twelfth P-type gate electrode 222P on the opposite side of the first direction X and the opposite side of the second direction Y, and connected to the second twelfth P-type gate electrode 222P.

[0188] In an exemplary embodiment, in at least one repeating unit, the eleventh N-type gate electrode 211N may have a first N-type gate length BN1, the eleventh P-type gate electrode 211P may have a first P-type gate length BP1, the first N-type gate length BN1 may be greater than the first P-type gate length BP1, and the first N-type gate length BN1 and the first P-type gate length BP1 may be dimensions in the second direction Y.

[0189] In an exemplary embodiment, in at least one repeating unit, AP1 / BP1 can be greater than AN1 / BN1, that is, the aspect ratio of the eleventh P-type transistor P11 in the first sub-pixel can be greater than the aspect ratio of the eleventh N-type transistor N11. Since the eleventh N-type transistor N11 and the eleventh P-type transistor P11 constitute a transmission gate with complementary characteristics, this disclosure, by setting the aspect ratio of the eleventh P-type transistor to be greater than the aspect ratio of the eleventh N-type transistor, can make the transmission gate in the first sub-pixel have substantially the same effect on the transmission of positive and negative voltages.

[0190] In an exemplary embodiment, in at least one repeating unit, the 21st N-type gate electrode 221N may have a second N-type gate length BN2, the 21st P-type gate electrode 221P may have a second P-type gate length BP2, the second N-type gate length BN2 may be greater than the second P-type gate length BP2, and the second N-type gate length BN2 and the second P-type gate length BP2 may be dimensions in the second direction Y.

[0191] In an exemplary embodiment, in at least one repeating unit, AP2 / BP2 can be greater than AN2 / BN2, meaning the aspect ratio of the twenty-first P-type transistor P21 in the second sub-pixel can be greater than the aspect ratio of the twenty-first N-type transistor N21. Since the twenty-first N-type transistor N21 and the twenty-first P-type transistor P21 constitute a transmission gate with complementary characteristics, this disclosure, by setting the aspect ratio of the twenty-first P-type transistor P21 to be greater than that of the twenty-first N-type transistor N21, can ensure that the transmission gate in the second sub-pixel transmits positive and negative voltages with essentially the same effect. This allows the N-type transistor and P-type transistor in the transmission gate to be simultaneously turned off or simultaneously turned on, improving the driving performance of the pixel driving circuit.

[0192] In an exemplary embodiment, for the twelfth P-type transistor P12 and the thirteenth N-type transistor N13, the twenty-second P-type transistor P22 and the twenty-third N-type transistor N23 that are adjacent in the second direction Y, the active region of the P-type transistor is rectangular in shape extending along the second direction Y, and the area where the gate electrode of the P-type transistor does not overlap with the active region is located on both sides of the gate electrode in the first direction X. The active region of the N-type transistor is rectangular in shape extending along the first direction X, and the area where the gate electrode of the N-type transistor does not overlap with the active region is located on both sides of the gate electrode in the second direction Y.

[0193] (3) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming a P-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming a P-type doped pattern in the opening regions by a doping process, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the P-type doped pattern in Figure 9A.

[0194] In an exemplary embodiment, the P-type doped pattern of each repeating unit in the display substrate may include at least a first P-type doped region 20A1, a second P-type doped region 20A2, a third P-type doped region 20A3, a fourth P-type doped region 20A4, and a fifth P-type doped region 20A5.

[0195] In an exemplary embodiment, in at least one repeating unit, the first P-type doped region 20A1, the second P-type doped region 20A2, and the third P-type doped region 20A3 can be strip-shaped (such as a vertical long rectangle) extending along the second direction Y, and are arranged sequentially along the first direction X. The fourth P-type doped region 20A4 and the fifth P-type doped region 20A5 can be strip-shaped (such as a horizontal long rectangle) extending along the first direction X. The fourth P-type doped region 20A4 can be disposed on one side of the first P-type doped region 20A1 in the second direction Y, and the fifth P-type doped region 20A5 can be disposed on one side of the third P-type doped region 20A3 in the second direction Y.

[0196] In an exemplary embodiment, the orthogonal projection of the first P-type doped region 20A1 onto the silicon substrate may include the orthogonal projection of the twelfth P-type active region 112P onto the silicon substrate, and the twelfth P-type active regions 112P on both sides of the twelfth P-type gate electrode 212P respectively form the twelfth P-type source region and the twelfth P-type drain region.

[0197] In an exemplary embodiment, the orthogonal projection of the second P-type doped region 20A2 onto the silicon substrate may include the orthogonal projections of the eleventh P-type active region 111P and the second eleventh P-type active region 121P onto the silicon substrate. The eleventh P-type active regions 111P on both sides of the eleventh P-type gate electrode 211P respectively form the eleventh P-type source region and the eleventh P-type drain region. The second eleventh P-type active regions 121P on both sides of the second eleventh P-type gate electrode 221P respectively form the second eleventh P-type source region and the second eleventh P-type drain region.

[0198] In an exemplary embodiment, the orthogonal projection of the third P-type doped region 20A3 onto the silicon substrate may include the orthogonal projection of the twenty-second P-type active region 122P onto the silicon substrate, and the twenty-second P-type active regions 122P on both sides of the twenty-second P-type gate electrode 222P respectively form the twenty-second P-type source region and the twenty-second P-type drain region.

[0199] In an exemplary embodiment, the orthogonal projection of the fourth P-type doped region 20A4 onto the silicon substrate may include the orthogonal projection of the first N-type power region 114N onto the silicon substrate, and the orthogonal projection of the fifth P-type doped region 20A5 onto the silicon substrate may include the orthogonal projection of the second N-type power region 124N onto the silicon substrate, that is, the first N-type power region 114N and the second N-type power region 124N are P-type doped.

[0200] (4) Forming an N-type doped (SN) region pattern. In an exemplary embodiment, forming an N-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming an N-type doped pattern in the opening regions by a doping process, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the N-type doped pattern in Figure 10A.

[0201] In an exemplary embodiment, the N-type doped pattern of each repeating unit in the display substrate may be located outside the P-type doped pattern, that is, the N-type doped region and the P-type doped region are complementary patterns.

[0202] In an exemplary embodiment, the orthogonal projection of the N-type doped region 20B onto the silicon substrate may include the orthogonal projections of the eleventh N-type active region 111N, the twelfth N-type active region 112N, the thirteenth N-type active region 113N, the twenty-first N-type active region 121N, the twenty-second N-type active region 122N, and the twenty-third N-type active region 123N onto the silicon substrate. The eleventh-type N-type active regions 111N on both sides of the eleventh-type N-type gate electrode 211N form the eleventh-type N-type source region and the eleventh-type N-type drain region, respectively. The twelfth-type N-type active regions 112N on both sides of the twelfth-type N-type gate electrode 212N form the twelfth-type N-type source region and the twelfth-type N-type drain region, respectively. The thirteenth-type N-type active regions 113N on both sides of the thirteenth-type N-type gate electrode 213N form the thirteenth-type N-type source region and the thirteenth-type N-type drain region, respectively. The twenty-first-type N-type active regions 121N on both sides of the twenty-first-type N-type gate electrode 221N form the twenty-first-type N-type source region and the twenty-first-type N-type drain region, respectively. The twenty-second-type N-type active regions 122N on both sides of the twenty-second-type N-type gate electrode 222N form the twenty-second-type N-type source region and the twenty-second-type N-type drain region, respectively. The twenty-third-type N-type active regions 123N on both sides of the twenty-third-type N-type gate electrode 223N form the twenty-third-type source region and the twenty-third-type drain region, respectively.

[0203] In an exemplary embodiment, the orthographic projection of the N-type doped region 20B onto the silicon substrate may also include the orthographic projections of the P-type power region 113P, the eleventh electrode 11, and the twenty-first electrode 21 onto the silicon substrate. The P-type power region 113P, the eleventh electrode 11 which is not shielded by the twelfth electrode 12, and the twenty-first electrode 21 which is not shielded by the twenty-second electrode 22 are N-type doped.

[0204] (5) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG11.

[0205] In an exemplary embodiment, the plurality of vias in each repeating unit of the display substrate may include at least: a first via V1 to a thirty-fifth via V35.

[0206] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the silicon substrate may be located within the range of the orthogonal projection of the eleventh N-type source region of the eleventh N-type active region 111N onto the silicon substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the eleventh N-type source region. The first via V1 is configured to allow the subsequently formed third connection electrode to be connected to the eleventh N-type source region through the via.

[0207] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the silicon substrate may be located within the range of the orthogonal projection of the eleventh-type drain region of the eleventh-type active region 111N onto the silicon substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the eleventh-type drain region. The second via V2 is configured to allow the subsequently formed first connection electrode to be connected to the eleventh-type drain region through the via.

[0208] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the silicon substrate can be located within the range of the orthogonal projection of the twelfth N-type source region 112N onto the silicon substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the twelfth N-type source region. The third via V3 is configured to allow a subsequently formed fourth connection electrode to connect to the twelfth N-type source region through this via. In an exemplary embodiment, multiple third vias V3 can be used to reduce contact resistance and improve connection reliability.

[0209] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the silicon substrate may lie within the orthogonal projection of the twelfth-type drain region of the twelfth-type active region 112N onto the silicon substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the twelfth-type drain region. The fourth via V4 is configured to allow a subsequently formed second connection electrode to connect to the twelfth-type drain region through this via. In an exemplary embodiment, multiple fourth vias V4 may be used to reduce contact resistance and improve connection reliability.

[0210] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the silicon substrate may be located within the range of the orthogonal projection of the thirteenth-type drain region of the thirteenth-type active region 113N onto the silicon substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the thirteenth-type drain region. The fifth via V5 is configured to allow the subsequently formed fifth connection electrode to be connected to the thirteenth-type drain region through the via.

[0211] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the silicon substrate can be located within the range of the orthogonal projection of the thirteenth N-type source region of the thirteenth N-type active region 113N onto the silicon substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the thirteenth N-type source region. The sixth via V6 is configured to allow the subsequently formed sixth connection electrode to be connected to the thirteenth N-type source region through the via.

[0212] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the silicon substrate can be located within the range of the orthogonal projection of the eleventh P-type source region of the eleventh P-type active region 111P onto the silicon substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the eleventh P-type source region. The seventh via V7 is configured to allow the subsequently formed third connection electrode to be connected to the eleventh P-type source region through the via.

[0213] In an exemplary embodiment, the orthogonal projection of the eighth via V8 onto the silicon substrate can be located within the range of the orthogonal projection of the eleventh P-type drain region of the eleventh P-type active region 111P onto the silicon substrate. The first and second insulating layers within the eighth via V8 are etched away, exposing the surface of the eleventh P-type drain region. The eighth via V8 is configured to allow the subsequently formed first connection electrode to be connected to the eleventh P-type drain region through the via.

[0214] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the silicon substrate may be within the range of the orthogonal projection of the twelfth P-type drain region of the twelfth P-type active region 112P onto the silicon substrate. The first and second insulating layers within the ninth via V9 are etched away, exposing the surface of the twelfth P-type drain region. The ninth via V9 is configured to allow the subsequently formed seventh connection electrode to be connected to the twelfth P-type drain region through the via.

[0215] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the silicon substrate may be within the range of the orthogonal projection of the twelfth P-type source region of the twelfth P-type active region 112P onto the silicon substrate. The first and second insulating layers within the tenth via V10 are etched away, exposing the surface of the twelfth P-type source region. The tenth via V10 is configured to allow a subsequently formed second connection electrode to be connected to the twelfth P-type source region through the via.

[0216] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-first N-type source region 121N onto the silicon substrate. The first and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the twenty-first N-type source region. The eleventh via V11 is configured to allow the subsequently formed thirteenth connection electrode to be connected to the twenty-first N-type source region through the via.

[0217] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the silicon substrate may be located within the range of the orthogonal projection of the twenty-first N-type drain region of the twenty-first N-type active region 121N onto the silicon substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the twenty-first N-type drain region. The twelfth via V12 is configured to allow the subsequently formed eleventh connection electrode to be connected to the twenty-first N-type drain region through the via.

[0218] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-second N-type source region 122N onto the silicon substrate. The first and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the twenty-second N-type source region. The thirteenth via V13 is configured to allow the subsequently formed fourteenth connection electrode to be connected to the twenty-second N-type source region through the via.

[0219] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the silicon substrate may be located within the range of the orthogonal projection of the twenty-second N-type drain region of the twenty-second N-type active region 122N onto the silicon substrate. The first and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the twenty-second N-type drain region. The fourteenth via V14 is configured to allow the subsequently formed twelfth connection electrode to be connected to the twenty-second N-type drain region through the via.

[0220] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the silicon substrate may be located within the range of the orthogonal projection of the twenty-third N-type drain region of the twenty-third N-type active region 123N onto the silicon substrate. The first and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the twenty-third N-type drain region. The fifteenth via V15 is configured to allow the subsequently formed fifteenth connection electrode to be connected to the twenty-third N-type drain region through the via.

[0221] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-third N-type source region 123N onto the silicon substrate. The first and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the twenty-third N-type source region. The sixteenth via V16 is configured to allow the subsequently formed sixteenth connection electrode to be connected to the twenty-third N-type source region through the via.

[0222] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-first P-type source region 121P onto the silicon substrate. The first and second insulating layers within the seventeenth via V17 are etched away, exposing the surface of the twenty-first P-type source region. The seventeenth via V17 is configured to allow the subsequently formed thirteenth connection electrode to be connected to the twenty-first P-type source region through the via.

[0223] In an exemplary embodiment, the orthogonal projection of the eighteenth via V18 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-first P-type drain region of the twenty-first P-type active region 121P onto the silicon substrate. The first and second insulating layers within the eighteenth via V18 are etched away, exposing the surface of the twenty-first P-type drain region. The eighteenth via V18 is configured to allow the subsequently formed eleventh connection electrode to be connected to the twenty-first P-type drain region through the via.

[0224] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the silicon substrate can be located within the range of the orthogonal projection of the twenty-second P-type drain region of the twenty-second P-type active region 122P onto the silicon substrate. The first and second insulating layers within the nineteenth via V19 are etched away, exposing the surface of the twenty-second P-type drain region. The nineteenth via V19 is configured to allow the subsequently formed seventeenth connection electrode to be connected to the twenty-second P-type drain region through the via.

[0225] In an exemplary embodiment, the orthogonal projection of the twentieth via V20 onto the silicon substrate may be located within the range of the orthogonal projection of the twentieth P-type source region 122P onto the silicon substrate. The first and second insulating layers within the twentieth via V20 are etched away, exposing the surface of the twentieth P-type source region. The twentieth via V20 is configured to allow the subsequently formed twelfth connection electrode to be connected to the twentieth P-type source region through the via.

[0226] In an exemplary embodiment, the orthogonal projection of the 21st via V21 onto the silicon substrate may be located within the range of the orthogonal projection of the 21st N-type gate electrode 221N onto the silicon substrate. The second insulating layer within the 21st via V21 is etched away, exposing the surface of the 21st N-type gate electrode 221N. The 21st via V21 is configured to allow the subsequently formed first scan signal line to be connected to the 21st N-type gate electrode 221N through the via.

[0227] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the silicon substrate may be located within the range of the orthogonal projection of the 12th N-type gate interconnect 212N-1 onto the silicon substrate. The second insulating layer within the 22nd via V22 is etched away, exposing the surface of the 12th N-type gate interconnect 212N-1. The 22nd via V22 is configured to allow the subsequently formed 21st connection electrode to be connected to the 12th N-type gate interconnect 212N-1 through the via.

[0228] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the silicon substrate may lie within the range of the orthogonal projection of the 13th N-type gate electrode 213N onto the silicon substrate. The second insulating layer within the 23rd via V23 is etched away, exposing the surface of the 13th N-type gate electrode 213N. The 23rd via V23 is configured to allow a subsequently formed third scan signal line to connect to the 13th N-type gate electrode 213N through this via. In an exemplary embodiment, there may be multiple 23rd vias V23 to reduce contact resistance and improve connection reliability.

[0229] In an exemplary embodiment, the orthogonal projection of the 24th via V24 onto the silicon substrate may be located within the range of the orthogonal projection of the 22nd N-type gate interconnect 222N-1 onto the silicon substrate. The second insulating layer within the 24th via V24 is etched away, exposing the surface of the 22nd N-type gate interconnect 222N-1. The 24th via V24 is configured to allow the subsequently formed 23rd connection electrode to be connected to the 22nd N-type gate interconnect 222N-1 through the via.

[0230] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the silicon substrate may fall within the range of the orthogonal projection of the 23rd N-type gate electrode 223N onto the silicon substrate. The second insulating layer within the 25th via V25 is etched away, exposing the surface of the 23rd N-type gate electrode 223N. The 25th via V25 is configured to allow a subsequently formed third scan signal line to connect to the 23rd N-type gate electrode 223N through this via. In an exemplary embodiment, there may be multiple 25th vias V25 to reduce contact resistance and improve connection reliability.

[0231] In an exemplary embodiment, the orthogonal projection of the 26th via V26 onto the silicon substrate may be located within the range of the orthogonal projection of the 11th P-type gate electrode 211P onto the silicon substrate. The second insulating layer within the 26th via V26 is etched away, exposing the surface of the 11th P-type gate electrode 211P. The 26th via V26 is configured to allow the subsequently formed second scan signal line to be connected to the 11th P-type gate electrode 211P through the via.

[0232] In an exemplary embodiment, the orthogonal projection of the 27th via V27 onto the silicon substrate may be within the range of the orthogonal projection of the 12th P-type gate connector 212P-1 onto the silicon substrate. The second insulating layer within the 27th via V27 is etched away, exposing the surface of the 12th P-type gate connector 212P-1. The 27th via V27 is configured to allow the subsequently formed 22nd connection electrode to be connected to the 12th P-type gate connector 212P-1 through the via.

[0233] In an exemplary embodiment, the orthogonal projection of the 28th via V28 onto the silicon substrate may be located within the range of the orthogonal projection of the 22nd P-type gate connector 222P-1 onto the silicon substrate. The second insulating layer within the 28th via V28 is etched away, exposing the surface of the 22nd P-type gate connector 222P-1. The 28th via V28 is configured to allow the subsequently formed 24th connection electrode to be connected to the 22nd P-type gate connector 222P-1 through the via.

[0234] In an exemplary embodiment, the orthographic projection of the 29th via V29 onto the silicon substrate may be within the range of the orthographic projection of the 12th connecting block 12-1 of the 12th electrode 12 onto the silicon substrate. The second insulating layer within the 29th via V29 is etched away, exposing the surface of the 12th connecting block 12-1. The 29th via V29 is configured to allow the subsequently formed first connecting electrode to be connected to the 12th connecting block 12-1 through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the thirtieth via V30 onto the silicon substrate may be located within the range of the orthogonal projection of the twentieth connecting block 22-1 of the twentieth electrode 22 onto the silicon substrate. The second insulating layer within the thirtieth via V30 is etched away, exposing the surface of the twentieth connecting block 22-1. The thirtieth via V30 is configured to allow the subsequently formed eleventh connecting electrode to be connected to the twentieth connecting block 22-1 through the via.

[0236] In an exemplary embodiment, the orthogonal projection of the thirty-first via V31 onto the silicon substrate may lie within the range of the orthogonal projection of the first N-type power region 114N onto the silicon substrate. The first and second insulating layers within the thirty-first via V31 are etched away, exposing the surface of the first N-type power region 114N. The thirty-first via V31 is configured to allow a subsequently formed eighth connection electrode to connect to the first N-type power region 114N through this via. In an exemplary embodiment, multiple thirty-first vias V31 may be used to reduce contact resistance and improve connection reliability.

[0237] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the silicon substrate may lie within the range of the orthogonal projection of the second N-type power region 124N onto the silicon substrate. The first and second insulating layers within the 32nd via V32 are etched away, exposing the surface of the second N-type power region 124N. The 32nd via V32 is configured to allow a subsequently formed ninth connection electrode to connect to the second N-type power region 124N through this via. In an exemplary embodiment, multiple 32nd vias V32 may be used to reduce contact resistance and improve connection reliability.

[0238] In an exemplary embodiment, the orthogonal projection of the 33rd via V33 onto the silicon substrate may lie within the range of the orthogonal projection of the P-type power region 113P onto the silicon substrate. The first and second insulating layers within the 33rd via V33 are etched away, exposing the surface of the P-type power region 113P. The 33rd via V33 is configured to allow the subsequently formed 10th connection electrode to connect to the P-type power region 113P through this via. In an exemplary embodiment, there may be multiple 33rd vias V33 to reduce contact resistance and improve connection reliability.

[0239] In an exemplary embodiment, the orthogonal projection of the 34th via V34 onto the silicon substrate may lie within the range of the orthogonal projection of the 11th electrode 11 onto the silicon substrate. The first and second insulating layers within the 34th via V34 are etched away, exposing the surface of the 11th electrode 11. The 34th via V34 is configured to allow the subsequently formed 25th connection electrode to connect to the 11th electrode 11 through this via. In an exemplary embodiment, multiple 34th vias V34 may be used to reduce contact resistance and improve connection reliability.

[0240] In an exemplary embodiment, the orthogonal projection of the thirty-fifth via V35 onto the silicon substrate may lie within the range of the orthogonal projection of the twenty-first electrode 21 onto the silicon substrate. The first and second insulating layers within the thirty-fifth via V35 are etched away, exposing the surface of the twenty-first electrode 21. The thirty-fifth via V35 is configured to allow the subsequently formed twenty-sixth connection electrode to connect to the twenty-first electrode 21 through this via. In an exemplary embodiment, multiple thirty-fifth vias V35 may be used to reduce contact resistance and improve connection reliability.

[0241] (6) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a second insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the first conductive layer in Figure 12A. In an exemplary embodiment, the first conductive layer may be referred to as a first metal layer.

[0242] In an exemplary embodiment, the first conductive layer pattern in each repeating unit of the display substrate may include at least: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a power connection line 34, and a first connection electrode 101 to a twenty-sixth connection electrode 126.

[0243] In an exemplary embodiment, the first scan signal line 31 can be a zigzag line extending along the first direction X, and can be continuously arranged in a unit row. The first scan signal line 31 can be connected to the eleventh N-type gate electrode 221N through the twenty-first via V21. Since the eleventh N-type gate electrode 211N and the eleventh N-type gate electrode 221N are connected into an integral structure by a connecting strip, the connection between the first scan signal line 31 and the gate electrode of the eleventh N-type transistor N11 and the gate electrode of the eleventh N-type transistor N21 is realized. The first scan signal line 31 can control the conduction or disconnection of the eleventh N-type transistor N11 in the first sub-pixel and the eleventh N-type transistor N21 in the second sub-pixel.

[0244] In an exemplary embodiment, the orthogonal projection of the first scan signal line 31 on the silicon substrate at least partially overlaps with the orthogonal projections of the twelfth N-type gate electrode 212N, the thirteenth N-type gate electrode 213N, the twenty-first N-type gate electrode 221N, the twenty-second N-type gate electrode 222N, the twenty-third N-type gate electrode 223N, the twenty-first P-type gate electrode 221P, and the twenty-second electrode plate 22 on the silicon substrate.

[0245] In an exemplary embodiment, the second scan signal line 32 can be a zigzag line extending along the first direction X, and can be continuously arranged in a unit row. The second scan signal line 32 can be connected to the eleventh P-type gate electrode 211P through the twenty-sixth via V26. Since the eleventh P-type gate electrode 211P and the twenty-first P-type gate electrode 221P are connected into an integral structure by a connecting strip, the connection between the second scan signal line 32 and the gate electrodes of the eleventh P-type transistor P11 and the twenty-first P-type transistor P21 is realized. The second scan signal line 32 can control the conduction or disconnection of the eleventh P-type transistor P11 in the first sub-pixel and the twenty-first P-type transistor P21 in the second sub-pixel.

[0246] In an exemplary embodiment, the orthogonal projection of the second scan signal line 32 on the silicon substrate at least partially overlaps with the orthogonal projections of the eleventh N-type gate electrode 211N, the twelfth N-type gate electrode 212N, the twenty-second N-type gate electrode 222N, the eleventh P-type gate electrode 211P, and the twelfth electrode plate 12 on the silicon substrate.

[0247] In an exemplary embodiment, in at least one repeating unit, the ratio of the extension length of the first scan signal line 31 to the extension length of the second scan signal line 32 can be approximately 0.95 to 1.05, where the extension length refers to the sum of the dimensions of the signal lines in their respective extension directions.

[0248] In an exemplary embodiment, in at least one repeating unit, the extension length of the first scan signal line 31 and the extension length of the second scan signal line 32 can be substantially equal, so that the first scan signal line 31 and the second scan signal line 32 form complementary traces of equal length. The eleventh N-type transistor N11 and the eleventh P-type transistor P11 in the first sub-pixel constitute a transmission gate with complementary characteristics, and the twenty-first N-type transistor N21 and the twenty-first P-type transistor P21 in the second sub-pixel constitute a transmission gate with complementary characteristics. The first scan signal line 31 and the second scan signal line 32 are differential signals (inverted signals) controlling the transmission gate. By setting the first scan signal line 31 and the second scan signal line 32 as complementary traces of equal length, this disclosure can achieve that the high-level signals and low-level signals transmitted by the first scan signal line 31 and the second scan signal line 32 have the same transmission distance and the same transmission delay, ensuring signal synchronization. It can also achieve that the N-type transistors and P-type transistors in the transmission gate are simultaneously turned off or simultaneously turned on, improving the driving performance of the pixel driving circuit.

[0249] In an exemplary embodiment, in at least one repeating unit, the zigzag-shaped first scan signal line 31 may include multiple horizontal sub-lines and multiple vertical sub-lines, and the zigzag-shaped second scan signal line 32 may include multiple horizontal sub-lines and multiple vertical sub-lines. The horizontal sub-lines may be straight lines extending along a first direction X, and the vertical sub-lines may be straight lines extending along a second direction Y. The number of horizontal sub-lines in the first scan signal line 31 and the number of horizontal sub-lines in the second scan signal line 32 may be equal, and the number of vertical sub-lines in the first scan signal line 31 and the number of vertical sub-lines in the second scan signal line 32 may be equal.

[0250] In an exemplary embodiment, the first scan signal line 31 may include at least an eleventh sub-line 311, a twelfth sub-line 312, a thirteenth sub-line 313, a fourteenth sub-line 314, a fifteenth sub-line 315, a sixteenth sub-line 316, and a seventeenth sub-line 317 connected in sequence. The eleventh sub-line 311, the thirteenth sub-line 313, the fifteenth sub-line 315, and the seventeenth sub-line 317 may be straight lines extending along a first direction X, while the twelfth sub-line 312, the fourteenth sub-line 314, and the sixteenth sub-line 316 may be stripes extending along a second direction Y.

[0251] In an exemplary embodiment, the first end of the twelfth sub-line 312 is connected to the eleventh sub-line 311, and the second end of the twelfth sub-line 312 extends along the second direction Y and is connected to the first end of the thirteenth sub-line 313. The first end of the fourteenth sub-line 314 is connected to the second end of the thirteenth sub-line 313, and the second end of the fourteenth sub-line 314 extends along the opposite direction of the second direction Y and is connected to the first end of the fifteenth sub-line 315. The first end of the sixteenth sub-line 316 is connected to the second end of the fifteenth sub-line 315, and the second end of the sixteenth sub-line 316 extends along the opposite direction of the second direction Y and is connected to the first end of the seventeenth sub-line 317.

[0252] In an exemplary embodiment, the second scan signal line 32 may include at least a 21st sub-line 321, a 22nd sub-line 322, a 23rd sub-line 323, a 24th sub-line 324, a 25th sub-line 325, a 26th sub-line 326, and a 27th sub-line 327 connected sequentially. The 21st sub-line 321, the 23rd sub-line 323, the 25th sub-line 325, and the 27th sub-line 327 may be straight lines extending along a second direction X, while the 22nd sub-line 322, the 24th sub-line 324, and the 26th sub-line 326 may be strips extending along a second direction Y.

[0253] In an exemplary embodiment, the first end of the twenty-second sub-line 322 is connected to the twenty-first sub-line 321, and the second end of the twenty-second sub-line 322 extends in the opposite direction of the second direction Y and is connected to the first end of the twenty-third sub-line 323. The first end of the twenty-fourth sub-line 324 is connected to the second end of the twenty-third sub-line 323, and the second end of the twenty-fourth sub-line 324 extends in the second direction Y and is connected to the first end of the twenty-fifth sub-line 325. The first end of the twenty-sixth sub-line 326 is connected to the second end of the twenty-fifth sub-line 325, and the second end of the twenty-sixth sub-line 326 extends in the second direction Y and is connected to the first end of the twenty-seventh sub-line 327.

[0254] In an exemplary embodiment, the ratio of the extension length of the eleventh sub-line 311 to the extension length of the twenty-first sub-line 321 can be approximately 0.95 to 1.05, the ratio of the extension length of the twelfth sub-line 312 to the extension length of the twenty-second sub-line 322 can be approximately 0.95 to 1.05, the ratio of the extension length of the thirteenth sub-line 313 to the extension length of the twenty-third sub-line 323 can be approximately 0.95 to 1.05, and the ratio of the extension length of the fourteenth sub-line 314 to the extension length of the twenty-third sub-line 323 can be approximately 0.95 to 1.05. The ratio of the extension lengths of the four sub-lines 324 can be approximately 0.95 to 1.05, the ratio of the extension length of the fifteenth sub-line 315 to the extension length of the twenty-fifth sub-line 325 can be approximately 0.95 to 1.05, the ratio of the extension length of the sixteenth sub-line 316 to the extension length of the twenty-sixth sub-line 326 can be approximately 0.95 to 1.05, and the ratio of the extension length of the seventeenth sub-line 317 to the extension length of the twenty-seventh sub-line 327 can be approximately 0.95 to 1.05.

[0255] In an exemplary embodiment, the twelfth sub-line 312 and the second twelfth sub-line 322 extend in opposite directions, meaning that the twelfth sub-line 312 extends in a direction away from the second scan signal line 32, while the second twelfth sub-line 322 extends in a direction away from the first scan signal line 31.

[0256] In an exemplary embodiment, the fourteenth sub-line 314 and the second fourteenth sub-line 324 extend in opposite directions, meaning that the fourteenth sub-line 314 extends toward the direction closer to the second scan signal line 32, while the second fourteenth sub-line 324 extends toward the direction closer to the first scan signal line 31.

[0257] In an exemplary embodiment, the sixteenth sub-line 316 and the second sixteenth sub-line 326 extend in opposite directions, meaning that the sixteenth sub-line 316 extends toward the direction closer to the second scan signal line 32, while the second sixteenth sub-line 326 extends toward the direction closer to the first scan signal line 31.

[0258] In an exemplary embodiment, the extension length of the first scan signal line 31 is the sum of the following lengths: the extension length of the eleventh sub-line 311 along the first direction X, the extension length of the twelfth sub-line 312 along the second direction Y, the extension length of the thirteenth sub-line 313 along the first direction X, the extension length of the fourteenth sub-line 314 along the second direction Y, the extension length of the fifteenth sub-line 315 along the first direction X, the extension length of the sixteenth sub-line 316 along the second direction Y, and the extension length of the seventeenth sub-line 317 along the first direction X.

[0259] In an exemplary embodiment, the extension length of the second scan signal line 32 is the sum of the following lengths: the extension length of the twenty-first sub-line 321 along the first direction X, the extension length of the twenty-second sub-line 322 along the second direction Y, the extension length of the twenty-third sub-line 323 along the first direction X, the extension length of the twenty-fourth sub-line 324 along the second direction Y, the extension length of the twenty-fifth sub-line 325 along the first direction X, the extension length of the twenty-sixth sub-line 326 along the second direction Y, and the extension length of the twenty-seventh sub-line 327 along the first direction X.

[0260] In an exemplary embodiment, a capacitance compensation block 32-1 may be provided on the 25th sub-line 325 of the second scan signal line 32. The capacitance compensation block 32-1 may be block-shaped and may be located on the side of the 25th sub-line 325 away from the first scan signal line 31 and connected to the 25th sub-line 325. The orthographic projection of the capacitance compensation block 32-1 on the silicon substrate at least partially overlaps with the orthographic projection of the 12th electrode plate 12 on the silicon substrate. The capacitance compensation block 32-1 can adjust the parasitic capacitance of the second scan signal line 32 to avoid capacitance differences.

[0261] In an exemplary embodiment, the third scan signal line 33 can be a zigzag line extending along the first direction X, and can be continuously arranged in a unit row. The third scan signal line 33 can be connected to the thirteenth N-type gate electrode 213N through the twenty-third via V23 on one hand, and to the twenty-third N-type gate electrode 223N through the twenty-fifth via V25 on the other hand. Thus, the connection between the third scan signal line 33 and the gate electrode of the thirteenth N-type transistor N13 and the gate electrode of the thirteenth N-type transistor N23 is realized. The third scan signal line 33 can control the conduction or disconnection of the thirteenth N-type transistor N13 in the first sub-pixel and the thirteenth N-type transistor N23 in the second sub-pixel.

[0262] In an exemplary embodiment, the orthogonal projection of the third scan signal line 33 onto the silicon substrate at least partially overlaps with the orthogonal projections of the twelfth N-type gate electrode 212N, the thirteenth N-type gate electrode 213N, the twenty-second N-type gate electrode 222N, the twenty-third N-type gate electrode 223N, and the twenty-second electrode plate 22 onto the silicon substrate.

[0263] In an exemplary embodiment, the power connection line 34 may be a zigzag line extending along the first direction X, may be continuously arranged in a unit row, and may be located on the side of the second scan signal line 32 away from the first scan signal line 31.

[0264] In an exemplary embodiment, the orthographic projection of the power connection line 34 on the silicon substrate at least partially overlaps with the orthographic projections of the twelfth N-type gate electrode 212N, the twenty-second N-type gate electrode 222N, and the twelfth electrode plate 12 on the silicon substrate.

[0265] In an exemplary embodiment, in at least one repeating unit, a shielding block 34-1 may be provided on the power connection line 34. The shielding block 34-1 may be a strip shape extending along the second direction Y. The first end of the shielding block 34-1 is connected to the power connection line 34, and the second end of the shielding block 34-1 extends in the opposite direction of the second direction Y. In the first direction X, the shielding block 34-1 may be disposed between the second electrode of the eleventh N-type transistor N11 and the gate electrode (twelfth P-type gate electrode 212P) of the twelfth P-type transistor P12. Since the power connection line 34 is connected to the subsequently formed second power line, the power connection line 34 and the shielding block 34-1 have the potential of the second power signal. The shielding block 34-1 with a constant potential can effectively shield the influence of the second electrode (first node S1) of the eleventh N-type transistor N11 on the gate electrode of the twelfth P-type transistor P12, thereby improving the working stability of the pixel driving circuit.

[0266] In an exemplary embodiment, the first connecting electrode 101 can be a straight line or a broken line extending along the first direction X. It can be disposed on the opposite side of the second direction Y of the eleventh N-type gate electrode 211N and the eleventh P-type gate electrode 211P. The first connecting electrode 101 can be connected to the eleventh N-type drain region through the second via V2, and to the eleventh P-type drain region through the eighth via V8. It can also be connected to the twelfth connecting block 12-1 through the twenty-ninth via V29. Since the twelfth connecting block 12-1 is connected to the twelfth plate 12, the first connecting electrode 101 realizes the interconnection between the second electrode of the eleventh N-type transistor N11, the second electrode of the eleventh P-type transistor P11, and the twelfth plate 12, forming the main part of the first node S1 of the pixel driving circuit in the first sub-pixel. The first connecting electrode 101 and the twelfth plate 12 have the potential of the first node in the first sub-pixel.

[0267] In an exemplary embodiment, in the first direction X, the shielding block 34-1 can be disposed between the first connecting electrode 101 and the gate electrode (twelfth P-type gate electrode 212P) of the twelfth P-type transistor P12, and in the second direction Y, the power connection line 34 can be disposed between the first connecting electrode 101 and the gate electrode (eleventh N-type gate electrode 211N) of the eleventh N-type transistor N11. Thus, the power connection line 34 and the shielding block 34-1 form a structure that semi-encloses the first connecting electrode 101. Not only can the power connection line 34 and the shielding block 34-1, with their constant potential, effectively shield the first node S1 from the influence of other signals, but the first connecting electrode 101, the power connection line 34, and the shielding block 34-1 can also form a parasitic capacitance, further increasing the capacity of the storage capacitor C.

[0268] In an exemplary embodiment, the shape of the second connection electrode 102 can be a straight line or a broken line extending along the first direction X. It can be disposed on the opposite side of the second direction Y of the twelfth N-type gate electrode 212N and the twelfth P-type gate electrode 212P. The second connection electrode 102 can be connected to the twelfth N-type drain region through the fourth via V4 and to the twelfth P-type source region through the tenth via V10. Thus, the interconnection between the second electrode of the twelfth N-type transistor N12 and the first electrode of the twelfth P-type transistor P12 is realized, forming the main part of the second node S2 of the pixel driving circuit in the first sub-pixel.

[0269] In an exemplary embodiment, the third connection electrode 103 can be a straight line or a broken line extending along the first direction X, and can be located on one side of the eleventh N-type gate electrode 211N and the eleventh P-type gate electrode 211P in the second direction Y. The third connection electrode 103 can be connected to the eleventh N-type source region through the first via V1, and to the eleventh P-type source region through the seventh via V7. The third connection electrode 103 realizes the interconnection between the first electrode of the eleventh N-type transistor N11 and the first electrode of the eleventh P-type transistor P11. The third connection electrode 103 is configured to be connected to the first data signal line in the subsequent formation of the first sub-pixel.

[0270] In an exemplary embodiment, the fourth connection electrode 104 may be a straight line or a broken line extending along the first direction X, and may be disposed on one side of the twelfth N-type gate electrode 212N in the second direction Y. The fourth connection electrode 104 may be connected to the twelfth N-type source region through the third via V3.

[0271] In an exemplary embodiment, the fifth connection electrode 105 may be a straight line or a broken line extending along the first direction X, and may be disposed between the first scan signal line 31 and the third scan signal line 33. The fifth connection electrode 105 may be connected to the thirteenth N-type drain region through the fifth via V5.

[0272] In an exemplary embodiment, the orthographic projection of the fifth connection electrode 105 onto the silicon substrate at least partially overlaps with the orthographic projection of the twelfth N-type gate electrode 212N onto the silicon substrate.

[0273] In an exemplary embodiment, the shape of the sixth connecting electrode 106 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the first scan signal line 31 and the third scan signal line 33. The sixth connecting electrode 106 can be connected to the thirteenth N-type source region through the sixth via V6, and the sixth connecting electrode 106 is configured to be connected to the first initial signal line in the subsequent formation of the first sub-pixel.

[0274] In an exemplary embodiment, the orthographic projection of the sixth connection electrode 106 onto the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth N-type gate electrode 213N onto the silicon substrate.

[0275] In an exemplary embodiment, the shape of the seventh connection electrode 107 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the second scan signal line 32 and the power connection line 34. The seventh connection electrode 107 can be connected to the twelfth P-type drain region through the ninth via V9.

[0276] In an exemplary embodiment, the shape of the eighth connection electrode 108 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the third scan signal line 33 away from the first scan signal line 31. The eighth connection electrode 108 can be connected to the first N-type power supply area 114N through the thirty-first via V31.

[0277] In an exemplary embodiment, the orthographic projection of the eighth connection electrode 108 onto the silicon substrate at least partially overlaps with the orthographic projection of the twelfth N-type gate electrode 212N onto the silicon substrate.

[0278] In an exemplary embodiment, the ninth connection electrode 109 may be a straight line or a broken line extending along the first direction X, and may be disposed on the side of the third scan signal line 33 away from the first scan signal line 31. The ninth connection electrode 109 may be connected to the second N-type power supply area 124N through the thirty-second via V32.

[0279] In an exemplary embodiment, the orthographic projection of the ninth connection electrode 109 on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second N-type gate electrode 222N on the silicon substrate.

[0280] In an exemplary embodiment, the ninth connecting electrode 109 in this repeating unit and the eighth connecting electrode 108 in the adjacent repeating unit in the first direction X can be an integral structure that is interconnected. The eighth connecting electrode 108 in this repeating unit and the ninth connecting electrode 109 in the adjacent repeating unit in the opposite direction of the first direction X can be an integral structure that is interconnected.

[0281] In an exemplary embodiment, the tenth connection electrode 110 may be a straight line or a broken line extending along the first direction X, and may be located on the side of the first connection electrode 101 away from the power connection line 34. The tenth connection electrode 110 may be connected to the P-type power area 113P through the thirty-third via V33, and the tenth connection electrode 110 may be configured to be connected to the first power line formed subsequently.

[0282] In an exemplary embodiment, the eleventh connecting electrode 111 can be a straight line or a broken line extending along the first direction X. It can be disposed on one side of the second direction Y of the twenty-first N-type gate electrode 221N and the twenty-first P-type gate electrode 221P. The eleventh connecting electrode 111 can be connected to the twenty-first N-type drain region through the twelfth via V12, and to the twenty-first P-type drain region through the eighteenth via V18. It can also be connected to the twenty-second connecting block 22-1 through the thirtieth via V30. Since the twenty-second connecting block 22-1 is connected to the twenty-second electrode plate 22, the eleventh connecting electrode 111 realizes the interconnection between the second electrode of the twenty-first N-type transistor N21, the second electrode of the twenty-first P-type transistor P21, and the twenty-second electrode plate 22, forming the main part of the first node S1 of the pixel driving circuit in the second sub-pixel. The eleventh connecting electrode 111 and the twenty-second electrode plate 22 have the potential of the first node in the second sub-pixel.

[0283] In an exemplary embodiment, the twelfth connecting electrode 112 can be a straight line or a broken line extending along the first direction X. It can be located on the side opposite to the second direction Y of the twelfth N-type gate electrode 222N and the twelfth P-type gate electrode 222P. The twelfth connecting electrode 112 can be connected to the twelfth N-type drain region through the fourteenth via V14, and to the twelfth P-type source region through the twentieth via V20. Thus, the interconnection between the second electrode of the twelfth N-type transistor N22 and the first electrode of the twelfth P-type transistor P22 is realized, forming the main part of the second node S2 of the pixel driving circuit in the second sub-pixel.

[0284] In an exemplary embodiment, the thirteenth connecting electrode 113 can be a straight line or a broken line extending along the first direction X, and can be located on the side opposite to the second direction Y of the twenty-first N-type gate electrode 221N and the twenty-first P-type gate electrode 221P. The thirteenth connecting electrode 113 can be connected to the twenty-first N-type source region through the eleventh via V11 on one hand, and to the twenty-first P-type source region through the seventeenth via V17 on the other hand, thus realizing the interconnection between the first pole of the twenty-first N-type transistor N21 and the first pole of the twenty-first P-type transistor P21. The thirteenth connecting electrode 113 is configured to be connected to the second data signal line in the subsequent formation of the second sub-pixel.

[0285] In an exemplary embodiment, the fourteenth connecting electrode 114 may be a straight line or a broken line extending along the first direction X, and may be disposed on one side of the second direction Y of the twenty-second N-type gate electrode 222N. The fourteenth connecting electrode 114 may be connected to the twenty-second N-type source region through the thirteenth via V13.

[0286] In an exemplary embodiment, the fourteenth connecting electrode 114 in this repeating unit and the fourth connecting electrode 104 in the adjacent repeating unit in the first direction X can be an integral structure that is interconnected. The fourth connecting electrode 104 in this repeating unit and the fourteenth connecting electrode 114 in the adjacent repeating unit in the opposite direction of the first direction X can be an integral structure that is interconnected.

[0287] In an exemplary embodiment, the fifteenth connecting electrode 115 may be a straight line or a broken line extending along the first direction X, and may be disposed between the first scan signal line 31 and the third scan signal line 33. The fifteenth connecting electrode 115 may be connected to the twenty-third N-type drain region through the fifteenth via V15.

[0288] In an exemplary embodiment, the orthographic projection of the fifteenth connection electrode 115 onto the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second N-type gate electrode 222N onto the silicon substrate.

[0289] In an exemplary embodiment, the sixteenth connecting electrode 116 may be a straight line or a broken line extending along the first direction X, and may be disposed between the first scan signal line 31 and the third scan signal line 33. The sixteenth connecting electrode may be connected to the twenty-third N-type source region through the sixteenth via V16. The sixteenth connecting electrode 116 is configured to be connected to the second initial signal line in the subsequent formation of the second sub-pixel.

[0290] In an exemplary embodiment, the orthographic projection of the sixteenth connection electrode on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-third N-type gate electrode 223N on the silicon substrate.

[0291] In an exemplary embodiment, the shape of the seventeenth connecting electrode 117 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the second scan signal line 32 and the power connection line 34. The seventeenth connecting electrode 117 can be connected to the twenty-second P-type drain region through the nineteenth via V19.

[0292] In an exemplary embodiment, the eighteenth connecting electrode 118 can be a straight line or a broken line extending along the first direction X, and can be disposed on the side of the power connection line 34 away from the second scan signal line 32. The orthographic projection of the eighteenth connecting electrode 118 on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth electrode plate 12 on the silicon substrate. The eighteenth connecting electrode 118 is configured as the third compensation electrode of this disclosure. In addition, the eighteenth connecting electrode 118 in this disclosure can also balance the metal density, avoid large metal layers or large blank areas, improve etching uniformity, and improve fabrication quality.

[0293] In an exemplary embodiment, the nineteenth connecting electrode 119 can be a straight line or a broken line extending along the first direction X, and can be disposed between the second scan signal line 32 and the power connection line 34. The orthographic projection of the nineteenth connecting electrode 119 on the silicon substrate at least partially overlaps with the orthographic projections of the eleventh N-type gate electrode 211N, the eleventh P-type gate electrode 211P, and the twelfth electrode plate 12 on the silicon substrate. The nineteenth connecting electrode 119 is configured as the first compensation electrode of this disclosure. In addition, the nineteenth connecting electrode 119 can also balance the metal density, avoid large metal layers or large blank areas, improve etching uniformity, and improve fabrication quality.

[0294] In an exemplary embodiment, the twentieth connecting electrode 120 can be a straight line or a broken line extending along the first direction X, and can be disposed between the first scan signal line 31 and the third scan signal line 33. The orthogonal projection of the twentieth connecting electrode 120 on the silicon substrate at least partially overlaps with the orthogonal projections of the twenty-first N-type gate electrode 221N, the twenty-first P-type gate electrode 221P, and the twenty-second electrode plate 22 on the silicon substrate. The twentieth connecting electrode 120 is configured as the second compensation electrode of this disclosure. In addition, the twentieth connecting electrode 120 can also balance the metal density, avoid large metal layers or large blank areas, improve etching uniformity, and improve fabrication quality.

[0295] In an exemplary embodiment, a compensation electrode block 120-1 may be provided on the twentieth connecting electrode 120. The compensation electrode block 120-1 may be block-shaped and may be disposed on the side of the twentieth connecting electrode 120 near the second scan signal line 32 and connected to the twentieth connecting electrode 120. The orthographic projection of the compensation electrode block 120-1 on the silicon substrate and the orthographic projection of the twentieth electrode 22 on the display substrate plane at least partially overlap. The compensation electrode block 120-1 may adjust the parasitic capacitance of the twentieth connecting electrode 120 to avoid capacitance differences.

[0296] In an exemplary embodiment, the shape of the twenty-first connecting electrode 121 can be a straight line or a broken line extending along the first direction X, and it can be located on the side of the power connection line 34 away from the second scan signal line 32. The twenty-first connecting electrode 121 can be connected to the twelfth N-type gate connecting block 212N-1 through the twenty-second via V22.

[0297] In an exemplary embodiment, the twenty-first connecting electrode 121 may extend into an adjacent repeating unit in the opposite direction of the first direction X, and the orthogonal projection of the twenty-first connecting electrode 121 on the silicon substrate at least partially overlaps with the orthogonal projections of the twelfth N-type gate electrode 212N, the twenty-second N-type gate electrode 222N, the twelfth P-type gate electrode 212P, and the twenty-second P-type gate electrode 222P on the silicon substrate.

[0298] In an exemplary embodiment, the twenty-first connecting electrode 121 is configured to be connected to the first connecting electrode 101 via a subsequently formed connecting electrode, thus the twenty-first connecting electrode 121 has the potential of the first node in the first sub-pixel. Since the shielding block 34-1 is disposed on one side of the twenty-first connecting electrode 121 in the first direction X, and the power connection line 34 is disposed on one side of the twenty-first connecting electrode 121 in the second direction Y, the power connection line 34 and the shielding block 34-1 form a structure that semi-encloses the twenty-first connecting electrode 121. Not only can the power connection line 34 and the shielding block 34-1, which have a constant potential, effectively shield the influence of other signals on the first node S1, but the twenty-first connecting electrode 121, the power connection line 34, and the shielding block 34-1 can also form a parasitic capacitance, which can further increase the capacity of the storage capacitor C.

[0299] In an exemplary embodiment, the shape of the 22nd connecting electrode 122 can be a strip shape extending along the second direction Y, and the 22nd connecting electrode 122 can be connected to the 12th P-type gate connecting block 212P-1 through the 27th via V27.

[0300] In an exemplary embodiment, the shape of the twenty-third connecting electrode 123 can be a strip shape extending along the first direction X, and the twenty-third connecting electrode 123 can be connected to the twenty-second N-type gate connecting block 222N-1 through the twenty-fourth via V24.

[0301] In an exemplary embodiment, the shape of the twenty-fourth connecting electrode 124 can be a strip shape extending along the second direction Y, and the twenty-fourth connecting electrode 124 can be connected to the twenty-second P-type gate connecting block 222P-1 through the twenty-eighth via V28.

[0302] In an exemplary embodiment, the shape of the twenty-fifth connecting electrode 125 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the twelfth electrode plate 12 away from the twenty-second electrode plate 22. The twenty-fifth connecting electrode 125 can be connected to the eleventh electrode plate 11 through the thirty-fourth through hole V34.

[0303] In an exemplary embodiment, the 25th connecting electrode 125 in this unit row can be an integral structure connected to the 9th connecting electrode 109 in the previous unit row through the electrode connecting strip 109-1. Since the 9th connecting electrode 109 in this repeating unit and the 8th connecting electrode 108 in the adjacent repeating unit in the first direction X can be an integral structure connected to each other, the first N-type power supply region 114N, the second N-type power supply region 124N and the 11th electrode plate 11 have the same potential, which can effectively stabilize the potential of the silicon substrate where the N-type transistor is located.

[0304] In an exemplary embodiment, the orthographic projection of the twenty-fifth connecting electrode 125 on the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second P-type active region 122P on the silicon substrate, and extends along the first direction X between the twelfth connecting electrode 112 and the twenty-third connecting electrode 123. Since the twenty-fifth connecting electrode 125 is connected to the eleventh electrode plate 11 through a via, and the eleventh electrode plate 11 has the potential of the second power supply signal, and the twelfth connecting electrode 112 is the second node S2, the extended structure of the twenty-fifth connecting electrode 125 with a constant potential can effectively shield the influence of other signals on the second node S2, thereby improving the working stability of the pixel driving circuit.

[0305] In an exemplary embodiment, the integrated ninth connection electrode 109 and the second fifteenth connection electrode 125 can be formed in a structure surrounding the second thirteenth connection electrode 123 in three directions. Since the second thirteenth connection electrode 123 is connected to the second twentieth N-type gate electrode 222N, which is the first node S1, the ninth connection electrode 109 and the second thirteenth connection electrode 125, which have constant potentials, can effectively shield the influence of other signals on the first node S1. Furthermore, the first node S1 and the second power supply signal can form a parasitic capacitance, which can further increase the capacity of the storage capacitor C.

[0306] In an exemplary embodiment, an electrode compensation block 125-1 may be provided on the twenty-fifth connecting electrode 125. The electrode compensation block 125-1 may be located on the side of the twenty-fifth connecting electrode 125 close to the eleventh connecting electrode 111 and connected to the twenty-fifth connecting electrode 125. In the first direction X, the electrode compensation block 125-1 may be located on the side of the eleventh connecting electrode 111 in the first direction X, and in the second direction Y, the twenty-fifth connecting electrode 125 may be located on the side of the eleventh connecting electrode 111 in the second direction Y. Since the eleventh connecting electrode 111 is the first node S1, the twenty-fifth connecting electrode 125 and the electrode compensation block 125-1 may form a structure that semi-encloses the first node S1, and the first node S1 and the second power signal may form a parasitic capacitance, which may further increase the capacity of the storage capacitor C.

[0307] In an exemplary embodiment, the shape of the twenty-sixth connecting electrode 126 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the twelfth electrode plate 12 and the twenty-second electrode plate 22. The twenty-sixth connecting electrode 126 can be connected to the twenty-first electrode plate 21 through the thirty-fifth through hole V35.

[0308] (7) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the pattern of the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG13.

[0309] In an exemplary embodiment, the plurality of vias in each repeating unit of the display substrate may include: the forty-first via V41 to the sixty-sixth via V66, and the seventy-first via V71 to the seventy-seventh via V77.

[0310] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate may be located within the range of the orthographic projection of the first connection electrode 101 on the silicon substrate. The third insulating layer in the forty-first via V41 is etched away, exposing the surface of the first connection electrode 101. The forty-first via V41 is configured to allow the subsequently formed thirty-first connection electrode to be connected to the first connection electrode 101 through the via.

[0311] In an exemplary embodiment, the orthogonal projection of the forty-second via V42 on the silicon substrate may be located within the range of the orthogonal projection of the second connection electrode 102 on the silicon substrate. The third insulating layer within the forty-second via V42 is etched away, exposing the surface of the second connection electrode 102. The forty-second via V42 is configured to allow the subsequently formed thirty-second connection electrode to be connected to the second connection electrode 102 through the via.

[0312] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the silicon substrate may be located within the range of the orthographic projection of the third connection electrode 103 on the silicon substrate. The third insulating layer within the forty-third via V43 is etched away, exposing the surface of the third connection electrode 103. The forty-third via V43 is configured to allow the first data signal line in the subsequently formed first sub-pixel to be connected to the third connection electrode 103 through the via.

[0313] In an exemplary embodiment, the orthogonal projection of the forty-fourth via V44 onto the silicon substrate may be located within the range of the orthogonal projection of the fourth connection electrode 104 onto the silicon substrate. The third insulating layer within the forty-fourth via V44 is etched away, exposing the surface of the fourth connection electrode 104. The forty-fourth via V44 is configured to allow the subsequently formed thirty-third connection electrode to be connected to the fourth connection electrode 104 through the via.

[0314] In an exemplary embodiment, the orthogonal projection of the forty-fifth via V45 onto the silicon substrate may be within the range of the orthogonal projection of the fifth connection electrode 105 onto the silicon substrate. The third insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the fifth connection electrode 105. The forty-fifth via V45 is configured to allow the subsequently formed thirty-second connection electrode to be connected to the fifth connection electrode 105 through the via.

[0315] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 onto the silicon substrate may be within the range of the orthographic projection of the sixth connection electrode 106 onto the silicon substrate. The third insulating layer within the forty-sixth via V46 is etched away, exposing the surface of the sixth connection electrode 106. The forty-sixth via V46 is configured to allow the first initial signal line in the subsequently formed first sub-pixel to be connected to the sixth connection electrode 106 through the via.

[0316] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 onto the silicon substrate may be within the range of the orthographic projection of the seventh connection electrode 107 onto the silicon substrate. The third insulating layer within the forty-seventh via V47 is etched away, exposing the surface of the seventh connection electrode 107. The forty-seventh via V47 is configured to allow the subsequently formed thirty-fourth connection electrode to be connected to the seventh connection electrode 107 through the via.

[0317] In an exemplary embodiment, the orthographic projection of the forty-eighth via V48 onto the silicon substrate may be within the range of the orthographic projection of the eighth connection electrode 108 onto the silicon substrate. The third insulating layer within the forty-eighth via V48 is etched away, exposing the surface of the eighth connection electrode 108. The forty-eighth via V48 is configured to allow a subsequently formed first vertical power line to be connected to the eighth connection electrode 108 through the via.

[0318] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 onto the silicon substrate may be within the range of the orthographic projection of the ninth connection electrode 109 onto the silicon substrate. The third insulating layer within the forty-ninth via V49 is etched away, exposing the surface of the ninth connection electrode 109. The forty-ninth via V49 is configured to allow a subsequently formed second vertical power line to be connected to the ninth connection electrode 109 through the via.

[0319] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 onto the silicon substrate may be within the range of the orthographic projection of the tenth connection electrode 110 onto the silicon substrate. The third insulating layer within the fiftieth via V50 is etched away, exposing the surface of the tenth connection electrode 110. The fiftieth via V50 is configured to allow a subsequently formed first power line to be connected to the tenth connection electrode 110 through the via.

[0320] In an exemplary embodiment, the orthographic projection of the 51st via V51 onto the silicon substrate may be within the range of the orthographic projection of the 11th connection electrode 111 onto the silicon substrate. The third insulating layer within the 51st via V51 is etched away, exposing the surface of the 11th connection electrode 111. The 51st via V51 is configured to allow the subsequently formed 35th connection electrode to be connected to the 11th connection electrode 111 through the via.

[0321] In an exemplary embodiment, the orthogonal projection of the 52nd via V52 onto the silicon substrate may be within the range of the orthogonal projection of the 12th connection electrode 112 onto the silicon substrate. The third insulating layer within the 52nd via V52 is etched away, exposing the surface of the 12th connection electrode 112. The 52nd via V52 is configured to allow the subsequently formed 36th connection electrode to be connected to the 12th connection electrode 112 through the via.

[0322] In an exemplary embodiment, the orthographic projection of the 53rd via V53 onto the silicon substrate may be within the range of the orthographic projection of the 13th connecting electrode 113 onto the silicon substrate. The third insulating layer within the 53rd via V53 is etched away, exposing the surface of the 13th connecting electrode 113. The 53rd via V53 is configured to allow the second data signal line in the subsequently formed second sub-pixel to be connected to the 13th connecting electrode 113 through the via.

[0323] In an exemplary embodiment, the orthographic projection of the 54th via V54 onto the silicon substrate may be within the range of the orthographic projection of the 14th connection electrode 114 onto the silicon substrate. The third insulating layer within the 54th via V54 is etched away, exposing the surface of the 14th connection electrode 114. The 54th via V54 is configured to allow the subsequently formed 37th connection electrode to be connected to the 14th connection electrode 114 through the via.

[0324] In an exemplary embodiment, the orthographic projection of the 55th via V55 onto the silicon substrate may be within the range of the orthographic projection of the 15th connection electrode 115 onto the silicon substrate. The third insulating layer within the 55th via V55 is etched away, exposing the surface of the 15th connection electrode 115. The 55th via V55 is configured to allow the subsequently formed 36th connection electrode to be connected to the 15th connection electrode 115 through the via.

[0325] In an exemplary embodiment, the orthographic projection of the 56th via V56 onto the silicon substrate may be within the range of the orthographic projection of the 16th connection electrode 116 onto the silicon substrate. The third insulating layer within the 56th via V56 is etched away, exposing the surface of the 16th connection electrode 116. The 56th via V56 is configured to allow the second initial signal line in the subsequently formed second sub-pixel to be connected to the 16th connection electrode 116 through the via.

[0326] In an exemplary embodiment, the orthographic projection of the 57th via V57 onto the silicon substrate may be within the range of the orthographic projection of the 17th connection electrode 117 onto the silicon substrate. The third insulating layer within the 57th via V57 is etched away, exposing the surface of the 17th connection electrode 117. The 57th via V57 is configured to allow the subsequently formed 38th connection electrode to be connected to the 17th connection electrode 117 through the via.

[0327] In an exemplary embodiment, the orthographic projection of the 58th via V58 onto the silicon substrate may be within the range of the orthographic projection of the 18th connection electrode 118 onto the silicon substrate. The third insulating layer within the 58th via V58 is etched away, exposing the surface of the 18th connection electrode 118. The 58th via V58 is configured to allow the subsequently formed 43rd connection electrode to be connected to the 18th connection electrode 118 through the via.

[0328] In an exemplary embodiment, the orthographic projection of the 59th via V59 onto the silicon substrate may be within the range of the orthographic projection of the 19th connection electrode 119 onto the silicon substrate. The third insulating layer within the 59th via V59 is etched away, exposing the surface of the 19th connection electrode 119. The 59th via V59 is configured to allow the subsequently formed 41st connection electrode to be connected to the 19th connection electrode 119 through the via.

[0329] In an exemplary embodiment, the orthogonal projection of the sixtieth via V60 onto the silicon substrate may be within the range of the orthogonal projection of the twentieth connection electrode 120 onto the silicon substrate. The third insulating layer within the sixtieth via V60 is etched away, exposing the surface of the twentieth connection electrode 120. The sixtieth via V60 is configured to allow the subsequently formed forty-second connection electrode to be connected to the twentieth connection electrode 120 through the via.

[0330] In an exemplary embodiment, the orthographic projection of the sixty-first via V61 onto the silicon substrate may be within the range of the orthographic projection of the twenty-first connecting electrode 121 onto the silicon substrate. The third insulating layer within the sixty-first via V61 is etched away, exposing the surface of the twenty-first connecting electrode 121. The sixty-first via V61 is configured to allow the subsequently formed thirty-ninth connecting electrode to be connected to the twenty-first connecting electrode 121 through the via.

[0331] In an exemplary embodiment, the orthographic projection of the sixty-second via V62 onto the silicon substrate may be within the range of the orthographic projection of the twenty-second connecting electrode 122 onto the silicon substrate. The third insulating layer within the sixty-second via V62 is etched away, exposing the surface of the twenty-second connecting electrode 122. The sixty-second via V62 is configured to allow the first reference signal line in the subsequently formed first sub-pixel to be connected to the twenty-second connecting electrode 122 through the via.

[0332] In an exemplary embodiment, the orthogonal projection of the sixty-third via V63 onto the silicon substrate may be within the range of the orthogonal projection of the twenty-third connecting electrode 123 onto the silicon substrate. The third insulating layer within the sixty-third via V63 is etched away, exposing the surface of the twenty-third connecting electrode 123. The sixty-third via V63 is configured to allow the subsequently formed forty connecting electrode to be connected to the twenty-third connecting electrode 123 through the via.

[0333] In an exemplary embodiment, the orthographic projection of the sixty-fourth via V64 onto the silicon substrate may be within the range of the orthographic projection of the twenty-fourth connecting electrode 124 onto the silicon substrate. The third insulating layer within the sixty-fourth via V64 is etched away, exposing the surface of the twenty-fourth connecting electrode 124. The sixty-fourth via V64 is configured to allow the second reference signal line in the subsequently formed second sub-pixel to be connected to the twenty-fourth connecting electrode 124 through the via.

[0334] In an exemplary embodiment, the orthographic projection of the sixty-fifth via V65 onto the silicon substrate may be within the range of the orthographic projection of the twenty-fifth connecting electrode 125 onto the silicon substrate. The third insulating layer within the sixty-fifth via V65 is etched away, exposing the surface of the twenty-fifth connecting electrode 125. The sixty-fifth via V65 is configured to allow a subsequently formed second power line to be connected to the twenty-fifth connecting electrode 125 through the via.

[0335] In an exemplary embodiment, the orthographic projection of the sixty-sixth via V66 onto the silicon substrate may be within the range of the orthographic projection of the twenty-sixth connection electrode 126 onto the silicon substrate. The third insulating layer within the sixty-sixth via V66 is etched away, exposing the surface of the twenty-sixth connection electrode 126. The sixty-sixth via V66 is configured to allow a subsequently formed second power line to be connected to the twenty-sixth connection electrode 126 through the via.

[0336] In an exemplary embodiment, the orthographic projection of the seventy-first via V71 onto the silicon substrate may be within the range of the orthographic projection of the first scan signal line 31 onto the silicon substrate. The third insulating layer within the seventy-first via V71 is etched away, exposing the surface of the first scan signal line 31. The seventy-first via V71 is configured to allow the subsequently formed forty-first connection electrode to be connected to the first scan signal line 31 through the via.

[0337] In an exemplary embodiment, the orthogonal projection of the seventy-second via V72 onto the silicon substrate may be located within the range of the orthogonal projection of the second scan signal line 32 onto the silicon substrate. The third insulating layer within the seventy-second via V72 is etched away, exposing the surface of the second scan signal line 32. The seventy-second via V72 is configured to allow the subsequently formed forty-second connection electrode to be connected to the second scan signal line 32 through the via.

[0338] In an exemplary embodiment, the orthogonal projection of the seventy-third via V73 onto the silicon substrate may be located within the range of the orthogonal projection of the third scan signal line 33 onto the silicon substrate. The third insulating layer within the seventy-third via V73 is etched away, exposing the surface of the third scan signal line 33. The seventy-third via V73 is configured to allow the subsequently formed forty-third connection electrode to be connected to the third scan signal line 33 through the via.

[0339] In an exemplary embodiment, the orthogonal projection of the seventy-fourth via V74 onto the silicon substrate may be located within the range of the orthogonal projection of the third scan signal line 33 onto the silicon substrate. The third insulating layer within the seventy-fourth via V74 is etched away, exposing the surface of the third scan signal line 33. The seventy-fourth via V74 is configured to allow the subsequently formed forty-fourth connection electrode to be connected to the third scan signal line 33 through the via.

[0340] In an exemplary embodiment, the orthographic projection of the seventy-fifth via V75 onto the silicon substrate may be within the range of the orthographic projection of the power connection line 34 onto the silicon substrate. The third insulating layer within the seventy-fifth via V75 is etched away, exposing the surface of the power connection line 34. The seventy-fifth via V75 is configured to allow the subsequently formed first vertical power line to be connected to the power connection line 34 through the via.

[0341] In an exemplary embodiment, the orthographic projection of the seventy-sixth via V76 onto the silicon substrate may be within the range of the orthographic projection of the power connection line 34 onto the silicon substrate. The third insulating layer within the seventy-sixth via V76 is etched away, exposing the surface of the power connection line 34. The seventy-sixth via V76 is configured to allow a subsequently formed second power line to be connected to the power connection line 34 through the via.

[0342] In an exemplary embodiment, the orthographic projection of the seventy-seventh via V77 onto the silicon substrate may be within the range of the orthographic projection of the power connection line 34 onto the silicon substrate. The third insulating layer within the seventy-seventh via V77 is etched away, exposing the surface of the power connection line 34. The seventy-seventh via V77 is configured to allow a subsequently formed second vertical power line to be connected to the power connection line 34 through the via.

[0343] (8) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on a third insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the second conductive layer in Figure 14A. In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal2) layer.

[0344] In an exemplary embodiment, the second conductive layer pattern in each repeating unit of the display substrate may include at least: the thirty-first connecting electrode 131 to the forty-fourth connecting electrode 144.

[0345] In an exemplary embodiment, the shape of the thirty-first connecting electrode 131 can be a strip extending along the second direction Y, and the thirty-first connecting electrode 131 can be connected to the first connecting electrode 101 through the forty-first via V41. Since the first connecting electrode 101 is the main part of the first node N1 of the first sub-pixel, the thirty-first connecting electrode 131 has the potential of the first node in the first sub-pixel.

[0346] In an exemplary embodiment, the shape of the thirty-second connecting electrode 132 can be a strip extending along the second direction Y. The thirty-second connecting electrode 132 can be connected to the second connecting electrode 102 through the forty-second via V42, and to the fifth connecting electrode 105 through the forty-fifth via V45. Since the second connecting electrode 102 is the main part of the second node S2 of the pixel driving circuit in the first sub-pixel, and the fifth connecting electrode 105 is connected to the thirteenth N-type drain region through a via, the thirty-second connecting electrode 132 realizes the connection between the second pole of the twelfth N-type transistor N12, the second pole of the thirteenth N-type transistor N13, and the first pole of the twelfth P-type transistor P12 in the first sub-pixel, forming a complete second node S2 in the first sub-pixel.

[0347] In an exemplary embodiment, the thirty-third connecting electrode 133 may include at least a first connecting block 133-1, a second connecting block 133-2, and a first connecting strip 133-3. The first connecting block 133-1 and the second connecting block 133-2 may be block-shaped (e.g., rectangular), and the first connecting strip 133-3 may be a zigzag line extending along the second direction Y. The first connecting strip 133-3 may be disposed on one side of the second connecting block 133-2 in the second direction Y, and may be disposed between the first connecting block 133-1 and the second connecting block 133-2, with both ends of the first connecting strip 133-3 connected to the first connecting block 133-1 and the second connecting block 133-2 respectively, forming a "C" shape. The first connecting block 133-1 may be connected to the fourth connecting electrode 104 through the forty-fourth through-hole V44.

[0348] In an exemplary embodiment, the shape of the thirty-fourth connecting electrode 134 may be a strip shape extending along the second direction Y, and the thirty-fourth connecting electrode 134 may be connected to the seventh connecting electrode 107 through the forty-seventh through-hole V47.

[0349] In an exemplary embodiment, the thirty-fifth connecting electrode 135 may be a strip shape extending along the second direction Y, and the thirty-fifth connecting electrode 135 may be connected to the eleventh connecting electrode 111 via the fifty-first via V51. Since the eleventh connecting electrode 111 is the main part of the first node N1 of the second sub-pixel, the thirty-fifth connecting electrode 135 has the potential of the first node in the second sub-pixel.

[0350] In an exemplary embodiment, the thirty-sixth connecting electrode 136 can be a strip extending along the second direction Y. The thirty-sixth connecting electrode 136 can be connected to the twelfth connecting electrode 112 via the fifty-second via V52, and to the fifteenth connecting electrode 115 via the fifty-fifth via V55. Since the twelfth connecting electrode 112 is the main part of the second node S2 of the pixel driving circuit in the second sub-pixel, and the fifteenth connecting electrode 115 is connected to the twenty-third N-type drain region via a via, the thirty-sixth connecting electrode 136 achieves the interconnection between the second pole of the twenty-second N-type transistor N22, the second pole of the twenty-third N-type transistor N23, and the first pole of the twenty-second P-type transistor P22 in the second sub-pixel, forming a complete second node S2 in the second sub-pixel.

[0351] In an exemplary embodiment, the thirty-seventh connecting electrode 137 may include at least a third connecting block 137-1, a fourth connecting block 137-2, and a second connecting strip 137-3. The third connecting block 137-1 and the fourth connecting block 137-2 may be block-shaped (e.g., rectangular). The third connecting block 137-1 may be disposed on one side of the fourth connecting block 137-2 in the second direction Y. The second connecting strip 137-3 may be disposed between the third connecting block 137-1 and the fourth connecting block 137-2, and both ends of the second connecting strip 137-3 are respectively connected to the third connecting block 137-1 and the fourth connecting block 137-2 to form a "C" shape. The third connecting block 137-1 may be connected to the fourteenth connecting electrode 114 through the fifty-fourth through-hole V54.

[0352] In an exemplary embodiment, in one repeating unit and another repeating unit adjacent to the first direction X, the first connecting block 133-1 and the third connecting block 137-1 can be connected to each other, the second connecting block 133-2 and the fourth connecting block 137-2 can be connected to each other, and the first connecting strip 133-3 and the second connecting strip 137-3 can be connected to each other.

[0353] In an exemplary embodiment, the thirty-seventh connecting electrode 137 in one repeating unit and the thirty-third connecting electrode 133 in another adjacent repeating unit in the first direction X can be an integrally connected structure. Similarly, the thirty-third connecting electrode 133 in one repeating unit and the thirty-seventh connecting electrode 137 in another adjacent repeating unit in the opposite direction of the first direction X can be an integrally connected structure. The integrally connected thirty-third connecting electrode 133 and the thirty-seventh connecting electrode 137 can form an "I" shape. This disclosure's integral "I" shape can also balance metal density, avoid large metal layers or large blank areas, improve etching uniformity, and enhance fabrication quality.

[0354] In an exemplary embodiment, the shape of the thirty-eighth connecting electrode 138 can be a strip shape extending along the second direction Y, and the thirty-eighth connecting electrode 138 can be connected to the seventeenth connecting electrode 117 through the fifty-seventh through-hole V57.

[0355] In an exemplary embodiment, the shape of the thirty-ninth connecting electrode 139 can be a strip extending along the second direction Y, and the thirty-ninth connecting electrode 139 can be connected to the twenty-first connecting electrode 121 through the sixty-first via V61.

[0356] In an exemplary embodiment, the 40th connecting electrode 140 can be a strip extending along the second direction Y. The 40th connecting electrode 140 can be connected to the 23rd connecting electrode 123 through the 63rd via V63. Since the 23rd connecting electrode 123 is connected to the 22nd N-type gate connecting block 222N-1 through the via, and the 22nd N-type gate connecting block 222N-1 is connected to the 22nd N-type gate electrode 222N, the connection between the 40th connecting electrode 140 and the 22nd N-type gate electrode 222N is achieved.

[0357] In an exemplary embodiment, the shape of the forty-first connecting electrode 141 can be a strip shape extending along the second direction Y. The forty-first connecting electrode 141 can be connected to the nineteenth connecting electrode 119 through the fifty-ninth via V59, and can be connected to the first scan signal line 31 through the seventy-first via V71. Since the orthographic projection of the first scan signal line 31 on the silicon substrate at least partially overlaps with the orthographic projections of the twenty-first N-type gate electrode 221N, the twenty-first P-type gate electrode 221P, and the twenty-second electrode plate 22 on the silicon substrate, and the orthographic projection of the nineteenth connecting electrode 119 on the silicon substrate at least partially overlaps with the orthographic projections of the eleventh N-type gate electrode 211N, the eleventh P-type gate electrode 211P, and the twelfth electrode plate 12 on the silicon substrate, the first scan signal has essentially the same effect on the capacitor plates and multiple transistors in the first and second sub-pixels. This ensures the uniformity and symmetry of the pixel driving circuits in the first and second sub-pixels, enabling not only uniform design of the process and coupling capacitors but also uniform design of the current distribution. This effectively improves display stability and uniformity, and enhances display effect and quality.

[0358] In an exemplary embodiment, the shape of the forty-second connecting electrode 142 can be a strip shape extending along the second direction Y. The forty-second connecting electrode 142 can be connected to the twentieth connecting electrode 120 through the sixtieth via V60, and can be connected to the second scan signal line 32 through the seventy-second via V72. Since the orthographic projection of the second scan signal line 32 on the silicon substrate at least partially overlaps with the orthographic projections of the eleventh N-type gate electrode 211N, the eleventh P-type gate electrode 211P, and the twelfth electrode plate 12 on the silicon substrate, and the orthographic projection of the twentieth connecting electrode 120 on the silicon substrate at least partially overlaps with the orthographic projections of the twenty-first N-type gate electrode 221N, the twenty-first P-type gate electrode 221P, and the twelfth electrode plate 22 on the silicon substrate, the influence of the second scan signal on the capacitor plates and multiple transistors in the first and second sub-pixels is basically the same. This ensures the uniformity and symmetry of the pixel driving circuits in the first and second sub-pixels, enabling not only uniform design of the process and coupling capacitors but also uniform design of the current distribution. This effectively improves display stability and uniformity, and enhances display effect and quality.

[0359] In an exemplary embodiment, the forty-third connecting electrode 143 can be a strip extending along the second direction Y. The forty-third connecting electrode 143 can be connected to the eighteenth connecting electrode 118 via the fifty-eighth via V58, and to the third scan signal line 33 via the seventy-third via V73. Since the orthographic projection of the third scan signal line 33 onto the silicon substrate at least partially overlaps with the orthographic projection of the twenty-second electrode 22 onto the silicon substrate, and the orthographic projection of the eighteenth connecting electrode 118 onto the silicon substrate at least partially overlaps with the orthographic projection of the twelfth electrode 12 onto the silicon substrate, the influence of the third scan signal on the capacitor plates in the first and second sub-pixels is substantially the same. This ensures the uniformity and symmetry of the pixel driving circuits in the first and second sub-pixels, achieving not only uniform design of the process and coupling capacitors, but also uniform design of the current distribution, effectively improving display stability and uniformity, and significantly enhancing display effect and quality.

[0360] In an exemplary embodiment, the shape of the forty-fourth connecting electrode 144 can be a strip shape extending along the second direction Y, and the forty-fourth connecting electrode 144 can be connected to the third scan signal line 33 through the seventy-fourth via V74.

[0361] In an exemplary embodiment, the orthographic projection of the forty-fourth connection electrode 144 on the silicon substrate at least partially overlaps with the orthographic projections of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, and the power connection line 34 on the silicon substrate.

[0362] In an exemplary embodiment, in the first direction X, the thirty-first connecting electrode 131 can be disposed between the first power line 41 and the forty-fourth connecting electrode 144. The forty-fourth connecting electrode 144 can be provided with a shielding strip 144-1 and a shielding frame 144-2. The shielding strip 144-1 can be a strip shape extending along the first direction X, and can be disposed on the side opposite to the second direction Y of the thirty-first connecting electrode 131. The first end of the shielding strip 144-1 is connected to the forty-fourth connecting electrode 144, and the second end of the shielding strip 144-1 extends towards the first direction X. The shielding frame 144-2 can be a mirrored "C" shape, and can be disposed on the side of the thirty-first connecting electrode 131 in the second direction Y. Both ends of the shielding frame 144-2 are connected to the forty-fourth connecting electrode 144, forming a ring structure.

[0363] In an exemplary embodiment, the forty-fourth connecting electrode 144, the shielding strip 144-1, and the shielding frame 144-2 can be an integral structure that is interconnected.

[0364] In an exemplary embodiment, the forty-fourth connecting electrode 144, the shielding strip 144-1, and the shielding frame 144-2 can form a semi-enclosed structure surrounding the thirty-first connecting electrode 131. Since the thirty-first connecting electrode 131 is the first node S1, the semi-enclosed structure can effectively shield the influence of the first data signal line on the first node S1. In addition, the "C"-shaped shielding frame 144-2 provided in this disclosure can also balance the metal density, avoid large metal layers or large blank areas, improve etching uniformity, and improve fabrication quality.

[0365] In an exemplary embodiment, the second conductive layer pattern of each repeating unit in the display substrate may further include a first power line 41, a second power line 42, a data signal line 43, an initial signal line 44, a reference signal line 45, a first vertical power line 51, a second vertical power line 52, and a third vertical power line 53. Each repeating unit has two data signal lines 43, 44, and 45.

[0366] In an exemplary embodiment, the first power line 41 can be a straight line or a broken line extending along the second direction Y, and can be disposed between the gate electrode of the twelfth N-type transistor N12 and the twelfth plate 12 and the second twelfth plate 22. The first power line 41 can be connected to the tenth connection electrode 110 through the fiftieth via V50. Since the tenth connection electrode 110 is connected to the P-type power region 113P through the via, the first power line 41 writes the first power signal into the silicon substrate where the P-type transistor is located.

[0367] In an exemplary embodiment, the first power line 41 may extend to a non-display area and be connected to a power lead that transmits a first power signal.

[0368] In an exemplary embodiment, the second power line 42 can be a straight line or a broken line extending along the second direction Y, and can be disposed between the first power line 41 and the gate electrode of the twenty-second N-type transistor N22. The second power line 42 can be connected to the twenty-fifth connecting electrode 125 via the sixty-fifth via V65, and to the twenty-sixth connecting electrode 126 via the sixty-sixth via V66. Since the twenty-fifth connecting electrode 125 is connected to the eleventh electrode 11 via a via, and the twenty-sixth connecting electrode 126 is connected to the twenty-first electrode 21 via a via, the eleventh electrode 11 and the twenty-first electrode 21 have the potential of the second power signal.

[0369] In an exemplary embodiment, the second power line 42 may extend to a non-display area and be connected to a power lead that transmits a second power signal.

[0370] In an exemplary embodiment, since the eleventh electrode 11 has the potential of the second power signal and the twelfth electrode 12 has the potential of the first node in the first sub-pixel, the eleventh electrode 11 and the twelfth electrode 12 form an eleventh capacitor in the first sub-pixel. Since the twenty-first electrode 21 has the potential of the second power signal and the twenty-second electrode 22 has the potential of the first node in the second sub-pixel, the twenty-first electrode 21 and the twenty-second electrode 22 form a twenty-first capacitor in the second sub-pixel.

[0371] In an exemplary embodiment, since the 25th connecting electrode 125 of this repeating unit and the 9th connecting electrode 109 in the repeating unit of the previous unit row are interconnected as an integral structure, and the 9th connecting electrode 109 and the 8th connecting electrode 108 in the adjacent repeating unit in the first direction X can be interconnected as an integral structure, and the 8th connecting electrode 108 and the 9th connecting electrode 109 are respectively connected to the first N-type power supply region 114N and the second N-type power supply region 124N, the second power line 42 writes the second power signal into the silicon substrate where the N-type transistors in the first sub-pixel and the second sub-pixel are located.

[0372] In an exemplary embodiment, the second power line 42 can also be connected to the power connection line 34 through the seventy-sixth via V76, thus realizing that the power connection line 34 extending along the first direction X and the second power line 42 extending along the second direction Y form a mesh-like interconnection structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0373] In an exemplary embodiment, the first data signal line 43-1 and the second data signal line 43-2 are both disposed between the gate electrode of the twelfth N-type transistor N12 and the twelfth plate 12 and the second twelfth plate 22.

[0374] In an exemplary embodiment, the shape of the first data signal line 43-1 can be a straight line or a broken line extending along the second direction Y, and can serve as the data signal line 43 in the first sub-pixel. The first data signal line 43-1 can be connected to the third connection electrode 103 in the first pixel through the forty-third via V43. Since the third connection electrode 103 is connected to the eleventh N-type source region and the eleventh P-type source region respectively through the via, the first data signal line 43-1 writes the data signal into the first electrode of the eleventh N-type transistor N11 and the first electrode of the eleventh P-type transistor P11 in the first sub-pixel.

[0375] In an exemplary embodiment, the second data signal line 43-2 can be a straight line or a broken line extending along the second direction Y, and can serve as the data signal line 43 in the second sub-pixel. The second data signal line 43-2 can be connected to the thirteenth connection electrode 113 in the second pixel through the fifty-third via V53. Since the thirteenth connection electrode 113 is connected to the twenty-first N-type source region and the twenty-first P-type source region respectively through the via, the second data signal line 43-2 writes the data signal into the first electrode of the twenty-first N-type transistor N21 and the first electrode of the twenty-first P-type transistor P21 in the second sub-pixel.

[0376] In an exemplary embodiment, the first data signal line 43-1 can be disposed on the side opposite to the first direction X of the first power line 41, and the second data signal line 43-2 can be disposed on the side of the first direction X of the first power line 41. That is, the first power line 41 is disposed between the first data signal line 43-1 and the second data signal line 43-2. ​​The first power line 41 with a constant potential can effectively shield the mutual influence between the two data signal lines, improve the working stability of the pixel driving circuit, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve the display quality.

[0377] In an exemplary embodiment, a forty-fourth connecting electrode 144 may be provided between the first data signal line 43-1 and the second data signal line 43-2 in the first direction X. The forty-fourth connecting electrode 144, which is connected to the third scan signal line 33 and has a ring structure, can avoid coupling between the two data signal lines.

[0378] In an exemplary embodiment, the distance between the second data signal line 43-2 and the gate electrode of the twelfth N-type transistor N22 can be greater than the distance between the first data signal line 43-1 and the gate electrode of the twelfth N-type transistor N12.

[0379] In an exemplary embodiment, a first initial signal line 44-1 and a first reference signal line 45-1 are provided between the first data signal line 43-1 and the gate electrode of the twelfth N-type transistor N12. Therefore, the distance between the first data signal line 43-1 and the twelfth N-type transistor N12 is relatively large, which can not only effectively reduce the crosstalk between the data signal line and the driving transistor, but also effectively reduce the parasitic capacitance between the data signal line and the driving transistor, improve the working stability of the pixel driving circuit, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve the display quality.

[0380] In an exemplary embodiment, a second initial signal line 44-2, a second reference signal line 45-2, and a second power supply line 42 are provided between the second data signal line 43-2 and the gate electrode of the 22nd N-type transistor N22. Therefore, the distance between the second data signal line 43-2 and the 22nd N-type transistor N22 is relatively large, which can not only effectively reduce the crosstalk between the data signal line and the driving transistor, but also effectively reduce the parasitic capacitance between the data signal line and the driving transistor, improve the working stability of the pixel driving circuit, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve the display quality.

[0381] In an exemplary embodiment, the shape of the first initial signal line 44-1 can be a straight line or a broken line extending along the second direction Y. As the initial signal line 44 in the first sub-pixel, it can be disposed between the first data signal line 43-1 and the gate electrode of the twelfth N-type transistor N12. The first initial signal line 44-1 can be connected to the sixth connection electrode 106 through the forty-sixth via V46. Since the sixth connection electrode 106 is connected to the thirteenth N-type source region through the via, the first initial signal line 44-1 writes the initial signal into the first electrode of the thirteenth N-type transistor N13 in the first sub-pixel.

[0382] In an exemplary embodiment, the second initial signal line 44-2 can be a straight line or a broken line extending along the second direction Y. As the initial signal line 44 in the second sub-pixel, it can be disposed between the second power line 42 and the gate electrode of the twenty-second N-type transistor N22. The second initial signal line 44-2 can be connected to the sixteenth connection electrode 116 through the fifty-sixth via V56. Since the sixteenth connection electrode 116 is connected to the twenty-third N-type source region through the via, the second initial signal line 44-2 writes the initial signal into the first electrode of the twenty-third N-type transistor N23 in each second sub-pixel.

[0383] In an exemplary embodiment, the first reference signal line 45-1 can be a straight line or a broken line extending along the second direction Y. As a reference signal line 45 in the first sub-pixel, it can be disposed between the first data signal line 43-1 and the first initial signal line 44-1. The first reference signal line 45-1 can be connected to the twenty-second connecting electrode 122 through the sixty-second via V62. Since the twenty-second connecting electrode 122 is connected to the twelfth P-type gate connecting block 212P-1 through the via, and the twelfth P-type gate connecting block 212P-1 and the twelfth P-type gate electrode 212P, the connection between the first reference signal line 45-1 and the gate electrode of the twelfth P-type transistor P12 in the first sub-pixel is realized. The first reference signal line 45-1 can control the conduction or disconnection of the twelfth P-type transistor P12 in the first sub-pixel.

[0384] In an exemplary embodiment, the second reference signal line 45-2 can be a straight line or a broken line extending along the second direction Y. As a reference signal line 45 in the second sub-pixel, it can be disposed between the second power line 42 and the second initial signal line 44-2. The second reference signal line 45-2 can be connected to the twenty-fourth connecting electrode 124 through the sixty-fourth via V64. Since the twenty-fourth connecting electrode 124 is connected to the twenty-second P-type gate electrode 222P through the via, the connection between the twenty-second P-type gate electrode 222P and the gate electrode of the twenty-second P-type transistor P22 in the second sub-pixel is realized. The second reference signal line 45-2 can control the conduction or disconnection of the twenty-second P-type transistor P22 in the second sub-pixel.

[0385] In an exemplary embodiment, the first vertical power line 51 can be a straight line or a broken line extending along the second direction Y, and can be located on the side of the first initial signal line 44-1 away from the first power line 41. The first vertical power line 51 can be provided with multiple first power connection blocks 51-1 and multiple second power connection blocks 51-2. The first power connection block 51-1 can be a strip extending along the first direction X. The first end of the first power connection block 51-1 is connected to the first vertical power line 51, and the second end of the first power connection block 51-1 extends towards the first power line 41 and is connected to the eighth connection electrode 108 through the forty-eighth via V48. The second power connection block 51-2 can also be a strip extending along the first direction X. The first end of the second power connection block 51-2 is connected to the first vertical power line 51, and the second end of the second power connection block 51-2 extends away from the first power line 41 and is connected to the power connection line 34 through the seventy-fifth via V75. Since the power connection cable 34 is connected to the second power cable 42 through a via, the connection between the first vertical power cable 51 and the second power cable 42 is realized.

[0386] In an exemplary embodiment, the second vertical power line 52 can be a straight line or a broken line extending along the second direction Y. It can be located on the side of the second initial signal line 44-2 away from the second power line 42. Multiple third power connection blocks 52-1 and multiple fourth power connection blocks 52-2 can be provided on the second vertical power line 52. The third power connection block 52-1 can be a strip extending along the first direction X. The first end of the third power connection block 52-1 is connected to the second vertical power line 52, and the second end of the third power connection block 52-1 extends towards the second power line 42 and is connected to the ninth connection electrode 109 through the forty-ninth via V49. The fourth power connection block 52-2 can be a strip extending along the first direction X. The first end of the fourth power connection block 52-2 is connected to the second vertical power line 52, and the second end of the fourth power connection block 52-2 extends away from the second power line 42 and is connected to the power connection line 34 through the seventy-seventh via V77. Since the power connection cable 34 is connected to the second power cable 42 through a via, the connection between the second vertical power cable 52 and the second power cable 42 is realized.

[0387] In an exemplary embodiment, the first vertical power line 51 in a repeating unit and the second vertical power line 52 in another adjacent repeating unit in the opposite direction of the first direction X can be an integral structure connected to each other. The second vertical power line 52 in a repeating unit and the first vertical power line 51 in another adjacent repeating unit in the first direction X can be an integral structure connected to each other. The first vertical power line 51 and the second vertical power line 52 of the integral structure can form a ring structure, and the thirty-third connecting electrode 133 and the thirty-seventh connecting electrode 137 are disposed in the ring structure.

[0388] In an exemplary embodiment, the power connection line 34 extending along the first direction X and the first vertical power line 51 and the second vertical power line 52 extending along the second direction Y form a plurality of mesh interconnected structures on the display substrate for transmitting the second power signal, which can further reduce the resistance of the second power line and reduce the voltage drop of the second power signal.

[0389] In an exemplary embodiment, the third vertical power line 53 can be a straight line or a broken line extending along the second direction Y, and can be located on the side opposite to the first direction X of the second power line 42. Multiple fifth power connection blocks 53-1 and multiple sixth power connection blocks 53-2 can be provided on the third vertical power line 53. The fifth power connection block 53-1 can be a strip extending along the first direction X. The first end of the fifth power connection block 53-1 is connected to the third vertical power line 53, and the second end of the fifth power connection block 53-1 extends towards the second power line 42 and then connects to the second power line 42. The sixth power connection block 53-2 can be a strip extending along the first direction X. The first end of the sixth power connection block 53-2 is connected to the third vertical power line 53, and the second end of the sixth power connection block 53-2 extends away from the second power line 42.

[0390] In an exemplary embodiment, in at least one repeating unit, the second power line 42, the third vertical power line 53, the plurality of fifth power connection blocks 53-1, and the plurality of sixth power connection blocks 53-2 can be an interconnected integral structure. The integral structure of the second power line 42 and the third vertical power line 53 can form a ring structure, and the thirty-fifth connection electrode 135 can be disposed within this ring structure. Not only can the ring structure with a constant potential shield the influence of other signals on the first node S1 of the pixel driving circuit, improving the working stability of the pixel driving circuit, but the thirty-fifth connection electrode 135 and the ring structure can also form a parasitic capacitance, which can further increase the capacity of the storage capacitor C, effectively improving the uniformity and stability of the output current or voltage of the pixel driving circuit, and improving the display quality. In addition, the provision of multiple fifth power connection blocks 53-1 in this disclosure can also balance the metal density, avoid large metal layers or large blank areas, improve etching uniformity, and improve the fabrication quality.

[0391] In an exemplary embodiment, the orthographic projections of the second power line 42 and the third vertical power line 53 onto the silicon substrate at least partially overlap with the orthographic projections of the twelfth electrode 12 and the second twelfth electrode 22 onto the silicon substrate.

[0392] In an exemplary embodiment, the orthographic projection of the sixth power connection block 53-2 on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh connection electrode 111 on the silicon substrate. Since the eleventh connection electrode 111 is the first node N1 of the second sub-pixel, the sixth power connection block 53-2, which has a constant potential (the potential of the second power signal), can effectively shield the first node N1 of the second sub-pixel, thereby improving the operational stability of the pixel driving circuit.

[0393] In an exemplary embodiment, the second power line 42 and the third vertical power line 53 form a two-wire structure, which can further reduce the resistance of the second power line and reduce the voltage drop of the second power signal.

[0394] (10) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the pattern of the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG15.

[0395] In an exemplary embodiment, the plurality of vias in each repeating unit of the display substrate may include: eighty-first via V81 to ninetieth via V90.

[0396] In an exemplary embodiment, the orthogonal projection of the 81st via V81 onto the silicon substrate may be within the range of the orthogonal projection of the 31st connection electrode 131 onto the silicon substrate. The fourth insulating layer within the 81st via V81 is etched away, exposing the surface of the 31st connection electrode 131. The 81st via V81 is configured to allow the subsequently formed 51st connection electrode to be connected to the 31st connection electrode 131 through the via.

[0397] In an exemplary embodiment, the orthogonal projection of the 82nd via V82 onto the silicon substrate may be within the range of the orthogonal projection of the 33rd connecting electrode 133 onto the silicon substrate. The fourth insulating layer within the 82nd via V82 is etched away, exposing the surface of the 33rd connecting electrode 133. The 82nd via V82 is configured to allow a subsequently formed first lateral power line or second lateral power line to be connected to the 33rd connecting electrode 133 through the via.

[0398] In an exemplary embodiment, there may be multiple 82 vias V82. The orthogonal projection of at least one 82 via V82 on the silicon substrate may be within the range of the orthogonal projection of the first connecting block 133-1 of the 33rd connecting electrode 133 on the silicon substrate. The orthogonal projection of at least one 82 via V82 on the silicon substrate may be within the range of the orthogonal projection of the second connecting block 133-2 of the 33rd connecting electrode 133 on the silicon substrate.

[0399] In an exemplary embodiment, the orthographic projection of the 83rd via V83 on the silicon substrate is within the range of the orthographic projection of the 34th connection electrode 134 on the silicon substrate. The fourth insulating layer within the 83rd via V83 is etched away, exposing the surface of the 34th connection electrode 134. The 83rd via V83 is configured to allow the subsequently formed 52nd connection electrode to be connected to the 34th connection electrode 134 through the via.

[0400] In an exemplary embodiment, the orthographic projection of the 84th via V84 onto the silicon substrate is within the range of the orthographic projection of the 35th connection electrode 135 onto the silicon substrate. The fourth insulating layer within the 84th via V84 is etched away, exposing the surface of the 35th connection electrode 135. The 84th via V84 is configured to allow the subsequently formed 53rd connection electrode to be connected to the 35th connection electrode 135 through the via.

[0401] In an exemplary embodiment, the orthographic projection of the 85th via V85 on the silicon substrate is within the range of the orthographic projection of the 37th connection electrode 137 on the silicon substrate. The fourth insulating layer within the 85th via V85 is etched away, exposing the surface of the 37th connection electrode 137. The 85th via V85 is configured to allow a subsequently formed first lateral power line or second lateral power line to be connected to the 37th connection electrode 137 through the via.

[0402] In an exemplary embodiment, there can be multiple 85 vias V85. The orthogonal projection of at least one 85 via V85 on the silicon substrate can be within the range of the orthogonal projection of the third connecting block 137-1 of the 37th connecting electrode 137 on the silicon substrate. The orthogonal projection of at least one 85 via V85 on the silicon substrate can be within the range of the orthogonal projection of the fourth connecting block 137-2 of the 37th connecting electrode 137 on the silicon substrate.

[0403] In an exemplary embodiment, the orthographic projection of the 86th via V86 onto the silicon substrate is within the range of the orthographic projection of the 38th connection electrode 138 onto the silicon substrate. The fourth insulating layer within the 86th via V86 is etched away, exposing the surface of the 38th connection electrode 138. The 86th via V86 is configured to allow the subsequently formed 54th connection electrode to be connected to the 38th connection electrode 138 through the via.

[0404] In an exemplary embodiment, the orthographic projection of the 87th via V87 onto the silicon substrate is within the range of the orthographic projection of the 39th connection electrode 139 onto the silicon substrate. The fourth insulating layer within the 87th via V87 is etched away, exposing the surface of the 39th connection electrode 139. The 87th via V87 is configured to allow the subsequently formed 51st connection electrode to be connected to the 39th connection electrode 139 through the via.

[0405] In an exemplary embodiment, the orthographic projection of the 88th via V88 onto the silicon substrate is within the range of the orthographic projection of the 40th connection electrode 140 onto the silicon substrate. The fourth insulating layer within the 88th via V88 is etched away, exposing the surface of the 40th connection electrode 140. The 88th via V88 is configured to allow the subsequently formed 53rd connection electrode to be connected to the 40th connection electrode 140 through the via.

[0406] In an exemplary embodiment, the orthographic projection of the 89th via V89 onto the silicon substrate is within the range of the orthographic projection of the first vertical power line 51 onto the silicon substrate. The fourth insulating layer within the 89th via V89 is etched away, exposing the surface of the first vertical power line 51. The 89th via V89 is configured to allow the subsequently formed 55th connection electrode 155 to be connected to the first vertical power line through the via.

[0407] In an exemplary embodiment, the orthographic projection of the 90th via V90 on the silicon substrate is within the range of the orthographic projection of the second vertical power line 52 on the silicon substrate. The fourth insulating layer within the 90th via V90 is etched away, exposing the surface of the second vertical power line 52. The 90th via V90 is configured to allow the subsequently formed 56th connection electrode to be connected to the second vertical power line 52 through the via.

[0408] (11) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern on a fourth insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a schematic diagram of the third conductive layer in Figure 16A. In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal3) layer.

[0409] In an exemplary embodiment, the third conductive layer pattern in each repeating unit of the display substrate may include at least: a first lateral power line 61, a second lateral power line 62, and fifty-first connecting electrodes 151 to fifty-sixth connecting electrodes 156.

[0410] In an exemplary embodiment, the first horizontal power line 61 and the second horizontal power line 62 can be straight or broken lines extending along the first direction X, and can be continuously arranged in a unit row. The first horizontal power line 61 can be arranged on one side of the second horizontal power line 62 in the second direction Y. The first horizontal power line 61 can be connected to the first connecting block 133-1 of the thirty-third connecting electrode 133 through the eighty-second via V82, and to the third connecting block 137-1 of the thirty-seventh connecting electrode 137 through the eighty-fifth via V85. The second horizontal power line 62 can be connected to the second connecting block 133-2 of the thirty-third connecting electrode 133 through the eighty-second via V82, and to the fourth connecting block 137-2 of the thirty-seventh connecting electrode 137 through the eighty-fifth via V85. Since the thirty-third connecting electrode 133 is connected to the fourth connecting electrode 104 through a via, the fourth connecting electrode 104 is connected to the twelfth N-type source region through a via, the thirty-seventh connecting electrode 137 is connected to the fourteenth connecting electrode 114 through a via, and the fourteenth connecting electrode 114 is connected to the twenty-second N-type source region through a via, the first lateral power line 61 and the second lateral power line 62 realize the writing of the first power signal into the first electrode of the twelfth N-type transistor N12 in the first sub-pixel and the first electrode of the twenty-second N-type transistor N22 in the second sub-pixel, respectively.

[0411] In an exemplary embodiment, the first horizontal power line 61 and the second horizontal power line 62 may extend to the non-display area and be connected to the power lead that transmits the first power signal.

[0412] In an exemplary embodiment, the first horizontal power line 61 and the second horizontal power line 62 in two partially adjacent cell rows can be isolated, while the first horizontal power line 61 and the second horizontal power line 62 in two partially adjacent cell rows can be an integral structure that is interconnected. For example, the first horizontal power line 61 in the Mth cell row and the second horizontal power line 62 in the M+1th cell row can be isolated, while the first horizontal power line 61 in the M+1th cell row and the second horizontal power line 62 in the M+2th cell row can be an integral structure that is interconnected.

[0413] In an exemplary embodiment, since the first power line 41, the first lateral power line 61, and the second lateral power line 62 all transmit the first power signal, the first lateral power line 61 and the second lateral power line 62 extending along the first direction X and the first power line 41 extending along the second direction Y form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0414] In an exemplary embodiment, the shape of the fifty-first connecting electrode 151 can be a straight line or a broken line extending along the first direction X. The fifty-first connecting electrode 151 can be connected to the thirty-first connecting electrode 131 through the eighty-first via V81, and can be connected to the thirty-ninth connecting electrode 139 through the eighty-seventh via V87. Since the thirty-first connecting electrode 131 is connected to the first connecting electrode 101 through a via, and the first connecting electrode 101 is the main part of the first node S1 of the pixel driving circuit in the first sub-pixel, the thirty-ninth connecting electrode 139 is connected to the twenty-first connecting electrode 121 through a via, and the twenty-first connecting electrode 121 is connected to the twelfth N-type gate connecting block 212N-1 through a via, and the twelfth N-type gate connecting block 212N-1 is connected to the twelfth N-type gate electrode 212N, the fifty-first connecting electrode 151 realizes the interconnection between the second pole of the eleventh N-type transistor N11, the second pole of the eleventh P-type transistor P11, the gate electrode of the twelfth N-type transistor N12 and the twelfth plate 12, forming a complete first node S1 in the first sub-pixel.

[0415] In an exemplary embodiment, the shape of the 52nd connecting electrode 152 can be a straight line or a broken line extending along the first direction X, and the 52nd connecting electrode 152 can be connected to the 34th connecting electrode 134 through the 83rd via V83.

[0416] In an exemplary embodiment, the shape of the fifty-third connecting electrode 153 can be a straight line or a broken line extending along the first direction X. The fifty-third connecting electrode 153 can be connected to the thirty-fifth connecting electrode 135 through the eighty-fourth via V84, and to the fortieth connecting electrode 140 through the eighty-eighth via V88. Since the 35th connecting electrode 135 is connected to the 11th connecting electrode 111 through a via, and the 11th connecting electrode 111 is the main part of the first node S1 of the pixel driving circuit in the second sub-pixel, the 40th connecting electrode 140 is connected to the 23rd connecting electrode 123 through a via, the 23rd connecting electrode 123 is connected to the 22nd N-type gate connecting block 222N-1, and the 22nd N-type gate connecting block 222N-1 is connected to the 22nd N-type gate electrode 222N, the 53rd connecting electrode 153 realizes the interconnection between the second pole of the 21st N-type transistor N21, the second pole of the 21st P-type transistor P21, the gate electrode of the 22nd N-type transistor N22, and the 22nd plate 22, forming a complete first node S1 in the second sub-pixel.

[0417] In an exemplary embodiment, the shape of the 54th connecting electrode 154 can be a straight line or a broken line extending along the first direction X, and the 54th connecting electrode 154 can be connected to the 38th connecting electrode 138 through the 86th via V86.

[0418] In an exemplary embodiment, the shape of the 55th connecting electrode 155 can be a broken line extending along the first direction X. The 55th connecting electrode 155 can be connected to the first vertical power line 51 through the 89th via V89. The 55th connecting electrode 155 has the potential of the second power signal.

[0419] In an exemplary embodiment, the shape of the fifty-sixth connecting electrode 156 can be a straight line or a broken line extending along the first direction X. The fifty-sixth connecting electrode 156 can be connected to the second vertical power line 52 through the ninetieth via V90. The fifty-sixth connecting electrode 156 has the potential of the second power signal.

[0420] In an exemplary embodiment, the 55th connecting electrode 155 in a repeating unit and the 56th connecting electrode 156 in an adjacent repeating unit in the opposite direction of the first direction X can be an integrally connected structure. Similarly, the 56th connecting electrode 106 in a repeating unit and the 55th connecting electrode 155 in an adjacent repeating unit in the first direction X can be an integrally connected structure. The 55th connecting electrode 155 and the 56th connecting electrode 156 extending along the first direction X, together with the first vertical power line 51 and the second vertical power line 52 extending along the second direction Y, form a plurality of mesh-like interconnected structures on the display substrate for transmitting the second power signal. This can further reduce the resistance of the second power line and decrease the voltage drop of the second power signal.

[0421] (12) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer covering the pattern of the third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG17.

[0422] In an exemplary embodiment, the plurality of vias in each repeating unit of the display substrate may include: ninety-first via V91 to ninety-fourth via V94.

[0423] In an exemplary embodiment, the orthogonal projection of the ninety-first via V91 onto the silicon substrate may be located within the range of the orthogonal projection of the fifty-first connecting electrode 151 onto the silicon substrate. The surface of the fifth insulating layer within the ninety-first via V91 is configured to allow the subsequently formed sixty-first connecting electrode to be connected to the fifty-first connecting electrode 151 through the via.

[0424] In an exemplary embodiment, the orthogonal projection of the 92nd via V92 onto the silicon substrate may be located within the range of the orthogonal projection of the 52nd connection electrode 152 onto the silicon substrate. The surface of the fifth insulating layer within the 92nd via V92 is configured to allow the subsequently formed 62nd connection electrode to be connected to the 52nd connection electrode 152 through the via.

[0425] In an exemplary embodiment, the orthogonal projection of the 93rd via V93 onto the silicon substrate may be located within the range of the orthogonal projection of the 53rd connection electrode 153 onto the silicon substrate. The surface of the fifth insulating layer within the 93rd via V93 is configured to allow the subsequently formed 63rd connection electrode to be connected to the 53rd connection electrode 153 through the via.

[0426] In an exemplary embodiment, the orthogonal projection of the 94th via V94 onto the silicon substrate may be located within the range of the orthogonal projection of the 54th connection electrode 154 onto the silicon substrate. The surface of the fifth insulating layer within the 94th via V94 is configured to allow the subsequently formed 64th connection electrode to be connected to the 54th connection electrode 154 through the via.

[0427] (13) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming a fourth conductive layer pattern on a fifth insulating layer, as shown in Figures 18A and 18B, where Figure 18B is a schematic diagram of the fourth conductive layer in Figure 18A. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth metal (Metal4) layer.

[0428] In an exemplary embodiment, the fourth conductive layer pattern in each repeating unit of the display substrate may include at least: the thirteenth electrode 13 of the twelfth capacitor, the twenty-third electrode 23 of the twenty-second capacitor, and the sixty-first connecting electrode 161 to the sixty-fourth connecting electrode 164.

[0429] In an exemplary embodiment, the thirteenth electrode plate 13 and the twenty-third electrode plate 23 can be shaped as a whole-face structure disposed in the repeating unit, forming an interconnected integral structure. The thirteenth electrode plate 13 can serve as the lower electrode plate of the twelfth capacitor in the first sub-pixel, and the twenty-third electrode plate 23 can serve as the lower electrode plate of the twenty-second capacitor in the second sub-pixel.

[0430] In an exemplary embodiment, in at least one cell row, a plurality of thirteenth electrode plates 13 and a plurality of twenty-third electrode plates 23 may be an integral structure interconnected with each other. In at least one cell column, a plurality of thirteenth electrode plates 13 and a plurality of twenty-third electrode plates 23 may be an integral structure interconnected with each other.

[0431] In an exemplary embodiment, in at least one repeating unit, a first opening K1 may be provided on the thirteenth electrode plate 13 and the twenty-third electrode plate 23 of the whole structure. The shape of the first opening K1 may be polygonal, and the first opening K1 is configured to accommodate the sixty-first connecting electrode 161 to the sixty-fourth connecting electrode 164.

[0432] In an exemplary embodiment, the sixty-first connecting electrode 161 can be block-shaped (e.g., rectangular), and can be connected to the fifty-first connecting electrode 151 via the ninety-first via V91. Since the fifty-first connecting electrode 151 has the potential of the first node S1 in the first sub-pixel, the sixty-first connecting electrode 161 also has the potential of the first node S1 in the first sub-pixel.

[0433] In an exemplary embodiment, the shape of the sixty-second connecting electrode 162 may be block-shaped (such as rectangular), and the sixty-second connecting electrode 162 may be connected to the fifty-second connecting electrode 152 through the ninety-second via V92.

[0434] In an exemplary embodiment, the sixty-third connecting electrode 163 can be block-shaped (e.g., rectangular), and can be connected to the fifty-third connecting electrode 153 via the ninety-third via V93. Since the fifty-third connecting electrode 153 has the potential of the first node S1 in the second sub-pixel, the sixty-third connecting electrode 163 also has the potential of the first node S1 in the second sub-pixel.

[0435] In an exemplary embodiment, the sixty-fourth connecting electrode 164 may be block-shaped (e.g., rectangular), and the sixty-fourth connecting electrode 164 may be connected to the fifty-fourth connecting electrode 154 through the ninety-fourth via V94.

[0436] (14) Forming a sixth insulating layer and a fifth conductive layer pattern. In an exemplary embodiment, forming the sixth insulating layer and the fifth conductive layer pattern may include: sequentially depositing a sixth insulating film and a fifth conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern, and a fifth conductive layer pattern disposed on the sixth insulating layer, as shown in Figures 19A and 19B, where Figure 19B is a schematic diagram of the fifth conductive layer in Figure 19A. In an exemplary embodiment, the fifth conductive layer may be referred to as the top electrode (CTOP) layer.

[0437] In an exemplary embodiment, the fifth conductive layer pattern in each repeating unit of the display substrate may include at least the fourteenth electrode 14 of the twelfth capacitor and the twenty-fourth electrode 24 of the twenty-second capacitor.

[0438] In an exemplary embodiment, the fourteenth electrode plate 14 can be rectangular in shape, and the corners of the rectangle can be chamfered, protruded, or grooved. The orthographic projection of the fourteenth electrode plate 14 on the silicon substrate at least partially overlaps with the orthographic projection of the thirteenth electrode plate 13 on the silicon substrate. The fourteenth electrode plate 14 can serve as the upper electrode plate of the twelfth capacitor in the first sub-pixel, and the thirteenth electrode plate 13 and the fourteenth electrode plate 14 form the twelfth capacitor in the first sub-pixel.

[0439] In an exemplary embodiment, the shape of the 24th electrode plate 24 can be rectangular, and the corners of the rectangle can be chamfered, raised, or grooved. The orthographic projection of the 24th electrode plate 24 on the silicon substrate at least partially overlaps with the orthographic projection of the 23rd electrode plate 23 on the silicon substrate. The 24th electrode plate 24 can serve as the lower electrode plate of the 22nd capacitor in the second sub-pixel, and the 23rd electrode plate 23 and the 24th electrode plate 24 form the 22nd capacitor in the second sub-pixel.

[0440] (15) Forming a seventh insulating layer pattern. In an exemplary embodiment, forming a seventh insulating layer pattern may include: depositing a seventh insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the seventh insulating film by a patterning process to form a seventh insulating layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the seventh insulating layer, as shown in FIG20.

[0441] In an exemplary embodiment, the plurality of vias in each repeating unit of the display substrate may include: via 101 to via 107.

[0442] In an exemplary embodiment, the orthographic projection of the first 101 via V101 on the silicon substrate is within the range of the orthographic projection of the sixty-first connection electrode 161 on the silicon substrate. The sixth and seventh insulating layers within the first 101 via V101 are etched away, exposing the surface of the sixty-first connection electrode 161. The first 101 via V101 is configured to allow the subsequently formed seventy-first connection electrode to be connected to the sixty-first connection electrode 161 through the via.

[0443] In an exemplary embodiment, the orthographic projection of the first 102 via V102 on the silicon substrate is within the range of the orthographic projection of the sixty-second connection electrode 162 on the silicon substrate. The sixth and seventh insulating layers within the first 102 via V102 are etched away, exposing the surface of the sixty-second connection electrode 162. The first 102 via V102 is configured to allow the subsequently formed seventy-second connection electrode to be connected to the sixty-second connection electrode 162 through the via.

[0444] In an exemplary embodiment, the orthographic projection of the first 103 via V103 on the silicon substrate is within the range of the orthographic projection of the sixty-third connection electrode 163 on the silicon substrate. The sixth and seventh insulating layers within the first 103 via V103 are etched away, exposing the surface of the sixty-third connection electrode 163. The first 103 via V103 is configured to allow the subsequently formed seventy-third connection electrode to be connected to the sixty-third connection electrode 163 through the via.

[0445] In an exemplary embodiment, the orthographic projection of the first 104 via V104 on the silicon substrate is within the range of the orthographic projection of the sixty-fourth connection electrode 164 on the silicon substrate. The sixth and seventh insulating layers within the first 104 via V104 are etched away, exposing the surface of the sixty-fourth connection electrode 164. The first 104 via V104 is configured to allow the subsequently formed seventy-fourth connection electrode to be connected to the sixty-fourth connection electrode 164 through the via.

[0446] In an exemplary embodiment, the orthographic projection of the first 105 via V105 onto the silicon substrate is within the range of the orthographic projection of the fourteenth electrode 14 onto the silicon substrate. The seventh insulating layer within the first 105 via V105 is etched away, exposing the surface of the fourteenth electrode 14. The first 105 via V105 is configured to allow the subsequently formed seventy-first connection electrode to be connected to the fourteenth electrode 14 through the via.

[0447] In an exemplary embodiment, the orthographic projection of the first 106 via V106 onto the silicon substrate is within the range of the orthographic projection of the 24th electrode 24 onto the silicon substrate. The seventh insulating layer within the first 106 via V106 is etched away, exposing the surface of the 24th electrode 24. The first 106 via V106 is configured to allow the subsequently formed 73rd connection electrode to be connected to the 24th electrode 24 through the via.

[0448] In an exemplary embodiment, the orthographic projection of the first 107 via V107 onto the silicon substrate is within the range of the orthographic projection of the thirteenth electrode plate 13 onto the silicon substrate. The sixth and seventh insulating layers within the first 107 via V107 are etched away, exposing the surface of the thirteenth electrode plate 13. The first 107 via V107 is configured to allow subsequently formed metal interconnects to be connected to the thirteenth electrode plate 13 through the via.

[0449] (16) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the sixth conductive thin film using a patterning process, and forming a sixth conductive layer pattern on a seventh insulating layer, as shown in Figures 21A and 21B, where Figure 21B is a schematic diagram of the sixth conductive layer in Figure 21A. In an exemplary embodiment, the sixth conductive layer may be referred to as a second metal interconnect (TM2) layer.

[0450] In an exemplary embodiment, the sixth conductive layer pattern in each repeating unit of the display substrate may include at least: a metal connection line 70, a seventy-first connection electrode 171, a seventy-second connection electrode 172, a seventy-third connection electrode 173, and a seventy-fourth connection electrode 174.

[0451] In an exemplary embodiment, the shape of the metal connecting line 70 can be a full-surface structure provided in the repeating unit. The metal connecting line 70 of the full-surface structure can be provided with a second opening K2. The shape of the second opening K2 can be polygonal. The second opening K2 is configured to accommodate the seventy-first connecting electrode 171 to the seventy-fourth connecting electrode 174.

[0452] In an exemplary embodiment, the metal connecting wire 70 can be connected to the thirteenth electrode plate 13 through the first 107 via V107. Since the thirteenth electrode plate 13 and the second thirteenth electrode plate 23 are an integral structure that is interconnected, the thirteenth electrode plate 13 and the second thirteenth electrode plate 23 have the same potential.

[0453] In an exemplary embodiment, the metal connecting line 70 can extend to the non-display area and connect to the power lead that transmits the second power signal. Since the thirteenth plate 13 and the second thirteenth plate 23 are an integral structure that is interconnected, the thirteenth plate 13 and the second thirteenth plate 23 have the potential of the second power signal.

[0454] In an exemplary embodiment, the metal interconnect 70 with a full-surface structure can further reduce the voltage drop of the second power signal, further improve the uniformity of the second power signal in the display substrate, further improve display uniformity, and further improve display quality and display performance.

[0455] In an exemplary embodiment, the seventy-first connecting electrode 171 can be a strip extending along the first direction X. The first end of the seventy-first connecting electrode 171 is connected to the sixty-first connecting electrode 161 through a first 101 via V101, and the second end of the seventy-first connecting electrode 171 is connected to the fourteenth electrode plate 14 through a first 105 via V105. Since the sixty-first connecting electrode 161 is connected to the fifty-first connecting electrode 151 through a via, and is the first node S1 of the pixel driving circuit in the first sub-pixel, the connection between the fourteenth electrode plate 14 and the first node S1 in the first sub-pixel is realized. The fourteenth electrode plate 14 has the potential of the first node in the first sub-pixel.

[0456] In an exemplary embodiment, the shape of the seventy-second connecting electrode 172 may be a broken line extending along the first direction X. The first end of the seventy-second connecting electrode 172 is connected to the sixty-second connecting electrode 162 through the first hundred and second via V102. The second end of the seventy-second connecting electrode 172 is configured to connect the first anode in the subsequently formed first sub-pixel.

[0457] In an exemplary embodiment, the seventy-third connecting electrode 173 can be a strip extending along the first direction X. The first end of the seventy-third connecting electrode 173 is connected to the sixty-third connecting electrode 163 via the first 103 via V103, and the second end of the seventy-third connecting electrode 173 is connected to the twenty-fourth electrode plate 24 via the first 106 via V106. Since the sixty-third connecting electrode 163 is connected to the fifty-third connecting electrode 153 via a via, forming the first node S1 of the pixel driving circuit in the second sub-pixel, the twenty-fourth electrode plate 24 is connected to the first node S1 in the second sub-pixel, and the twenty-fourth electrode plate 24 has the potential of the first node in the second sub-pixel.

[0458] In an exemplary embodiment, the shape of the seventy-fourth connecting electrode 174 may be a zigzag line extending along the first direction X. The first end of the seventy-fourth connecting electrode 174 is connected to the sixty-fourth connecting electrode 164 through the first 104 via V104. The second end of the seventy-fourth connecting electrode 174 is configured to connect the second anode in the subsequently formed second sub-pixel.

[0459] In an exemplary embodiment, since the thirteenth plate 13 has the potential of the second power signal and the fourteenth plate 14 has the potential of the first node in the first sub-pixel, the thirteenth plate 13 and the fourteenth plate 14 form the twelfth capacitor in the first sub-pixel, and the eleventh capacitor and the twelfth capacitor in parallel form the first storage capacitor in the first sub-pixel.

[0460] In an exemplary embodiment, since the 23rd electrode plate 23 has the potential of the second power signal and the 24th electrode plate 24 has the potential of the first node in the second sub-pixel, the 23rd electrode plate 23 and the 24th electrode plate 24 form the 22nd capacitor in the second sub-pixel, and the 21st capacitor and the 22nd capacitor in parallel form the second storage capacitor in the second sub-pixel.

[0461] In an exemplary embodiment, the eleventh and twenty-first capacitors are MOS capacitors, and the twelfth and twenty-second capacitors are MIM capacitors. This disclosure, by using MOS and MIM capacitors connected in parallel to form a storage capacitor, not only achieves a larger capacitance value and, while meeting design requirements, allows for a more compact arrangement of the pixel driving circuit, thus improving the resolution of the display device, but also achieves lower leakage current, improving the driving performance of the pixel driving circuit.

[0462] (17) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming an eighth insulating layer pattern may include: depositing an eighth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the eighth insulating film by a patterning process to form an eighth insulating layer covering the pattern of the sixth conductive layer, wherein a plurality of vias are provided on the eighth insulating layer, as shown in FIG22.

[0463] In an exemplary embodiment, the eighth insulating layer pattern in each repeating unit of the display substrate may include at least a first anode via V110 and a second anode via V120.

[0464] In an exemplary embodiment, the orthographic projection of the first anode via V110 on the silicon substrate is within the range of the orthographic projection of the seventy-second connecting electrode 172 on the silicon substrate. The eighth insulating layer within the first anode via V110 is etched away, exposing the surface of the seventy-second connecting electrode 172. The first anode via V110 is configured to allow the first anode of the subsequently formed first sub-pixel to be connected to the seventy-second connecting electrode 172 through the via.

[0465] In an exemplary embodiment, the orthogonal projection of the second anode via V120 onto the silicon substrate is within the range of the orthogonal projection of the seventy-fourth connecting electrode 174 onto the silicon substrate. The eighth insulating layer within the second anode via V120 is etched away, exposing the surface of the seventy-fourth connecting electrode 174. The second anode via V120 is configured to allow the second anode of the subsequently formed second sub-pixel to be connected to the seventy-fourth connecting electrode 174 through the via.

[0466] Figure 23 is a schematic diagram of the structure of a storage capacitor according to an exemplary embodiment of the present disclosure. As shown in Figure 23, the pixel driving circuit in the first sub-pixel may include a first storage capacitor, which may include an eleventh capacitor and a twelfth capacitor in parallel. The pixel driving circuit in the second sub-pixel may include a second storage capacitor, which may include a twenty-first capacitor and a twenty-second capacitor in parallel. The eleventh and twenty-first capacitors are MOS capacitors, and the twelfth and twenty-second capacitors are MIM capacitors.

[0467] In an exemplary embodiment, the twelfth capacitor may include a stacked thirteenth plate 13 and a fourteenth plate 14. The thirteenth plate 13 may be disposed in the fourth conductive layer (Metal4), and the fourteenth plate 14 may be disposed in the fifth conductive layer (CTOP). The thirteenth plate 13 may be connected to a metal connection line 70 located in the sixth conductive layer (TM2). The thirteenth plate 13 has a potential of a second power signal. The fourteenth plate 14 may be connected to a sixty-first connection electrode 161 located in the fourth conductive layer via a seventy-first connection electrode 171 located in the sixth conductive layer (TM2). The thirteenth plate 13 has a potential of the first node S1 in the first sub-pixel. Therefore, the thirteenth plate 13 and the fourteenth plate 14 form the twelfth capacitor in the first sub-pixel.

[0468] In an exemplary embodiment, the twenty-second capacitor may include a stacked twenty-third electrode 23 and a twenty-fourth electrode 24. The twenty-third electrode 23 may be disposed in the fourth conductive layer (Metal4), and the twenty-fourth electrode 24 may be disposed in the fifth conductive layer (CTOP). The twenty-third electrode 23 may be connected to a metal connection line 70 located in the sixth conductive layer (TM2). The twenty-third electrode 23 has a potential of a second power signal. The twenty-fourth electrode 24 may be connected to a sixty-third connection electrode 163 located in the fourth conductive layer via a seventy-third connection electrode 173 located in the sixth conductive layer (TM2). The twenty-third electrode 23 has a potential of the first node S1 in the second sub-pixel. Therefore, the twenty-third electrode 23 and the twenty-fourth electrode 24 form the twenty-second capacitor in the second sub-pixel.

[0469] In an exemplary embodiment, since the twelfth and twentieth capacitors are parallel plate capacitors, and only one insulating layer is provided between the thirteenth plate 13 and the fourteenth plate 14, and only one insulating layer is provided between the twenty-third plate 23 and the twenty-fourth plate 24, the capacitance can be effectively guaranteed. Under the premise of meeting the design requirements, the arrangement of the pixel driving circuit can be made more compact, which helps to improve the resolution of the display device.

[0470] In an exemplary embodiment, the capacitance of the first capacitor and the second capacitor can be further increased by increasing the number of conductive layers or decreasing the thickness of the insulating layer, and this disclosure does not limit the scope of the invention.

[0471] In an exemplary embodiment, subsequent fabrication processes may include forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color filter structure layer, and a second encapsulation layer, etc., which will not be described in detail here.

[0472] Thus, the display substrate of this disclosure is formed. In an exemplary embodiment, the display substrate may include at least: a silicon substrate, a first insulating layer disposed on the silicon substrate, a gate conductive layer disposed on the side of the first insulating layer away from the silicon substrate, a second insulating layer disposed on the side of the gate conductive layer away from the silicon substrate, a first conductive layer (Metal1) disposed on the side of the second insulating layer away from the silicon substrate, a third insulating layer disposed on the side of the first conductive layer away from the silicon substrate, a second conductive layer (Metal2) disposed on the side of the third insulating layer away from the silicon substrate, a fourth insulating layer disposed on the side of the second conductive layer away from the silicon substrate, a third conductive layer (Metal3) disposed on the side of the fourth insulating layer away from the silicon substrate, a fifth insulating layer disposed on the side of the third conductive layer away from the silicon substrate, a fourth conductive layer (Metal4) disposed on the side of the fifth insulating layer away from the silicon substrate, a sixth insulating layer disposed on the side of the fourth conductive layer away from the silicon substrate, a fifth conductive layer (CTOP) disposed on the side of the sixth insulating layer away from the silicon substrate, a seventh insulating layer disposed on the side of the fifth conductive layer away from the silicon substrate, a sixth conductive layer (TM2) disposed on the side of the seventh insulating layer away from the silicon substrate, and an eighth insulating layer disposed on the side of the sixth conductive layer away from the silicon substrate.

[0473] In an exemplary embodiment, the silicon substrate may include at least an eleventh electrode and a twenty-first electrode, the gate conductive layer may include at least a twelfth electrode and a twenty-second electrode, the fourth conductive layer may include at least a thirteenth electrode and a twenty-third electrode, and the fifth conductive layer may include at least a fourteenth electrode and a twenty-fourth electrode.

[0474] In an exemplary embodiment, the first to eighth insulating layers can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc., and can be a single-layer structure or a multi-layer composite structure. The first to sixth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), etc., or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of Mo, Cu, and Mo layers, etc. In an exemplary embodiment, the planar shape of the via can be rectangular, circular, or elliptical, etc., and the dimensions of multiple vias can be the same or different, which is not limited herein.

[0475] An exemplary embodiment of this disclosure provides a display substrate in which, by setting the first scan signal line and the second scan signal line controlling the transmission gate as complementary traces of equal length, the high-level signals and low-level signals transmitted by the first scan signal line and the second scan signal line can have the same transmission distance and the same transmission delay, ensuring signal synchronization. This also enables the N-type transistor and P-type transistor in the transmission gate to be simultaneously turned off or simultaneously turned on, improving the driving performance of the pixel driving circuit.

[0476] This disclosure sets the aspect ratio of the eleventh P-type transistor in the first sub-pixel to be greater than that of the eleventh N-type transistor, and the aspect ratio of the twenty-first P-type transistor in the second sub-pixel to be greater than that of the twenty-first N-type transistor. This makes the transmission gates in the first and second sub-pixels transmit positive and negative voltages in a basically consistent manner, and allows the N-type transistors and P-type transistors in the transmission gates to be simultaneously turned off or simultaneously turned on, thereby improving the driving performance of the pixel driving circuit.

[0477] This disclosure effectively reduces the footprint of the pixel driving circuit by arranging transistors and signal lines in repeating units (including two sub-pixels) as the smallest unit, thus improving the resolution of the display device. Compared to arranging transistors and signal lines in units of a single sub-pixel, where each sub-pixel contains both N-type and P-type transistors (N-type transistors housed in P-wells and P-type transistors in N-wells), the manufacturing process requires maintaining a certain distance between these different wells. Therefore, sub-pixel-based layouts increase the footprint of the pixel driving circuit. This disclosure, by considering the placement of N-type and P-type transistors in two sub-pixels in a unified manner, allows for the grouping of transistors of the same type, avoiding their discrete distribution and thus effectively reducing the footprint of the pixel driving circuit.

[0478] This disclosure, by setting a second P-type transistor in the pixel driving circuit, with the second P-type transistor positioned between the second N-type transistor and the light-emitting device, can effectively reduce the latch-up of the second N-type transistor, effectively avoid defects in the entire display area caused by a short circuit in the light-emitting device (EL), and improve product reliability.

[0479] This disclosure, by setting a shielding block connected to the power supply line, provides a shielding block 34-1 with a constant potential, which can effectively shield the mutual influence between the eleventh N-type transistor and the twelfth P-type transistor, improve the working stability of the pixel driving circuit, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve display quality and display performance.

[0480] This disclosure, by setting a first compensation electrode and a second compensation electrode, ensures that the effect of the first scanning signal on the capacitor plates and multiple transistors in the first and second sub-pixels is substantially the same. This guarantees the uniformity and symmetry of the pixel driving circuits in the first and second sub-pixels, enabling not only uniform design of the process and coupling capacitors but also uniform design of the current distribution. This effectively improves display stability and uniformity, and significantly enhances display effect and quality.

[0481] This disclosure improves the operational stability of the pixel driving circuit by placing a first power line between the first data signal line and the second data signal line. The first power line, which has a constant potential, can effectively shield the mutual influence between the two data signal lines.

[0482] This disclosure, by setting a larger distance between the first data signal line and the twelfth N-type transistor, and a larger distance between the second data signal line and the twentieth twelfth N-type transistor, can not only effectively reduce crosstalk between the data signal line and the driving transistor, but also effectively reduce parasitic capacitance between the data signal line and the driving transistor, thereby improving the working stability of the pixel driving circuit.

[0483] This disclosure uses a parallel combination of MOS capacitors and MIM capacitors to form a storage capacitor, which not only achieves a larger capacitance value and makes the pixel driving circuit layout more compact while meeting design requirements, thus helping to improve the resolution of the display device, but also achieves less leakage current and improves the driving performance of the pixel driving circuit.

[0484] This disclosure, by forming a mesh-like interconnected structure for transmitting the first power signal and the second power signal, can not only effectively reduce the resistance of the power lines and decrease the voltage drop of the power signals, but also effectively improve the uniformity of the power signals in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0485] This disclosure improves tolerance to process fluctuations and particle defects by adjusting the number of metal layers, trace positions, and trace spacing, reducing the proportion of line and point defects and improving product yield. Through the layout of the pixel driving circuit, the resistance and voltage drop of the power supply traces are significantly reduced, significantly improving circuit performance and enhancing display brightness uniformity. By adding a shielding structure, crosstalk to key nodes of the pixel driving circuit is significantly reduced, lowering signal crosstalk and improving display stability. This disclosure fully utilizes the layout space, optimizing the arrangement of N-type and P-type transistors, effectively reducing the area occupied by the pixel driving circuit. The display resolution can be greater than or equal to 3135 PPI (sub-pixel size ≤ 8.1 μm), resulting in better display stability and smoothness. It effectively reduces dizziness in VR applications and the screen-door effect in AR applications, effectively increasing immersion and improving the user experience.

[0486] The fabrication process disclosed herein is based on a 0.11μm integrated circuit process, which is highly compatible with existing fabrication processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0487] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as Micro OLED microdisplays, OLED displays, quantum dot displays (QLED), light-emitting diode microdisplays (Micro LED or Mini LED) or quantum dot light-emitting diode microdisplays (QDLED), etc., and this disclosure does not limit them.

[0488] In exemplary embodiments, the pixel driving circuit of the display substrate disclosed herein can be applied to product types including but not limited to integrated silicon-based, glass-based, printed circuit board (PCB)-based substrate materials, amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), low-temperature polycrystalline oxide (LTPO), oxide semiconductor materials represented by indium gallium zinc oxide (IGZO), and devices such as thin-film transistors (TFTs), metal-oxide semiconductors (MOS), and diodes with structures such as back channel etching structure (BCE), etch stop layer structure (ESL), top gate structure, and dual gate structure.

[0489] The structure of the display device and its fabrication process in the exemplary embodiments disclosed herein are merely illustrative examples. The corresponding structure and the patterning process may be modified or increased or decreased according to actual circumstances. This disclosure does not limit the scope of the invention.

[0490] This exemplary embodiment also provides a display device, including the aforementioned display substrate. The display device of this disclosure can be used in virtual reality devices, augmented reality devices, extended reality devices, mixed reality devices, sights, and rangefinders, and can also be used in, but is not limited to, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or any product or component with display functionality.

[0491] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of repeating units, each repeating unit including a first sub-pixel and a second sub-pixel, both the first and second sub-pixels including a pixel driving circuit; the pixel driving circuit in the first sub-pixel includes at least an eleventh N-type transistor and an eleventh P-type transistor, a twelfth N-type transistor, a thirteenth N-type transistor, and a twelfth P-type transistor forming transmission gates; the pixel driving circuit in the second sub-pixel includes at least a twenty-first N-type transistor and a twenty-first P-type transistor, a twenty-second N-type transistor, a twenty-third N-type transistor, and a twenty-second P-type transistor forming transmission gates; the gate electrodes of the eleventh N-type transistor and the twenty-first N-type transistor are connected to a first scan signal line; the gate electrodes of the eleventh P-type transistor and the twenty-first P-type transistor are connected to a second scan signal line; the first terminals of the eleventh N-type transistor and the eleventh P-type transistor are interconnected and connected to a first data signal line; the second terminals of the eleventh N-type transistor and the eleventh P-type transistor are interconnected. The second electrodes are interconnected and connected to the gate electrode of the twelfth N-type transistor. The second electrode of the twelfth N-type transistor is connected to the second electrode of the thirteenth N-type transistor and the first electrode of the twelfth P-type transistor. The first electrodes of the twentieth N-type transistor and the twentieth P-type transistor are interconnected and connected to the second data signal line. The second electrodes of the twentieth N-type transistor and the twentieth P-type transistor are interconnected and connected to the gate electrode of the twentieth N-type transistor. The second electrode of the twentieth N-type transistor is connected to the second electrode of the twentieth N-type transistor and the first electrode of the twentieth P-type transistor. The first scan signal line and the second scan signal line are zigzag lines whose main body extends along the first direction. The first scan signal line is disposed on one side of the second scan signal line in the second direction. The first direction and the second direction intersect. In at least one repeating unit, the ratio of the extension length of the first scan signal line to the extension length of the second scan signal line is 0.95 to 1.

05. 2.The display substrate of claim 1, wherein, In at least one repeating unit, both the first scan signal line and the second scan signal line include a plurality of horizontal sub-lines and a plurality of vertical sub-lines. The horizontal sub-lines are straight lines extending along the first direction, and the vertical sub-lines are straight lines extending along the second direction. The number of horizontal sub-lines in the first scan signal line is equal to the number of horizontal sub-lines in the second scan signal line, and the number of vertical sub-lines in the first scan signal line is equal to the number of vertical sub-lines in the second scan signal line. 3.The display substrate of claim 1, wherein, The first electrode of the twelfth N-type transistor and the first electrode of the second twelfth N-type transistor are both connected to the first power line. The first data signal line, the second data signal line and the first power line are in the shape of a straight line or a broken line whose main body extends along the second direction. In at least one repeating unit, the first power line is disposed between the first data signal line and the second data signal line. 4.The display substrate of claim 3, wherein, The gate electrode of the thirteenth N-type transistor and the gate electrode of the twenty-third N-type transistor are connected to the third scan signal line; at least one repeating unit further includes a forty-fourth connection electrode connected to the third scan signal line; in the first direction, the forty-fourth connection electrode is disposed between the first data signal line and the first power supply line. 5.The display substrate of claim 4, wherein, At least one repeating unit further includes a thirty-first connecting electrode having the potential of a first node in the first sub-pixel, the thirty-first connecting electrode being disposed between the first power line and the forty-fourth connecting electrode; a shielding strip and a shielding frame are connected to the forty-fourth connecting electrode, the shielding strip being disposed on one side of the third-first connecting electrode in the second direction, and the shielding frame being disposed on one side of the third-first connecting electrode in the second direction, the forty-fourth connecting electrode, the shielding strip, and the shielding frame forming a structure that semi-encloses the thirty-first connecting electrode. 6.The display substrate of claim 1, wherein, In at least one repeating unit, the pixel driving circuit of the first sub-pixel further includes a first storage capacitor, the first storage capacitor including at least an eleventh capacitor and a twelfth capacitor connected in parallel; the pixel driving circuit of the second sub-pixel further includes a second storage capacitor, the second storage capacitor including at least a twenty-first capacitor and a twenty-second capacitor connected in parallel; in at least one repeating unit, the eleventh capacitor and the twenty-first capacitor are disposed in the middle region of the repeating unit in the first direction, the eleventh capacitor and the twenty-first capacitor are arranged sequentially along the second direction, and the twenty-first capacitor is disposed on one side of the eleventh capacitor in the second direction; the twelfth N-type transistor and the twenty-twelfth N-type transistor are disposed in the edge regions on both sides of the eleventh capacitor and the twenty-first P-type transistor in the first direction, the eleventh N-type transistor and the eleventh P-type transistor are disposed between the eleventh capacitor and the twelfth N-type transistor, and the twenty-first N-type transistor and the twenty-first P-type transistor are disposed between the twenty-first capacitor and the twenty-first N-type transistor in the first sub-pixel. 7.The display substrate of claim 6, wherein, In at least one repeating unit, the eleventh N-type transistor is disposed on the side of the twelfth N-type transistor near the eleventh capacitor, and the eleventh P-type transistor is disposed on the side of the eleventh N-type transistor near the eleventh capacitor; the twenty-first N-type transistor is disposed on the side of the twelfth N-type transistor near the twenty-first capacitor, and the twenty-first P-type transistor is disposed on the side of the twenty-first N-type transistor near the twenty-first capacitor; the twenty-first N-type transistor is disposed on the side of the eleventh N-type transistor in the second direction, and the twenty-first P-type transistor is disposed on the side of the eleventh P-type transistor in the second direction. 8.The display substrate of claim 6, wherein, In at least one repeating unit, the twelfth P-type transistor is disposed between the twelfth N-type transistor and the eleventh N-type transistor, the thirteenth N-type transistor is disposed between the twelfth N-type transistor and the eleventh N-type transistor, the twelfth P-type transistor is disposed between the twelfth N-type transistor and the eleventh capacitor, the thirteenth N-type transistor is disposed on one side of the twelfth P-type transistor in the second direction, and the thirteenth N-type transistor is disposed on one side of the twelfth P-type transistor in the second direction. 9.The display substrate of claim 6, wherein, The eleventh capacitor includes an eleventh electrode and a twelfth electrode stacked together, wherein the orthographic projection of the twelfth electrode on the display substrate plane at least partially overlaps with the orthographic projection of the eleventh electrode on the display substrate plane; the second eleventh capacitor includes a twenty-first electrode and a twenty-second electrode stacked together, wherein the orthographic projection of the twenty-second electrode on the display substrate plane at least partially overlaps with the orthographic projection of the twenty-first electrode on the display substrate plane. The orthographic projection of the first scanning signal line on the display substrate plane at least partially overlaps with the orthographic projections of the gate electrode of the 21st N-type transistor, the gate electrode of the 21st P-type transistor, and the 22nd electrode plate on the display substrate plane; At least one repeating unit further includes a first compensation electrode, which is connected to the first scan signal line. The orthographic projection of the first compensation electrode on the display substrate plane at least partially overlaps with the orthographic projections of the gate electrode of the eleventh N-type transistor, the gate electrode of the eleventh P-type transistor, and the twelfth electrode plate on the display substrate plane. 10.The display substrate of claim 6, wherein, The eleventh capacitor includes an eleventh and a twelfth electrode stacked together, and the orthographic projection of the twelfth electrode on the display substrate plane at least partially overlaps with the orthographic projection of the eleventh electrode on the display substrate plane; the second eleventh capacitor includes a twenty-first and a twenty-second electrode stacked together, and the orthographic projection of the twenty-second electrode on the display substrate plane at least partially overlaps with the orthographic projection of the twenty-first electrode on the display substrate plane; the orthographic projection of the second scan signal line on the display substrate plane at least partially overlaps with the gate electrode of the eleventh N-type transistor, the gate electrode of the eleventh P-type transistor, and the orthographic projection of the twelfth electrode on the display substrate plane; At least one repeating unit further includes a second compensation electrode, which is connected to the second scan signal line. The orthographic projection of the second compensation electrode on the display substrate plane at least partially overlaps with the orthographic projections of the gate electrode of the 21st N-type transistor, the gate electrode of the 21st P-type transistor, and the 22nd electrode plate on the display substrate plane. 11.The display substrate of claim 10, wherein, A capacitor compensation block is connected to the second scanning signal line, and the orthographic projection of the capacitor compensation block on the display substrate plane at least partially overlaps with the orthographic projection of the twelfth electrode plate on the display substrate plane. 12.The display substrate of claim 1, wherein, The twelfth N-type transistor includes at least a twelfth N-type active region, the thirteenth N-type transistor includes at least a thirteenth N-type active region, the twelfth P-type transistor includes at least a twelfth P-type active region, the twelfth N-type transistor includes at least a twenty-twelfth N-type active region, the twelfth N-type transistor includes at least a twenty-thirteenth N-type active region, and the twelfth P-type transistor includes at least a twenty-twelfth P-type active region; a first spacing exists between the twelfth N-type active region and the twelfth P-type active region, or a first spacing exists between the twelfth N-type active region and the twelfth N-type active region; a second spacing exists between the twelfth N-type active region and the thirteenth N-type active region, or a second spacing exists between the twelfth N-type active region and the twelfth N-type active region; the first spacing is greater than the second spacing, and the first spacing and the second spacing are dimensions in the first direction. 13.The display substrate of claim 1, wherein, The eleventh-N type transistor includes at least an eleventh-N type active region, the thirteenth-N type transistor includes at least a thirteenth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, and the twelfth-P type transistor includes at least a twelfth-P type active region; there is a third spacing between the eleventh-N type active region and the twelfth-P type active region, and there is a fourth spacing between the thirteenth-N type active region and the twenty-first-N type active region, the third spacing being greater than the fourth spacing, and the third spacing and the fourth spacing being dimensions in the first direction. 14.The display substrate of claim 1, wherein, The eleventh-N type transistor includes at least an eleventh-N type active region, the eleventh-P type transistor includes at least an eleventh-P type active region, the twelfth-N type transistor includes at least a twelfth-N type active region, the thirteenth-N type transistor includes at least a thirteenth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, the twenty-second-N type transistor includes at least a twenty-second-N type active region, and the twenty-third-N type transistor includes at least a twenty-third-N type active region; there is a second spacing between the twelfth-N type active region and the thirteenth-N type active region, or there is a second spacing between the twenty-second-N type active region and the twenty-third-N type active region; there is a fourth spacing between the thirteenth-N type active region and the twenty-first-N type active region, and a fifth spacing between the eleventh-N type active region and the eleventh-P type active region, the fifth spacing being greater than the second spacing and the fifth spacing being greater than the fourth spacing, wherein the second spacing, the fourth spacing, and the fifth spacing are dimensions in the first direction. 15.The display substrate of claim 1, wherein, The twelfth N-type transistor includes at least a twelfth N-type active region, the thirteenth N-type transistor includes at least a thirteenth N-type active region, the twenty-first N-type transistor includes at least a twenty-first N-type active region, the twenty-twelfth N-type transistor includes at least a twenty-second N-type active region, the twenty-third N-type transistor includes at least a twenty-third N-type active region, and the twenty-first P-type transistor includes at least a twenty-first P-type active region; a second spacing exists between the twelfth N-type active region and the thirteenth N-type active region, or a second spacing exists between the twelfth N-type active region and the twenty-third N-type active region; a fourth spacing exists between the thirteenth N-type active region and the twenty-first N-type active region, and a sixth spacing exists between the twenty-first N-type active region and the twenty-first P-type active region, the sixth spacing being greater than the second spacing and the sixth spacing being greater than the fourth spacing, wherein the second spacing, the fourth spacing, and the sixth spacing are dimensions in the first direction. 16.The display substrate of claim 1, wherein, The eleventh N-type transistor includes at least an eleventh N-type active region, the thirteenth N-type transistor includes at least a thirteenth N-type active region, the twenty-first N-type transistor includes at least a twenty-first N-type active region, the eleventh P-type transistor includes at least an eleventh P-type active region, the twelfth P-type transistor includes at least a twelfth P-type active region, and the twenty-first P-type transistor includes at least a twenty-first P-type active region. There is a seventh spacing between the twelfth P-type active region and the thirteenth N-type active region, an eighth spacing between the eleventh N-type active region and the twenty-first N-type active region, and a ninth spacing between the eleventh P-type active region and the twenty-first P-type active region. The seventh spacing is greater than the eighth spacing, and the seventh spacing is greater than the ninth spacing. The seventh spacing, the eighth spacing, and the ninth spacing are dimensions in the second direction. 17.The display substrate of claim 1, wherein, The eleventh-N type transistor includes at least an eleventh-N type active region, the twelfth-N type transistor includes at least a twelfth-N type active region, the twenty-first-N type transistor includes at least a twenty-first-N type active region, the twenty-second-N type transistor includes at least a twenty-second-N type active region, the eleventh-P type transistor includes at least an eleventh-P type active region, the twelfth-P type transistor includes at least a twelfth-P type active region, the twenty-first-P type transistor includes at least a twenty-first-P type active region, and the twenty-second-P type transistor includes at least a twenty-second-P type active region; the active length of the eleventh-P type active region 111P is less than the active length of the eleventh-N type active region 111N, the active length of the twelfth-P type active region is less than the active length of the twelfth-N type active region, the active length of the twelfth-P type active region is less than the active length of the twelfth-N type active region, and the active length of the twelfth-P type active region is less than the active length of the twelfth-N type active region. 18.The display substrate of claim 1, wherein, The second electrodes of the eleventh N-type transistor and the eleventh P-type transistor are interconnected by a first connection electrode having the potential of the first node in the first sub-pixel; at least one repeating unit further includes a power connection line with a potential of a second power signal and a shielding block, the power connection line being a straight line or a broken line extending along the first direction, the shielding block being a strip extending along the second direction and connected to the power connection line; the shielding block is disposed on one side of the first connection electrode in the opposite direction of the first direction, the power connection line is disposed on one side of the first connection electrode in the second direction, and the power connection line and the shielding block form a structure that semi-encloses the first connection electrode.

19. The display substrate of claim 1, wherein, At least one repeating unit further includes a twenty-first connecting electrode having a potential of a first node in the first sub-pixel, a power connection line having a potential of a second power signal, and a shielding block. The twenty-first connecting electrode is connected to the gate electrode of the twelfth N-type transistor. The shape of the power connection line is a straight line or a broken line extending along the first direction. The shape of the shielding block is a strip extending along the second direction and is connected to the power connection line. The shielding block is disposed on one side of the twenty-first connecting electrode in the first direction, and the power connection line is disposed on one side of the twenty-first connecting electrode in the second direction. The power connection line and the shielding block form a structure that semi-encloses the twenty-first connecting electrode. 20.The display substrate of claim 1, wherein, The second electrode of the 21st N-type transistor and the second electrode of the 21st P-type transistor are interconnected by an 11th connection electrode having the potential of the first node in the second sub-pixel; at least one repeating unit further includes a 25th connection electrode having the potential of a second power signal and an electrode compensation block, the 25th connection electrode being in the shape of a straight line or a broken line extending along the first direction, the electrode compensation block being in the shape of a block and connected to the 25th connection electrode; the electrode compensation block is disposed on one side of the 11th connection electrode in the first direction, the 25th connection electrode is disposed on one side of the 11th connection electrode in the second direction, and the 25th connection electrode and the electrode compensation block form a structure that semi-encloses the 11th connection electrode. 21.The display substrate of claim 1, wherein, At least one repeating unit further includes a twenty-third connecting electrode having a potential of the first node in the second sub-pixel, and a ninth connecting electrode, a twenty-fifth connecting electrode, and an electrode connecting strip having a potential of the second power signal. The twenty-third connecting electrode is connected to the gate electrode of the twenty-second N-type transistor. The electrode connecting strip is disposed on one side of the twenty-third connecting electrode in the opposite direction to the first direction. The ninth connecting electrode and the twenty-fifth connecting electrode are respectively disposed on both sides of the twenty-third connecting electrode in the second direction. The ninth connecting electrode is connected to the twenty-fifth connecting electrode through the electrode connecting strip. The ninth connecting electrode, the twenty-fifth connecting electrode, and the electrode connecting strip form a structure that semi-encloses the twenty-third connecting electrode. 22.The display substrate of claim 1, wherein, At least one repeating unit further includes a thirty-fifth connecting electrode having the potential of the first node in the second sub-pixel, a second power line, and a third vertical power line. The second power line and the third vertical power line are in the shape of a straight line or a broken line extending along the second direction. The third vertical power line is disposed on the side opposite to the first direction of the second power line and is connected to the second power line through a plurality of fifth power connecting blocks. The thirty-fifth connecting electrode is disposed within the annular structure formed by the second power line, the third vertical power line, and the fifth power line.

23. A display device comprising a display substrate as described in any one of claims 1 to 22.

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