Pixel circuit and display apparatus

Abstract

A pixel circuit and a display apparatus. In the pixel circuit, a data writing sub-circuit is configured to transmit, in a data writing phase, a data signal received at the data writing sub-circuit to a first node in response to a first scan signal received at a first scan signal terminal; a first light-emitting sub-circuit is configured to transmit, in a light emission phase, a first voltage signal received at a first voltage signal terminal to a second node in response to a first light emission signal received at a first light emission signal terminal; a first storage sub-circuit is coupled to a first node and a fifth node; the fifth node is coupled to a first initialization signal terminal; and a second storage sub-circuit is coupled to the fifth node and a third node. In a first transition phase, the first initialization signal terminal receives a first initialization signal and transmits same to the fifth node; and the first transition phase is between the data writing phase and the light emission phase.

Description

Pixel circuits and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and display device. Background Technology

[0002] With the development of display technology, display devices (such as mobile phones, laptops, or tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) display devices have received widespread attention due to their advantages such as active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thin design. Summary of the Invention

[0003] On one hand, a pixel circuit is provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting sub-circuit, a second light-emitting sub-circuit, a first storage sub-circuit, and a second storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node; the driving sub-circuit is configured to generate a driving current based on the voltage of the first node and the voltage of the third node; the data writing sub-circuit is coupled to the first node, a first scan signal terminal, and a data signal terminal; the data writing sub-circuit is configured to, during the data writing phase, in response to a first scan signal received at the first scan signal terminal, transmit a data signal received at the data writing sub-circuit to the first node; the first light-emitting sub-circuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal, and the second node; the first light-emitting sub-circuit is configured to, during the light-emitting phase, in response to a first light-emitting signal received at the first light-emitting signal terminal, transmit the first voltage signal... The first voltage signal received at the signal terminal is transmitted to the second node; the second light-emitting sub-circuit is coupled to the third node, the second light-emitting signal terminal, and the fourth node; the second light-emitting sub-circuit is configured to, in the light-emitting phase, in response to the second light-emitting signal received at the second light-emitting signal terminal, transmit the driving current at the third node to the fourth node; the first storage sub-circuit is coupled to the first node and the fifth node; the fifth node is coupled to the first initialization signal terminal; the second storage sub-circuit is coupled to the fifth node and the third node; wherein, in the first transition phase, the first initialization signal terminal receives the first initialization signal transmitted to the fifth node, and the first transition phase is located between the data writing phase and the light-emitting phase.

[0004] In some embodiments, the pixel circuit further includes a first reset sub-circuit. The first reset sub-circuit is connected to the first initialization signal terminal, the first reset signal terminal, and the fourth node; the first reset sub-circuit is configured to, during the first transition phase, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fifth node.

[0005] In some embodiments, the first reset sub-circuit includes a first transistor, the first terminal of the first transistor is connected to the first initialization signal terminal, the second terminal is connected to the fourth node, and the control terminal is connected to the first reset signal terminal.

[0006] In some embodiments, the first reset sub-circuit is further configured to, in a first target phase, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fourth node; the first target phase includes at least a partial reset phase, a compensation phase, and a data writing phase; the pixel circuit further includes a second reset sub-circuit, the second reset sub-circuit being connected to the first initialization signal terminal, the second reset signal terminal, and the first node; the second reset sub-circuit is configured to, in a second target phase, in response to a second reset signal received at the second reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the first node; the second target phase includes a reset phase and a compensation phase; wherein, within a display frame period, the duration of the first target phase is not equal to the duration of the second target phase.

[0007] In some embodiments, the reset phase includes a first reset phase and a second reset phase; the first reset sub-circuit is further configured to, in the second reset phase, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fifth node.

[0008] In some embodiments, the first initialization signal terminal and the fifth node are directly connected.

[0009] On the other hand, a pixel circuit is provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting sub-circuit, a second light-emitting sub-circuit, a first type of storage sub-circuit, and a third storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node; the driving sub-circuit is configured to generate a driving current based on the voltage of the first node and the voltage of the third node; the data writing sub-circuit is coupled to the first node, a first scan signal terminal, and a data signal terminal; the data writing sub-circuit is configured to, during the data writing phase, in response to a first scan signal received at the first scan signal terminal, transmit a data signal received at the data writing sub-circuit to the first node; the first light-emitting sub-circuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal, and the second node; the first light-emitting sub-circuit is configured to, during the light-emitting phase, In response to a first light-emitting signal received at the first light-emitting signal terminal, a first voltage signal received at the first voltage signal terminal is transmitted to the second node; the second light-emitting sub-circuit is coupled to the third node, the second light-emitting signal terminal, and the fourth node; the second light-emitting sub-circuit is configured to, during the light-emitting phase, in response to a second light-emitting signal received at the second light-emitting signal terminal, transmit a drive current at the third node to the fourth node; the first type of storage sub-circuit is coupled to the first node and the third node; the third storage sub-circuit is connected to a target signal terminal and a target node, the target node being at least one of the first node and the third node.

[0010] In some embodiments, the first type of storage sub-circuit includes a first storage sub-circuit and a second storage sub-circuit. The first storage sub-circuit is coupled to the first node and the fifth node. The second storage sub-circuit is coupled to the fifth node and the third node. The pixel circuit further includes a first reset sub-circuit and a second reset sub-circuit. The first reset sub-circuit is coupled to the first initialization signal terminal, the first reset signal terminal, and the fifth node. The first reset sub-circuit is further configured to, in a first target phase, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fifth node. The first target phase includes a partial reset phase, a compensation phase, and a data writing phase. The second reset sub-circuit is coupled to the first initialization signal terminal, the second reset signal terminal, and the first node. The second reset sub-circuit is configured to, in a second target phase, in response to a second reset signal received at the second reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the first node. The second target phase includes a reset phase and a compensation phase. Within a display frame period, the duration of the first target phase is equal to the duration of the second target phase.

[0011] In some embodiments, the pixel circuit further includes a third reset sub-circuit coupled to a second initialization signal terminal, a third reset signal terminal, and a fourth node; the third reset sub-circuit is configured to, in a third target phase, in response to a third reset signal received at the third reset signal terminal, transmit a second initialization signal received at the second initialization signal terminal to the fourth node; the third target phase includes at least a partial reset phase.

[0012] In some embodiments, the signal received at the target signal terminal is the same as the signal received at the first voltage signal terminal, the signal received at the first initialization signal terminal, or the signal received at the second initialization signal terminal.

[0013] In another aspect, a display device is provided. The display device includes a pixel circuit as described in any of the above embodiments.

[0014] In another aspect, a method for driving a pixel circuit is provided for driving a pixel circuit as described in any of the above embodiments.

[0015] In some embodiments, a display frame cycle includes a data writing phase, a first transition phase, and a light emission phase; in the data writing phase, the data writing sub-circuit, in response to a first scan signal received at a first scan signal terminal, transmits a data signal received at a data signal terminal to a first node; in the first transition phase, a first initialization signal received at a first initialization signal terminal is transmitted to the fifth node; in the light emission phase, the first light emission sub-circuit, in response to a first light emission signal received at the first light emission signal terminal, transmits a first voltage signal received at the first voltage signal terminal to the second node; the driving sub-circuit, under the control of the data signal at the first node and the voltage at the third node, generates a driving current and outputs the driving current to the third node; the second light emission sub-circuit, in response to a second light emission signal received at the second light emission signal terminal, transmits the driving current at the third node to the fourth node.

[0016] In some embodiments, during the first transition phase, the first reset sub-circuit responds to the first reset signal received at the first reset signal terminal by transmitting the first initialization signal received at the first initialization signal terminal to the fifth node.

[0017] In some embodiments, a display frame cycle further includes a compensation phase, which is located before the data writing phase; in the compensation phase, the first reset sub-circuit responds to a first reset signal received at the first reset signal terminal and transmits a first initialization signal received at the first initialization signal terminal to the fourth node; the first light-emitting sub-circuit responds to a first light-emitting signal received at the first light-emitting signal terminal and transmits a first voltage signal received at the first voltage signal terminal to the second node; under the control of the voltage at the first node, the driving sub-circuit transmits the voltage at the second node to the third node and charges the third node.

[0018] In some embodiments, a display frame cycle further includes a reset phase, which precedes the compensation phase. The reset phase includes a first reset phase and a second reset phase. In the first reset phase, a second reset sub-circuit, in response to a second reset signal received at the second reset signal terminal, transmits a first initialization signal received at the first initialization signal terminal to the first node. In the second reset phase, the second reset sub-circuit, in response to the second reset signal received at the second reset signal terminal, transmits a first initialization signal received at the first initialization signal terminal to the first node. The first reset sub-circuit, in response to the first reset signal received at the first reset signal terminal, transmits a first initialization signal received at the first initialization signal terminal to the first node. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0020] Figure 1 is a structural diagram of a display device according to some embodiments;

[0021] Figure 2 is another structural diagram of a display device according to some embodiments;

[0022] Figure 3 is a structural diagram of a display device including a display panel according to some embodiments;

[0023] Figure 4 is a structural diagram of a display panel including a substrate and pixel circuitry according to some embodiments;

[0024] Figure 5 is a cross-sectional view along section line AA in Figure 4;

[0025] Figure 6 is a structural diagram of a pixel circuit according to some embodiments;

[0026] Figure 7 is a structural diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

[0027] Figure 8 is another structural diagram of a pixel circuit according to some embodiments;

[0028] Figure 9 is another structural diagram of a pixel circuit including transistors and capacitors according to some embodiments;

[0029] Figure 10 is a timing diagram of a pixel circuit according to some embodiments;

[0030] Figure 11 is another timing diagram of a pixel circuit according to some embodiments;

[0031] Figure 12 is another structural diagram of a pixel circuit according to some embodiments;

[0032] Figure 13 is another structural diagram of a pixel circuit including transistors and capacitors according to some embodiments;

[0033] Figure 14 is another structural diagram of a pixel circuit according to some embodiments;

[0034] Figure 15 is another structural diagram of a pixel circuit including transistors and capacitors according to some embodiments;

[0035] Figure 16 is yet another timing diagram of a pixel circuit according to some embodiments. Detailed Implementation

[0036] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0039] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0040] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0041] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0042] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0043] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0044] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0045] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0046] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0047] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0048] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0049] In the embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0050] In the circuits provided in the embodiments of this disclosure, the first node, the second node, the third node, the fourth node, and the fifth node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0051] In the embodiments of this disclosure, a “low level” in the pixel circuit refers to a level that enables the operated transistors included therein to be turned on, and correspondingly, a “high level” refers to a level that prevents the operated transistors included therein from being turned on (i.e., the transistor is turned off).

[0052] In the circuits provided in the embodiments of this disclosure, N-type transistors are used as an example for illustration. It should be noted that the embodiments of this disclosure include, but are not limited to, this. For example, one or more transistors in the circuits provided in the embodiments of this disclosure can also be P-type transistors, simply by connecting the terminals of the selected type of transistor in accordance with the terminals of the corresponding transistors in the embodiments of this disclosure, and providing the corresponding high or low potential at the corresponding potential terminals.

[0053] As shown in Figures 1 and 2, some embodiments of this disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) text or images.

[0054] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display.

[0055] In some examples, as shown in Figure 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in Figure 1.

[0056] In some other examples, as shown in Figure 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in Figure 2.

[0057] In some embodiments, as shown in FIG3, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0058] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 3), and the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 3).

[0059] The driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.

[0060] The housing 300 can be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed inside the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0061] As shown in Figure 3, the longitudinal section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0062] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0063] For example, the display panel 100 described above may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. The embodiments disclosed herein do not impose specific limitations.

[0064] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0065] In some embodiments, as shown in Figures 4 and 5, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0066] The substrate 10 may be made of polymer resin or glass. Exemplarily, the substrate 10 may be flexible, and the material used for the substrate 10 may include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granules (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). For example, the substrate 10 may be rigid, including a glass material containing SiO2 as the main component.

[0067] As shown in Figure 4, a plurality of sub-pixels 20 are disposed on the substrate 10. The plurality of sub-pixels 20 can be arranged in multiple rows and columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0068] The aforementioned plurality of sub-pixels 20 may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color. The first, second, and third colors are three primary colors. For example, the first color may be red, the second color blue, and the third color green; however, this embodiment does not impose specific limitations.

[0069] In some embodiments, as shown in Figures 4 and 5, each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on the substrate 10. The pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (C).

[0070] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In the embodiments of this disclosure, thin-film transistors are used as an example for illustration.

[0071] For example, transistor 211 is an oxide thin-film transistor, which has a higher carrier mobility, thus improving the response speed of transistor 211.

[0072] As shown in Figure 5, transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114, with the source 2112 and drain 2113 respectively in contact with the active portion 2111. Storage capacitor 212 includes two plates disposed opposite to each other.

[0073] It should be noted that the source 2112 and drain 2113 mentioned above can be interchanged, that is, 2112 in Figure 5 represents the drain and 2113 represents the source.

[0074] The pixel circuit 21 described above has various structures, which can be selected and configured according to actual needs. For example, the structure of the pixel circuit 21 may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C", etc. Here, "T" represents transistor 211, and the number before "T" indicates the number of transistors 211; "C" represents storage capacitor 212, and the number before "C" indicates the number of storage capacitors 212.

[0075] As shown in Figure 5, the light-emitting device 22 includes a first electrode 221, a light-emitting functional layer 222, and a second electrode 223. The first electrode 221 can be electrically connected, for example, to the source 2112 or drain 2113 of a plurality of transistors 211 that serve as driving transistors. Figure 5 illustrates the electrical connection between the first electrode 221 and the drain 2113 of the transistor 211. The material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).

[0076] It should be noted that the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; or, the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22. The following example, using the first electrode 221 as the anode of the light-emitting device 22 and the second electrode 223 as the cathode of the light-emitting device 22, provides an exemplary description of the embodiments of this disclosure.

[0077] For example, as shown in FIG5, the first electrode 221 (cathode) is a monolayer structure.

[0078] The aforementioned light-emitting functional layer 222 may include only the light-emitting layer, or it may include at least one of the following in addition to the light-emitting layer: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0079] In some embodiments, as shown in FIG5, the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on the side of the plurality of sub-pixels 20 away from the substrate 10, and the encapsulation layer 30 is used to encapsulate the light-emitting device 22 to improve the lifespan of the light-emitting device 22. The encapsulation layer 30 can be an encapsulation film or an encapsulation substrate, and the embodiments disclosed herein are not specifically limited thereto.

[0080] For example, the encapsulation layer 30 may include a single encapsulation film, or it may include two or more encapsulation films stacked together. For instance, as shown in FIG5, the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked along a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0081] In some embodiments, as shown in Figures 6 to 9, the pixel circuit 21 includes a driving sub-circuit 201, a data writing sub-circuit 202, a first light-emitting sub-circuit 203, a second light-emitting sub-circuit 204, and a first type of storage sub-circuit 205.

[0082] In some examples, as shown in Figures 6-9, the drive sub-circuit 201 is coupled to a first node N1, a second node N2, and a third node N3. The drive sub-circuit 201 is configured to generate a drive current based on the voltage of the first node N1 and the voltage of the third node N3, and to pass the drive current to the third node N3.

[0083] For example, as shown in Figures 7 and 9, the driving sub-circuit 201 includes a second transistor T2, the first terminal of the second transistor T2 is connected to the second node N2, the second terminal is connected to the third node N3, and the control terminal is connected to the first node N1.

[0084] In some examples, as shown in Figures 6 to 11, the data writing sub-circuit 202 is coupled to the first node N1, the first scan signal terminal GATE1, and the data signal terminal DATA. The data writing sub-circuit 202 is configured to, during the data writing phase P1, transmit the data signal received at the data writing sub-circuit 202 to the first node N1 in response to the first scan signal received at the first scan signal terminal GATE1.

[0085] For example, as shown in Figures 7 and 9, the data writing sub-circuit 202 includes a third transistor T3. The first terminal of the third transistor T3 is connected to the data signal terminal DATA, the second terminal is connected to the first node N1, and the control terminal is connected to the first scan signal terminal GATE1.

[0086] In some examples, as shown in Figures 6 to 11, the first light-emitting sub-circuit 203 is coupled to the first voltage signal terminal VDD, the first light-emitting signal terminal EM1, and the second node N2. The first light-emitting sub-circuit 203 is configured to, in the light-emitting phase P2, in response to the first light-emitting signal received at the first light-emitting signal terminal EM1, transmit the first voltage signal received at the first voltage signal terminal VDD to the second node N2.

[0087] For example, as shown in Figures 7 and 9, the first light-emitting sub-circuit 203 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first voltage signal terminal VDD, the second terminal is connected to the second node N2, and the control terminal is connected to the first light-emitting signal terminal EM1.

[0088] In some examples, as shown in Figures 6-11, the second light-emitting sub-circuit 204 is coupled to the third node N3, the second light-emitting signal terminal EM2, and the fourth node N4. The second light-emitting sub-circuit 204 is configured to, during the light-emitting phase P2, in response to the second light-emitting signal received at the second light-emitting signal terminal EM2, transfer the driving current at the third node N3 to the fourth node N4. The fourth node N4 is connected to the anode of the light-emitting device 22.

[0089] For example, as shown in Figures 7 and 9, the second light-emitting sub-circuit 204 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the control terminal is connected to the second light-emitting signal terminal EM2.

[0090] Based on this, as shown in Figures 6, 7, 8, and 9, the cathode of the light-emitting device 22 is coupled to the second voltage signal terminal VSS. The output level of the second voltage signal terminal VSS is lower than the high level output of the first voltage signal terminal VDD.

[0091] In some examples, as shown in Figures 6 to 9, the first type of storage sub-circuit 205 is coupled to the first node N1 and the third node N3.

[0092] For example, the first type of storage sub-circuit 205 includes a first storage sub-circuit 2051 and a second storage sub-circuit 2052.

[0093] In some examples, as shown in Figures 6 to 9, the first storage sub-circuit 2051 is coupled to the first node N1 and the fifth node N5.

[0094] For example, as shown in Figures 7 and 9, the first storage sub-circuit 2051 includes a first storage capacitor C1, the first plate of the first storage capacitor C1 is connected to the first node N1, and the second plate is connected to the fifth node N5.

[0095] In some examples, as shown in Figures 6 to 9, the second storage sub-circuit 2052 is coupled to the fifth node N5 and the third node N3.

[0096] For example, as shown in Figures 7 and 9, the second storage sub-circuit 2052 includes a second storage capacitor C2, the first plate of the second storage capacitor C2 is connected to the third node N3, and the second plate is connected to the fifth node N5.

[0097] Based on the above structure, as shown in Figures 10 and 11, during the data writing stage P1, the data writing sub-circuit 202 responds to the first scan signal received at the first scan signal terminal GATE1 and transmits the data signal received at the data signal terminal DATA to the first node N1, and the first storage capacitor C1 stores the data signal at the first node N1.

[0098] During the light-emitting stage P2, the first light-emitting sub-circuit 203 responds to the first light-emitting signal received at the first light-emitting signal terminal EM1 and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the data signal at the first node N1 and the voltage at the third node N3, the driving sub-circuit 201 generates a driving current and outputs the driving current to the third node N3. The second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the driving current at the third node N3 to the fourth node N4, that is, to the light-emitting device 22, so that the light-emitting device 22 emits light, thereby causing the display panel 100 to display an image.

[0099] In related technologies, horizontal lines appearing on the display panel indicate poor display consistency and a poor display effect. The inventors discovered that during the first transition phase (located between the data writing phase and the light-emitting phase), the first and third nodes are in a floating state. The voltage change values ​​at the first node and the third node are not equal, resulting in horizontal lines appearing on the display panel.

[0100] To address the aforementioned technical problems, some embodiments of this disclosure provide a pixel circuit 21, as shown in Figures 6 to 11, in which the fifth node N5 is coupled to the first initialization signal terminal VINIT1. During the first transition phase P0, the first initialization signal received at the first initialization signal terminal VINIT1 can be transmitted to the fifth node N5.

[0101] In this configuration, during the first transition phase P0, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5, which stabilizes the voltage at the fifth node N5, thereby stabilizing the voltages at the first node N1 and the third node N3. This reduces the difference between the voltage variations at the first node N1 and the third node N3, improving the horizontal stripe problem on the display panel 100 and enhancing its display performance.

[0102] In some embodiments, as shown in Figures 10 and 11, the first transition phase and the light emission phase are consecutive.

[0103] With this configuration, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 throughout all stages between the data writing stage P1 and the light emission stage P2. This can keep the voltage at the fifth node N5 stable, further improve the problem of horizontal lines generated in the display panel 100, and further enhance the display effect of the display panel 100.

[0104] In some embodiments, as shown in FIG6 and FIG7, the pixel circuit 21 further includes a first reset sub-circuit 206.

[0105] In some examples, the first reset sub-circuit 206 is connected to the first initialization signal terminal VINIT1, the first reset signal terminal RESET1, and the fourth node N4. The first reset sub-circuit 206 is configured to, in the first transition phase P0, in response to the first reset signal received at the first reset signal terminal RESET1, pass the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0106] For example, as shown in FIG7, the first reset sub-circuit 206 includes a first transistor T1, the first terminal of the first transistor T1 is connected to the first initialization signal terminal VINIT1, the second terminal is connected to the fifth node N5, and the control terminal is connected to the first initialization signal terminal VINIT1.

[0107] In this configuration, during the first transition phase P0, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5, thereby keeping the voltage of the fifth node N5 stable.

[0108] In some embodiments, as shown in Figures 6, 7, and 11, the first reset sub-circuit 206 is further configured to, in a first target phase, in response to a first reset signal received at the first reset signal terminal RESET1, transmit a first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5. The first target phase includes at least a partial reset phase P4, a compensation phase P3, and a data writing phase P1.

[0109] In this configuration, during the first target phase, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5, so that the voltage of the fifth node N5 remains stable, which is beneficial to improving the display effect of the display panel 100.

[0110] In other examples, as shown in Figures 7 and 10, the reset phase P4 includes a first reset phase P41 and a second reset phase P42. In the second reset phase P42, the first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0111] In some examples, as shown in Figures 7 and 11, during the entire reset phase, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0112] In some embodiments, as shown in FIG6 and FIG7, the pixel circuit 21 further includes a second reset sub-circuit 207.

[0113] In some examples, as shown in Figures 6, 7, 10, and 11, the second reset sub-circuit 207 is coupled to the first initialization signal terminal VINIT1, the second reset signal terminal RESET2, and the first node N1. The second reset sub-circuit 207 is configured to, in a second target phase, in response to a second reset signal received at the second reset signal terminal RESET2, transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. The second target phase includes a reset phase P4 and a compensation phase P3.

[0114] For example, as shown in FIG7, the second reset sub-circuit 207 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first initialization signal terminal VINIT1, the second terminal is connected to the first node N1, and the control terminal is connected to the second reset signal terminal RESET2.

[0115] In this configuration, during the second target stage, the second reset sub-circuit 207 responds to the second reset signal received at the second reset signal terminal RESET2 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1, thereby initializing the first node N1. This can improve the problem of the voltage remaining on the first node N1 from the previous image frame affecting the display image of the next image frame, thereby improving the brightness consistency of the display panel 100.

[0116] Based on the above structure, it can be seen that the first reset sub-circuit 206 and the second reset sub-circuit 207 are connected to the first initialization signal terminal VINIT1, which simplifies the circuit structure.

[0117] Based on this, the durations of the first target stage and the second target stage are not equal. That is, the signal received at the first reset signal terminal RESET1 is different from the signal received at the second reset signal terminal RESET2. The gate drive circuit connected to the first reset signal terminal RESET1 is different from the gate drive circuit connected to the second reset signal terminal RESET2. This allows for flexible control of the conduction duration of the first target stage and the second target stage according to the actual situation, thereby increasing the applicability of the pixel circuit 21.

[0118] In some embodiments, as shown in FIG6 and FIG7, the pixel circuit 21 further includes a third reset sub-circuit 208.

[0119] In some examples, as shown in Figures 6 and 7, the third reset sub-circuit 208 is coupled to the second initialization signal terminal VINIT2, the third reset signal terminal RESET3, and the fourth node N4. The third reset sub-circuit 208 is configured to, in response to a third reset signal received at the third reset signal terminal RESET3, pass a second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4. This includes at least a partial reset phase P4.

[0120] For example, as shown in FIG7, the third reset sub-circuit 208 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the second initialization signal terminal VINIT2, the second terminal is connected to the fourth node N4, and the control terminal is connected to the third reset signal terminal RESET3.

[0121] In this configuration, during at least the partial reset phase P4, the third reset sub-circuit 208 responds to the third reset signal received at the third reset signal terminal RESET3 and transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4, thereby initializing the fourth node N4. This can improve the problem of the voltage remaining at the fourth node N4 from the previous image frame affecting the display image of the next image frame, thereby improving the brightness consistency of the display panel 100.

[0122] For example, as shown in FIG10, the first reset stage P41 includes a first sub-stage P411 and a second sub-stage P412. At this time, in the second sub-stage P412 and the second reset stage P42, the third reset sub-circuit 208, in response to the third reset signal received at the third reset signal terminal RESET3, transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0123] Alternatively, exemplarily, during the entire reset phase P4, the third reset sub-circuit 208, in response to the third reset signal received at the third reset signal terminal RESET3, transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0124] In other embodiments, as shown in Figures 8 and 9, the first initialization signal terminal VINIT1 and the fifth node N5 are directly connected.

[0125] In this configuration, during the first transition phase P0, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5, which stabilizes the voltage at the fifth node N5, thereby stabilizing the voltages at the first node N1 and the third node N3. This reduces the difference between the voltage variations at the first node N1 and the third node N3, improving the horizontal stripe problem on the display panel 100 and enhancing its display performance.

[0126] Furthermore, in other stages outside the first transition phase P0 in a display frame period P, the first initialization signal received at the first initialization signal terminal VINIT1 can also be transmitted to the fifth node N5, which can keep the voltage at the fifth node N5 stable, so that the voltage at the first node N1 and the voltage at the third node N3 can be kept stable, thereby further improving the display effect of the display panel 100.

[0127] Some embodiments of this disclosure also provide a pixel circuit 21, as shown in Figures 12 to 15, which further includes a third storage sub-circuit 209.

[0128] In some examples, the third storage sub-circuit 209 is connected to the target signal terminal and the target node, which is at least one of the first node N1 and the third node N3.

[0129] For example, as shown in Figures 13 and 15, the third storage sub-circuit 209 includes a third storage capacitor C3, the first plate of the third storage capacitor C3 is connected to the target signal terminal, and the second substrate is connected to the target node.

[0130] In this configuration, during the first transition phase P0, the third storage sub-circuit 209 can keep the voltage at the first node N1 and the voltage at the third node N3 stable. This reduces the difference between the voltage change values ​​at the first node N1 and the third node N3, thereby improving the problem of horizontal lines appearing on the display panel 100 and enhancing the display effect of the display panel 100.

[0131] Furthermore, in other stages of a display frame period P besides the first transition stage P0, the third storage sub-circuit 209 can also keep the voltage at the first node N1 and the voltage at the third node N3 stable, thereby further improving the display effect of the display panel 100.

[0132] In some examples, as shown in Figures 12 and 13, the third storage sub-circuit 209 is coupled to the target signal terminal and the first node N1.

[0133] In other examples, as shown in Figures 14 and 15, the third storage sub-circuit 209 is coupled to the target signal terminal and the third node N3.

[0134] In some other examples, the third storage sub-circuit 209 and the target signal terminal are coupled to the first node N1 and the third node N3.

[0135] In some embodiments, as shown in Figures 12 to 16, the pixel circuit 21 further includes a first reset circuit 206 and a second reset circuit 207.

[0136] In some examples, the first reset sub-circuit 206 is coupled to the first initialization signal terminal VINIT1, the first reset signal terminal RESET1, and the fifth node N5. The first reset sub-circuit 206 is also configured to, in a first target phase, in response to a first reset signal received at the first reset signal terminal RESET1, pass the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5. The first target phase includes a partial reset phase P4, a compensation phase P3, and a data writing phase P1.

[0137] For example, as shown in Figures 13 and 15, the first reset sub-circuit 206 includes a first transistor T1, the first terminal of the first transistor T1 is connected to the first initialization signal terminal VINIT1, the second terminal is connected to the fifth node N5, and the control terminal is connected to the first initialization signal terminal VINIT1.

[0138] In this configuration, during the first target phase, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5, so that the voltage of the fifth node N5 remains stable, which is beneficial to improving the display effect of the display panel 100.

[0139] For example, as shown in FIG16, the reset phase P4 includes a first reset phase P41 and a second reset phase P42. In the second reset phase P42, the first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0140] In some examples, as shown in Figures 12-16, the second reset sub-circuit 207 is coupled to the first initialization signal terminal VINIT1, the second reset signal terminal RESET2, and the first node N1. The second reset sub-circuit 207 is configured to, in response to the second reset signal received at the second reset signal terminal RESET2, transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 during the second target phase. The second target phase includes a reset phase P4 and a compensation phase P3.

[0141] For example, as shown in Figures 13 and 15, the second reset sub-circuit 207 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first initialization signal terminal VINIT1, the second terminal is connected to the first node N1, and the control terminal is connected to the second reset signal terminal RESET2.

[0142] In this configuration, during the second target stage, the second reset sub-circuit 207 responds to the second reset signal received at the second reset signal terminal RESET2 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1, thereby initializing the first node N1. This can improve the problem of the voltage remaining on the first node N1 from the previous image frame affecting the display image of the next image frame, thereby improving the brightness consistency of the display panel 100.

[0143] In some embodiments, as shown in FIG16, during the first transition phase P0, the third storage sub-circuit 209 can stabilize the voltage at the first node N1 and the voltage at the third node N3. Therefore, during the first transition phase P0, the first reset sub-circuit 206 can cut off the second reset signal terminal RESET2 and the fifth node N5, meaning the first target phase may not include at least a portion of the first transition phase P0. Therefore, the duration of the first target phase can be shortened. The first target phase includes only a portion of the reset phase P4, which can further shorten the duration of the first target phase.

[0144] Based on this, the second objective stage only includes the reset stage P4 and the compensation stage P3, and the duration of the second objective stage is shorter. Therefore, the duration of the first objective stage can be made equal to the duration of the second objective stage.

[0145] In this configuration, the first initialization signal terminal VINIT1 and the second initialization signal terminal VINIT2 are connected to the same gate drive circuit. This reduces the number of gate drive circuits and helps to achieve the goal of narrow bezels in the display panel 100.

[0146] In some examples, as shown in Figures 12-16, the third reset sub-circuit 208 is coupled to the second initialization signal terminal VINIT2, the third reset signal terminal RESET3, and the fourth node N4. The third reset sub-circuit 208 is configured to, in response to the third reset signal received at the third reset signal terminal RESET3, transmit the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4. This includes at least a partial reset phase P4.

[0147] For example, as shown in Figures 13 and 15, the third reset sub-circuit 208 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the second initialization signal terminal VINIT2, the second terminal is connected to the fourth node N4, and the control terminal is connected to the third reset signal terminal RESET3.

[0148] In this configuration, during at least the partial reset phase P4, the third reset sub-circuit 208 responds to the third reset signal received at the third reset signal terminal RESET3 and transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4, thereby initializing the fourth node N4. This can improve the problem of the voltage remaining at the fourth node N4 from the previous image frame affecting the display image of the next image frame, thereby improving the brightness consistency of the display panel 100.

[0149] In some examples, as shown in Figure 16, the first reset phase P41 includes a first sub-phase P411 and a second sub-phase P412. At this time, in the second sub-phase P412 and the second reset phase P42, the third reset sub-circuit 208, in response to the third reset signal received at the third reset signal terminal RESET3, transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0150] In other examples, throughout the reset phase P4, the third reset sub-circuit 208, in response to the third reset signal received at the third reset signal terminal RESET3, transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0151] In some embodiments, the signal received at the target signal terminal is the same as the signal received at the first voltage signal terminal, the signal received at the first initialization signal terminal, or the signal received at the second initialization signal terminal.

[0152] This configuration simplifies the structure of the pixel circuit 21.

[0153] The following detailed description, with reference to the timing diagram, illustrates the operation of the pixel circuit 21 within one display frame period P. The following embodiment uses N-type transistors as an example. One display frame period P includes a data writing phase P1, a first transition phase P0, and a light-emitting phase P2.

[0154] In some embodiments, the circuit diagrams in Figures 7 and 9 are described in detail with reference to the timing diagrams in Figures 10 and 11.

[0155] In the data writing stage P1, the data writing sub-circuit 202 responds to the first scan signal received at the first scan signal terminal GATE1 and transmits the data signal received at the data signal terminal DATA to the first node N1, and the first storage capacitor C1 stores the data signal at the first node N1.

[0156] For example, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in Figures 10 and 11, during the data writing stage P1, the first scan signal is 1, the first reset signal is 1, the first light emission signal is 0, the second light emission signal is 0, the second reset signal is 0, and the third reset signal is 0. Here, "0" represents a low level and "1" represents a high level.

[0157] In this configuration, the first scan signal terminal GATE1 and the first reset signal terminal RESET1 are at high levels, and the third transistor T3 and the first transistor T1 are turned on. The first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the second reset signal terminal RESET2, and the third reset signal terminal RESET2 are at low levels, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0158] At this time, the data signal received at the data signal terminal DATA is transmitted to the first node N1 through the third transistor T3, and the first storage capacitor C1 stores the data signal at the first node N1. The first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0159] During the first transition phase P0, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5.

[0160] In some embodiments, as shown in FIG6 and FIG7, the pixel circuit 21 further includes a first reset sub-circuit 206.

[0161] During the first transition phase P0, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0162] In some examples, as shown in Figures 10 and 11, the first transition phase P0 includes a first phase P01 and a second phase P02.

[0163] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in Figures 10 and 11, in the first stage P01, the first reset signal is 1, the first scan signal is 0, the first light emission signal is 0, the second light emission signal is 0, the second reset signal is 0, and the third reset signal is 0.

[0164] In this case, the first reset signal terminal RESET1 is high, and the first transistor T1 is turned on. The first scan signal terminal GATE1, the first light emission signal terminal EM1, the second light emission signal terminal EM2, the second reset signal terminal RESET2, and the third reset signal terminal RESET2 are low, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0165] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0166] In the second stage P02, the first reset signal is 1, the second light emission signal is 1, the first scan signal is 0, the first light emission signal is 0, the second reset signal is 0, and the third reset signal is 0.

[0167] In this case, the first reset signal terminal RESET1 and the second light emission signal terminal EM2 are input with a high level, and the first transistor T1 and the fifth transistor T5 are turned on. The first scan signal terminal GATE1, the first light emission signal terminal EM1, the second reset signal terminal RESET2, and the third reset signal terminal RESET2 are input with a low level, and the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0168] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1, and the voltage at the third node N3 can be transmitted to the fourth node N4 through the fifth transistor T5.

[0169] During the light-emitting stage P2, the first light-emitting sub-circuit 203 responds to the first light-emitting signal received at the first light-emitting signal terminal EM1 and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the data signal at the first node N1 and the voltage at the third node N3, the driving sub-circuit 201 generates a driving current and outputs the driving current to the third node N3. The second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the driving current at the third node N3 to the fourth node N4, that is, to the light-emitting device 22, so that the light-emitting device 22 emits light, thereby causing the display panel 100 to display an image.

[0170] For example, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in Figures 10 and 11, during the light-emitting stage P2, the first light-emitting signal is 1, the second light-emitting signal is 1, the first scan signal is 0, the first reset signal is 0, the second reset signal is 0, and the third reset signal is 0.

[0171] In this case, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are input with a high level, and the fourth transistor T4 and the fifth transistor T5 are turned on. The first scan signal terminal GATE1, the first reset signal terminal RESET1, the second reset signal terminal RESET2 and the third reset signal terminal RESET2 are input with a low level, and the third transistor T3, the first transistor T1, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0172] At this time, the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the fourth transistor T4. The second transistor T2 generates a driving current based on the data signal of the first node N1 and the voltage of the third node N3, and transmits the driving current to the third node N3. The driving current at the third node N3 is transmitted to the fourth node N4 through the fifth transistor T5, that is, to the light-emitting device 22.

[0173] In this configuration, during the first transition phase P0, the first reset sub-circuit 206 responds to the first reset signal received at the first reset signal terminal RESET1 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5, thereby keeping the voltage of the fifth node N5 stable.

[0174] In some embodiments, as shown in Figures 10 and 11, a display frame period P further includes a compensation phase P3, which is located before the data writing phase P1.

[0175] During the compensation phase P3, the first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5. The first light-emitting sub-circuit 203, in response to the first light-emitting signal received at the first light-emitting signal terminal EM1, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the voltage at the first node N1, the drive sub-circuit 201 transmits the voltage at the second node N2 to the third node N3 and charges the third node N3.

[0176] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in Figures 10 and 11, during compensation phase P3, the first reset signal is 1, the second reset signal is 1, the first light emission signal is 1, the first scan signal is 0, the second light emission signal is 0, and the third reset signal is 0.

[0177] In this configuration, the first reset signal terminal RESET1, the second reset signal terminal RESET2, and the first light-emitting signal terminal EM1 are input at high levels, and the first transistor T1, the sixth transistor T6, and the fourth transistor T4 are turned on. The first scan signal terminal GATE1, the second light-emitting signal terminal EM2, and the third reset signal terminal RESET2 are input at low levels, and the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0178] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1, and the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the third transistor T3. The voltage at the second node N2 charges the third node N3 through the second transistor T2.

[0179] In some embodiments, a display frame period P further includes a reset phase P4.

[0180] In some embodiments, as shown in FIG10, the reset phase P4 includes a first reset phase P41 and a second reset phase P42.

[0181] In the first reset phase P41, the second reset sub-circuit 207 responds to the second reset signal received at the second reset signal terminal RESET2 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1.

[0182] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG10, in the first reset phase P41, the second reset signal is 1, the first reset signal is 0, the first light emission signal is 0, the first scan signal is 0, and the second light emission signal is 0.

[0183] In this situation, the second reset signal terminal RESET2 is high, and the sixth transistor T6 is turned on. The first reset signal terminal RESET1, the first light-emitting signal terminal EM1, the first scan signal terminal GATE1, and the second light-emitting signal terminal EM2 are low, and the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0184] At this time, the second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the sixth transistor T6.

[0185] In the second reset phase P42, the second reset sub-circuit 207, in response to the second reset signal received at the second reset signal terminal RESET2, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. The first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0186] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG10, in the second reset phase P42, the second reset signal is 1, the first reset signal is 1, the first light emission signal is 0, the first scan signal is 0, and the second light emission signal is 0.

[0187] In this case, the second reset signal terminal RESET2 and the first reset signal terminal RESET1 are input to a high level, and the sixth transistor T6 and the first transistor T1 are turned on. The first light-emitting signal terminal EM1, the first scan signal terminal GATE1, and the second light-emitting signal terminal EM2 are input to a low level, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0188] At this time, the second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the sixth transistor T6. The first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0189] In other embodiments, as shown in FIG11, during the reset phase P4, the second reset sub-circuit 207, in response to the second reset signal received at the second reset signal terminal RESET2, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. The first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0190] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG11, during the reset phase P4, the second reset signal is 1, the first reset signal is 1, the first light emission signal is 0, the first scan signal is 0, and the second light emission signal is 0.

[0191] In this case, the second reset signal terminal RESET2 and the first reset signal terminal RESET1 are input to a high level, and the sixth transistor T6 and the first transistor T1 are turned on. The first light-emitting signal terminal EM1, the first scan signal terminal GATE1, and the second light-emitting signal terminal EM2 are input to a low level, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0192] At this time, the second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the sixth transistor T6. The first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0193] In some embodiments, as shown in FIG10, the first reset phase P41 further includes a first sub-phase P411 and a second sub-phase P412.

[0194] In the second sub-stage P412 and the second reset stage P42, the third reset sub-circuit 208 responds to the third reset signal received at the third reset signal terminal RESET3 and transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0195] For example, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIG10, in the second sub-stage P412 and the second reset stage P42, the third reset signal is 1.

[0196] In this case, the third reset signal terminal RESET3 is input at a high level, and the seventh transistor T7 is turned on.

[0197] At this time, the third initialization signal received at the third initialization signal terminal is transmitted to the fourth node N4 through the seventh transistor T7.

[0198] Based on this, as shown in Figure 10, in at least part of the second sub-stage P412 and the second reset stage P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0199] In some examples, only in the second sub-stage P412, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0200] In other examples, only during the second reset phase P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0201] In some other examples, during the second sub-stage P412 and the second reset stage P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0202] In other embodiments, as shown in Figures 8 and 9, the first initialization signal terminal VINIT1 and the fifth node N5 are directly connected. In this case, the timing diagram corresponding to the pixel circuit 21 differs from that in the above embodiments in that there is no timing diagram for the first reset signal terminal; the timing diagrams for the remaining signal terminals are the same and will not be described again here.

[0203] In some embodiments, the circuit diagrams in Figures 13 and 15 are described in detail with reference to the timing diagram in Figure 16.

[0204] In the data writing stage P1, the data writing sub-circuit 202 responds to the first scan signal received at the first scan signal terminal GATE1 and transmits the data signal received at the data signal terminal DATA to the first node N1, and the first storage capacitor C1 stores the data signal at the first node N1.

[0205] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG16, during the data writing stage P1, the first scan signal is 1, the first reset signal is 1, the first light emission signal is 0, the second light emission signal is 0, the second reset signal is 0, and the third reset signal is 0. Here, "0" represents a low level and "1" represents a high level.

[0206] In this configuration, the first scan signal terminal GATE1 and the first reset signal terminal RESET1 are at high levels, and the third transistor T3 and the first transistor T1 are turned on. The first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the second reset signal terminal RESET2, and the third reset signal terminal RESET2 are at low levels, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0207] At this time, the data signal received at the data signal terminal DATA is transmitted to the first node N1 through the third transistor T3, and the first storage capacitor C1 stores the data signal at the first node N1. The first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0208] During the first transition phase P0, the third storage sub-circuit 209 keeps the voltage at the first node N1 and the voltage at the third node N3 stable.

[0209] During the light-emitting stage P2, the first light-emitting sub-circuit 203 responds to the first light-emitting signal received at the first light-emitting signal terminal EM1 and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the data signal at the first node N1 and the voltage at the third node N3, the driving sub-circuit 201 generates a driving current and outputs the driving current to the third node N3. The second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the driving current at the third node N3 to the fourth node N4, that is, to the light-emitting device 22, so that the light-emitting device 22 emits light, thereby causing the display panel 100 to display an image.

[0210] For example, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIG16, during the light-emitting stage P2, the first light-emitting signal is 1 and the second light-emitting signal is 1. The first scan signal is 0, the first reset signal is 0, the second reset signal is 0, and the third reset signal is 0.

[0211] In this case, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are input with a high level, and the fourth transistor T4 and the fifth transistor T5 are turned on. The first scan signal terminal GATE1, the first reset signal terminal RESET1, the second reset signal terminal RESET2 and the third reset signal terminal RESET2 are input with a low level, and the third transistor T3, the first transistor T1, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0212] At this time, the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the fourth transistor T4. The second transistor T2 generates a driving current based on the data signal of the first node N1 and the voltage of the third node N3, and transmits the driving current to the third node N3. The driving current at the third node N3 is transmitted to the fourth node N4 through the fifth transistor T5, that is, to the light-emitting device 22.

[0213] In this configuration, during the first transition phase P0, the third storage sub-circuit 209 can keep the voltage at the first node N1 and the voltage at the third node N3 stable. This reduces the difference between the voltage change values ​​at the first node N1 and the third node N3, thereby improving the problem of horizontal lines appearing on the display panel 100 and enhancing the display effect of the display panel 100.

[0214] In some embodiments, as shown in FIG16, a display frame period P further includes a compensation phase P3, which is located before the data writing phase P1.

[0215] During the compensation phase P3, the first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5. The first light-emitting sub-circuit 203, in response to the first light-emitting signal received at the first light-emitting signal terminal EM1, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. Under the control of the voltage at the first node N1, the drive sub-circuit 201 transmits the voltage at the second node N2 to the third node N3 and charges the third node N3.

[0216] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in 16, during compensation phase P3, the first reset signal is 1, the second reset signal is 1, the first light emission signal is 1, the first scan signal is 0, the second light emission signal is 0, and the third reset signal is 0.

[0217] In this configuration, the first reset signal terminal RESET1, the second reset signal terminal RESET2, and the first light-emitting signal terminal EM1 are input at high levels, and the first transistor T1, the sixth transistor T6, and the fourth transistor T4 are turned on. The first scan signal terminal GATE1, the second light-emitting signal terminal EM2, and the third reset signal terminal RESET2 are input at low levels, and the third transistor T3, the fifth transistor T5, and the seventh transistor T7 are turned off.

[0218] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1, and the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the third transistor T3. The voltage at the second node N2 charges the third node N3 through the second transistor T2.

[0219] In some embodiments, a display frame period P further includes a reset phase P4.

[0220] In some embodiments, as shown in FIG16, the reset phase P4 includes a first reset phase P41 and a second reset phase P42.

[0221] In the first reset phase P41, the second reset sub-circuit 207 responds to the second reset signal received at the second reset signal terminal RESET2 and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1.

[0222] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG16, in the first reset phase P41, the second reset signal is 1, the first reset signal is 0, the first light emission signal is 0, the first scan signal is 0, and the second light emission signal is 0.

[0223] In this situation, the second reset signal terminal RESET2 is high, and the sixth transistor T6 is turned on. The first reset signal terminal RESET1, the first light-emitting signal terminal EM1, the first scan signal terminal GATE1, and the second light-emitting signal terminal EM2 are low, and the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0224] At this time, the second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the sixth transistor T6.

[0225] In the second reset phase P42, the second reset sub-circuit 207, in response to the second reset signal received at the second reset signal terminal RESET2, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. The first reset sub-circuit 206, in response to the first reset signal received at the first reset signal terminal RESET1, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the fifth node N5.

[0226] For example, each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212. As shown in FIG16, in the second reset phase P42, the second reset signal is 1, the first reset signal is 1, the first light emission signal is 0, the first scan signal is 0, and the second light emission signal is 0.

[0227] In this case, the second reset signal terminal RESET2 and the first reset signal terminal RESET1 are input to a high level, and the sixth transistor T6 and the first transistor T1 are turned on. The first light-emitting signal terminal EM1, the first scan signal terminal GATE1, and the second light-emitting signal terminal EM2 are input to a low level, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off.

[0228] At this time, the second initialization signal received at the second initialization signal terminal VINIT2 is transmitted to the first node N1 through the sixth transistor T6. The first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the fifth node N5 through the first transistor T1.

[0229] In some embodiments, as shown in FIG16, the first reset phase P41 further includes a first sub-phase P411 and a second sub-phase P412.

[0230] In the second sub-stage P412 and the second reset stage P42, the third reset sub-circuit 208 responds to the third reset signal received at the third reset signal terminal RESET3 and transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the fourth node N4.

[0231] For example, each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in FIG16, in the second sub-stage P412 and the second reset stage P42, the third reset signal is 1.

[0232] In this case, the third reset signal terminal RESET3 is input at a high level, and the seventh transistor T7 is turned on.

[0233] At this time, the third initialization signal received at the third initialization signal terminal is transmitted to the fourth node N4 through the seventh transistor T7.

[0234] Based on this, as shown in Figure 16, in at least part of the second sub-stage P412 and the second reset stage P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0235] In some examples, only in the second sub-stage P412, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0236] In other examples, only during the second reset phase P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0237] In some other examples, during the second sub-stage P412 and the second reset stage P42, the second light-emitting sub-circuit 204 responds to the second light-emitting signal received at the second light-emitting signal terminal EM2 and transmits the third initialization signal received at the fourth node N4 to the third node N3.

[0238] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0239] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, comprising: The driving sub-circuit is coupled to the first node, the second node, and the third node; The driving sub-circuit is configured to generate a driving current based on the voltage of the first node and the voltage of the third node; A data writing sub-circuit is coupled to the first node, the first scan signal terminal, and the data signal terminal; the data writing sub-circuit is configured to, during the data writing phase, in response to the first scan signal received at the first scan signal terminal, transmit the data signal received at the data writing sub-circuit to the first node. A first light-emitting sub-circuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal and a second node; the first light-emitting sub-circuit is configured to, during the light-emitting phase, in response to a first light-emitting signal received at the first light-emitting signal terminal, transmit a first voltage signal received at the first voltage signal terminal to the second node. The second light-emitting sub-circuit is coupled to the third node, the second light-emitting signal terminal and the fourth node; the second light-emitting sub-circuit is configured to, during the light-emitting phase, in response to the second light-emitting signal received at the second light-emitting signal terminal, transmit the driving current at the third node to the fourth node. The first storage sub-circuit is coupled to the first node and the fifth node; The fifth node is coupled to the first initialization signal terminal; The second storage sub-circuit is coupled to the fifth node and the third node; In the first transition phase, the first initialization signal terminal receives the first initialization signal and transmits it to the fifth node. The first transition phase is located between the data writing phase and the light emission phase.

2. The pixel circuit according to claim 1, further comprising: The first reset sub-circuit is connected to the first initialization signal terminal, the first reset signal terminal, and the fourth node; The first reset sub-circuit is configured to, in the first transition phase, in response to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the fifth node.

3. The pixel circuit of claim 2, wherein, The first reset circuit includes: The first transistor has its first terminal connected to the first initialization signal terminal, its second terminal connected to the fourth node, and its control terminal connected to the first reset signal terminal.

4. The pixel circuit according to claim 2 or 3, wherein, The first reset sub-circuit is further configured to, in the first target phase, in response to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the fourth node; The first target stage includes at least a partial reset stage, a compensation stage, and a data writing stage; The pixel circuit also includes: The second reset sub-circuit is connected to the first initialization signal terminal, the second reset signal terminal, and the first node; the second reset sub-circuit is configured to, in a second target phase, in response to a second reset signal received at the second reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the first node; the second target phase includes a reset phase and a compensation phase. Within a single display frame cycle, the duration of the first target phase is not equal to the duration of the second target phase.

5. The pixel circuit of claim 4, wherein, The reset phase includes a first reset phase and a second reset phase; The first reset sub-circuit is further configured to, in the second reset phase, in response to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the fifth node.

6. The pixel circuit of claim 1, wherein, The first initialization signal terminal is directly connected to the fifth node.

7. A pixel circuit, comprising: The driving sub-circuit is coupled to the first node, the second node, and the third node; The driving sub-circuit is configured to generate a driving current based on the voltage of the first node and the voltage of the third node; A data writing sub-circuit is coupled to the first node, the first scan signal terminal, and the data signal terminal; the data writing sub-circuit is configured to, during the data writing phase, in response to the first scan signal received at the first scan signal terminal, transmit the data signal received at the data writing sub-circuit to the first node. A first light-emitting sub-circuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal and a second node; the first light-emitting sub-circuit is configured to, during the light-emitting phase, in response to a first light-emitting signal received at the first light-emitting signal terminal, transmit a first voltage signal received at the first voltage signal terminal to the second node. The second light-emitting sub-circuit is coupled to the third node, the second light-emitting signal terminal and the fourth node; the second light-emitting sub-circuit is configured to, during the light-emitting phase, in response to the second light-emitting signal received at the second light-emitting signal terminal, transmit the driving current at the third node to the fourth node. The first type of storage sub-circuit is coupled to the first node and the third node; The third storage sub-circuit is connected to the target signal terminal and the target node, wherein the target node is at least one of the first node and the third node.

8. The pixel circuit of claim 7, wherein, The first type of storage sub-circuit includes: The first storage sub-circuit is coupled to the first node and the fifth node; The second storage sub-circuit is coupled to the fifth node and the third node; The pixel circuit also includes: A first reset sub-circuit is coupled to a first initialization signal terminal, a first reset signal terminal, and the fifth node; the first reset sub-circuit is further configured to, in a first target phase, in response to a first reset signal received at the first reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the fifth node; the first target phase includes a partial reset phase, a compensation phase, and a data writing phase. The second reset sub-circuit is coupled to the first initialization signal terminal, the second reset signal terminal, and the first node; the second reset sub-circuit is configured to, in a second target phase, in response to a second reset signal received at the second reset signal terminal, transmit a first initialization signal received at the first initialization signal terminal to the first node; the second target phase includes a reset phase and a compensation phase. Within a display frame cycle, the duration of the first target phase is equal to the duration of the second target phase.

9. The pixel circuit according to claim 7 or 8, further comprising: A third reset sub-circuit is coupled to a second initialization signal terminal, a third reset signal terminal, and a fourth node; the third reset sub-circuit is configured to, in a third target phase, in response to a third reset signal received at the third reset signal terminal, transmit a second initialization signal received at the second initialization signal terminal to the fourth node; the third target phase includes at least a partial reset phase.

10. The pixel circuit according to any one of claims 7 to 9, wherein The signal received at the target signal terminal is the same as the signal received at the first voltage signal terminal, the signal received at the first initialization signal terminal, or the signal received at the second initialization signal terminal.

11. A display device comprising a pixel circuit as described in any one of claims 1 to 10.

12. A method for driving a pixel circuit, used to drive a pixel circuit as described in any one of claims 1 to 6, wherein a display frame cycle includes a data writing phase, a first transition phase, and a light emission phase; During the data writing phase, the data writing sub-circuit responds to the first scan signal received at the first scan signal terminal and transmits the data signal received at the data signal terminal to the first node. During the first transition phase, the first initialization signal is received at the first initialization signal terminal and transmitted to the fifth node; During the light-emitting phase, the first light-emitting sub-circuit responds to the first light-emitting signal received at the first light-emitting signal terminal and transmits the first voltage signal received at the first voltage signal terminal to the second node. The driving sub-circuit generates a driving current under the control of the data signal at the first node and the voltage at the third node, and outputs the driving current to the third node; the second light-emitting sub-circuit responds to the second light-emitting signal received at the second light-emitting signal terminal and transmits the driving current at the third node to the fourth node.

13. The driving method according to claim 12, wherein, During the first transition phase, the first reset sub-circuit responds to the first reset signal received at the first reset signal terminal and transmits the first initialization signal received at the first initialization signal terminal to the fifth node.

14. The driving method according to claim 13, wherein A display frame cycle also includes a compensation phase, which precedes the data writing phase; During the compensation phase, the first reset sub-circuit responds to the first reset signal received at the first reset signal terminal and transmits the first initialization signal received at the first initialization signal terminal to the fourth node; the first light-emitting sub-circuit responds to the first light-emitting signal received at the first light-emitting signal terminal and transmits the first voltage signal received at the first voltage signal terminal to the second node. Under the control of the voltage at the first node, the driving sub-circuit transmits the voltage at the second node to the third node and charges the third node.

15. The driving method according to claim 14, wherein A display frame cycle also includes a reset phase, which precedes the compensation phase, and the reset phase includes a first reset phase and a second reset phase; During the first reset phase, the second reset sub-circuit responds to the second reset signal received at the second reset signal terminal and transmits the first initialization signal received at the first initialization signal terminal to the first node; During the second reset phase, the second reset sub-circuit responds to the second reset signal received at the second reset signal terminal and transmits the first initialization signal received at the first initialization signal terminal to the first node; the first reset sub-circuit responds to the first reset signal received at the first reset signal terminal and transmits the first initialization signal received at the first initialization signal terminal to the fourth node.

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