Display panel and display apparatus

Abstract

Provided in the embodiments of the present application are a display panel and a display apparatus. By means of making the projection of data lines on a substrate non-overlap with the projection of an anode of a light-emitting device on the substrate, the display panel can reduce the parasitic capacitance between the data lines and the anode, such that the total capacitance on the data lines can be reduced. When the data lines are used for the input of a signal, the rise time and fall time of a charging signal can be reduced, thereby improving the charging rate, avoiding mis-charging, and avoiding display abnormalities.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used due to their advantages such as self-emission, wide color gamut, low power consumption, and the ability to achieve flexible displays. OLED displays are driven by pixel driving circuits. However, during the use of OLED displays, it has been found that the impedance of signal lines such as data lines and scan lines is relatively high, and the parasitic capacitance between data lines and scan lines and other signals is also large. When driving OLED displays, this can easily lead to increased rise and fall times of data lines and scan lines, resulting in insufficient pixel charging, poor display quality, and even mischarging, causing display abnormalities. Furthermore, for large-size displays, the impedance and parasitic capacitance of data lines and scan lines increase further, leading to insufficient pixel charging or even failure to charge pixels or mischarging, thus causing display abnormalities.

[0003] Therefore, existing display devices suffer from a technical problem where large parasitic capacitance in signal lines leads to poor display quality. Invention Overview

[0004] This application provides a display panel and a display device to solve the technical problem that existing display devices have large parasitic capacitance in signal lines, leading to poor display performance.

[0005] In a first aspect, embodiments of this application provide a display panel, the display panel comprising:

[0006] Substrate;

[0007] A driving circuit layer is disposed on one side of the substrate, and the driving circuit layer includes a pixel driving circuit and a data line electrically connected to the pixel driving circuit.

[0008] A light-emitting functional layer is disposed on the side of the driving circuit layer away from the substrate. The light-emitting functional layer includes a light-emitting device, and the anode of the light-emitting device is connected to the corresponding pixel driving circuit.

[0009] The projection of the data line onto the substrate does not overlap with the projection of the anode of the light-emitting device onto the substrate.

[0010] Secondly, embodiments of this application provide a display device, which includes a display panel as described in any of the above embodiments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0013] Figure 1 is a stack-up diagram of the various film layers of the comparative display device provided in the embodiments of this application.

[0014] Figure 2 is a plan view of the display panel provided in an embodiment of this application.

[0015] Figure 3 is a first cross-sectional schematic diagram of the display panel provided in an embodiment of this application.

[0016] Figure 4 is a second cross-sectional schematic diagram of the display panel provided in an embodiment of this application.

[0017] Figure 5 is a circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application.

[0018] Figure 6 is a stacked diagram of the film layers of the pixel unit of the display panel provided in the embodiment of this application.

[0019] Figure 7 is an exploded view of the active layer of the display panel in Figure 6.

[0020] Figure 8 is an exploded view of the first gate layer of the display panel in Figure 6.

[0021] Figure 9 is an exploded view of the second gate layer of the display panel in Figure 6.

[0022] Figure 10 is an exploded view of the first source-drain layer of the display panel in Figure 6.

[0023] Figure 11 is an exploded view of the second source-drain layer of the display panel in Figure 6.

[0024] Figure 12 is an exploded view of the pixel electrode layer of the display panel in Figure 6.

[0025] Figure 13 is an exploded view of another first source-drain layer in the display panel provided in the embodiment of this application. Embodiments of the present invention

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] In the description of this application, it should be understood that the terms "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified. In the description of this application, "perpendicular" means completely perpendicular to 90° or almost completely perpendicular, for example, the range of included angles between 80° and 100° is considered perpendicular. Similarly, "parallel" means completely parallel or almost completely parallel, for example, the range of completely parallel angles between 10° is considered parallel.

[0028] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" refers to a direct connection between two things, and "electrical connection" refers to a connection that can be direct or indirect through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] To illustrate the principle behind the technical problems in the embodiments of this application, this application provides a contrast display device. It should be understood that this contrast display device cannot be considered prior art in the embodiments of this application. As shown in Figure 1, the contrast display device includes multiple sub-pixel units. Each sub-pixel unit includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a data signal line 202, a first scan line 203, a second scan line 204, and a high-potential power signal line 205. As can be seen from Figure 1, the orthographic projection of the data signal line 202 overlaps with the anode 201 of the light-emitting device. Therefore, the data signal line 202 will generate coupling capacitance with the anode 201 of the light-emitting device, resulting in an increase in the total capacitance of the data signal line 202. Consequently, the voltage drop of the signal transmitted on the data signal line 202 will increase, and the rise time and fall time of the signal output by the data signal line 202 will increase, leading to insufficient pixel charging rate and even crosstalk problems caused by misalignment. As shown in Figure 1, both the first scan line 203 and the second scan line 204 are double-layered designs, with a large overlap area with the data signal line 202. This leads to a further increase in the total capacitance of the data signal line 202, and the scan lines are also affected by parasitic capacitance, resulting in crosstalk. Furthermore, as the size of the display device increases, the impedance and parasitic capacitance of the data lines and scan lines will further increase, potentially leading to insufficient pixel charging or even failure to charge pixels or mischarging, resulting in display abnormalities. Therefore, existing display devices suffer from the technical problem of large parasitic capacitance in the signal lines causing display defects.

[0030] This application provides a display panel and a display device to solve the above-mentioned technical problems.

[0031] Figure 2 is a plan view of the display panel provided in an embodiment of this application. Figure 3 is a first cross-sectional view of the display panel provided in an embodiment of this application. Figure 4 is a second cross-sectional view of the display panel provided in an embodiment of this application. Figure 5 is a circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application. Figure 6 is a stacked diagram of the film layers of the pixel unit of the display panel provided in an embodiment of this application. Figure 7 is an exploded view of the active layer of the display panel in Figure 6. Figure 8 is an exploded view of the first gate layer of the display panel in Figure 6. Figure 9 is an exploded view of the second gate layer of the display panel in Figure 6. Figure 10 is an exploded view of the first source-drain layer of the display panel in Figure 6. Figure 11 is an exploded view of the second source-drain layer of the display panel in Figure 6. Figure 12 is an exploded view of the pixel electrode layer of the display panel in Figure 6. Figure 13 is an exploded view of another first source-drain layer in the display panel provided in an embodiment of this application.

[0032] As shown in Figures 2 to 13, this application embodiment provides a display panel 1, which includes a substrate 11, a driving circuit layer 12, and a light-emitting functional layer 14. The driving circuit layer 12 is disposed on one side of the substrate 11, and includes a pixel driving circuit 120 and a data line Data connected to the pixel driving circuit 120. The light-emitting functional layer 14 is disposed on the side of the driving circuit layer 12 away from the substrate 11, and includes a light-emitting device LED. The anode of the light-emitting device LED is connected to the pixel driving circuit 120.

[0033] The projection of the data line Data on the substrate 11 does not overlap with the projection of the anode ANO of the light-emitting device LED on the substrate 11.

[0034] This application provides a display panel that reduces the parasitic capacitance between the data line and the anode by ensuring that the projection of the data line on the substrate does not overlap with the projection of the anode of the light-emitting device on the substrate. This reduces the total capacitance on the data line, and when using the data line as the input signal, it reduces the rise and fall times of the charging signal, thereby improving the charging rate, avoiding overshoot, and preventing display abnormalities.

[0035] Specifically, the non-overlapping of the projection of the data line onto the substrate and the projection of the anode of the light-emitting device onto the substrate means that the distance between the projections of the data line onto the substrate and the projections of the anode of the light-emitting device onto the substrate is greater than or equal to 0. This allows the distance between the projections of the data line onto the substrate and the projections of the anode of the light-emitting device onto the substrate to be greater than 0.

[0036] Specifically, it is understood that in a pixel driving circuit, each transistor has a gate, a first electrode, and a second electrode. However, in actual fabrication, to reduce the space occupied by the transistors, individual electrodes are not provided for some transistors. Instead, the electrodes and signal lines of each transistor are directly connected. For example, in a pixel driving circuit, the first electrode of driving transistor T1 and the second electrode of switching transistor T2 are connected to the first node A. When fabricating the driving transistor and the switching transistor, it is not necessary to separately provide the first electrode of the driving transistor and the second electrode of the switching transistor. The active pattern of the driving transistor is directly connected to the active pattern of the switching transistor. The connection point between the active pattern of the driving transistor and the switching transistor can be considered as the first node A, thereby reducing the number of transistor electrodes and reducing the space occupied by the transistors. Similarly, other structures not shown in the film layer diagram also adopt the above design, as described above. They will not be repeated in the following embodiments.

[0037] Specifically, in the actual fabrication process, in order to reduce the space occupied by transistors, another way is to make the electrodes of multiple transistors share the same structure, or the electrodes of transistors and signal lines share the same structure. For example, the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor. However, in actual design, it is not necessary to set the first electrode of the compensation transistor and the second electrode of the first initialization transistor separately. Instead, a single structure is used as the first electrode of the compensation transistor and the second electrode of the first initialization transistor. Similarly, for other cases where the same structure is used as the electrodes and / or signal lines of multiple transistors, please refer to the above description. It will not be repeated in the following embodiments.

[0038] Specifically, the display panel includes multiple repeating units. Each repeating unit may include one pixel unit, such as the pixel unit shown in Figure 6 of this embodiment, or a pixel unit whose initialization connection line is electrically connected to the first electrode of the first initialization transistor. A repeating unit may also include two pixel units. The difference between the two pixel units is that the initialization connection line in one pixel unit is electrically connected to the first electrode of the first initialization transistor, and the first electrode of the first initialization transistor is connected to the first initialization signal line, thereby reducing the voltage drop of the first initialization signal line. The initialization connection line in the other pixel unit is electrically connected to the second initialization signal line, thereby reducing the voltage drop of the second initialization signal line. For other parts, the two pixel units may be the same. The following embodiment uses a repeating unit including two pixel units as an example for illustration.

[0039] Specifically, the display panel 1 may include multiple pixel units 140. Each pixel unit 140 may include a first sub-pixel unit 140a, a second sub-pixel unit 140b, and a third sub-pixel unit 140c. Each of the first sub-pixel unit 140a, the second sub-pixel unit 140b, and the third sub-pixel unit 140c includes a pixel driving circuit 120 and a light-emitting device (LED). The design of the light-emitting devices of the first sub-pixel unit 140a, the second sub-pixel unit 140b, and the third sub-pixel unit 140c may be different. Specifically, the light-emitting colors of the light-emitting devices of the first sub-pixel unit 140a, the second sub-pixel unit 140b, and the third sub-pixel unit 140c may be different, and / or the areas of the light-emitting devices may be different, and / or the thickness of the light-emitting devices may be different.

[0040] Specifically, the emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit can be red, green, and blue, respectively. However, the embodiments of this application are not limited to this. For example, the emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit can be red, blue, and green, respectively, or the emission colors of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit can be blue, green, and red, respectively.

[0041] Specifically, in the embodiments of this application, it should be noted that, except for the differences explicitly stated, the design of all pixel units can refer to the pixel unit design provided in the embodiments of this application. Similarly, the design of all pixel driving circuits can refer to the pixel driving circuit design in the embodiments of this application. For example, the difference between two pixel driving circuits is that the high-potential power line in one pixel driving circuit is different from the high-potential power line in the other pixel driving circuit, while the other designs of the two pixel driving circuits are the same. Therefore, when describing the design of the pixel driving circuit, it can be assumed that, except for the difference in the high-potential power line, the other designs of the two pixel driving circuits are the same. Similarly, the differences and similar designs of the pixel units can be determined, which will not be repeated in the following embodiments.

[0042] Specifically, the above embodiments are illustrated by reducing the parasitic capacitance between the data line and the anode of the light-emitting device. However, the embodiments of this application are not limited to this. The parasitic capacitance between the data line and the scan line, and the parasitic capacitance between the scan line and the high-potential power line can be reduced, thereby reducing the total capacitance of the data line and / or the scan line, reducing the parasitic capacitance of each signal line in the display panel, and improving the display effect.

[0043] Specifically, the light-emitting functional layer 14 includes a light-emitting device LED, and the pixel electrode layer 141 in the light-emitting functional layer 14 includes the anode ANO of the light-emitting device LED.

[0044] Specifically, as shown in Figure 2, the display panel 1 includes a display area AA and a non-display area NA, with pixel units disposed within the display area AA.

[0045] Specifically, since this application describes the display panel from the perspectives of the display panel circuit, film layer structure, and the design of each film layer, some structures may belong to both one structure and another. This is because they are defined from different angles. For example, the pixel driving circuit belongs to the driving circuit layer, which is considered from the perspective of the film layer structure. The pixel driving circuit is formed by the structure in the driving circuit layer. In addition, the pixel unit includes the pixel driving circuit, which is considered from the perspective of the pixel unit design. Each pixel unit needs to be driven by the corresponding pixel driving circuit. It can be understood that the pixel driving circuit belonging to the two structures of the driving circuit layer and the pixel unit is the same pixel driving circuit. Similarly, other similar limitations can be found in the above description and will not be repeated in the following embodiments.

[0046] In some embodiments, as shown in Figures 2 to 13, the driving circuit layer 12 includes a first gate layer 124 and a first source-drain layer 128, wherein the first gate layer 124 is disposed between the substrate 11 and the first source-drain layer 128.

[0047] The first gate layer 124 includes a first scan connection line SL1, and the first source-drain layer 128 includes a first scan signal line Scan(n). The first scan connection line SL1 is connected to the first scan signal line Scan(n). The projection of the first scan signal line Scan(n) on the substrate 11 overlaps with the projection of the data line Data on the substrate 11, but the projection of the first scan connection line SL1 on the substrate 11 does not overlap with the projection of the data line Data on the substrate. By ensuring that the projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate, the parasitic capacitance of the scan signal line and the data line can be reduced.

[0048] Specifically, compared to the dual-layer design of the first scan line 203 in the contrast display device, where the two parts of the first scan line 203 cannot overlap in order to avoid the routing of the second node, resulting in two overlaps between the first scan line 203 and a data signal line, this embodiment of the application makes the first scan signal line a single-layer design. The first scan connection line is connected to the first scan signal line to drive the transistor. The projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate, which can reduce the parasitic capacitance between the scan signal line and the data line.

[0049] In some embodiments, as shown in Figures 2 to 13, the driving circuit layer 12 further includes a second source-drain layer 132, which is disposed on the side of the first source-drain layer 128 away from the first gate layer 124. The second source-drain layer 132 also includes a high-potential power supply line VDD. The first scan connection line SL1 includes a connection portion SL1a and a functional portion SL1b. The connection portion SL1a connects the functional portion SL1b and the first scan signal line Scan(n).

[0050] Wherein, the projection of the connecting part SL1a on the substrate 11 does not overlap with the projection of the high-potential power line VDD on the substrate 11, and the projection of a part of the functional part SL1b on the substrate 11 does not overlap with the projection of the high-potential power line VDD on the substrate 11, thereby reducing the overlap area between the scan signal line and the high-potential power line and reducing parasitic capacitance.

[0051] In some embodiments, as shown in Figures 2 to 13, the first source-drain layer 128 further includes a second scan signal line Reset-Q, and the first gate layer 124 further includes a second scan connection line SL2. The second scan connection line SL2 is connected to the second scan signal line Reset-Q. The projection of the second scan signal line Reset-Q on the substrate 11 overlaps with the projection of the data line Data on the substrate 11, while the projection of the second scan connection line SL2 on the substrate 11 does not overlap with the projection of the data line Data on the substrate 11.

[0052] Specifically, compared to the dual-layer design of the second scan line 204 in the contrast display device, where the two parts of the second scan line located on different metal layers overlap with the data line respectively, resulting in two overlaps between the second scan line and the data line (although there will be overlapping parts), leading to a large parasitic capacitance of the second scan line and the data signal line, this embodiment of the application makes the second scan signal line a single-layer design. The second scan connection line is connected to the second scan signal line to drive the transistor. The projection of the second scan connection line on the substrate does not overlap with the projection of the data line on the substrate, which can reduce the parasitic capacitance of the scan signal line and the data line.

[0053] In some embodiments, as shown in Figures 2 to 13, the driving circuit layer 12 further includes a first initialization signal line VI-Q, and the distance between the projection of the second scan signal line Reset-Q on the substrate 11 and the projection of the first initialization signal line VI-Q on the substrate 11 is smaller than the distance between the projection of the second scan signal line Reset-Q on the substrate 11 and the projection of the first scan signal line Scan(n) on the substrate 11.

[0054] Specifically, compared to the situation in contrast display devices where the spacing between the first and second scan lines is relatively close in order to make the first scan line a double-layer design, which may lead to a short circuit, the embodiments of this application increase the spacing between the first and second scan signal lines by making the spacing between the first scan signal line and the second scan signal line smaller than the spacing between the projections of the second scan signal line and the first initialization signal line on the substrate, thereby reducing the risk of short circuit between the two.

[0055] In some embodiments, as shown in Figures 2 to 13, the display panel includes a plurality of pixel units 140 arranged in an array. Each pixel unit 140 includes a plurality of sub-pixel units (e.g., a first sub-pixel unit 140a, a second sub-pixel unit 140b, and a third sub-pixel unit 140c). The driving circuit layer 12 includes a first via and a high-potential power line VDD. The first scan signal line Scan(n) passes through the first via and is connected to the first scan connection line SL1. The first via is disposed between the data line Data and the high-potential power line VDD within the same sub-pixel unit.

[0056] In some embodiments, as shown in Figures 2 to 13, the pixel driving circuit 120 includes a compensation transistor T3 and a driving transistor T1, a first light-emitting control transistor T5, and a second light-emitting control transistor T6 connected in series between the high-potential power line VDD and the anode of the light-emitting device LED.

[0057] The driving circuit layer 12 includes a first gate layer 124, a first source-drain layer 128, and a second source-drain layer 132. The first gate layer 124 is disposed between the substrate 11 and the first source-drain layer 128. The first source-drain layer 128 is disposed between the first gate layer 124 and the second source-drain layer 132. The first gate layer 124 includes the gate T1G of the driving transistor T1. The first source-drain layer 128 includes the first electrode T3S of the compensation transistor T3 and the second electrode T6D of the light-emitting control transistor T6. The second source-drain layer 132 includes a high-potential power line VDD and an anode connection line ANO-L.

[0058] The display panel 1 further includes a second via, a third via, and a fourth via. The first electrode T3S of the compensation transistor T3 passes through the second via and is connected to the gate of the driving transistor T1. The anode of the light-emitting device LED passes through the third via and is connected to the anode connection line ANO-L. The anode connection line ANO-L passes through the fourth via and is connected to the second electrode T6D of the second light-emitting control transistor T6. The second via is correspondingly disposed to the gate T1G of the driving transistor T1, and the third and fourth vias are correspondingly disposed to the anode connection line ANO-L.

[0059] Specifically, it is understandable that since each via is filled with a structure and the film layers are stacked, the position of each via cannot be seen. It is understandable that the position of each via can be determined based on the position of each structure.

[0060] In some embodiments, as shown in FIG5, the pixel driving circuit 120 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first initialization transistor T4. The gate T2G of the switching transistor T2 is connected to the first scan signal line Scan(n), the first electrode of the switching transistor T2 is connected to the data line Data, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at a first node A. The gate of the compensation transistor T3 is connected to the first scan signal line Scan(n), the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at a second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1 at a third node B. The gate of the first initialization transistor T4 is connected to the second scan signal line Reset-Q, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-Q, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at a second node Q.

[0061] Specifically, the projection of the first scan signal line Scan(n) on the substrate 11 overlaps with the projection of the data line Data on the substrate 11 at one point, and / or the projection of the second scan signal line Reset-Q on the substrate 11 overlaps with the projection of the data line Data on the substrate 11 at one point. By ensuring that the projections of the first scan signal line and the data line on the substrate overlap at one point, and / or the projections of the second scan signal line and the data line on the substrate overlap at one point, the overlap area between the first scan signal line and the data line can be reduced, and / or the overlap area between the second scan signal line and the data line can be reduced. This reduces the parasitic capacitance of the first scan signal line and the data line, and / or reduces the parasitic capacitance of the second scan signal line and the data line, thus reducing the total capacitance of the first scan signal line, and / or the total capacitance of the second scan signal line, and the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and enhance display effect.

[0062] Specifically, the projection of a first scan signal line on the substrate and the projection of a data line on the substrate can overlap at one point, thereby reducing the overlap area between the first scan signal line and the data line, thus reducing the parasitic capacitance of the first scan signal line and the data line, reducing the total capacitance of the first scan signal line and the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0063] Specifically, the projection of the second scan signal line on the substrate and the projection of the data line on the substrate can overlap at one point, thereby reducing the overlap area between the second scan signal line and the data line, thus reducing the parasitic capacitance of the second scan signal line and the data line, reducing the total capacitance of the second scan signal line and the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0064] Specifically, the projections of the first scan signal line and the data line on the substrate can overlap at one point, and the projections of the second scan signal line and the data line on the substrate can also overlap at one point. This reduces the overlap area between the first and second scan signal lines and the data line, thereby reducing the parasitic capacitance of the first and second scan signal lines and the data line, and ultimately reducing the total capacitance of the first, second, and data lines. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and enhance the display effect.

[0065] Specifically, it can be seen that the first scan line 203 in the comparison display device adopts a double-layer design, and the two parts of the first scan line 203 cannot overlap in order to avoid the routing of the second node. This results in two overlaps between the first scan line 203 and a data signal line, and the parasitic capacitance of the first scan line and the data signal line is relatively large. However, in the embodiment of this application, by having the projection of a first scan signal line on the substrate overlap with the projection of a data line on the substrate at one point, the overlap area of ​​the first scan signal line and the data line can be reduced, thereby reducing the parasitic capacitance of the first scan signal line and the data line, reducing the total capacitance of the first scan signal line, and reducing the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0066] Specifically, it can be seen that the second scan line 204 in the comparison display device adopts a double-layer design. The two parts of the second scan line located in different metal layers overlap with the data line respectively, resulting in two overlaps between the second scan line and the data line (although there will be overlapping parts in the two overlaps). This leads to a large parasitic capacitance of the second scan line and the data signal line. In this embodiment, by making the projection of a second scan signal line on the substrate overlap with the projection of a data line on the substrate at one point, the parasitic capacitance of the second scan signal line and the data line can be reduced, the total capacitance of the second scan signal line can be reduced, and the total capacitance of the data line can be reduced. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0067] Specifically, it can be understood that the display panel includes multiple first scan signal lines, each of which can drive one row of pixel units. The first scan signal line Scan(n) is the nth first scan signal line among the multiple first scan signal lines, where n is greater than or equal to 1 and is a positive integer. The first scan signal line Scan(n) can be connected to a gate driving circuit to input signals, or it can directly input signals through a driver chip. Similarly, the display panel can include multiple second scan signal lines and multiple third scan signal lines, each of which drives one row of pixel units. The second and third scan signal lines can also be connected to a gate driving circuit or input signals through a driver chip. The gate driving circuit connected to the second and third scan signal lines can be the same as or different from the gate driving circuit connected to the first scan signal lines.

[0068] In some embodiments, as shown in Figures 3 to 13, the display panel 1 further includes a high-potential power line VDD, which is electrically connected to the pixel driving circuit 120. The projection of the high-potential power line VDD on the substrate 11 overlaps with the projection of the first scan signal line Scan(n) on the substrate. The width K1 of the portion of the high-potential power line VDD corresponding to the first scan signal line Scan(n) is less than or equal to the width of other portions of the high-potential power line VDD (for example, in Figure 11, the width K1 of the portion of the high-potential power line VDD corresponding to the first scan signal line is equal to the width K1 of the portion of the high-potential power line VDD corresponding to the first electrode of the first light-emitting control transistor; the width K1 of the portion of the high-potential power line VDD corresponding to the first scan signal line is less than the width K2 of the portion of the high-potential power line VDD corresponding to the second electrode of the storage capacitor). By making the width of the portion of the high-potential power line corresponding to the first scan signal line smaller than or equal to the width of the other portions of the high-potential power line, the parasitic capacitance of the first scan signal line and the high-potential power line is reduced, thereby reducing the total capacitance of the first scan signal line and the high-potential power line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and enhance display effect.

[0069] Specifically, as shown in Figures 1 and 6, it can be seen that the overlap between the high-potential power signal line 205 and the first scan line 203 in the comparison display device is relatively large, resulting in a large parasitic capacitance between the two. In this embodiment, by making the width of the portion corresponding to the high-potential power signal line and the first scan signal line less than or equal to the width of other portions of the high-potential power line, the parasitic capacitance between the first scan signal line and the high-potential power line is reduced, thereby reducing the total capacitance of the first scan signal line and the high-potential power line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and enhance the display effect.

[0070] Specifically, the width of the portion of the high-potential power signal line corresponding to the first scan signal line can be the minimum width of the high-potential power signal line, and the width of the portion of the high-potential power signal line corresponding to the first electrode of the first light-emitting control transistor can be the minimum width or greater than the minimum width of the high-potential power signal line.

[0071] Specifically, the width of the portion of the high-potential power signal line corresponding to the first scan signal line is 7 micrometers.

[0072] In some embodiments, as shown in Figures 3 to 13, the display panel 1 includes a plurality of pixel units 140 arranged in an array. Each pixel unit 140 includes a first sub-pixel unit 140a, a second sub-pixel unit 140b, and a third sub-pixel unit 140c. The first sub-pixel unit 140a includes a first light-emitting device 241, the second sub-pixel unit 140b includes a second light-emitting device 242, and the third sub-pixel unit 140c includes a third light-emitting device 243. The areas of the anodes ANO1 of the first light-emitting device 241, ANO2 of the second light-emitting device 242, and ANO3 of the third light-emitting device 243 are different from each other. Since different light-emitting devices have different luminous efficiencies, by making the areas of the anodes of the first, second, and third light-emitting devices different, the volume of the light-emitting devices can be set according to their luminous efficiency, ensuring consistent brightness across all devices and improving the display effect.

[0073] Specifically, it can be understood that a light-emitting device (LED) includes a first light-emitting device, a second light-emitting device, and a third light-emitting device, and the anode of the light-emitting device includes the anode of the first light-emitting device, the anode of the second light-emitting device, and the anode of the third light-emitting device.

[0074] Specifically, as shown in Figures 3 and 4, the light-emitting functional layer 14 includes a pixel electrode layer 141, a pixel definition layer 142, a light-emitting material layer 143, and a common electrode layer 144. The light-emitting material layer 143 includes a first light-emitting material layer 143a, a second light-emitting material layer 143b, and a third light-emitting material layer 143c, each emitting a different color. Specifically, the pixel electrode layer forms the anode of the light-emitting device, the light-emitting material layer forms the light-emitting material of the light-emitting device, and the common electrode forms the cathode of the light-emitting device.

[0075] Specifically, taking the first light-emitting material layer 143a, the second light-emitting material layer 143b, and the third light-emitting material layer 143c as examples, where the light-emitting colors are red, green, and blue respectively, since the luminous efficiency of each light-emitting material is different, specifically, the luminous efficiency of the blue light-emitting material is the lowest and the luminous efficiency of the red light-emitting material is the highest, the area of ​​the anode of the first light-emitting device can be smaller than the area of ​​the anode of the second light-emitting device, and the area of ​​the anode of the second light-emitting device is smaller than the area of ​​the anode of the third light-emitting device.

[0076] In some embodiments, as shown in Figures 3 to 13, in the first direction X, the width of the anode ANO1 of the first light-emitting device 241 is smaller than the width of the anode ANO2 of the second light-emitting device 242; the width of the anode ANO2 of the second light-emitting device 242 is smaller than the width of the anode ANO3 of the third light-emitting device 243; and the angle between the first direction X and the extension direction of the data line Data is greater than 0 and less than or equal to 90 degrees. By making the width of the anode of the first light-emitting device smaller than the width of the anode of the second light-emitting device, and the width of the anode of the second light-emitting device smaller than the width of the anode of the third light-emitting device, the volume of the light-emitting devices can be set according to the luminous efficiency of each light-emitting device, so that the luminous brightness of each light-emitting device can be consistent, thereby improving the display effect.

[0077] In some embodiments, as shown in Figures 3 to 13, the distance between the anode ANO1 of the first light-emitting device 241 and the anode ANO2 of the second light-emitting device 242 is equal to the distance between the anode ANO2 of the second light-emitting device 242 and the anode ANO3 of the third light-emitting device 243; the distance between the anode ANO1 of the first light-emitting device 241 and the anode ANO2 of the second light-emitting device 242 is equal to the distance between the anode ANO3 of the third light-emitting device 243 and the anode ANO1 of the first light-emitting device 241. By making the distance between the anodes of the first and second light-emitting devices equal to the distance between the anodes of the second and third light-emitting devices, and the distance between the anodes of the first and second light-emitting devices equal to the distance between the anodes of the third light-emitting device and the anode of the first light-emitting device, data lines can be set between each light-emitting device, reducing the impedance of the initialization signal line, without occupying too much space, and increasing the aperture ratio. In some embodiments, as shown in Figure 5, the pixel driving circuit 120 further includes:

[0078] The first light-emitting control transistor T5 has its gate connected to the light-emitting control signal line EM, its first electrode connected to the high-potential power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A.

[0079] The second light-emitting control transistor T6 has its gate connected to the light-emitting control signal line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B.

[0080] The second initialization transistor T7 has its gate connected to the third scan signal line Reset-A, its first electrode connected to the second initialization signal line VI-A, its second electrode connected to the second light-emitting control transistor T6 at the fourth node C, and its second electrode connected to the anode of the light-emitting device LED at the fourth node C.

[0081] A storage capacitor Cst, one plate of which is connected to the high-potential power line VDD, and the other plate of which is connected to the gate of the driving transistor T1 at the second node Q.

[0082] Specifically, as shown in Figure 5, the cathode of the light-emitting device LED is connected to the low-potential power line VSS.

[0083] In some embodiments, as shown in FIG3, the driving circuit layer 12 includes an active layer 122, a first gate layer 124, a second gate layer 126, a first source-drain layer 128, and a second source-drain layer 132. The first gate layer 124 is disposed on the side of the active layer 122 away from the substrate, the second gate layer 126 is disposed on the side of the first gate layer 124 away from the active layer 122, the first source-drain layer 128 is disposed on the side of the second gate layer 126 away from the first gate layer 124, and the second source-drain layer 132 is disposed on the side of the first source-drain layer 128 away from the second gate layer 126.

[0084] Specifically, as shown in Figure 3, the driving circuit layer 12 further includes a buffer layer 121, a first gate insulating layer 123, a second gate insulating layer 125, an interlayer insulating layer 127, a passivation layer 129, a first planarization layer 131, a second planarization layer 133, and a third planarization layer 134. The buffer layer 121 is disposed between the substrate 11 and the active layer 122. The first gate insulating layer 123 is disposed between the active layer 122 and the first gate layer 124. The second gate insulating layer 125 is disposed between the first gate layer 124 and the second gate layer 126. The interlayer insulating layer 127 is disposed between the second gate layer 126 and the first source / drain layer 128. The passivation layer 129 is disposed between the first source / drain layer 128 and the first planarization layer 131. The first planarization layer 131 is disposed between the second source / drain layer 132 and the passivation layer 129. The second planarization layer 133 is disposed between the second source / drain layer 132 and the third planarization layer 134.

[0085] Specifically, as shown in Figure 3, the light-emitting functional layer 14 also includes a pixel definition layer 142, a light-emitting material layer 143, and a common electrode layer 144.

[0086] Specifically, the pixel definition layer 142 may include a first pixel definition layer 142a and a second pixel definition layer 142b, and the pixel definition layer may also be a single-layer design.

[0087] In some embodiments, as shown in Figures 6 and 7, the driving circuit layer 12 further includes an active layer 122. The display panel 1 includes a plurality of pixel units 140 arranged in an array. Each pixel unit 140 includes three pixel driving circuits 120. In each pixel driving circuit 120, the active layer 122 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T3A of a compensation transistor T3, an active pattern T4A of a first initialization transistor T4, and an active pattern T5A of a first light-emitting control transistor T5. The active pattern T6A of the second light-emitting control transistor T6, the active pattern T7A of the second initialization transistor T7, the first portion VI-Q-1 of the first initialization signal line VI-Q, and the first portion VI-A-1 of the second initialization signal line VI-A, the active pattern T1A of the driving transistor T1, the first portion VI-Q-1 of the first initialization signal line VI-Q, and the first portion VI-A-1 of the second initialization signal line VI-A are arranged along the first direction X, and the active pattern T2A of the switching transistor T2 and the active pattern T7A of the first initialization transistor T4 are also present. Pattern T4A, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6, and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y. The active pattern T3A of the compensation transistor T3 includes a portion arranged along the first direction X and a portion arranged along the second direction Y. The active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T3A of the compensation transistor T3, the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y. The active pattern T6A of T6 is connected, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, the first part VI-Q-1 of the first initialization signal line VI-Q is connected to the active pattern T4A of the first initialization transistor T4, and the first part VI-A-1 of the second initialization signal line VI-A is connected to the active pattern T7A of the second initialization transistor T7.

[0088] The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0089] Specifically, as shown in Figures 6 and 7, it can be seen that in a row of pixel units, the first part of the first initialization signal line VI-Q, VI-Q-1, is continuous, and the first part of the second initialization signal line VI-A, VI-A-1, is continuous.

[0090] Specifically, Figures 6 to 13 are partial views of two rows of pixel units, so it can be seen that the second initialization transistor is located above the compensation transistor.

[0091] In some embodiments, as shown in Figures 3 to 6 and Figure 8, the driving circuit layer 12 further includes a first gate layer 124. In each pixel driving circuit 120, the first gate layer 124 includes the gate T1G of the driving transistor T1, the gate T2G of the switching transistor T2, the gate T3G of the compensation transistor T3, the gate T4G of the first initialization transistor T4, the gate T5G of the first light-emitting control transistor T5, the gate T6G of the second light-emitting control transistor T6, the gate T7G of the second initialization transistor T7, the first plate Cst1 of the storage capacitor Cst, the first portion EM1 of the light-emitting control line EM, and the first portion Reset-A-1 of the third scan signal line Reset-A. The first portion Reset-A-1 of the third scan signal line Reset-A, the gate T4G of the first initialization transistor T4, the gate T3G of the compensation transistor T3, the gate T1G of the driving transistor T1, and the first portion EM1 of the light-emitting control line EM are sequentially spaced along the second direction Y.

[0092] Specifically, as shown in Figures 6 and 8, it can be seen that in a row of pixel units, the first part of the third scan signal line Reset-A, Reset-A-1, is continuous, and the first part of the light emission control line EM, EM1, is continuous.

[0093] Specifically, as shown in Figure 8, the gate T2G of the switching transistor T2 is connected to the gate T3G of the compensation transistor T3.

[0094] Specifically, as shown in Figure 8, some structures are identified by multiple marks. This is because the electrodes and signal lines share the same structure, and the signals transmitted on this structure are the same (ignoring voltage drop). For example, the gate T7G of the second initialization transistor T7 and the first part EM1 of the light-emitting control line EM are identified by the same structure. This is because the first part of the light-emitting control line EM corresponds to the part of the second initialization transistor T7 as the gate T7G of the second initialization transistor T7. Similarly, the meaning of other structures identified by multiple marks can be determined.

[0095] Specifically, as shown in Figures 6 to 8, it can be understood that the gate of each transistor is set in correspondence with the active pattern of each transistor. For example, the gate T3G of the compensation transistor is set in correspondence with the active pattern T3A of the compensation transistor T3.

[0096] In some embodiments, as shown in Figures 5 to 8, the gate T3G of the compensation transistor T3 includes a first gate T3Ga and a second gate T3Gb. The first gate T3Ga and the second gate T3Gb are connected. By making the gate of the compensation transistor a dual-gate design, the gate control capability of the display panel can be improved and the leakage current can be reduced.

[0097] In some embodiments, as shown in Figures 5 to 8, the gate T4G of the first initialization transistor T4 includes a third gate T4Ga and a fourth gate T4Gb, with the third gate T4Ga and the fourth gate T4Gb connected. By making the gate of the first initialization transistor a dual-gate design, the gate control capability of the display panel can be improved and the leakage current reduced.

[0098] In some embodiments, as shown in Figures 3 to 6 and Figure 9, the driving circuit layer 12 further includes a second gate layer 126. In each pixel driving circuit 120, the second gate layer 126 includes a second portion VI-Q-2 of a first initialization signal line VI-Q, a first power connection line VDD-L1, a second electrode Cst2 of a storage capacitor Cst, and a repair line Record. The first power connection line VDD-L1 is connected to the second electrode Cst2 of the storage capacitor Cst. The second portion VI-Q-2 of the first initialization signal line VI-Q, the first power connection line VDD-L1, and the repair line Record are sequentially spaced along the second direction Y. The second portion VI-Q-2 of the first initialization signal line VI-Q is connected to the first portion VI-Q-1 of the first initialization signal line VI-Q. By connecting the first portion of the first initialization signal line and the second portion of the second initialization signal line, the impedance of the first initialization signal line can be reduced.

[0099] Specifically, as shown in Figures 6 and 9, it can be seen that in a row of pixel units, the second part of the first initialization signal line VI-Q, VI-Q-2, is continuous.

[0100] Specifically, as shown in Figures 6 and 9, the first power supply connection line VDD-L1 is connected to the second plate Cst2 of the storage capacitor Cst. The second plate Cst2 of the storage capacitor Cst is provided with a second via. The second plate Cst2 of the storage capacitor Cst is correspondingly set with the first plate Cst1 of the storage capacitor Cst. The first electrode of the compensation transistor can pass through the second via and be connected to the gate of the driving transistor.

[0101] Specifically, as shown in Figure 9, by setting a repair line (Record) in the pixel unit, when a sub-pixel unit or pixel unit malfunctions, the connection between the anode of the corresponding light-emitting device of the sub-pixel unit and the pixel driving circuit can be disconnected, and the repair line can be directly connected to the anode of the sub-pixel unit to directly drive the sub-pixel unit and avoid dark spots. When the sub-pixel unit or pixel unit is not malfunctioning, the repair line (Record) can be left floating.

[0102] In some embodiments, as shown in Figures 3 to 6 and Figure 10, the driving circuit layer 12 further includes a first source-drain layer 128. In each pixel driving circuit 120, the first source-drain layer 128 includes a first electrode T2S of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a first electrode T4S of a first initialization transistor T4, a second electrode T4D of a first initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a second initialization transistor T7, a second electrode T7D of a second initialization transistor T7, a second portion VI-A-2 of a second initialization signal line VI-A, a first scan signal line Scan(n), a second scan signal line Reset-Q, and a third scan signal line Reset-Q. The second part of t-A, Reset-A-2, the second part of the light emission control line EM, EM2, and the second power supply connection line VDD-L2; the second part of the third scan signal line Reset-A, Reset-A-2, the second part of the second initialization signal line VI-A, VI-A-2, the first electrode T4S of the first initialization transistor T4, the second scan signal line Reset-Q, the first scan signal line Scan(n), the first electrode T2S of the switching transistor T2, the second power supply connection line VDD-L2, the second part of the light emission control line EM2, and the first electrode T5S of the first light emission control transistor T5 are arranged sequentially at intervals along the second direction Y, and the second power supply connection line VDD-L2 is connected to the second plate Cst2 of the storage capacitor Cst.

[0103] Specifically, as shown in Figures 6 to 10, the first and second electrodes of each transistor are connected to the active pattern of each transistor.

[0104] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the second part of the third scan signal line Reset-A, Reset-A-2, is connected to the first part of the third scan signal line Reset-A, Reset-A-1, thereby reducing the impedance of the third scan signal line.

[0105] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the second part VI-A-2 of the second initialization signal line VI-A is continuous, and the second part VI-A-2 of the second initialization signal line VI-A is connected to the first part VI-A-1 of the second initialization signal line VI-A, thereby reducing the impedance of the second initialization signal line.

[0106] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the second scan signal line Reset-Q is continuous, and the second scan signal line Reset-Q is connected to the gate T4G of the first initialization transistor T4 in each pixel driving circuit.

[0107] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the first scan signal line Scan(n) is continuous, and the first scan signal line Scan(n) is connected to the gate T2G of the switching transistor T2 in each pixel driving circuit.

[0108] Specifically, as shown in Figures 6 to 10, the first electrode T3S of the compensation transistor T3 passes through the second via and is connected to the gate T1G of the driving transistor T1.

[0109] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the second power connection line VDD-L2 is continuous and connected to the second plate Cst2 of the storage capacitor Cst, so that the second power connection line VDD-L2 is connected to the first power connection line VDD-L1, thereby reducing the impedance of the high-potential power line.

[0110] Specifically, as shown in Figures 6 to 10, it can be seen that in a row of pixel units, the second part EM2 of the light emission control line EM is continuous, and the second part EM2 of the light emission control line EM is connected to the first part EM1 of the light emission control line EM, thereby reducing the impedance of the light emission control line.

[0111] Specifically, as shown in Figures 6 to 13, the second scan signal line Reset-Q adopts a single-layer trace design. Compared with the double-layer design of the second scan line in the comparison display device, this results in a larger parasitic capacitance between the second scan line and the data signal line. The embodiments of this application can reduce the parasitic capacitance between the second scan signal line and the data line, reduce the total capacitance of the second scan signal line, and reduce the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0112] In some embodiments, the display panel 1 includes a plurality of pixel units 140 arranged in an array, and the driving circuit layer 12 further includes a first gate layer 124, a second gate layer 126, a first source-drain layer 128, and a second source-drain layer 132. The second gate layer 126 includes a first power connection line VDD-L1, and the first source-drain layer 128 includes a second power connection line VDD-L2. The second power connection line VDD-L2 connects the first power connection line VDD-L1 and the high-potential power line VDD.

[0113] In some embodiments, as shown in Figures 3 to 6 and Figure 11, the driving circuit layer 12 further includes a second source-drain layer 132. In each pixel unit 140, the second source-drain layer 132 includes three data lines Data, three high-potential power lines VDD, one low-potential power line VSS, one initialization connection line VI-AL, and three anode connection lines ANO-L. The three data lines Data and the three high-potential power lines VDD are alternately arranged along the first direction X. The low-potential power line VSS is disposed between one data line Data and one high-potential power line VDD. The initialization connection line VI-AL is disposed between another data line Data and another high-potential power line VDD. Each anode connection line ANO-L is disposed between one high-potential power line VDD and one data line Data. The three high-potential power lines VDD are connected to the second power connection line VDD-L2.

[0114] Specifically, as shown in Figures 6 and 11, the data line (Data), high-potential power line (VDD), low-potential power line (VSS), initialization connection line (VI-AL), and anode connection line (ANO-L) are all set along the second direction Y.

[0115] Specifically, as shown in Figures 6 to 11, the data line Data is connected to the first electrode T2S of the switching transistor T2, and the high-potential power line VDD is connected to the second power connection line VDD-L2. This allows for the meshing of the high-potential power line VDD, reducing its impedance. It can be understood that the signals on the first and second power connection lines are signals from the high-potential power line, and the first and second power connection lines can be considered as part of the high-potential power line.

[0116] In some embodiments, as shown in Figures 3 to 6 and Figures 11 to 12, the light-emitting functional layer 14 includes a pixel electrode layer 141. In each pixel unit 140, the pixel electrode layer 141 includes the anodes ANO of three light-emitting devices LED. The anodes ANO of each light-emitting device LED are connected to an anode connection line ANO-L, and the anode connection line ANO-L is connected to the second electrode T6D of a second light-emitting control transistor T6.

[0117] Specifically, the projection of the anode of the light-emitting device onto the substrate overlaps with the projection of the high-potential power line onto the substrate.

[0118] Specifically, as shown in Figure 12, the anode ANO of the light-emitting device LED is arranged along the second direction Y, and the anodes ANO of multiple light-emitting devices LED are spaced apart along the first direction X. The anode ANO of each light-emitting device LED is connected to the anode connecting line ANO-L, and the anode connecting line ANO-L is connected to the second electrode T6D of the second light-emitting control transistor T6, thereby realizing the connection between the light-emitting device and the second light-emitting control transistor.

[0119] Specifically, the projection of the anode of the second light-emitting device onto the substrate overlaps with the projection of the initialization connection line onto the substrate, and the projection of the anode of the third light-emitting device onto the substrate overlaps with the projection of the low-potential power line onto the substrate.

[0120] In some embodiments, the pixel driving circuit further includes a first light-emitting control transistor.

[0121] In some embodiments, as shown in Figures 3 to 13, the display panel 1 includes a plurality of pixel units 140 arranged in an array. Each pixel unit 140 includes a first sub-pixel unit 140a, a second sub-pixel unit 140b, and a third sub-pixel unit 140c. The first sub-pixel unit 140a includes a first light-emitting device 241, the second sub-pixel unit 140b includes a second light-emitting device 242, and the third sub-pixel unit 140c includes a third light-emitting device 243. The pixel driving circuit 120 includes a first pixel driver that is electrically connected to the anode of the first light-emitting device 241, the anode of the second light-emitting device 242, and the anode of the third light-emitting device 243, respectively. The circuit includes a second pixel driving circuit 120a, a second pixel driving circuit 120b, and a third pixel driving circuit 120c. The data line Data includes a first data line Data-R, a second data line Data-G, and a third data line Data-B, which are electrically connected to the first pixel driving circuit 120a, the second pixel driving circuit 120b, and the third pixel driving circuit 120c, respectively. The high-potential power line VDD includes a first high-potential power line VDD1, a second high-potential power line VDD2, and a third high-potential power line VDD3, which are electrically connected to the first pixel driving circuit 120a, the second pixel driving circuit 120b, and the third pixel driving circuit 120c, respectively.

[0122] Specifically, the distance between the portion where the first high-potential power line VDD1 connects to the second power connection line VDD2 and the first data line Data-R is greater than the distance between the portion where the first high-potential power line VDD1 connects to the first electrode T5S of the first light-emitting control transistor T5 and the first data line Data-R; the distance between the portion where the second high-potential power line VDD2 connects to the second power connection line VDD-L2 and the second data line Data-G is equal to the distance between the portion where the second high-potential power line VDD2 connects to the first electrode T5S of the first light-emitting control transistor T5 and the second data line Data-G; and the distance between the portion where the third high-potential power line VDD3 connects to the second power connection line VDD-L2 and the third data line Data-B is equal to the distance between the portion where the third high-potential power line VDD3 connects to the first electrode T5S of the first light-emitting control transistor T5 and the third data line Data-B; thus ensuring that the distance between the openings of the second and third planarization layers and the sidewalls of the pixel definition layer meets the requirements.

[0123] Specifically, the first data line Data-R, the second data line Data-G, and the third data line Data-B can correspond to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit, respectively. It can be understood that when the display panel is used, the brightness of different sub-pixel units can be the same or different. Therefore, there may be situations where different driving voltages are used to drive different sub-pixel units. This allows the first data line Data-R, the second data line Data-G, and the third data line Data-B to input different voltages, so that each sub-pixel unit displays the corresponding brightness.

[0124] Specifically, the first high-potential power line VDD1, the second high-potential power line VDD2, and the third high-potential power line VDD3 can correspond to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit, respectively. The first high-potential power line VDD1, the second high-potential power line VDD2, and the third high-potential power line VDD3 can be the same or different.

[0125] In some embodiments, the pixel driving circuit further includes a second light-emitting control transistor.

[0126] In some embodiments, as shown in Figures 6 and 10, within each pixel unit 140, the first source-drain layer 128 includes three second electrodes T6D of the second light-emitting control transistors T6 respectively located within three pixel driving circuits 120. The area of ​​the second electrode T6D of one second light-emitting control transistor T6 is larger than the area of ​​the second electrodes T6D of the other two second light-emitting control transistors T6. By making the area of ​​the second electrode of one second light-emitting control transistor larger than the area of ​​the second electrodes of the other two second light-emitting control transistors, each second light-emitting control transistor can be connected to the anode of the light-emitting device via an anode connection line.

[0127] In some embodiments, as shown in Figures 6 to 13, within two adjacent pixel units 140, one pixel unit 140 has a first connecting line L1, and the other pixel unit 140 has a second connecting line L2. The first connecting line L1 is connected to the initialization connecting line VI-AL and the second portion VI-A-2 of the second initialization signal line VI-A within the corresponding pixel unit 140. The second connecting line L2 is connected to the initialization connecting line VI-AL and the first electrode T4S of the first initialization transistor T4 within the corresponding pixel unit 140. By having one pixel unit have a first connecting line connecting the initialization connecting line and the second portion of the second initialization signal line, the initialization connecting line can reduce the impedance of the second initialization signal line. Similarly, by having the other pixel unit have a second connecting line connecting the initialization connecting line and the first electrode of the first initialization transistor, the initialization connecting line can reduce the impedance of the first initialization signal line.

[0128] Specifically, the initialization connection line and the second initialization signal line can be connected outside the display area to realize the mesh structure design of the second initialization signal line, and the initialization connection line and the first initialization signal line can be connected outside the display area to realize the mesh structure design of the first initialization signal line.

[0129] Specifically, the display panel may include multiple repeating units, each repeating unit comprising two pixel units. The difference between the two pixel units is that one pixel unit has a first connecting line, while the other pixel unit has a second connecting line. The first connecting line is connected to the initialization connecting line and the second part of the second initialization signal line within the corresponding pixel unit. The second connecting line is connected to the initialization connecting line and the first electrode of the first initialization transistor within the corresponding pixel unit. The initialization connecting lines within the two pixel units are designed accordingly to connect the first connecting line and the second connecting line respectively. For other parts, the design within the two pixel units can be the same. Accordingly, the design of all pixel units of the display panel can be determined based on the design of the repeating units.

[0130] Specifically, the above embodiments are illustrated using the example of a repeating unit comprising two pixel units. However, the embodiments of this application are not limited to this. The repeating unit may comprise only one pixel unit. The design of the pixel unit can refer to the pixel unit shown in FIG6. Alternatively, the pixel unit may be designed to have a second connecting line within it, which is connected to the initialization connecting line and the first electrode of the first initialization transistor. The remaining parts can refer to the pixel unit in FIG6.

[0131] In some embodiments, as shown in Figures 6 to 13, the pixel driving circuit 120 further includes a switching transistor T2, and the gates T2G of the switching transistors T2 in the plurality of pixel driving circuits 120 are spaced apart. By spaced apart the gates of the switching transistors in the plurality of pixel driving circuits, the gates of the switching transistors in the pixel driving circuits are prevented from overlapping with the data lines, reducing the parasitic capacitance of the first scan signal line and the data line, reducing the total capacitance of the first scan signal line, and reducing the total capacitance of the data line. This can prevent crosstalk caused by insufficient pixel charging time or even incorrect charging, improve display uniformity, and improve display effect.

[0132] Specifically, compared to the dual-layer design of the first scan line 203 in the contrast display device, which results in two overlaps between the first scan line 203 and a data signal line, in this embodiment, when setting the first scan signal line Scan(n), the gate T2G of the switching transistor T2, and the gate T3G of the compensation transistor, the portion serving as the gate T2G of the switching transistor T2 and the gate T3G of the compensation transistor is retained in the first gate layer, while the portion connecting the gate T2G of two adjacent switching transistors T2 is removed. This ensures that the portion serving as the gate T2G of the switching transistor T2 and the gate T3G of the compensation transistor does not overlap with the data line, thereby reducing the parasitic capacitance of the first scan signal line and the data line.

[0133] Specifically, as shown in Figure 4, the display panel 1 also includes an encapsulation layer 15, which includes a first inorganic layer, an organic layer, and a second inorganic layer.

[0134] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0135] Specifically, the active layer material includes silicon semiconductor materials, specifically low-temperature polycrystalline silicon; or the active layer material includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0136] Specifically, the driving transistor, switching transistor, compensation transistor, first initialization transistor, first light-emitting control transistor, second light-emitting control transistor, and second initialization transistor can be either P-type transistors or N-type transistors.

[0137] Specifically, the above embodiments provide a detailed description of the display panel from aspects such as the circuit of the display panel, the film layer structure, the specific design of each film layer, and the connection and relative relationships between each film layer. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, in each pixel unit, the first source-drain layer includes the second electrodes of three second light-emitting control transistors located in three pixel driving circuits respectively. The area of ​​the second electrode of one second light-emitting control transistor is larger than the area of ​​the second electrodes of the other two second light-emitting control transistors. In two adjacent pixel units, one pixel unit is provided with a first connection line, and the other pixel unit is provided with a second connection line. The first connection line is connected to the second part of the initialization connection line and the second initialization signal line in the corresponding pixel unit, and the second connection line is connected to the initialization connection line and the first electrode of the first initialization transistor in the corresponding pixel unit.

[0138] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0139] Specifically, the display panel includes an organic light-emitting diode (OLED) display panel.

[0140] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0141] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0142] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0143] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel comprising: Substrate; A driving circuit layer is disposed on one side of the substrate, and the driving circuit layer includes a pixel driving circuit and a data line electrically connected to the pixel driving circuit. A light-emitting functional layer is disposed on the side of the driving circuit layer away from the substrate. The light-emitting functional layer includes a light-emitting device, and the anode of the light-emitting device is connected to the corresponding pixel driving circuit. The projection of the data line onto the substrate does not overlap with the projection of the anode of the light-emitting device onto the substrate.

2. The display panel of claim 1, wherein, The driving circuit layer includes a first gate layer and a first source-drain layer, wherein the first gate layer is disposed between the substrate and the first source-drain layer; Wherein, the first gate layer includes a first scan connection line, the first source-drain layer includes a first scan signal line, the first scan connection line is connected to the first scan signal line, the projection of the first scan signal line on the substrate overlaps with the projection of the data line on the substrate, and the projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

3. The display panel of claim 2, wherein, The driving circuit layer further includes a second source-drain layer, which is disposed on the side of the first source-drain layer away from the first gate layer. The second source-drain layer also includes a high-potential power line. The first scan connection line includes a connection portion and a functional portion, and the connection portion connects the functional portion and the first scan signal line. Wherein, the projection of the connecting portion on the substrate does not overlap with the projection of the high-potential power line on the substrate, and the projection of a portion of the functional part on the substrate does not overlap with the projection of the high-potential power line on the substrate.

4. The display panel of claim 2, wherein, The first source-drain layer further includes a second scan signal line, and the first gate layer further includes a second scan connection line. The second scan connection line is connected to the second scan signal line. The projection of the second scan signal line on the substrate overlaps with the projection of the data line on the substrate, while the projection of the second scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

5. The display panel of claim 4, wherein, The driving circuit layer further includes a first initialization signal line, wherein the distance between the projection of the second scan signal line on the substrate and the projection of the first initialization signal line on the substrate is smaller than the distance between the projection of the second scan signal line on the substrate and the projection of the first scan signal line on the substrate.

6. The display panel of claim 2, wherein, The display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixel units. The driving circuit layer includes a first via and a high-potential power line. The first scan signal line passes through the first via and is connected to the first scan connection line. The first via is disposed between the data line and the high-potential power line within the same sub-pixel unit.

7. The display panel of claim 1, wherein, The pixel driving circuit includes a compensation transistor and a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor connected in series between the high-potential power line and the anode of the light-emitting device. The driving circuit layer includes a first gate layer, a first source-drain layer, and a second source-drain layer. The first gate layer is disposed between the substrate and the first source-drain layer. The first source-drain layer is disposed between the first gate layer and the second source-drain layer. The first gate layer includes the gate of the driving transistor. The first source-drain layer includes a first electrode of a compensation transistor and a second electrode of a second light-emitting control transistor. The second source-drain layer includes a high-potential power line and an anode connection line. The display panel further includes a second via, a third via, and a fourth via. The first electrode of the compensation transistor passes through the second via and is connected to the gate of the driving transistor. The anode of the light-emitting device passes through the third via and is connected to the anode connection line. The anode connection line passes through the fourth via and is connected to the second electrode of the second light-emitting control transistor. The second via is correspondingly disposed to the gate of the driving transistor, and the third and fourth vias are correspondingly disposed to the anode connection line.

8. The display panel of claim 1, wherein, The display panel includes multiple pixel units arranged in an array. The driving circuit layer further includes a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer. The second gate layer includes a first power connection line, and the first source-drain layer includes a second power connection line. In each pixel unit, the second source-drain layer includes three data lines, three high-potential power lines, one low-potential power line, one initialization connection line, and three anode connection lines. The second power connection line connects the first power connection line and the high-potential power line. The three data lines and the three high-potential power lines are alternately arranged along a first direction. The low-potential power line is disposed between one data line and one high-potential power line. The initialization connection line is disposed between another data line and another high-potential power line. Each anode connection line is disposed between one high-potential power line and one data line.

9. The display panel of claim 8, wherein, The light-emitting functional layer includes a pixel electrode layer. In each pixel unit, the pixel electrode layer includes the anodes of three light-emitting devices. The anode of each light-emitting device is connected to an anode connection line. The projection of the anode of the light-emitting device on the substrate overlaps with the projection of the high-potential power line on the substrate.

10. The display panel of claim 9, wherein, The pixel driving circuit further includes a first light-emitting control transistor. The pixel unit includes a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit. The first sub-pixel unit includes a first light-emitting device, the second sub-pixel unit includes a second light-emitting device, and the third sub-pixel unit includes a third light-emitting device. The pixel driving circuit includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are electrically connected to the anode of the first light-emitting device, the anode of the second light-emitting device, and the anode of the third light-emitting device, respectively. The three data lines include a first data line, a second data line, and a third data line that are electrically connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively. The three high-potential power lines include a first high-potential power line, a second high-potential power line, and a third high-potential power line that are electrically connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively. Specifically, the distance between the portion of the first high-potential power line connected to the second power connection line and the first data line is greater than the distance between the portion of the first high-potential power line connected to the first electrode of the first light-emitting control transistor and the first data line; the distance between the portion of the second high-potential power line connected to the second power connection line and the second data line is equal to the distance between the portion of the second high-potential power line connected to the first electrode of the first light-emitting control transistor and the second data line; and the distance between the portion of the third high-potential power line connected to the second power connection line and the third data line is equal to the distance between the portion of the third high-potential power line connected to the first electrode of the first light-emitting control transistor and the third data line.

11. The display panel of claim 9, wherein, The pixel driving circuit further includes a second light-emitting control transistor. In each pixel unit, the first source-drain layer includes the second electrodes of three second light-emitting control transistors located in the three pixel driving circuits respectively. The area of ​​the second electrode of one second light-emitting control transistor is larger than the area of ​​the second electrodes of the other two second light-emitting control transistors.

12. The display panel according to any one of claims 1 to 11, wherein, The pixel driving circuit further includes a switching transistor, and the gates of the switching transistors in the plurality of pixel driving circuits are spaced apart.

13. A display device comprising a display panel, the display panel comprising: Substrate; A driving circuit layer is disposed on one side of the substrate, and the driving circuit layer includes a pixel driving circuit and a data line electrically connected to the pixel driving circuit. A light-emitting functional layer is disposed on the side of the driving circuit layer away from the substrate. The light-emitting functional layer includes a light-emitting device, and the anode of the light-emitting device is connected to the corresponding pixel driving circuit. The projection of the data line onto the substrate does not overlap with the projection of the anode of the light-emitting device onto the substrate.

14. The display device of claim 13, wherein, The driving circuit layer includes a first gate layer and a first source-drain layer, wherein the first gate layer is disposed between the substrate and the first source-drain layer; Wherein, the first gate layer includes a first scan connection line, the first source-drain layer includes a first scan signal line, the first scan connection line is connected to the first scan signal line, the projection of the first scan signal line on the substrate overlaps with the projection of the data line on the substrate, and the projection of the first scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

15. The display device of claim 14, wherein, The driving circuit layer further includes a second source-drain layer, which is disposed on the side of the first source-drain layer away from the first gate layer. The second source-drain layer also includes a high-potential power line. The first scan connection line includes a connection portion and a functional portion, and the connection portion connects the functional portion and the first scan signal line. Wherein, the projection of the connecting portion on the substrate does not overlap with the projection of the high-potential power line on the substrate, and the projection of a portion of the functional part on the substrate does not overlap with the projection of the high-potential power line on the substrate.

16. The display device of claim 14, wherein, The first source-drain layer further includes a second scan signal line, and the first gate layer further includes a second scan connection line. The second scan connection line is connected to the second scan signal line. The projection of the second scan signal line on the substrate overlaps with the projection of the data line on the substrate, while the projection of the second scan connection line on the substrate does not overlap with the projection of the data line on the substrate.

17. The display device of claim 16, wherein, The driving circuit layer further includes a first initialization signal line, wherein the distance between the projection of the second scan signal line on the substrate and the projection of the first initialization signal line on the substrate is smaller than the distance between the projection of the second scan signal line on the substrate and the projection of the first scan signal line on the substrate.

18. The display device of claim 14, wherein, The display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixel units. The driving circuit layer includes a first via and a high-potential power line. The first scan signal line passes through the first via and is connected to the first scan connection line. The first via is disposed between the data line and the high-potential power line within the same sub-pixel unit.

19. The display device of claim 13, wherein, The pixel driving circuit includes a compensation transistor and a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor connected in series between the high-potential power line and the anode of the light-emitting device. The driving circuit layer includes a first gate layer, a first source-drain layer, and a second source-drain layer. The first gate layer is disposed between the substrate and the first source-drain layer. The first source-drain layer is disposed between the first gate layer and the second source-drain layer. The first gate layer includes the gate of the driving transistor. The first source-drain layer includes a first electrode of a compensation transistor and a second electrode of a second light-emitting control transistor. The second source-drain layer includes a high-potential power line and an anode connection line. The display panel further includes a second via, a third via, and a fourth via. The first electrode of the compensation transistor passes through the second via and is connected to the gate of the driving transistor. The anode of the light-emitting device passes through the third via and is connected to the anode connection line. The anode connection line passes through the fourth via and is connected to the second electrode of the second light-emitting control transistor. The second via is correspondingly disposed to the gate of the driving transistor, and the third and fourth vias are correspondingly disposed to the anode connection line.

20. The display device of claim 13, wherein, The display panel includes multiple pixel units arranged in an array. The driving circuit layer further includes a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer. The second gate layer includes a first power connection line, and the first source-drain layer includes a second power connection line. In each pixel unit, the second source-drain layer includes three data lines, three high-potential power lines, one low-potential power line, one initialization connection line, and three anode connection lines. The second power connection line connects the first power connection line and the high-potential power line. The three data lines and the three high-potential power lines are alternately arranged along a first direction. The low-potential power line is disposed between one data line and one high-potential power line. The initialization connection line is disposed between another data line and another high-potential power line. Each anode connection line is disposed between one high-potential power line and one data line.

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