Electronic device and manufacturing method therefor, packaging structure and electronic apparatus

Abstract

Provided are an electronic device and a manufacturing method therefor, a packaging structure and an electronic apparatus, relating to the technical field of chip packaging. The electronic device can be used as a substrate and an adapter board, and the electronic device comprises a first glass layer and a second glass layer which are stacked; a first surface of the first glass layer is provided with a first recess for providing a first conductive member, and a second conductive member is provided in the first glass layer, the first conductive member being connected to the second conductive member; a third surface of the second glass layer is provided with a second recess for providing a third conductive member, and a fourth conductive member is provided in the second glass layer, the third conductive member being connected to the fourth conductive member; the first conductive member and the third conductive member may be metal lines, and the second conductive member and the fourth conductive member may be through glass vias filled with conductive metal; the second conductive member is connected to the fourth conductive member. In this way, when the electronic device is connected to a chip, warpage of the electronic device and the chip due to thermal mismatch is less likely to occur; and the thickness and packaging volume of the electronic device are smaller.

Description

Electronic devices and their fabrication methods, packaging structures, electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411885821.8, filed on December 18, 2024, entitled "Electronic Devices and Preparation Methods Thereof, Packaging Structures, and Electronic Devices", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip packaging technology, and in particular to electronic devices, their preparation methods, packaging structures, and electronic devices. Background Technology

[0003] As the market becomes increasingly diversified, applications such as artificial intelligence, big data, and cloud computing are emerging, placing higher demands on the packaging size, electrical performance, and reliability of electronic devices corresponding to these applications.

[0004] Taking a chip in a packaging structure as an example, the chip can be directly connected to the substrate, or it can be connected to the substrate via an adapter board. Currently, the substrate and adapter board are mainly made of resin, which may cause warping problems between the chip and the substrate, the chip and the adapter board, or the adapter board and the substrate due to thermal mismatch. Summary of the Invention

[0005] The embodiments of this application provide an electronic device and its preparation method, packaging structure, and electronic device. The electronic device has advantages such as a low coefficient of thermal expansion, a low dielectric constant, and is not prone to warping. Furthermore, the electronic device has a small thickness and packaging volume.

[0006] In a first aspect, an electronic device is provided that can be applied in the field of chip packaging, and the electronic device can be used as a substrate and an adapter board. The electronic device includes a first glass layer and a second glass layer stacked together. The first glass layer has a first surface and a second surface facing away from each other, and a first groove is formed on the first surface. The second glass layer has a third surface and a fourth surface facing away from each other, and a second groove is formed on the fourth surface. The first surface of the first glass layer and the third surface of the second glass layer are opposite to each other. The electronic device also includes a first conductive element, a second conductive element, a third conductive element, and a fourth conductive element. The first conductive element is located in the first groove, the second conductive element is located in the first glass layer, and the second conductive element penetrates through the first surface and the second surface. The third conductive element is located in the second groove, the fourth conductive element is located in the second glass layer, and the fourth conductive element penetrates through the third surface and the fourth surface. The first conductive element and the third conductive element can be metal circuits, and the second conductive element and the fourth conductive element can be glass vias (TGVs) filled with conductive metal. The third conductive element and the fourth conductive element are connected. The connection between the second conductive element and the fourth conductive element means that the first conductive element, the second conductive element, the third conductive element, and the fourth conductive element can achieve a communication connection to realize the interconnection of circuits between the first glass layer and the second glass layer.

[0007] Compared to resin materials, the first and second glass layers have a lower coefficient of thermal expansion (CTE), resulting in a lower overall CTE for the electronic device. This reduces the likelihood of warping due to thermal mismatch when the electronic device (e.g., substrate or adapter) is connected to other electronic components (e.g., chips). Furthermore, the high flatness of glass minimizes the warping of the electronic device itself, further reducing the probability of warping. Glass also has a high modulus, making the electronic device less prone to deformation or warping under stress, thus exhibiting good stability. In summary, the electronic device is less prone to warping, demonstrating superior stability and reliability. Because the electronic device is less prone to warping, the density of the first and third conductive components can be increased while maintaining high structural stability. This improves the design density, design freedom, accuracy, and reliability of the circuitry within the electronic device, meeting the increasing demands of chip packaging. In addition, the main material of electronic devices is glass, which has a low dielectric constant and results in less loss during the transmission of electrical signals.

[0008] In the aforementioned electronic device, the first conductive element is disposed in the first groove and the third conductive element is disposed in the second groove. Compared to the first conductive element being disposed between the first and second glass layers and the third conductive element being disposed on the side of the second glass layer away from the first glass layer, the first and third conductive elements in the electronic device do not need to occupy additional space in the thickness direction, which can significantly reduce the thickness and packaging volume of the electronic device.

[0009] In one possible implementation, a third groove is formed on the second surface of the first glass layer, and a fifth conductive element is disposed in the third groove. The fifth conductive element can be a metal circuit. The fifth conductive element is connected to the second conductive element, that is, the first conductive element, the second conductive element, the third conductive element, the fourth conductive element, and the fifth conductive element can be connected to achieve communication, so as to realize the circuit between the first glass layer and the second glass layer.

[0010] Thus, a first conductive element is provided in the first groove on the first surface of the first glass layer, and a second conductive element is provided in the third groove on the second surface of the first glass layer. The first and third conductive elements can be metal circuits, and the electronic device has higher circuit integration and more complex circuit design capabilities, which is conducive to meeting the increasing chip packaging requirements.

[0011] In one possible implementation, a buffer layer is provided between the groove wall of the first groove and the first conductive element.

[0012] A relatively soft buffer layer is provided between the groove wall of the first groove and the first conductive component. This provides high adhesion and bonding between the groove wall and the buffer layer, and between the buffer layer and the first conductive component, thereby improving the reliability and stability of the first glass layer. Furthermore, it effectively prevents damage to the structure of the first groove during the fabrication of the first conductive component.

[0013] In some examples, buffer layers may be provided between the groove wall of the second groove and the third conductive element, between the first glass layer and the second conductive element, and between the second glass layer and the fourth conductive element.

[0014] In one possible implementation, the electronic device further includes an insulating adhesive layer bonded between a first surface of the first glass layer and a third surface of the second glass layer. This mitigates the risk of delamination between the first and second glass layers in the electronic device.

[0015] In one possible implementation, the connection between the second conductive element and the fourth conductive element includes: the second conductive element penetrating the insulating layer and connecting to the fourth conductive element; or, the second conductive element penetrating the insulating layer and connecting to the third conductive element, and the third conductive element connecting to the fourth connecting element. This enables a communication connection between the second and fourth conductive elements.

[0016] In one possible implementation, the electronic device further includes: a third glass layer, a sixth conductive element, and a seventh conductive element; the third glass layer is disposed on the side of the second glass layer away from the first glass layer, and has a fifth surface and a sixth surface disposed opposite to each other, with a fourth groove formed on the sixth surface, and the fifth surface and the fourth surface facing each other; the sixth conductive element is located in the fourth groove, and the seventh conductive element is located within the third glass layer, penetrating through the fifth surface and the sixth surface, and the sixth conductive element and the seventh conductive element are connected; the sixth conductive element can be a metal circuit, and the seventh conductive element can be a glass through-hole filled with conductive metal; wherein, the fourth conductive element and the seventh conductive element are connected, that is, the first conductive element, the second conductive element, the third conductive element, the fourth conductive element, the sixth conductive element, and the seventh conductive element can achieve a communication connection to realize the interconnection of circuits between the first glass layer, the second glass layer, and the third glass layer. In other words, at least one glass layer can also be disposed on the side of the second glass layer away from the first glass layer.

[0017] By incorporating a third glass layer, a sixth conductive element, and a seventh conductive element into electronic devices, more circuits can be arranged within a limited space. This facilitates higher circuit density and more complex circuit design capabilities. Furthermore, since circuits can be placed on multiple glass layers, the routing path can be better controlled, which is beneficial for improving the electrical signal transmission effect of electronic devices. As a result, electronic devices exhibit superior electrical performance and reliability.

[0018] In one possible implementation, the electronic device further includes: a fourth glass layer, an eighth conductive element, and a ninth conductive element; the fourth glass layer is disposed on the side of the first glass layer away from the second glass layer, and has a seventh surface and an eighth surface disposed opposite to each other, the seventh surface having a fifth groove, and the eighth surface and the second surface being opposite to each other; the eighth conductive element is located in the fifth groove, and the ninth conductive element is located within the fourth glass layer, penetrating through the seventh surface and the eighth surface; the eighth conductive element and the ninth conductive element are connected, the eighth conductive element can be a metal circuit, and the ninth conductive element can be a glass through-hole filled with conductive metal; wherein, the second conductive element and the ninth conductive element are connected; that is, the first conductive element, the second conductive element, the third conductive element, the fourth conductive element, the eighth conductive element, and the ninth conductive element can achieve a communication connection to realize the interconnection of circuits between the first glass layer, the second glass layer, and the fourth glass layer. In other words, at least one glass layer can also be disposed on the side of the first glass layer away from the second glass layer.

[0019] By incorporating a fourth glass layer, an eighth conductive element, and a ninth conductive element into electronic devices, more circuits can be arranged within a limited space, which is beneficial for achieving higher circuit density and more complex circuit design capabilities. In addition, since circuits can be placed on multiple glass layers, the routing path can be better controlled, which is beneficial for improving the electrical signal transmission effect of electronic devices. As a result, electronic devices have superior electrical performance and reliability.

[0020] In a second aspect, a method for fabricating an electronic device is provided. The method includes: providing a first glass layer having a first surface and a second surface disposed opposite to each other; the first surface having a first groove; and the first glass layer having a first through-hole penetrating the first and second surfaces; disposing a first conductive element within the first groove; disposing a first conductive post within the first through-hole to obtain a second conductive element; and connecting the first and second conductive elements; disposing a second glass layer on one side of the first glass layer; the second glass layer including a third surface and a fourth surface disposed opposite to each other, the third surface facing the first surface; the fourth surface having a second groove; and the second glass layer having a second through-hole penetrating the third and fourth surfaces; disposing a third conductive element within the second groove; and disposing a second conductive post within the second through-hole to obtain a fourth conductive element; connecting the third and fourth conductive elements; and connecting the second and fourth conductive elements. This enables communication connections between the first, second, third, and fourth conductive elements, and allows for circuit interconnection between the first and second glass layers.

[0021] The electronic devices prepared by the above method have a low coefficient of thermal expansion. When the electronic devices (such as substrates or adapters) are connected to other electronic components (such as chips), they are less prone to warping due to thermal mismatch. The electronic devices also have a low dielectric constant, resulting in less loss during electrical signal transmission, and have a smaller thickness and volume. Furthermore, the preparation process using this method is simple, inexpensive, and easily industrialized.

[0022] In one possible implementation, a third groove is formed on the second surface of the first glass layer, a fifth conductive element is disposed in the third groove, and the fifth conductive element is connected to the second conductive element. In this way, the fabricated electronic device has higher integration and more complex circuit design capabilities, which is beneficial for meeting the increasing demands of chip packaging.

[0023] In one possible implementation, placing the second glass layer on one side of the first glass layer includes bonding the first surface of the first glass layer and the third surface of the second glass layer together using an insulating adhesive layer. This can mitigate the potential for delamination between the first and second glass layers in electronic devices.

[0024] In some examples, a third glass layer is provided, having a fifth surface and a sixth surface disposed opposite to each other, the fifth surface of the third glass layer being opposite to the fourth surface of the second glass layer, the sixth surface having a fourth groove, the third glass layer having a third through hole penetrating the fifth surface and the sixth surface, a sixth conductive element being disposed in the fourth groove, a third conductive post being disposed in the third through hole to obtain a seventh conductive element, the sixth conductive element and the seventh conductive element being connected, and the fourth conductive element and the seventh conductive element being connected.

[0025] In some examples, a fourth glass layer is provided, having a seventh surface and an eighth surface disposed opposite to each other, the eighth surface of the fourth glass layer being opposite to the second surface of the first glass layer, the seventh surface having a fifth groove, the fourth glass layer having a fourth through hole penetrating the seventh surface and the eighth surface, an eighth conductive element being disposed in the fifth groove, a fourth conductive post being disposed in the fourth through hole to obtain a ninth conductive element, the eighth conductive element and the ninth conductive element being connected, and the fourth conductive element and the ninth conductive element being connected.

[0026] Thirdly, a packaging structure is provided, the packaging structure comprising: an electronic device and a chip, the chip being disposed on the electronic device; wherein the electronic device includes an electronic device as in any possible implementation of the first aspect, or an electronic device prepared by a method in any possible implementation of the second aspect.

[0027] In one possible implementation, the package structure includes a plurality of stacked electronic devices and a chip disposed on the plurality of stacked electronic devices.

[0028] Fourthly, an electronic device is provided, comprising: a circuit board and a packaging structure according to any possible implementation of the third aspect, the packaging structure being disposed on the circuit board.

[0029] The technical effects of any possible implementation of the third and fourth aspects can be found in the technical effects of different implementations of the first or second aspects described above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 is a schematic diagram of the electronic device;

[0032] Figure 2 is a schematic diagram of a packaging structure;

[0033] Figure 3 is a schematic diagram of another packaging structure;

[0034] Figure 4 is a schematic diagram of the structure of some electronic devices provided in the embodiments of this application;

[0035] Figure 5 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0036] Figure 6 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0037] Figure 7 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0038] Figure 8 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0039] Figure 9 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0040] Figure 10 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0041] Figure 11 is a schematic diagram of the structure of some other electronic devices provided in the embodiments of this application;

[0042] Figure 12 is a schematic diagram of the process for fabricating some electronic devices according to an embodiment of this application;

[0043] Figure 13 is a schematic diagram of the process for fabricating some electronic devices according to an embodiment of this application;

[0044] Figure 14 is a schematic diagram of the process for fabricating other electronic devices provided in the embodiments of this application;

[0045] Figure 15 is a schematic diagram of some packaging structures provided in the embodiments of this application;

[0046] Figure 16 is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0047] Figure 17 is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0048] Figure 18 is a schematic diagram of some other packaging structures provided in the embodiments of this application;

[0049] Figure 19 shows schematic diagrams of some packaging structures;

[0050] Figure 20 is a schematic diagram of some other packaging structures provided in the embodiments of this application.

[0051] Reference numerals: 1-Packaging structure; 2-Circuit board; 3-Ring component; 11 / 11A / 11B / 11C-Chip; 12-Bottom filler; C1-First electrical connection structure; 20-Substrate; 21-First resin material; 22-First metal circuit; C2-Second electrical connection structure; 30-Adapter board; 31-Second resin material; 32-Through silicon via; 33-Second metal circuit; C3-Third electrical connection structure; 100 / 100A / 100B-Electronic device; 110-First glass layer; 111 / 1111 / 1112-First conductive element; 111A-First groove; 111L-First conductive line; 112 / 1121 / 1122-Second conductive element; 113-Fifth conductive element; 113A-Third groove; 113L-Second conductive line. 120 - Second glass layer; 121 / 1211 / 1212 - Third conductive element; 121A - Second groove; 121L - Third conductive wire; 122 / 1221 / 1222 - Fourth conductive element. 130 - First insulating adhesive layer; 131 - Adhesive layer; 1311 - Sintering region. 140 - Third glass layer; 141 - Sixth conductive element; 141A - Fourth groove; 141L - Fourth conductive wire; 142 - Seventh conductive element. 150 - Second insulating adhesive layer; 160 - Third insulating adhesive layer. 170 - Fourth glass layer; 171 / 1711 / 1712 - Eighth conductive element; 171A - Fifth groove; 171L - Fifth conductive wire; 172 / 1721 / 1722 - Ninth conductive element. 180 - Buffer layer; 1000 - Carrier plate. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments.

[0053] In the following, the terms "first," "second," etc., are used only for descriptive purposes to distinguish identical or similar items that have substantially the same function and effect, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the embodiments of this application, the term "connection" should be interpreted broadly; unless otherwise explicitly specified and limited, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0054] This application provides an electronic device that can be a server, optical communication device, mobile phone, tablet computer, laptop computer, personal digital assistant (PDA), camera, personal computer, laptop computer, in-vehicle device, wearable device, augmented reality (AR) glasses, AR headset, virtual reality (VR) glasses, or VR headset, or any other device that requires data processing / storage / transmission / reception. This application does not impose any special limitations on the specific form of the aforementioned electronic device.

[0055] Figure 1 is a schematic diagram of the structure of an electronic device. Referring to Figure 1, the electronic device includes a circuit board 2, such as a printed circuit board (PCB). A package structure 1 is disposed on the circuit board 2, and the package structure 1 and the circuit board 2 are electrically connected. The package structure 1 can transmit signals with the modules within the circuit board 2. In some embodiments, the package structure 1 and the circuit board 2 can be electrically connected through an electrical connection structure. For example, the package structure 1 and the circuit board 2 can be electrically connected through the second electrical connection structure C2 in Figure 2, or through the third electrical connection structure C3 in Figure 3. The second electrical connection structure C2 and the third electrical connection structure C3 each independently include a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPB). It is understood that Figure 1 only exemplarily shows some components included in the electronic device, and the actual shape, size, position, and construction of these components are not limited to Figure 1.

[0056] Figure 2 is a schematic diagram of a packaging structure. Referring to Figure 2, the packaging structure 1 includes a chip 11 and an organic substrate 20. The organic substrate 20 includes a first metal line 22 and a first resin material 21 disposed around the first metal line 22. The organic substrate 20 is disposed on one side of the chip 11. One end of the first metal line 22 in the organic substrate 20 is electrically connected to the chip 11, and the other end of the first metal line 22 is connected to the circuit board in Figure 1. In some examples, the chip 11 and the first metal line 22 can be electrically connected through an electrical connection structure C1. The electrical connection structure C1 can include microbumps (uBump) or controlled collapse chip connections. An underfill for the chip 11 can be disposed around the electrical connection structure C1 to fill the gap between the chip 11 and the organic substrate 20, thereby enhancing the connection strength between the chip 11 and the organic substrate 20. In other words, the packaging structure 1 shown in Figure 2 does not include an adapter board.

[0057] Figure 3 is a schematic diagram of another packaging structure. Referring to Figure 3, the packaging structure 1 includes chip 11A, chip 11B, chip 11C (i.e., the packaging structure 1 includes multiple chips), organic adapter plate 30, and organic substrate 20. The organic substrate 20 includes a first metal line 22 and a first resin material 21 disposed around the first metal line 22. The organic adapter plate 30 includes a through silicon via 32 (TSV) filled with conductive material, a second metal line 33, and a second resin material 31 disposed around the through silicon via 32 and the second metal line 33. Different chips can be electrically connected via the second metal line 33. For example, chips 11A and 11B can be electrically connected via the second metal line 33, and chips 11B and 11C can also be electrically connected via the second metal line 33. Chips 11A / 11B / 11C can be electrically connected to the first metal line 22 via metal-filled through-silicon vias 32 or the second metal line 33. For example, chips 11A / 11C and the first metal line 22 can be electrically connected via metal-filled through-silicon vias 32, and chips 11B and the first metal line 22 can be electrically connected via the second metal line 33. Chips 11A, 11B, and 11C and the organic adapter board 30 can be electrically connected via electrical connection structure C1; the organic adapter board 30 and the organic substrate 20 can be electrically connected via electrical connection structure C2; ​​and the organic substrate 20 and the circuit board 2 can be electrically connected via electrical connection structure C3. In other words, the packaging structure 1 shown in Figure 3 includes an interposer layer.

[0058] The packaging structure 1 shown in Figures 2 and 3 may also include more or fewer components, combinations of certain components, certain split components, arrangements of different components, etc., which are not specifically limited in this application embodiment.

[0059] The organic substrate 20 and the chip, as well as the organic adapter plate 30 and the chip, have significantly different coefficients of thermal expansion. When the temperature changes, stress concentration easily occurs between these two points, leading to poor reliability of the packaging structure 1. For example, referring to Figure 2, when the organic substrate 20 is connected to the chip, the significant difference in their coefficients of thermal expansion can cause thermal mismatch, making both the organic substrate 20 and the chip prone to warping, further reducing the reliability of the packaging structure 1. Similarly, referring to Figure 3, when the organic adapter plate 30 is connected to the chip, the significant difference in their coefficients of thermal expansion can also cause thermal mismatch, making both the organic adapter plate 30 and the chip prone to warping, further reducing the reliability of the packaging structure 1. Furthermore, the thermal expansion coefficients of the organic adapter plate 30 and the organic substrate 20 cannot be specifically set, making it difficult for the thermal expansion coefficients of the organic adapter plate 30 and the organic substrate 20 to be fully matched. This may cause warping between the organic adapter plate 30 and the organic substrate 20 due to thermal mismatch.

[0060] As markets become increasingly diversified, applications such as artificial intelligence, big data, and cloud computing are emerging. These applications require higher computing speeds, higher bandwidth, and relatively lower costs and power consumption, leading to larger and more complex chips in the electronic devices used in these applications. For example, in fields such as radio frequency terminals, more functional chips are typically integrated to achieve higher module integration and better frequency performance. Similarly, in computing product lines, more functional chips are needed to achieve higher computing power, larger memory, and the demands of large data transmission. These situations place higher demands on the wiring density, signal integrity, and electrical performance of the substrate or adapter board. Currently, these problems can be addressed by increasing the number of layers in the substrate or adapter board and then wiring each layer separately.

[0061] Since the organic substrate 20 or organic adapter board 30 is mainly made of resin, increasing the number of layers in the organic substrate 20 or organic adapter board 30 may cause at least one of the following problems: The resin material has a high coefficient of thermal expansion, and the organic substrate 20 or organic adapter board 30 may expand or contract significantly with temperature changes, causing the circuit traces in the organic substrate 20 or organic adapter board 30 to easily deform, affecting the reliability of the circuit, especially in multilayer organic substrate 20 or organic adapter board 30, where the reliability of the circuit deteriorates significantly; the organic substrate 20 or organic adapter board 30 has poor flatness, making it prone to warping or deformation during manufacturing, especially in multilayer manufacturing, where flatness issues directly affect the accuracy and reliability of the circuit; due to the susceptibility of the organic substrate 20 or organic adapter board 30 to thermal expansion and warping, especially in multilayer manufacturing, high-density traces are difficult to achieve, limiting the flexibility and performance of circuit design.

[0062] Based on this, embodiments of this application provide an electronic device that has advantages such as a low coefficient of thermal expansion, a low dielectric constant, and low susceptibility to warping, and also has a small thickness and package size. When the electronic device and the chip are electrically connected, the matching degree of their coefficients of thermal expansion is high, mitigating the potential risks of warping caused by thermal mismatch between the electronic device and the chip.

[0063] This application provides an electronic device 100, referring to FIG4, applied in the field of chip packaging. The electronic device 100 can be used as a substrate and an adapter board. The electronic device 100 includes a first glass layer 110 and a second glass layer 120 stacked together. The first glass layer 110 has a first surface and a second surface opposite to each other, with a first groove 111A formed on the first surface. The second glass layer 120 has a third surface and a fourth surface opposite to each other, with a second groove 121A formed on the fourth surface. The third surface of the second glass layer is opposite to the first surface of the first glass layer. In some examples, the first surface of the first glass layer 110 is relatively close to the second glass layer 120, and the second surface of the first glass layer 110 is relatively far from the second glass layer 120. Furthermore, the first glass layer 110 may be plate-shaped, and the first and second surfaces may be the two surfaces with the largest areas of the first glass layer 110. In some examples, the third surface of the second glass layer 120 is relatively close to the first glass layer 110, and the fourth surface of the second glass layer 120 is relatively far from the first glass layer 110. In addition, the second glass layer 120 may be plate-shaped, and the third and fourth surfaces may be the two surfaces of the second glass layer 120 with the largest area.

[0064] The electronic device 100 further includes a first conductive element 111, a second conductive element 112, a third conductive element 121, and a fourth conductive element 122. The first conductive element 111 is located in a first groove 111A, the second conductive element 112 is located in a first glass layer 110, and the second conductive element 112 penetrates the first surface and the second surface. The first conductive element 111 and the second conductive element 112 are connected. The third conductive element 121 is located in a second groove 121A, the fourth conductive element 122 is located in a second glass layer 120, and the fourth conductive element 122 penetrates the third surface and the fourth surface. The third conductive element 121 and the fourth conductive element 122 are connected. The second conductive element 112 and the fourth conductive element 122 are connected, that is, the first conductive element 111, the second conductive element 112, the third conductive element 121, and the fourth conductive element 122 can achieve a communication connection to realize the interconnection of the circuit between the first glass layer 110 and the second glass layer 120. In some examples, the first conductive element 111 and the third conductive element 121 can be metal wires, and the material of the metal wires can be at least one of copper, aluminum, or silver. In some examples, the second conductive element 112 includes a first through hole and a first conductive post disposed within the first through hole, the first through hole penetrating a first surface and a second surface; the fourth conductive element 122 includes a second through hole and a second conductive post disposed within the second through hole, the second through hole penetrating a third surface and a fourth surface; the first conductive post in the second conductive element 112 and the second conductive post in the fourth conductive element 122 can both be made of copper.

[0065] Compared to resin materials, the first glass layer 110 and the second glass layer 120 have smaller coefficients of thermal expansion, resulting in a lower overall coefficient of thermal expansion for the electronic device 100. When the electronic device 100 (such as a substrate or adapter board) is connected to other electronic components (such as chips), the electronic device 100 (such as a substrate or adapter board) and other electronic components (such as chips) are less prone to warping due to thermal mismatch. Because glass has high flatness, the electronic device 100 also has high flatness, resulting in minimal warping, further reducing the probability of warping between the electronic device 100 and other electronic components (such as chips). Furthermore, because glass has a high modulus, the electronic device 100 is less prone to deformation or warping under stress, exhibiting good stability. In summary, the electronic device 100 is less prone to warping and possesses superior stability and reliability. Because the electronic device 100 is less prone to warping, more circuits can be incorporated into it (e.g., more first conductive elements 111 can be placed in the first glass layer 110, and more third conductive elements 121 can be placed in the second glass layer 120). This improves the design density, design freedom, accuracy, and reliability of the circuits in the electronic device 100, meeting the increasing demands of chip packaging. Furthermore, since the main material of the electronic device 100 is glass, it has a low dielectric constant, resulting in lower losses during electrical signal transmission.

[0066] In the above-mentioned electronic device 100, the first conductive element 111 is disposed in the first groove 111A and the third conductive element 121 is disposed in the second groove 121A. In the thickness direction, the first conductive element 111 and the third conductive element 121 in the electronic device 100 do not need to occupy additional space, which can significantly reduce the thickness and packaging volume of the electronic device 100.

[0067] When the electronic device 100 is used as a substrate in the packaging structure 1, and this substrate is connected to the chip, the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the chip are highly matched. When the temperature changes, neither the substrate nor the chip is prone to warping, and the electrical signal conduction between the substrate and the chip is excellent, with less loss during electrical signal transmission. In addition, due to the small thickness and packaging volume of the substrate, the packaging volume of the packaging structure 1 including the substrate is small.

[0068] In other embodiments, referring to FIG5, in the electronic device 100, the first glass layer 110 and the second glass layer 120 are connected by an adhesive layer 131. A first conductive element 111 is disposed within the adhesive layer 131 between the first glass layer 110 and the second glass layer 120, and a third conductive element 121 is disposed on one side of the first glass layer 110. On the one hand, since the first conductive element 111 is not disposed in the first groove 111A of the first glass layer 110, but is disposed within the adhesive layer 131 between the first glass layer 110 and the second glass layer 120, the adhesive layer 131 needs to achieve both bonding of the first glass layer 110 and the second glass layer 120. Furthermore, the thickness and conductivity of the third conductive element 121 disposed in the adhesive layer 131 need to be considered. If the adhesive layer 131 is too thin, the first glass layer 110 and the second glass layer 120 may squeeze the third conductive element 121, thus affecting its conductivity. Therefore, a thicker adhesive layer 131 is usually used to bond the first glass layer 110 and the second glass layer 120. On the other hand, the third conductive element 121 is disposed on the side of the first glass layer 110 away from the second glass layer 120, which means that the third conductive element 121 needs to occupy a certain size in the thickness direction, increasing the thickness and volume of the electronic device 100. In summary, the electronic device shown in Figure 5 has a large thickness and volume.

[0069] In the embodiments of this application, A and B being positioned opposite each other can mean that A and B are positioned face to face. For example, when the first surface and the third surface are positioned opposite each other, the first surface and the third surface overlap in at least a portion of their area along a certain direction.

[0070] In some embodiments, referring to FIG6, a third groove 113A is formed on the second surface of the first glass layer 110, and a fifth conductive element 113 is disposed in the third groove 113A; the fifth conductive element 113 is connected to the second conductive element 112, that is, the first conductive element 111, the second conductive element 112, the third conductive element 121, the fourth conductive element 122, and the fifth conductive element 113 can achieve a communication connection. In some examples, the fifth conductive element 113 can be a metal circuit, and the material of the metal circuit can be at least one of copper, aluminum, or silver.

[0071] Thus, conductive elements (which can be metal circuits) are provided on both the first and second surfaces of the first glass layer 110, giving the electronic device 100 higher circuit integration and more complex circuit design capabilities, which is beneficial for meeting the increasing chip packaging requirements.

[0072] In some embodiments, the electronic device 100 may further include multiple glass layers. These multiple glass layers may all be disposed on the side of the first glass layer 110 away from the second glass layer 120; alternatively, they may all be disposed on the side of the second glass layer 120 away from the first glass layer 110; or, a portion of the multiple glass layers may be disposed on the side of the first glass layer 110 away from the second glass layer 120, and another portion of the multiple glass layers may be disposed on the side of the second glass layer 120 away from the first glass layer 110. The arrangement of the multiple glass layers and the conductive elements disposed within them can be referenced to the arrangement of the second glass layer 120 and the conductive elements disposed within it, and will not be repeated here. Figures 7, 8, and 9 are merely examples, and the embodiments of this application do not limit the number of multiple glass layers or the number, structure, or position of the conductive elements disposed within them.

[0073] For example, referring to Figures 7 and 8, the electronic device 100 further includes a third glass layer 140, a sixth conductive element 141, and a seventh conductive element 142. The third glass layer 140 is disposed on the side of the second glass layer 120 away from the first glass layer 110. The third glass layer 140 has a fifth surface and a sixth surface disposed opposite to each other. A fourth groove 141A is formed on the sixth surface, and the fifth surface and the fourth surface are opposite to each other. The sixth conductive element 141 is located in the fourth groove 141A, and the seventh conductive element 142 passes through the fifth surface and the sixth surface. The sixth conductive element 141 and the seventh conductive element 142 are connected. The fourth conductive element 122 and the seventh conductive element 142 are connected, that is, the first conductive element 111, the second conductive element 112, the third conductive element 121, the fourth conductive element 122, the sixth conductive element 141, and the seventh conductive element 142 can achieve communication connection to realize the interconnection of circuits between the first glass layer 110, the second glass layer 120, and the third glass layer 140. In other words, at least one more glass layer may be disposed on the side of the second glass layer 120 away from the first glass layer 110. In some examples, the sixth conductive element 141 may be a metal circuit, and the material of the metal circuit may be at least one of copper, aluminum or silver; in some examples, the seventh conductive element 142 includes a third through hole and a third conductive post disposed in the third through hole, the third through hole penetrating the fifth surface and the sixth surface, and the third conductive post in the seventh conductive element 142 may be copper.

[0074] By setting a third glass layer 140, a sixth conductive element 141, and a seventh conductive element 142 in the electronic device 100, more circuits can be arranged in a limited space, which is conducive to achieving higher circuit density and more complex circuit design capabilities. In addition, since circuits can be set in multiple glass layers, the routing path can be better controlled, which is conducive to improving the electrical signal transmission effect and improving the electrical performance and reliability of the electronic device 100.

[0075] The electronic device 100 shown in Figure 7 and the electronic device 100 shown in Figure 8 are two feasible examples. The difference between Figure 7 and Figure 8 is as follows: In the electronic device 100 shown in Figure 7, a first groove 111A is provided on the first surface of the first glass layer 110, and a first conductive element 111 is provided in the first groove 111A. That is, the first glass layer 110 has a groove on only one side, and a conductive element (which can be a metal circuit) is provided in the groove. In the electronic device 100 shown in Figure 8, the first groove 111A is provided on the first surface of the first glass layer 110, and a first conductive element 111 is provided in the first groove 111A. Furthermore, a third groove 113A is provided on the second surface of the first glass layer 110, and a fifth conductive element 113 is provided in the third groove 113A. That is, grooves are provided on both sides of the first glass layer 110, and conductive elements (which can be metal circuits) are provided in the grooves on both sides.

[0076] For example, referring to Figure 9, the electronic device 100 further includes: a fourth glass layer 170, an eighth conductive element 171, and a ninth conductive element 172; the fourth glass layer 170 is disposed on the side of the first glass layer 110 away from the second glass layer 120, and the fourth glass layer 170 has a seventh surface and an eighth surface disposed opposite to each other, the seventh surface has a fifth groove 171A, and the eighth surface and the second surface are opposite to each other; the eighth conductive element 171 is located in the fifth groove 171A, and the ninth conductive element 172 penetrates through the seventh surface and the eighth surface; the eighth conductive element 171 and the ninth conductive element 172 are connected, as are the second conductive element 112 and the ninth conductive element 172, that is, the first conductive element 111, the second conductive element 112, the third conductive element 121, the fourth conductive element 122, the eighth conductive element 171, and the ninth conductive element 172 can achieve communication connection to realize the interconnection of the circuit between the first glass layer 110, the second glass layer 120, and the fourth glass layer 170. In other words, at least one more glass layer may be disposed on the side of the first glass layer 110 away from the second glass layer 120. In some examples, the eighth conductive element 171 may be a metal circuit, and the material of the metal circuit may be at least one of copper, aluminum or silver; in some examples, the ninth conductive element 172 includes a fourth through hole and a fourth conductive post disposed in the fourth through hole, the fourth through hole penetrating the seventh surface and the eighth surface, and the material of the fourth conductive post in the ninth conductive element 172 may be copper.

[0077] By setting a fourth glass layer 170, an eighth conductive element 171, and a ninth conductive element 172 in the electronic device 100, more circuits can be arranged in a limited space, which is conducive to achieving higher circuit density and more complex circuit design capabilities. In addition, since circuits can be set in multiple glass layers, the routing path can be better controlled, which is conducive to improving the electrical signal transmission effect and improving the electrical performance and reliability of the electronic device 100.

[0078] For example, the electronic device 100 further includes: a third glass layer 140, a fourth glass layer 170, a sixth conductive element 141, a seventh conductive element 142, an eighth conductive element 171, and a ninth conductive element 172. The arrangement of the third glass layer 140, the sixth conductive element 141, and the seventh conductive element 142 in this embodiment can be referenced to the arrangement corresponding to Figure 7 or Figure 8. The arrangement of the fourth glass layer 170, the eighth conductive element 171, and the ninth conductive element 172 in this embodiment can be referenced to the arrangement corresponding to Figure 9. In other words, at least one glass layer is disposed on the side of the second glass layer 120 away from the first glass layer 110, and at least one glass layer is disposed on the side of the first glass layer 110 away from the second glass layer 120.

[0079] The following explains the connection methods between the components in the electronic device 100. Of course, the components in the electronic device 100 can also be connected in other ways, and the embodiments of this application do not constitute a limitation.

[0080] In some embodiments, the connection methods of different conductive elements in the same glass layer include: the different conductive elements are connected by direct contact, or the different conductive elements are connected by conductive lines. The following example mainly uses the connection relationship of the first conductive element 111, the second conductive element 112, and the fifth conductive element 113 in the first glass layer 110 as an example for illustration. The connection methods of the other glass layers and the conductive elements disposed in the glass layer are similar and will not be described again.

[0081] For example, referring to Figure 8, only a single second conductive element 112 is provided in the first glass layer 110. The first conductive element 111 and the second conductive element 112 can be connected by a first conductive line 111L, and the fifth conductive element 113 and the second conductive element 112 can be connected by a second conductive line 113L. Additionally, referring to Figures 8 and 10, the third conductive element 121 and the fourth conductive element 122 are connected by a third conductive line 121L, the sixth conductive element 141 and the seventh conductive element 142 are connected by a fourth conductive line 141L, and the eighth conductive element 171 and the ninth conductive element are connected by a fifth conductive line 171L.

[0082] As another example, referring to Figure 9, multiple second conductive elements 112 can be disposed in the first glass layer 110. One second conductive element 112 and the first conductive element 111 can be connected through a first conductive line 111L, and another second conductive element 112 and the fifth conductive element 113 can be connected through a second conductive line 113L. That is, the first conductive element 111 and the fifth conductive element 113 can be connected to the same second conductive element 112, and the first conductive element 111 and the fifth conductive element 113 can also be connected to different second conductive elements 112.

[0083] As another example, referring to Figure 9, multiple second conductive elements 112 can be disposed in the first glass layer 110. The first conductive element 111 includes multiple first sub-conductive elements, and the third conductive element 121 includes multiple third sub-conductive elements. Some of the first sub-conductive elements are connected to one second conductive element 112, and other first sub-conductive elements are connected to another second conductive element 112. In addition, some third sub-conductive elements are connected to one second conductive element 112, and other third conductive elements are connected to another second conductive element 112. That is, the first conductive element 111 can be connected to different second conductive elements 112, and the fifth conductive element 113 can also be connected to different second conductive elements 112.

[0084] In some embodiments, the connection methods for conductive elements in different glass layers include: direct contact between the conductive elements in different glass layers to achieve connection, or connection between the conductive elements in different glass layers through conductive wires. The connection methods illustrated in the following examples can be applied to other glass layers and the conductive elements disposed in the glass layers.

[0085] For example, referring to Figure 9, the second conductive element 112 and the fourth conductive element 122 are connected through direct contact. The second conductive element 112 and the fourth conductive element 122 can be made of the same material or different materials.

[0086] For another example, referring to Figure 10, the second conductive element 1121 and the first conductive element 1111 are connected through the first conductive line 111L; the first conductive element 1111 and the fourth conductive element 1221 are connected through direct contact; the fourth conductive element 1221 and the third conductive element 1211 are connected through the third conductive line 121L; the second conductive element 1121 can also be connected to the fifth conductive element 113 through the second conductive line 113L; the fifth conductive element 113 and the ninth conductive element 1721 are connected through direct contact; and the ninth conductive element 1721 and the eighth conductive element 1711 are connected through the fourth conductive line 171L. In this scheme, the fifth conductive element 113 is disposed on the second surface of the first glass layer 110.

[0087] As another example, referring to Figure 10, the second conductive element 1122 and the first conductive element 1112 are connected through the first conductive line 111L; the first conductive element 1112 and the fourth conductive element 1222 are connected through direct contact; the fourth conductive element 1222 and the third conductive element 1212 are connected through the third conductive line 121L; the second conductive element 1122 can also be connected through direct contact with the ninth conductive element 1722; the ninth conductive element 1722 and the eighth conductive element 1712 are connected through the fourth conductive line 171L. In this design, the second surface of the first glass layer 110 does not have a fifth conductive element 113.

[0088] In some other embodiments, referring to FIG5, the second conductive element 112 and the fourth conductive element 122 in the first glass layer 110 are connected by sintering. A sintering region 1311 is formed between the second conductive element 112 and the fourth conductive element 122. The sintering region 1311 occupies a large area, resulting in a large thickness of the adhesive layer 131 and a large thickness and size of the electronic device 100.

[0089] In some embodiments, the first conductive line 111L, the second conductive line 113L, the third conductive line 121L, the fourth conductive line 141L, and the fifth conductive line 171L can all be metal circuits. In some embodiments, the first conductive element 1111, the first conductive element 1112, the third conductive element 1211, the third conductive element 1212, the eighth conductive element 1711, and the eighth conductive element 1712 can all be metal circuits. In some embodiments, the second conductive element 1121, the second conductive element 1122, the fourth conductive element 1221, the fourth conductive element 1222, the ninth conductive element 1721, and the ninth conductive element 1722 can all be glass through-holes filled with conductive pillars, wherein the conductive pillars can be made of copper.

[0090] In some embodiments, referring to FIG11, a buffer layer 180 is provided between the groove wall of the first groove 111A and the first conductive element 1111. The relatively soft buffer layer 180 provides high adhesion and bonding between the groove wall of the first groove 111A and the buffer layer 180, and between the buffer layer 180 and the first conductive element 1111. This improves the reliability and stability of the first glass layer 110. Furthermore, it effectively prevents damage to the structure of the first groove 111A during the fabrication of the first conductive element 1111. For example, the material of the buffer layer 180 can be an organic compound or an oxide. Organic compounds can be polyimide, and oxides can be silicon dioxide (SiO2), etc. In addition, referring to Figure 11, buffer layers 180 can be provided between the groove wall of the second groove 121A and the third conductive element 1211, between the first glass layer 110 and the second conductive element 1121, and between the second glass layer 120 and the fourth conductive element 1221.

[0091] In some examples, referring to Figures 10 and 11, a buffer layer 180 is provided between the groove wall of the first groove 111A and the first conductive element 1111, and a buffer layer 180 is also provided between the first glass layer 110 and the second conductive element 1121. One end of the first conductive wire 111L can pass through the buffer layer 180 between the groove wall of the first groove 111A and the first conductive element 1111, and the other end of the first conductive wire 111L can pass through the buffer layer 180 between the first glass layer 110 and the second conductive element 1121. In this way, the first conductive element 1111 and the second conductive element 1121 can be connected through the first conductive wire 111L. Of course, referring to Figure 11, the connection between other conductive elements can be made in the same way as the connection between the first conductive element 1111 and the second conductive element 1121, which will not be described in detail here.

[0092] In some embodiments, referring to FIG8, the electronic device 100 may further include a first insulating adhesive layer 130, which is bonded between a first surface of the first glass layer 110 and a third surface of the second glass layer 120, thereby mitigating the risk of delamination of the electronic device 100. In some embodiments, referring to FIG8, the electronic device 100 may further include a second insulating adhesive layer 150, which is bonded between a fourth surface of the second glass layer 120 and a fifth surface of the third glass layer 140. In some embodiments, referring to FIG9, the electronic device 100 may further include a third insulating adhesive layer 160, which is bonded between a second surface of the first glass layer 110 and an eighth surface of the fourth glass layer 170. For example, the materials of the first insulating adhesive layer 130, the second insulating adhesive layer 150, and the third insulating adhesive layer 160 may each independently include polyimide, benzocyclobutene, or Ajinomoto build-up film (ABF). Of course, if the electronic device 100 has other glass layers, other insulating adhesive layers can also be used to bond the glass layers together.

[0093] The embodiments of this application do not limit the thickness of the first glass layer 110, the second glass layer 120, the third glass layer 140, and the fourth glass layer 170. The thickness of the first glass layer 110, the second glass layer 120, the third glass layer 140, and the fourth glass layer 170 can be selected according to actual design requirements.

[0094] This application provides a method for fabricating an electronic device 100. Referring to FIG12, the method includes:

[0095] S100: Provide a first glass layer having a first surface and a second surface disposed opposite to each other, the first surface having a first groove and a first through hole penetrating the first surface and the second surface.

[0096] In this step, referring to (1) in Figure 13 and (1) in Figure 14, a first groove 111A is formed on the first surface of the first glass layer 110 for a first conductive element 111 to be subsequently placed in the first groove 111A. A first through hole is formed in the first glass layer 110, penetrating the first surface and the second surface, for a first conductive post to be subsequently placed into the first through hole to obtain a second conductive element 112.

[0097] To more clearly show each preparation step in Figures 13(1) to 13(6), only some reference numerals for each step are shown in Figures 13(1) to 13(5), while all reference numerals for the electronic device 100 are shown in Figure 13(6). The reference numerals in Figure 14 are similar to those in Figure 13.

[0098] In some embodiments, the structure of the first groove 111A can be a blind groove. The first groove 111A can be formed on the first glass layer 110 by laser-induced etching of the first surface of the first glass layer 110, followed by chemical etching to remove excess glass material to obtain the first groove 111A. Alternatively, the first groove 111A can be formed on the first glass layer 110 by dry etching, such as using high-energy plasma to etch the exposed first surface to remove unwanted glass material to obtain the first groove 111A. These methods are merely examples and do not constitute a limitation on the methods of forming the first groove 111A in the embodiments of this application.

[0099] In some embodiments, the size of the first groove 111A can be set according to the size of the first conductive element 111 to be prepared, as long as the first surface and the first conductive element 111 are substantially flush. In some embodiments, the method of processing the first glass layer 110 to obtain the first through hole may include laser processing, wet etching, or plasma etching, etc.

[0100] In some embodiments, step S100 further includes: referring to (1) in FIG13, firstly, a first glass layer 110 is disposed on the surface of a carrier 1000, then a first groove 111A is formed on the first surface of the first glass layer 110, and a first through hole is formed in the first glass layer 110, penetrating the first and second surfaces. An adhesive layer can be used to adhere the first glass layer 110 to the surface of the carrier 1000, as shown in (6) in FIG13. Subsequently, the carrier 1000 can be removed by removing the adhesive layer. Thus, the carrier 1000 can support the first glass layer 110, which is beneficial for the fabrication process of the electronic device 100. In other embodiments, referring to (1) in FIG14, a carrier 1000 is not required, and the first glass layer 110 can be processed directly. In this embodiment, the thickness of the first glass layer 110 is typically larger.

[0101] The difference between the fabrication processes shown in Figures 13 and 14 is that in the fabrication process shown in Figure 13, the electronic device 100 is usually fabricated along a single direction (such as a single direction perpendicular to the thickness of the carrier plate 1000). When the electronic device 100 is used as a substrate in a packaging structure, the first glass layer 110 can serve as a build-up layer (BU) in the electronic device 100. In the fabrication process shown in Figure 14, the electronic device 100 can be fabricated along two directions (such as two directions perpendicular to the first surface of the first glass layer 110). When the electronic device 100 is used as a substrate in a packaging structure, the first glass layer 110 can serve as a core layer in the electronic device 100.

[0102] S200: A first conductive element is provided in the first groove, and a second conductive element is obtained by providing a first conductive post in the first through hole. The first conductive element and the second conductive element are connected.

[0103] In some embodiments, referring to (2) in FIG13 and (2) in FIG14, setting the first conductive element 111 in the first groove 111A includes: firstly forming a first seed layer on the surface of the first groove 111A (typically by wet process or physical vapor deposition); then forming a conductive material on the first seed layer (typically by electroplating copper (E-lytic Cu)) to obtain the first conductive element 111. The materials of the first seed layer and the conductive material can be copper.

[0104] In one embodiment, obtaining the second conductive element 112 by setting a first conductive post in a first through hole includes: firstly, forming a second seed layer on the surface of the first through hole; then forming a first metal on the second seed layer to obtain the first conductive post, thereby obtaining the second conductive element 112. The method of setting the second seed layer can refer to that of setting the first seed layer, and the method of setting the first metal can refer to that of a conductive material.

[0105] In some embodiments, step S120 further includes: before forming the first seed layer on the surface of the first groove 111A, pre-forming a buffer layer on the surface of the first groove 111A (the material of the buffer layer can be an organic compound or an oxide; the organic compound can be polyimide, etc., and the oxide can be silicon dioxide, etc., which are not specifically limited in this embodiment), and then forming the first seed layer on the buffer layer; in this way, a relatively soft buffer layer is provided between the groove wall of the first groove 111A and the first conductive element 111, and the groove wall of the first groove 111A and the buffer layer, as well as the buffer layer and the first conductive element 111, have high adhesion and bonding effect, which can improve the reliability and stability of the first glass layer 110. In addition, it can also effectively avoid damage to the structure of the first groove 111A during the process of preparing the first conductive element 111. Of course, a buffer layer can also be provided between the first glass layer 110 and the second conductive element 112.

[0106] In some embodiments, after a first conductive element 111 is disposed in the first groove 111A and a first conductive post is disposed in the first through hole to obtain a second conductive element 112, the first surface and the second surface of the first glass layer 110 are leveled. This facilitates the placement of other glass layers on the first surface and the second surface of the first glass layer 110, improving the connection effect between the first glass layer 110 and other glass layers. For example, the leveling of the first surface and the second surface of the first glass layer 110 includes treating the first surface and the second surface with etching or chemical mechanical polishing (CMP) to remove additional material on the first surface and the second surface, thereby improving the flatness of the first surface and the second surface.

[0107] In some embodiments, referring to (2) in FIG13 and (2) in FIG14, the first conductive element 111 can be connected by direct contact with the second conductive element 112, and the first conductive element 111 and the second conductive element 112 can also be connected by a metal line.

[0108] In some embodiments, referring to (2) in FIG14, the method of fabricating electronic device 100 may further include: forming a third groove 113A on the second surface of the first glass layer 110, disposing a fifth conductive element 113 in the third groove 113A, and connecting the third conductive element 121 and the second conductive element 112.

[0109] S300: A second glass layer is disposed on one side of the first glass layer. The second glass layer includes a third surface and a fourth surface disposed opposite to each other. The third surface and the first surface are opposite to each other. The fourth surface has a second groove and a second through hole penetrating the third surface and the fourth surface.

[0110] In this step, the second glass layer 120 is disposed on one side of the first glass layer 110, and the first surface of the first glass layer 110 and the third surface of the second glass layer 120 are opposite to each other. For example, referring to (3) in FIG13 and (3) in FIG14, the first insulating adhesive layer 130 can be used to bond the first surface of the first glass layer 110 and the third surface of the second glass layer 120. For example, the first insulating adhesive layer 130 is formed on the first surface of the first glass layer 110, and the first insulating adhesive layer 130 can be in liquid form or dry film form. Furthermore, referring to (3) in FIG14, when the fifth conductive element 113 is disposed in the first glass layer 110, a fourth glass layer 170 can be disposed on the side of the first glass layer 110 away from the second glass layer 120, and the second surface of the first glass layer 110 and the eighth surface of the fourth glass layer 170 can be bonded using a third insulating adhesive layer 160.

[0111] Furthermore, in step S300, the setting of the second groove 121A can refer to the setting method of the first groove 111A in step S100; the setting of the second through hole in the second glass layer 120 can refer to the setting method of the first through hole in the first glass layer 110 in step S100.

[0112] In some embodiments, referring to (4) in FIG13 and (4) in FIG14, before the second through hole is opened in the second glass layer 120, the first insulating adhesive layer 130 opposite to the second conductive element 112 is removed so that the subsequently prepared fourth conductive element 122 can directly contact the second conductive element 112 to achieve connection.

[0113] In other embodiments, before forming the second through-hole in the second glass layer 120, the first insulating adhesive layer 130 opposite the first conductive element 111 can be removed so that the subsequently fabricated fourth conductive element 122 can directly contact the first conductive element 111. Then, the first conductive element 111 and the second conductive element 112 are connected to achieve the connection between the second conductive element 112 and the fourth conductive element 122. The first insulating adhesive layer 130 can be removed by laser ablation.

[0114] In some embodiments, step S300 further includes: referring to (4) in FIG14, before forming the fourth through hole in the fourth glass layer 170, removing the third insulating adhesive layer 160 opposite the second conductive element 112 so that the subsequently prepared ninth conductive element 172 can directly contact the second conductive element 112. Alternatively, before forming the fourth through hole in the fourth glass layer 170, the third insulating adhesive layer 160 opposite the fifth conductive element 113 can also be removed so that the subsequently prepared ninth conductive element 172 can directly contact the fifth conductive element 113, and then the fifth conductive element 113 and the second conductive element 112 are connected to achieve the connection between the second conductive element 112 and the ninth conductive element 172, thus obtaining the electronic device 100 shown in FIG10.

[0115] S400: A third conductive element is provided in the second groove, and a second conductive post is provided in the second through hole to obtain a fourth conductive element. The third conductive element and the fourth conductive element are connected, and the second conductive element and the fourth conductive element are also connected.

[0116] In some embodiments, before forming the second through hole in the second glass layer 120, the first insulating adhesive layer 130 opposite the second conductive element 112 can be removed, a third seed layer can be formed on the second conductive element 112, and a second metal can be formed on the third seed layer to obtain a second conductive pillar, thereby obtaining the fourth conductive element 122. In this way, the second conductive element 112 and the fourth conductive element 122 can be connected through direct contact. The arrangement of the third seed layer can refer to that of the first seed layer, and the arrangement of the second metal can refer to that of a conductive material.

[0117] In other embodiments, referring to (5) in Figure 13 and (5) in Figure 14, before forming the second through hole in the second glass layer 120, the first insulating adhesive layer 130 opposite the first conductive element 111 can be removed, and then a fourth seed layer can be formed on the first conductive element 111, and then a second conductive post can be formed on the fourth seed layer to obtain the fourth conductive element 122. In this way, the fourth conductive element 122 can directly contact the first conductive element 111, and then the first conductive element 111 and the second conductive element 112 can be connected to realize the connection between the second conductive element 112 and the fourth conductive element 122. The arrangement of the fourth seed layer can refer to that of the first seed layer.

[0118] The method for fabricating the electronic device 100 in this application embodiment further includes: fabricating other glass layers and conductive elements disposed therein on the side of the second glass layer 120 away from the first glass layer 110; or, fabricating other glass layers and conductive elements disposed therein on the side of the fourth glass layer 170 away from the first glass layer 110. The fabrication method is similar to the fabrication method of the second glass layer 120 and the conductive elements disposed therein, and will not be described again here.

[0119] This application provides a packaging structure 1. Referring to Figures 15 to 18, the packaging structure 1 includes an electronic device 100 and a chip (the chip can be chip 11 in Figure 15, or chip 11A, chip 11B, and chip 11C in Figures 16 to 18). The electronic device 100 and the chip are connected. The electronic device 100 can be the same as the one described in the above embodiments, or it can be the electronic device 100 prepared by the preparation method described in the above embodiments. The electronic device 100 can be used as a substrate or an adapter board.

[0120] In some embodiments, referring to Figures 15 to 17, the package structure 1 may include a single electronic device 100. In some embodiments, referring to Figure 18, the package structure 1 may also include a plurality of stacked electronic devices 100.

[0121] The following explanation addresses the case where package structure 1 includes only a single electronic device 100:

[0122] For example, referring to Figure 15, when the electronic device 100 serves as the substrate in the packaging structure 1, the difference between the thermal expansion coefficients of the chip and the substrate is small when the chip is directly connected to the substrate. This reduces the likelihood of warping due to thermal mismatch between the chip and the substrate, and also minimizes electrical signal transmission loss between them. Furthermore, due to the small thickness and package volume of the substrate, the packaging structure 1 has a relatively small thickness and package volume. In other words, the packaging structure 1 of this solution only contains the substrate and does not include an adapter plate; the electronic device 100 in this embodiment serves as the substrate.

[0123] For another example, referring to Figure 16, when the electronic device 100 serves as the substrate in the packaging structure 1, the adapter plate 30 is made of resin. When the chip is connected to the substrate via the adapter plate 30, the difference between the thermal expansion coefficients of the substrate and the adapter plate 30 is small. Therefore, warping is less likely to occur between the substrate and the adapter plate 30 due to thermal mismatch, and the electrical signal transmission loss between the substrate and the adapter plate 30 is also low. Furthermore, due to the small thickness and packaging volume of the substrate, the packaging structure 1 has a smaller thickness and packaging volume. In other words, the packaging structure 1 of this solution includes an adapter plate 30 and a substrate. The adapter plate 30 is made of resin, and the electronic device 100 in this embodiment serves as the substrate.

[0124] As another example, referring to Figure 17, when the electronic device 100 serves as an adapter plate in the packaging structure 1, the difference between the thermal expansion coefficients of the chip and the adapter plate is small when the chip is connected to the substrate 20 via the adapter plate. This reduces the likelihood of warping due to thermal mismatch between the chip and the adapter plate, and also minimizes electrical signal transmission loss between them. Furthermore, due to the small thickness and package volume of the adapter plate, the packaging structure 1 has a smaller thickness and package volume. In other words, the packaging structure 1 of this solution includes an adapter plate and a substrate 20, where the substrate 20 is made of resin material, and the electronic device 100 in this embodiment serves as the adapter plate.

[0125] The following explains the case where package structure 1 includes multiple electronic devices 100:

[0126] For example, referring to Figure 18, when two electronic devices 100 serve as the substrate and adapter plate in the packaging structure 1 respectively (e.g., electronic device 100A serves as the adapter plate and electronic device 100B serves as the substrate), when the chip is connected to the substrate through the adapter plate, the difference between the thermal expansion coefficients of the chip and the adapter plate is small, and the difference between the thermal expansion coefficients of the substrate and the adapter plate is also small. Therefore, warping problems due to thermal mismatch are less likely to occur between the chip and the adapter plate, and between the adapter plate and the substrate, and the electrical signal transmission loss between the chip, the adapter plate, and the substrate is also small. Furthermore, due to the small thickness and packaging volume of the adapter plate and the substrate, the packaging structure 1 has a small thickness and packaging volume. In other words, the packaging structure 1 of this solution contains an adapter plate and a substrate, and the electronic device 100 in this embodiment serves as both the adapter plate and the substrate. Of course, the packaging structure 1 may also include more than two electronic devices 100. For example, the packaging structure 1 may include multiple substrates, which can be electronic devices 100.

[0127] Figure 19 shows some schematic diagrams of packaging structures, where (1) in Figure 19 is a side view of the packaging structure and (2) in Figure 19 is a top view of the packaging structure.

[0128] Referring to Figure 19, in a conventional packaging structure, when the substrate 20 and chip 11 are connected, the coefficient of thermal expansion of the substrate 20 is usually greater than that of the chip 11, and the substrate 20 is likely to warp due to stress. To suppress the impact of substrate 20 warping on the packaging structure, an annular element 3 is usually provided on the side of the substrate 20 near the chip 11 (for example, the annular element 3 can be connected to the edge of the substrate 20). The coefficient of thermal expansion of the annular element 3 is usually greater than that of the substrate 20, and a stress opposite in direction to the previous stress (the previous stress refers to the stress between the substrate 20 and the chip 11) is generated between the annular element 3 and the substrate 20, ultimately reducing the probability of substrate 20 warping and protecting the packaging structure. The material of the annular element 3 can be metal or the like.

[0129] Figure 20 is a schematic diagram of some other packaging structures provided in the embodiments of this application, wherein (1) in Figure 20 is a side view of the packaging structure and (2) in Figure 20 is a top view of the packaging structure.

[0130] Referring to Figure 20, using the electronic device 100 of this application embodiment as a substrate, since the difference in thermal expansion coefficients between the chip 11 and the substrate is small, the substrate is not prone to warping. Therefore, the ring member 3 can be omitted in the packaging structure 1 of this application embodiment. In this way, the effective usable area within the packaging structure 1 can be expanded, and the manufacturing cost of the packaging structure 1 can be reduced.

[0131] This application provides an electronic device comprising the packaging structure 1 described above and a circuit board 2, wherein the packaging structure 1 is disposed on the circuit board 2. Since the principle by which this electronic device solves the problem is similar to that of the packaging structure 1 described above, the implementation of this electronic device can refer to the implementation of the packaging structure 1 described above, and repeated details will not be elaborated further.

[0132] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. An electronic device used as a substrate or adapter board, characterized in that, Includes a first glass layer and a second glass layer stacked together; The first glass layer has a first surface and a second surface disposed opposite to each other, and a first groove is formed on the first surface; The second glass layer has a third surface and a fourth surface disposed opposite to each other, the fourth surface having a second groove, and the third surface being opposite to the first surface; The electronic device further includes a first conductive element, a second conductive element, a third conductive element, and a fourth conductive element; the first conductive element is located within the first groove, the second conductive element is located within the first glass layer, and the second conductive element penetrates the first surface and the second surface; the third conductive element is located within the second groove, the fourth conductive element is located within the second glass layer, and the fourth conductive element penetrates the third surface and the fourth surface; the third conductive element and the fourth conductive element are connected. The second conductive element and the fourth conductive element are connected.

2. The electronic device according to claim 1, characterized in that, A third groove is formed on the second surface of the first glass layer, and a fifth conductive element is disposed in the third groove; the fifth conductive element is connected to the second conductive element.

3. The electronic device according to claim 1 or 2, characterized in that, A buffer layer is provided between the groove wall of the first groove and the first conductive component.

4. The electronic device according to any one of claims 1-3, characterized in that, Also includes: An insulating adhesive layer is bonded between the first surface of the first glass layer and the third surface of the second glass layer.

5. The electronic device according to claim 4, characterized in that, The connection between the second conductive element and the fourth conductive element includes: the second conductive element penetrating the insulating adhesive layer and being connected to the fourth conductive element, or the second conductive element penetrating the insulating adhesive layer and being connected to the third conductive element, and the third conductive element being connected to the fourth connector.

6. The electronic device according to any one of claims 1-5, characterized in that, Also includes: The third glass layer, the sixth conductive element, and the seventh conductive element; The third glass layer is disposed on the side of the second glass layer away from the first glass layer. The third glass layer has a fifth surface and a sixth surface disposed opposite to each other. A fourth groove is formed on the sixth surface. The fifth surface and the fourth surface are opposite to each other. The sixth conductive element is located in the fourth groove. The seventh conductive element is located in the third glass layer. The seventh conductive element penetrates the fifth surface and the sixth surface. The sixth conductive element and the seventh conductive element are connected. The fourth conductive element and the seventh conductive element are connected.

7. The electronic device according to claim 2, characterized in that, Also includes: The fourth glass layer, the eighth conductive element, and the ninth conductive element; The fourth glass layer is disposed on the side of the first glass layer away from the second glass layer. The fourth glass layer has a seventh surface and an eighth surface disposed opposite to each other. The seventh surface has a fifth groove, and the eighth surface is opposite to the second surface. The eighth conductive element is located in the fifth groove, the ninth conductive element is located in the fourth glass layer, and the ninth conductive element penetrates the seventh surface and the eighth surface; The eighth conductive element and the ninth conductive element are connected; The second conductive element and the ninth conductive element are connected.

8. A method for fabricating an electronic device, characterized in that, include: A first glass layer is provided, the first glass layer having a first surface and a second surface disposed opposite to each other, the first surface having a first groove and a first through hole penetrating the first surface and the second surface; A first conductive element is provided in the first groove, and a first conductive post is provided in the first through hole to obtain a second conductive element. The first conductive element and the second conductive element are connected. A second glass layer is disposed on one side of the first glass layer. The second glass layer includes a third surface and a fourth surface disposed opposite to each other. The third surface is opposite to the first surface. The fourth surface has a second groove and a second through hole penetrating the third surface and the fourth surface. A third conductive element is provided in the second groove, and a second conductive post is provided in the second through hole to obtain a fourth conductive element. The third conductive element and the fourth conductive element are connected, and the second conductive element and the fourth conductive element are also connected.

9. The method according to claim 8, characterized in that, A third groove is formed on the second surface, a fifth conductive element is disposed in the third groove, and the fifth conductive element and the second conductive element are connected.

10. The method according to claim 8 or 9, characterized in that, Depositing the second glass layer on one side of the first glass layer includes: bonding the first surface of the first glass layer and the third surface of the second glass layer with an insulating adhesive layer.

11. A packaging structure, characterized in that, include: An electronic device and a chip, wherein the chip is disposed on the electronic device; wherein the electronic device includes the electronic device as described in any one of claims 1-7, or the electronic device prepared by the method described in any one of claims 8-10.

12. The packaging structure according to claim 11, characterized in that, The packaging structure includes a plurality of stacked electronic devices and the chip, with the chip disposed on the plurality of stacked electronic devices.

13. An electronic device, characterized in that, include: The circuit board and the packaging structure according to claim 11 or 12, wherein the packaging structure is disposed on the circuit board.

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