Circuit structure, electronic component packaging structure, and electronic device

Abstract

The present application relates to the technical field of high-speed signal transmission, and provides a circuit structure, an electronic component packaging structure, and an electronic device. The circuit structure, the electronic component packaging structure, and the electronic device comprise a carrier substrate, a first circuit layer, an interconnect structure, and a connection structure. The carrier substrate is provided with an accommodation hole. The first circuit layer is located on one surface of the carrier substrate. The interconnect structure is located in the accommodation hole. The interconnect structure is fixedly connected to the carrier substrate by means of the connection structure. The interconnect structure comprises a wire, one end of the wire is connected to the first circuit layer, and the other end of the wire is used for being electrically connected to an electronic component. The present application can achieve high-bandwidth and high-density interconnection of a circuit structure.

Description

Circuit structure, electronic device packaging structure and electronic equipment

[0001] This application claims priority to Chinese patent application filed on December 20, 2024, with application number 202411913761.6 and entitled "Circuit Structure, Electronic Device Packaging Structure and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of high-speed signal transmission technology, and in particular to a circuit structure, electronic device packaging structure, and electronic equipment. Background Technology

[0003] In the field of high-speed serial interface interconnects, the performance of key components such as high-speed serializers and deserializers, high-speed analog-to-digital converters (ADCs), and high-speed digital-to-analog converters (DACs) is crucial to modern electronic systems. In the package substrate design of these components, the vertical interconnect structure plays a central role in connecting and transmitting signals. The vertical interconnect structure includes solder balls and plated through holes (PTHs) on the package core layer, serving as bridges for signal transmission between different layers.

[0004] However, existing plated vias in vertical interconnect structures suffer from impedance discontinuities. When high-speed signals pass through these discontinuous areas, reflection, attenuation, and dispersion occur, limiting further bandwidth improvements in the entire interconnect system. Furthermore, existing plated vias cannot achieve high-density interconnects. Therefore, optimizing vertical interconnect structures to improve bandwidth and achieve high-density interconnects has become a critical issue that urgently needs to be addressed in the field of high-speed serial interface interconnects. Summary of the Invention

[0005] This application provides a circuit structure, an electronic device packaging structure, and an electronic device. The aim is to achieve high bandwidth and high density interconnection in the circuit structure.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] On one hand, this application provides a circuit structure including a carrier board, a first circuit layer, an interconnect structure, and a connection structure. The first circuit layer is located on one surface of the carrier board; the carrier board has a receiving hole, the interconnect structure is located in the receiving hole, and the interconnect structure is fixedly connected to the carrier board through the connection structure; the interconnect structure includes a wire, one end of which is connected to the first circuit layer, and the other end of which is used for electrical connection to an electronic device.

[0008] The circuit structure provided in this application features receiving holes on a carrier board. This allows an interconnect structure, including wires, to be housed within these holes and fixedly connected to the carrier board via a connecting structure, thus ensuring the position of the interconnect structure and the carrier board is fixed. One end of the wire connects to the first circuit layer, and the other end connects to an electronic device. The electronic device can then establish a signal connection with the first circuit layer via the wire. By housing the interconnect structure within the receiving holes on the carrier board and fixing it to the carrier board via the connecting structure, the interconnect structure can be fabricated independently. After fabrication, it can be installed and fixed to the receiving holes on the carrier board via the connecting structure. This design eliminates the need for electroplating metal into through-holes to form plated holes for signal interconnection. Because the circuit structure provided in this application does not use plated hole interconnection, but instead connects the electronic device to the first circuit layer via wires in the interconnect structure mounted within the receiving holes, the wires used for signal transmission are smaller than the plated holes. Therefore, this application can open more accommodating holes within the limited area of ​​the carrier board to lay out more conductors, or lay out more conductors in a single accommodating hole, thereby achieving high-density interconnection; in addition, since this application does not use plated via interconnection, but uses conductors that are easy to impedance match with other transmission lines in the entire link to achieve signal interconnection, it can improve the impedance discontinuity problem of the line structure, thereby increasing the interconnection bandwidth.

[0009] In one possible implementation, the interconnect structure includes a first structure; the first structure includes a dielectric layer and a conductor connected to the dielectric layer.

[0010] The first structure of this application provides a dielectric layer, which can fix the wires to a certain extent, preventing them from moving or falling out within the receiving hole and enhancing their stability. In addition, the presence of the dielectric layer can also protect the wires from mechanical damage to a certain extent, extending their lifespan. Furthermore, the dielectric layer can also prevent electrical short circuits between the wires and the carrier board to a certain extent, ensuring normal signal transmission.

[0011] In one possible implementation, the first structure further includes a first reference layer and a second reference layer; a dielectric layer is located between the first reference layer and the second reference layer, and a wire is located within the dielectric layer; a ground via is provided within the dielectric layer, one end of the ground via being connected to the first reference layer, and the other end of the ground via being connected to the second reference layer.

[0012] The first structure of this application, using the above-described configuration, can be a stripline structure. This stripline structure provides a shielding layer for the conductor, effectively blocking interference from external electromagnetic fields and protecting the conductor. Simultaneously, this shielding effect reduces signal attenuation and distortion during transmission, improving the stability and reliability of signal transmission. Furthermore, the stripline structure facilitates higher impedance matching with other transmission lines throughout the link, resulting in smaller impedance fluctuations in the line structure, which are easier to control and can meet the requirements of high-speed, high-frequency signal transmission.

[0013] In one possible implementation, the first structure further includes a third reference layer located within the dielectric layer and between the first and second reference layers; the ground via is connected to the third reference layer.

[0014] This application provides an additional shielding and isolation for conductors by setting a third reference layer and connecting it to a ground via. This third reference layer helps reduce crosstalk. It also provides an additional return path for signals, especially in high-frequency signal transmission where the return path may no longer be limited to the first and second reference layers. This additional return path helps reduce ground potential difference and ground noise, improving signal integrity and stability.

[0015] In one possible implementation, the first structure further includes a plurality of third reference layers and a plurality of fourth reference layers, and the wires include a plurality of first wires and a plurality of second wires; the plurality of third reference layers and the plurality of fourth reference layers are all located within the dielectric layer, and the plurality of third reference layers are located between the first reference layers and the plurality of fourth reference layers;

[0016] Along the first direction, the third reference layer and the first conductor are alternately and spaced apart, and the first direction is parallel to the first reference layer;

[0017] Along the first direction, the fourth reference layer and the second conductor are alternately and spaced apart;

[0018] The first conductor is set to correspond to the fourth reference layer, and the second conductor is set to correspond to the third reference layer.

[0019] This application, through the aforementioned arrangement, enables the first and second conductors to be staggered, effectively reducing electromagnetic interference and crosstalk between adjacent conductors. The staggered arrangement also helps reduce signal reflection and attenuation during transmission, thereby improving signal integrity and stability. Especially for high-speed signal transmission, this ensures that the signal maintains high quality upon arrival at the receiving end.

[0020] In one possible implementation, the conductors include a coupled first conductor and a second conductor, which are parallel and spaced apart; the first conductor and the second conductor are used to transmit differential signals.

[0021] The first structure of this application uses coupled first and second conductors to transmit differential signals as a differential pair. Because the two conductors of the differential pair are tightly coupled, the resulting electromagnetic fields cancel each other out, thus reducing radiation and sensitivity to external interference. This provides better suppression of electromagnetic interference and radio frequency interference, helping to maintain signal integrity, especially during high-speed signal transmission. Furthermore, differential signals can transmit higher data rates and larger signal amplitudes, making them suitable for communication interfaces requiring high bandwidth and high data rates.

[0022] In one possible implementation, the first conductor and the second conductor are arranged along a first direction, the first conductor having a larger dimension in the first direction than the first conductor having a larger dimension in the second direction, and the second conductor having a larger dimension in the first direction than the second conductor having a larger dimension in the second direction; the first direction is parallel to the first reference layer, and the second direction is parallel to the arrangement direction of the first reference layer and the second reference layer.

[0023] This application arranges the first and second coupled wires along a first direction, such that the dimension of the first wire in the first direction is larger than its dimension in the second direction, and the dimension of the second wire in the first direction is larger than its dimension in the second direction. This forms a narrow-side coupling structure. The narrow-side coupling of the differential pairs results in a smaller spacing between them, tighter coupling, and less susceptibility to external interference, thus helping to reduce crosstalk between adjacent differential pairs.

[0024] In one possible implementation, the first conductor and the second conductor are arranged along a second direction, the first conductor having a larger dimension in the first direction than the second conductor in the second direction, and the second conductor having a larger dimension in the first direction than the second conductor in the second direction; the first direction is parallel to the first reference layer, and the second direction is parallel to the arrangement direction of the first and second reference layers.

[0025] Since the dimension of the first conductor in the first direction is larger than its dimension in the second direction, and the dimension of the second conductor in the first direction is larger than its dimension in the second direction, this application arranges the first and second conductors along the second direction, enabling wide-side coupling. This wide-side coupling allows for a larger spacing between differential pairs, which helps reduce signal loss during transmission. Furthermore, the larger spacing reduces the impact of manufacturing tolerances on impedance, making impedance control of the differential pairs easier.

[0026] In one possible implementation, the first structure further includes a first reference layer; a dielectric layer is present between the first reference layer and the wire.

[0027] That is, in addition to a stripline structure, the first structure of this application can also be a microstrip line structure. The microstrip line structure is small in size and light in weight, making it suitable for applications with high requirements for size and weight; in addition, the microstrip line structure is simple in structure, highly reliable, and suitable for long-term stable operation environments.

[0028] In one possible implementation, the side of the conductor facing away from the first reference layer has a dielectric layer.

[0029] That is, in addition to having a dielectric layer on the side of the conductor closest to the first reference layer, the conductor can also have a dielectric layer on the side facing away from the first reference layer, thus having dielectric layers on both opposite sides of the conductor. With dielectric layers on both opposite sides of the conductor, the distribution of the electromagnetic field around the conductor is more symmetrical. This symmetry helps reduce electromagnetic wave radiation and leakage, improving the electromagnetic compatibility performance of the transmission line. Furthermore, the double-sided dielectric layer structure provides better support and protection for the conductor, enhancing its mechanical stability and helping to prevent deformation or damage under external forces, thus improving circuit reliability. Moreover, microstrip lines with a double-sided dielectric layer structure are easier to integrate and connect with other circuit components, simplifying manufacturing and processing, and reducing production costs and complexity.

[0030] In one possible implementation, the conductor includes a coupled first conductor and a second conductor for transmitting differential signals; the first conductor and the second conductor are spaced apart along a first direction, the first conductor having a larger dimension in the first direction than the first conductor having a larger dimension in the second direction, and the second conductor having a larger dimension in the first direction than the second conductor having a larger dimension in the second direction; the first direction is parallel to a first reference layer, and the second direction is parallel to the arrangement direction of the first reference layer and the dielectric layer.

[0031] When the first structure of this application adopts a microstrip line structure, the conductors include a first conductor and a second conductor coupled to each other. The size of the first conductor in the first direction is larger than that in the second direction, and the size of the second conductor in the first direction is larger than that in the second direction. By arranging the first conductor and the second conductor at intervals along the first direction, narrow-side coupling of the differential pairs of the first structure can be achieved. The spacing between the differential pairs with narrow-side coupling is smaller, the coupling is tighter, and the signal is less susceptible to external interference, which helps to reduce crosstalk between adjacent differential pairs.

[0032] In one possible implementation, the first structure comprises multiple structures arranged in an array.

[0033] The interconnect structure of this application employs multiple first structures, which enables the interconnect structure to process multiple signals in parallel, thereby improving the efficiency and throughput of signal processing. This is particularly advantageous for application scenarios that require simultaneous processing of large amounts of data (such as high-speed data transmission, image processing, etc.). Arranging multiple first structures in an array can achieve higher circuit density and integration within a limited space, which helps to reduce the size and weight of the circuit structure and improve its portability and reliability.

[0034] In one possible implementation, a dielectric layer and multiple power layers are provided between two adjacent first structures, with the multiple power layers located within the dielectric layer between the two adjacent first structures; the multiple power layers are arranged at intervals.

[0035] This application, by setting up multiple power layers, enables more flexible and efficient power distribution. Different power layers can be assigned to different power supply voltages, thereby meeting the diverse power supply needs of complex systems. Assigning multiple power layers to multiple power supply voltages also helps reduce power path length and impedance, improving power distribution efficiency.

[0036] In one possible implementation, multiple power layers are spaced apart along a first direction, which is parallel to a first reference layer.

[0037] This application, by arranging multiple power layers spaced apart along a first direction, enables more uniform power distribution, avoiding voltage drops and power noise problems caused by excessively long power paths or uneven distribution. This helps ensure that all parts of the circuit receive a stable and consistent power supply voltage, improving circuit performance and reliability. Furthermore, the co-location of multiple power layers on the same layer facilitates power management. During design, different power regions can be divided on the same layer according to actual needs, providing independent power supplies for different circuit modules or functional units, thus enabling more refined power management and control.

[0038] In one feasible approach, the connection structure is adhesive.

[0039] This application uses adhesive to bond the interconnect structure to the receiving holes of the carrier board, which can prevent the interconnect structure from falling off during long-term vibration or use, thereby improving the stability and reliability of the circuit structure. Furthermore, the adhesive typically has some thermal conductivity, which helps the interconnect structure dissipate heat better, reducing its operating temperature and extending its service life. In addition, using adhesive bonding can save board space, increase the miniaturization of the circuit structure, and facilitate more compact circuit design and high-density signal interconnection.

[0040] In one possible implementation, there are multiple receiving holes and multiple interconnect structures; the multiple interconnect structures are disposed one-to-one within the multiple receiving holes.

[0041] This application incorporates multiple vias, each containing an interconnect structure. This allows the substrate to support multiple interconnect structures, enabling parallel signal transmission and increasing signal channels. This, in turn, improves signal transmission efficiency and throughput, facilitating high-speed data transmission and complex signal processing. Furthermore, arranging multiple vias on the substrate, each containing an interconnect structure, allows for more complex circuit layouts and higher wiring density requirements. This facilitates greater functional integration within a limited space, meeting the miniaturization and high-performance demands of modern electronic products.

[0042] In one feasible approach, the circuit structure is a packaging substrate, and the carrier board is a core layer.

[0043] The circuit structure also includes a second circuit layer, which is located on the side of the core board layer away from the first circuit layer;

[0044] One end of the conductor is connected to the first circuit layer, and the other end of the conductor is electrically connected to electronic devices through the second circuit layer.

[0045] The circuit structure of this application is a packaging substrate, with a core layer as the carrier. Interconnect structures can be embedded and fixed within the core layer of the packaging substrate. One end of the conductors in the interconnect structure within the core layer can be connected to a first circuit layer, and the other end can be connected to a second circuit layer. Different electronic devices can be connected to the first and second circuit layers respectively, thus enabling signal interconnection between different electronic devices through the packaging substrate.

[0046] In one feasible approach, the circuit structure is a circuit board.

[0047] That is, the circuit structure of this application can be a circuit board, so that different electronic devices on the circuit board can achieve signal interconnection through the interconnection structure in the circuit board.

[0048] On the other hand, this application provides an electronic device packaging structure, which includes an electronic device and the aforementioned circuit structure, wherein the circuit structure is a packaging substrate, and the electronic device is connected to the packaging substrate.

[0049] The packaging substrate of the electronic device packaging structure of this application adopts the above-mentioned circuit structure, which can realize the connection between the packaging substrate and the electronic device. Since the circuit structure does not use plated via interconnection, but uses conductors that are easier to impedance match with other transmission lines in the whole link to achieve signal interconnection, the impedance discontinuity problem of the circuit structure can be improved, thereby increasing the interconnection bandwidth. In addition, since the circuit structure does not use plated via, but uses conductors of the interconnection structure for signal transmission, and the conductors are smaller than the size of plated via, this application can open more accommodating vias within the limited area of ​​the substrate to lay out more conductors, or lay out more conductors in a single accommodating via, thereby achieving high-density interconnection.

[0050] In another aspect, this application also provides an electronic device, which includes a circuit board and the above-mentioned electronic device packaging structure, wherein the electronic device packaging structure is connected to the circuit board.

[0051] Since the electronic device includes the aforementioned electronic component packaging structure, the electronic device and the electronic component packaging structure can solve the same technical problems and achieve the same technical effects.

[0052] In one feasible implementation, the circuit board has the circuit structure described above. By employing this circuit structure, electronic components on the circuit board can be interconnected. Attached Figure Description

[0053] Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0054] Figure 2 is a schematic diagram of the structure of an electronic device provided by the related technology;

[0055] Figure 3 is one of the schematic diagrams of the circuit structure provided in the embodiment of this application;

[0056] Figure 4 is a schematic diagram of the carrier plate provided in an embodiment of this application;

[0057] Figure 5 is a schematic diagram of one of the first structures provided in the embodiments of this application;

[0058] Figure 6 is a second structural schematic diagram of the first structure provided in the embodiment of this application;

[0059] Figure 7 is a third structural schematic diagram of the first structure provided in the embodiment of this application;

[0060] Figure 8 is a top view of Figure 7;

[0061] Figure 9 is a second schematic diagram of the circuit structure provided in the embodiment of this application;

[0062] Figure 10 is a schematic diagram of the line structure in Figure 9 from a first-view perspective;

[0063] Figure 11 is a schematic diagram of the line structure in Figure 9 from a second perspective;

[0064] Figure 12 is a fourth structural schematic diagram of the first structure provided in the embodiment of this application;

[0065] Figure 13 is a fifth structural schematic diagram of the first structure provided in the embodiment of this application;

[0066] Figure 14 is a sixth structural schematic diagram of the first structure provided in the embodiment of this application;

[0067] Figure 15 is a seventh structural schematic diagram of the first structure provided in the embodiment of this application;

[0068] Figure 16 is a schematic diagram of one of the interconnection structures provided in the embodiments of this application;

[0069] Figure 17 is a top view of the interconnection structure in Figure 16;

[0070] Figure 18 is a second schematic diagram of the interconnection structure provided in the embodiment of this application;

[0071] Figure 19 is a schematic diagram of a package substrate in which one part of the substrate uses plated holes and the other part uses the interconnect structure of this application.

[0072] Figure 20 is a comparison of the insertion loss obtained when the packaging substrate uses plated via interconnects and the interconnect structure of this application.

[0073] Figure 21 is a comparison of return loss obtained when the packaging substrate is interconnected using plated vias and interconnected using the interconnect structure of this application.

[0074] Reference numerals: 01-Electronic device; 100-Circuit structure; 10-Carrier board; 11-Hole accommodating device; 20-First circuit layer; 30-Second circuit layer; 40-Interconnection structure; 41-First structure; 411-Wire; 4111-First wire; 4112-Second wire; 412-Dielectric layer; 413-First reference layer; 414-Second reference layer; 415-Ground hole; 416-Third reference layer; 417-Fourth reference layer; 42-Power layer; a-First direction; b-Second direction; 200-Circuit board; 300-Electronic device packaging structure; 310-Packaging substrate; 311-Core board layer; 320-Chip; 400-Electrical connection component. Detailed Implementation

[0075] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0077] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0078] This application provides an electronic device 01. The electronic device 01 may include a mobile phone, tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or other equipment such as home appliances, aircraft engine control systems, avionics systems, automotive systems, and downhole oil exploration systems. This application does not impose any special limitations on the specific form of the aforementioned electronic device 01.

[0079] Figure 1 is a schematic diagram of the structure of the electronic device 01 provided in an embodiment of this application. As shown in Figure 1, the electronic device 01 may include a circuit board 200, such as a printed circuit board (PCB), which can be connected to an electronic device package structure 300. The electronic device package structure 300 can be electrically connected to the circuit board 200 via an electrical connection component 400, thereby enabling the electronic device package structure 300 to achieve signal interconnection with other chips 320, other electronic devices, or other electronic modules on the circuit board 200.

[0080] In alternative embodiments, the electrical connection component 400 may include a plurality of solder balls, such as a ball grid array (BGA); or, the electrical connection component 400 may include a plurality of conductive pillars, such as metal pillars.

[0081] The circuit board 200 provided in this application embodiment can be used to transmit high-speed signals. The circuit board 200 includes, but is not limited to: base plate, middle plate, back plate, flexible printed circuit board (FPC), rigid circuit board 200, rigid-flex board, terminal circuit board 200, packaging carrier 10, low-temperature cofired ceramics (LTCC) substrate or high-temperature cofired ceramics (HTCC) substrate, etc.

[0082] In this embodiment, the circuit board 200 can be a single-layer board, a double-layer board, or a multi-layer board. That is, the circuit board 200 can include a single-layer circuit board or a multi-layer circuit board. The circuit board can be a single-sided board or a double-sided board. That is, the circuit board can include an insulating layer and a wiring layer located on one side of the insulating layer; or, the circuit board can also include an insulating layer and wiring layers located on opposite sides of the insulating layer.

[0083] There can be a bonding layer between two adjacent circuit boards, and the two adjacent circuit boards can be bonded and fixed together by the bonding layer.

[0084] In one implementation, the bonding layer can be an insulating layer.

[0085] In one implementation, the bonding layer can be formed by laminating a prepreg (PP).

[0086] The electronic device packaging structure 300 may include a circuit structure 100 and electronic devices. The circuit structure 100 may be a packaging substrate 310, and the electronic devices may be connected to the packaging substrate 310. The packaging substrate 310 may be connected to a circuit board 200.

[0087] The electronic device can be a chip 320, or a passive device such as a connector, capacitor, or inductor. The electronic device can be electrically connected to the packaging substrate 310, and can be interconnected with other electronic devices through the packaging substrate 310 and the circuit board 200.

[0088] The number of chips 320 can be two or more. Figure 1 is an example of a chip 320 consisting of one chip. It should be understood that one chip 320 is merely an example and is not intended to limit this application.

[0089] In addition, the chip 320 shown in Figure 1 can be a single chip 320 or multiple chips 320 stacked in three dimensions, and this application does not limit it in this way.

[0090] In some implementations, chip 320 may include memory, system on chip (SOC), analog chip 320, digital chip 320, etc.

[0091] The packaging substrate 310 can be a system-in-package (SIP) carrier 10, a single-chip package (SCP) carrier 10, a multi-chip package (MCP) carrier 10, or a ball grid array (BGA) carrier 10, etc.

[0092] The electronic device packaging structure 300 may further include a package body (not shown in FIG1) and a heat sink (not shown in FIG1). The package body is packaged on the side of the packaging substrate 310 where the chip 320 is located, so as to package the chip 320 and other devices on the packaging substrate 310. The heat sink is connected to the side of the packaging substrate 310 facing away from the chip 320, so as to dissipate heat for the electronic devices such as the chip 320 packaged in the package body and ensure the electrical performance of the chip 320 and other devices.

[0093] In some embodiments, the package may also integrate structures with control functions, such as controllers with control circuitry. These controllers are electrically connected to the chip 320 and can control the operation of the chip 320. For safety and reliability, the temperature status of the electronic device package structure 300 can be monitored in real time. For example, a temperature sensor can be integrated into the electronic device package structure 300. If the temperature is too high or rises too quickly, it indicates an abnormality in the electronic device package structure 300, and preventative actions can be taken in advance, such as turning off the power.

[0094] The circuit board 200 can be a line structure 100 including interconnect structure 40.

[0095] The packaging substrate 310 of the electronic device packaging structure 300 can also be a circuit structure 100 including an interconnect structure 40. The specific structure of the circuit structure 100 will be described in detail this afternoon.

[0096] The interconnect structure 40 can be used to transmit signals for devices such as the package substrate 310 or the circuit board 200 that require vertical signal transmission. For example, the package substrate 310 or the circuit board 200 can transmit signals at high speed between different chips 320 through the interconnect structure 40.

[0097] With the continuous advancement of technology, especially the rapid development of large-scale integrated circuit technology, new electronic materials technology, and packaging interconnect technology, electronic devices 01 are moving towards miniaturization and lightweighting. Against this backdrop, vertical interconnect structures 40 have attracted considerable attention due to their advantages over planar interconnects, such as shortening signal transmission paths, effectively reducing the area occupied by interconnects on the circuit board 200 to help the system achieve smaller size and lighter weight, wider transmission bandwidth, and lower power consumption.

[0098] However, despite the numerous advantages of the vertical interconnect structure 40, some challenges remain in the related technology. As shown in Figure 2, which is a schematic diagram of the structure of the electronic device 01 provided by the related technology, when the vertical interconnect structure 40 is adopted, the impedance discontinuities in structures such as the plated through holes (PTH) on the core layer 311 of the packaging substrate 310, the plated holes on the circuit board 200, and the solder balls of the chip 320 limit the further improvement of the interconnect bandwidth of the device.

[0099] To improve impedance discontinuities on the solder ball side of chip 320 and thus increase interconnect bandwidth, in some examples, this can be achieved by reducing the ball pitch and ball size between adjacent solder balls on chip 320.

[0100] To improve the impedance discontinuity on the plated via side of the packaging substrate 310 and circuit board 200, in some examples, improvements to the existing device structure or innovations in the manufacturing process can be employed. However, current methods of improving the existing device structure and innovating the manufacturing process generally require a larger device area and cannot achieve high-density and high-bandwidth interconnects. Therefore, a new circuit structure 100 is proposed below. This circuit structure 100 involves opening receiving holes 11 on a carrier board 10 and separately fabricating an interconnect structure 40 with conductors 411. The interconnect structure 40 is then fixed within the receiving holes 11 of the carrier board 10 via a connecting structure. In this way, signal transmission can be achieved through the conductors 411 of the interconnect structure 40 without the need to electroplate metal material within the receiving holes 11 to form plated holes, thus improving the impedance discontinuity problem. At the same time, since this application uses an interconnect structure 40 with conductors 411 to achieve signal transmission, the conductors 411 are smaller in size compared to using plated holes. Therefore, this application can open more receiving holes 11 within a limited area to arrange more conductors 411, or arrange more conductors 411 within a single receiving hole 11, thereby achieving high-density interconnection.

[0101] Figure 3 is a schematic diagram of one of the circuit structure 100 provided in an embodiment of this application, and Figure 4 is a schematic diagram of the carrier board 10 provided in an embodiment of this application. Referring to Figures 3 and 4, the circuit structure 100 provided in this application may include a carrier board 10, which has receiving holes 11.

[0102] For example, the circuit structure 100 described above can be a packaging substrate 310; or, the circuit structure 100 described above can also be a circuit board 200.

[0103] The carrier board 10 can be made of epoxy resin, glass fiber, etc., and this application does not impose any special restrictions on the specific material of the carrier board 10. The carrier board 10 can serve as an insulating material and supporting structure for the circuit structure 100 to ensure the stability and reliability of the circuit structure 100.

[0104] The receiving hole 11 is provided in the carrier plate 10. For example, the receiving hole 11 can completely penetrate the carrier plate 10, that is, the receiving hole 11 can be a through hole; or, the receiving hole 11 can also partially penetrate the carrier plate 10, that is, the receiving hole 11 can be a blind hole; or, the receiving hole 11 can also be a groove located in the carrier plate 10.

[0105] For example, when the circuit structure 100 is a packaging substrate 310, the carrier board 10 can be a core layer 311, and the receiving hole 11 can completely penetrate the core layer 311; as another example, when the circuit structure 100 is a circuit board 200, the receiving hole 11 can completely penetrate the circuit board 200; as yet another example, when the circuit structure 100 is a circuit board 200, the receiving hole 11 can also be a slot located inside the circuit board 200 (that is, both openings of the receiving hole 11 are blocked by the layers of the circuit board 200).

[0106] The circuit structure 100 provided in this application may include a first circuit layer 20, which is located on a surface of the carrier board 10.

[0107] The first line layer 20 may have only one layer or may include multiple layers. Figure 3 is an illustration of the first line layer 20 including multiple layers, and is not intended to limit this application.

[0108] Figure 16 is one of the structural schematic diagrams of the interconnection structure 40 provided in the embodiments of this application, Figure 17 is a top view of the interconnection structure 40 in Figure 16, and Figure 18 is another structural schematic diagram of the interconnection structure 40 provided in the embodiments of this application. Referring to Figures 16 to 18, the line structure 100 provided in this application may further include the interconnection structure 40.

[0109] It should be understood that the specific structures of the interconnection structure 40 shown in Figures 16 to 18 are merely examples and are not specific limitations on the interconnection structure 40 of this application.

[0110] The interconnect structure 40 of this application is located within the receiving hole 11. The radial dimension of the receiving hole 11 can be set according to the radial dimension of the interconnect structure 40. The receiving hole 11 is used to accommodate the interconnect structure 40.

[0111] Furthermore, this application does not limit the specific form of the receiving hole 11. The cross-section of the receiving hole 11 can be square, circular, triangular, polygonal, or irregular in shape, etc. As long as the receiving hole 11 can accommodate the interconnect structure 40 so that the interconnect structure 40 can be disposed within the receiving hole 11, for example, the shape of the hole wall of the receiving hole 11 can be adapted to the shape of the interconnect structure 40.

[0112] The circuit structure 100 provided in this application may include a connection structure, through which the interconnection structure 40 can be fixedly connected to the carrier board 10.

[0113] The specific form of the connection structure is not limited in this application. For example, in one possible implementation, the connection structure is an adhesive.

[0114] Using adhesive to bond the interconnect structure 40 to the receiving hole 11 of the carrier board 10 can prevent the interconnect structure 40 from detaching from the carrier board 10 during long-term vibration or use, thereby improving the stability and reliability of the circuit structure 100. In addition, adhesive typically has certain thermal conductivity, which helps the interconnect structure 40 dissipate heat better, reducing its operating temperature and extending its service life. Furthermore, using adhesive bonding can save board space, increase the miniaturization of the circuit structure 100, and facilitate more compact circuit design and high-density signal interconnection.

[0115] For example, the adhesive can be epoxy resin, silicone rubber, or other adhesives. These adhesives have good bonding strength, temperature resistance, and electrical insulation properties, which can ensure that the interconnect structure 40 is firmly fixed in the carrier board 10, while meeting the electrical performance requirements of the circuit.

[0116] Besides adhesive, other connection structures can be used to fix the carrier plate 10 and the interconnection structure 40. Adhesive is just one example and is not a limitation on the connection structure. For example, welding can be used.

[0117] Please refer to Figure 3. The interconnection structure 40 may include a wire 411, one end of which is connected to the first circuit layer 20, and the other end of which is used for electrical connection to electronic devices.

[0118] That is, the interconnect structure 40 of this application includes a conductor 411, which enables the first circuit layer 20 and electronic devices to be connected. Specifically, the circuit structure 100 provided in this application does not use plated vias for signal interconnection, but instead uses the conductor 411 of the interconnect structure 40 mounted within the receiving via 11 to connect the electronic devices to the first circuit layer 20. Therefore, since this application does not use plated via interconnection but instead uses conductor 411 with better impedance continuity for signal interconnection, the impedance discontinuity problem of the circuit structure 100 can be improved, thereby increasing the interconnect bandwidth.

[0119] For example, as shown in Figure 3, the length direction of the conductor 411 (or the extension direction of the conductor 411) is parallel to the thickness direction of the carrier plate 10.

[0120] The length direction of the conductor 411 is parallel to the thickness direction of the carrier plate 10. This parallelism can be absolute or relative. In other words, the parallelism between the length direction of the conductor 411 and the thickness direction of the carrier plate 10 allows for process errors.

[0121] This application provides an accommodating hole 11 within the carrier board 10, and places the interconnect structure 40 within the accommodating hole 11 of the carrier board 10. A connecting structure secures the interconnect structure 40 to the carrier board 10. This allows the interconnect structure 40 to be fabricated independently, and after fabrication, it is installed and fixed to the accommodating hole 11 of the carrier board 10 via the connecting structure. The conductors 411 of the interconnect structure 40 enable connection between the first circuit layer 20 and electronic devices. In other words, this application does not employ the method of electroplating metal into through-holes to form plated holes, thereby achieving signal interconnection through plated holes. Instead, the electronic device is connected to the first circuit layer 20 through the wires 411 of the interconnect structure 40 assembled in the accommodating hole 11. Compared with the signal transmission of the plated hole, the signal transmission line of this application occupies less area on the carrier board 10 (the size of the wire 411 is smaller than the size of the plated hole). Therefore, this application can open more accommodating holes 11 to lay more wires 411 in a limited area, or lay more wires 411 in a single accommodating hole 11, thereby achieving high-density interconnection.

[0122] For example, the interconnect structure 40 of this application can adopt a multi-layer board structure, such as a PCB multi-layer board; it can also adopt a connector; it can also adopt a conductor with wires 411, etc. That is, this application does not limit the specific form of the interconnect structure 40, as long as the interconnect structure 40 has wires 411 that can connect the first circuit layer 20 and electronic devices.

[0123] In other embodiments, besides employing the interconnect structure 40, the circuit structure 100 can also utilize vertical via interconnects fabricated using advanced packaging processes and new materials. For example, smaller vias and hole spacing can be achieved on a glass substrate, such as through-glass vias (TGVs), thereby achieving high-bandwidth, high-density interconnects; smaller vias and hole spacing can also be achieved on a silicon-based interposer, such as through-silicon vias (TSVs), thereby achieving high-bandwidth, high-density interconnects.

[0124] In one possible implementation, the interconnect structure 40 may include a first structure 41. The first structure 41 may include a dielectric layer 412 and a wire 411 connected to the dielectric layer 412.

[0125] The dielectric layer 412 may be located on one side of the conductor 411; the dielectric layer 412 may also be located on opposite sides of the conductor 411; the dielectric layer 412 may also surround the sidewall of the conductor 411.

[0126] In addition, the opposite ends of the conductor 411 are exposed from the dielectric layer 412, so that one end of the conductor 411 can be connected to the first circuit layer 20, and the other end of the conductor 411 can be used to connect electronic devices.

[0127] The first structure 41 of this application includes a dielectric layer 412 and a conductor 411. In this way, the dielectric layer 412 can fix the conductor 411 to a certain extent, preventing the conductor 411 from moving or falling out within the receiving hole 11, thereby enhancing the stability of the conductor 411. In addition, the presence of the dielectric layer 412 can also protect the conductor 411 from mechanical damage to a certain extent, thereby extending the life of the conductor 411. Furthermore, the dielectric layer 412 can also prevent electrical short circuits between the conductor 411 and the carrier board 10 to a certain extent, thereby ensuring normal signal transmission of the conductor 411.

[0128] For example, the first structure 41 can be a stripline structure, a microstrip line structure, or a connector.

[0129] For example, when the first structure 41 uses a connector, the first structure 41 may include a dielectric layer 412 and a wire 411, with the dielectric layer 412 disposed around the sidewall of the wire 411.

[0130] For example, Figure 5 is a schematic diagram of one of the structures of the first structure 41 provided in the embodiments of this application. Referring to Figure 5, when the first structure 41 adopts a stripline structure, in one possible implementation, the first structure 41 may include a dielectric layer 412, a conductor 411, a first reference layer 413 and a second reference layer 414; the dielectric layer 412 is located between the first reference layer 413 and the second reference layer 414, and the conductor 411 is located within the dielectric layer 412.

[0131] That is, the first structure 41 can adopt a stripline structure, the dielectric layer 412 is located between the first reference layer 413 and the second reference layer 414, and the conductor 411 is located inside the dielectric layer 412.

[0132] For example, the dielectric layer 412 can also be considered as consisting of two parts, one part being located on one side of the conductor 411 and the other part being located on the other side of the conductor 411. The stripline is a strip-shaped signal line located between the mating surfaces of the two parts of the dielectric layer 412. The two opposing surfaces of the dielectric layer 412 are each provided with a reference layer (one of which is a first reference layer 413 and the other is a second reference layer 414), thereby making the signal line located between the two reference layers.

[0133] The reference layer is the ground layer, also known as the ground plane or ground layer.

[0134] As shown in Figure 5, a ground hole 415 is provided in the dielectric layer 412. One end of the ground hole 415 is connected to the first reference layer 413, and the other end of the ground hole 415 is connected to the second reference layer 414.

[0135] The ground via 415 is a metallized via. The first reference layer 413 and the second reference layer 414 are electrically connected through the ground via 415, which ensures that the potentials of the first reference layer 413 and the second reference layer 414 are equal. The ground via 415 can be obtained by forming a through hole in the first structure 41 and placing a conductive metal material inside the through hole to form the ground via 415. The two ends of the conductive metal material are respectively connected to the first reference layer 413 and the second reference layer 414.

[0136] The first structure 41 adopts the aforementioned stripline structure, with the conductor 411 embedded between the first reference layer 413 and the second reference layer 414. This structure forms a natural shielding layer, effectively blocking interference from external electromagnetic fields and providing protection for the signal traces. This shielding effect helps reduce signal attenuation and distortion during transmission, improving signal stability and reliability. Simultaneously, the stripline structure makes it easier to achieve high impedance matching with other transmission lines in the entire link, resulting in smaller impedance fluctuations in the line structure 100 and easier control.

[0137] In addition, since the conductor 411 is surrounded by the dielectric layer 412, the electromagnetic field is more evenly distributed around the conductor 411, thereby reducing the generation and propagation of electromagnetic interference (EMI).

[0138] In one possible implementation, referring further to FIG5, the first structure 41 may further include a third reference layer 416, which is located within the dielectric layer 412 and between the first reference layer 413 and the second reference layer 414. A ground via 415 is connected to the third reference layer 416.

[0139] The aforementioned third reference layer 416 is located between the first reference layer 413 and the second reference layer 414, and can serve as an intermediate reference layer or an internal reference layer. The third reference layer 416 can also be a stratum or a ground plane.

[0140] The third reference layer 416 can provide additional shielding and isolation for the conductor 411, helping to reduce crosstalk. It can also provide an additional return path for the signal, especially in high-frequency signal transmission, where the signal return may no longer be limited to the first reference layer 413 and the second reference layer 414. This additional return path helps to reduce ground potential difference and ground noise, improving signal integrity and stability.

[0141] When the first structure 41 includes a third reference layer 416, the ground via 415 can pass through the third reference layer 416 and connect one end to the first reference layer 413 and the other end to the second reference layer 414. The ground via 415 can also be connected to the third reference layer 416.

[0142] Figure 6 is a second structural schematic diagram of the first structure 41 provided in the embodiment of this application. Referring to Figure 6, in one possible implementation, the first structure 41 may include a first reference layer 413, a second reference layer 414, a dielectric layer 412, and a conductor 411; the first structure 41 may also include a plurality of third reference layers 416 and a plurality of fourth reference layers 417, and the conductor 411 includes a plurality of first conductors 4111 and a plurality of second conductors 4112.

[0143] Among them, multiple third reference layers 416 and multiple fourth reference layers 417 are located within the dielectric layer 412, and multiple third reference layers 416 are located between the first reference layer 413 and multiple fourth reference layers 417.

[0144] That is, multiple third reference layers 416 are located between the first reference layer 413 and multiple fourth reference layers 417, and multiple fourth reference layers 417 are located between the second reference layer 414 and multiple third reference layers 416.

[0145] Along the first direction a, as shown in Figure 6, the third reference layer 416 and the first conductor 4111 are alternately and spaced apart, and the first direction a is parallel to the first reference layer 413.

[0146] That is, there is a third reference layer 416 between the two first conductors 4111, and the third reference layer 416 can separate two adjacent first conductors 4111 arranged along the first direction a; or, there is a first conductor 4111 between the two third reference layers 416, and the first conductor 4111 has a third reference layer 416 spaced apart from the first conductor 4111 on both sides.

[0147] Along the first direction a, the fourth reference layer 417 and the second conductor 4112 are alternately and spaced apart. Thus, there is a fourth reference layer 417 between two second conductors 4112, which can separate two adjacent second conductors 4112 arranged along the first direction a; or, there is a second conductor 4112 between two fourth reference layers 417.

[0148] The first conductor 4111 is configured to correspond to the fourth reference layer 417, and the second conductor 4112 is configured to correspond to the third reference layer 416.

[0149] In other words, in the first structure 41, as shown in Figure 6, the first conductor 4111 and the second conductor 4112 can also be arranged in a staggered manner. Arranging the conductors 411 in a staggered manner effectively reduces electromagnetic interference (EMI) and crosstalk between adjacent conductors 411. The staggered arrangement also helps reduce signal reflection and attenuation during transmission, thereby improving signal integrity and stability. This is particularly important for high-speed signal transmission, ensuring that the signal maintains high quality upon arrival at the receiving end.

[0150] When the first structure 41 adopts a stripline structure, the first structure 41 can be used to transmit single-ended signals or differential signals, and this application does not limit it.

[0151] For example, when the first structure 41 is used to transmit differential signals, Figure 7 is a third structural schematic diagram of the first structure 41 provided in the embodiment of this application, Figure 8 is a top view of Figure 7, and Figure 12 is a fourth structural schematic diagram of the first structure 41 provided in the embodiment of this application. In one possible implementation, please refer to Figures 7 and 8, or Figure 12, the wire 411 may include a coupled first wire 4111 and a second wire 4112, the first wire 4111 and the second wire 4112 are parallel and spaced apart; the first wire 4111 and the second wire 4112 are used to transmit differential signals.

[0152] In this system, signals can be transmitted on both the first wire 4111 and the second wire 4112. The signals transmitted on the first wire 4111 and the second wire 4112 have the same amplitude but opposite phase. The signal receiver compares the difference between these two voltages to determine the logic state transmitted by the transmitter. A first wire 4111 and a second wire 4112 can form a differential pair for transmitting differential signals.

[0153] The first conductor 4111 and the second conductor 4112 can be of the same length. This ensures that the two differential signals always maintain opposite polarities, reducing common-mode components, thereby reducing interference and ensuring signal quality.

[0154] Furthermore, the widths of the first conductor 4111 and the second conductor 4112 can also be kept consistent, and the spacing between the first conductor 4111 and the second conductor 4112 can also remain unchanged. This will help reduce signal reflection and attenuation during transmission and improve signal integrity and stability.

[0155] The conductor 411 of the first structure 41 of this application includes a coupled first conductor 4111 and a second conductor 4112. In this way, the first conductor 4111 and the second conductor 4112 can be used as a differential pair to transmit differential signals. Since the two conductors 411 of the differential pair are tightly coupled, the electromagnetic fields formed can cancel each other out, thereby reducing radiation to the outside world and sensitivity to external interference. This provides better suppression of electromagnetic interference and radio frequency interference, and helps to maintain signal integrity, especially when the signal is transmitted at high speed.

[0156] In addition, differential signals can support larger voltage swings because the signal swings relative to a common-mode level (usually ground). This means that differential signals can transmit higher data rates and larger signal amplitudes, making them suitable for communication interfaces that require high bandwidth and high data rates.

[0157] When the first wire 4111 and the second wire 4112 are used to transmit differential signals, the first wire 4111 and the second wire 4112 can be in the form of narrow-side coupling or wide-side coupling, and this application does not limit them.

[0158] For example, referring to Figures 7 and 8, in one possible implementation, the first conductor 4111 and the second conductor 4112 are arranged along a first direction a. The size of the first conductor 4111 in the first direction a is larger than the size of the first conductor 4111 in the second direction b. The size of the second conductor 4112 in the first direction a is larger than the size of the second conductor 4112 in the second direction b. The first direction a is parallel to the first reference layer 413, and the second direction b is parallel to the arrangement direction of the first reference layer 413 and the second reference layer 414.

[0159] As shown in Figure 8, the first direction a is the horizontal direction of the orientation shown in Figure 8, and the second direction b is the vertical direction of the orientation shown in Figure 8. It should be understood that the above-mentioned horizontal and vertical directions are only for ease of understanding and are used as an example to illustrate the orientation shown in Figure 8, and are not intended to limit this application.

[0160] Both the first conductor 4111 and the second conductor 4112 have wide sides and narrow sides. The size of the first conductor 4111 in the first direction a is greater than the size of the first conductor 4111 in the second direction b. The size of the second conductor 4112 in the first direction a is greater than the size of the second conductor 4112 in the second direction b. This indicates that the first conductor 4111 and the second conductor 4112 adopt a narrow-side coupling form.

[0161] The differential pairs adopt a narrow-side coupling form, with a smaller spacing between the differential pairs and tighter coupling. The signal is less susceptible to external interference, which helps to reduce crosstalk between adjacent differential pairs.

[0162] Figure 9 is a second schematic diagram of the circuit structure 100 provided in the embodiment of this application. Figure 10 is a schematic diagram of the circuit structure 100 of Figure 9 from a first perspective. Figure 11 is a schematic diagram of the circuit structure 100 of Figure 9 from a second perspective. When the differential pair adopts narrow-side coupling, and the first structure 41 is embedded in the carrier plate 10, the circuit structure 100 can be referred to as shown in Figures 9, 10 and 11.

[0163] In addition to using narrow-side coupling, as shown in Figure 12, in one possible implementation, the first conductor 4111 and the second conductor 4112 are arranged along the second direction b. The size of the first conductor 4111 in the first direction a is larger than the size of the first conductor 4111 in the second direction b, and the size of the second conductor 4112 in the first direction a is larger than the size of the second conductor 4112 in the second direction b. The first direction a is parallel to the first reference layer 413, and the second direction b is parallel to the arrangement direction of the first reference layer 413 and the second reference layer 414.

[0164] That is, the first conductor 4111 and the second conductor 4112 can also be arranged along the second direction b. Since the size of the first conductor 4111 in the first direction a is larger than its size in the second direction b, and the size of the second conductor 4112 in the first direction a is larger than its size in the second direction b, the first conductor 4111 and the second conductor 4112 are respectively wide sides in the first direction a, and respectively narrow sides in the second direction b. The first conductor 4111 and the second conductor 4112 adopt wide-side coupling.

[0165] The use of wide-side coupling, with a larger spacing between differential pairs, helps reduce signal loss during transmission. In addition, since the larger spacing reduces the impact of manufacturing tolerances on impedance, wide-side coupling also makes it easier to control the impedance of differential pairs.

[0166] The choice between narrow-side coupling and wide-side coupling depends on specific design requirements, including signal speed, impedance requirements, wiring density, electromagnetic compatibility, and manufacturing costs. This application does not impose any special restrictions on the specific coupling form of differential pairs.

[0167] For example, Figure 13 is a fifth structural schematic diagram of the first structure 41 provided in the embodiment of this application. When the first structure 41 adopts a microwire structure, in one possible implementation, please refer to Figure 13, the first structure 41 may include a dielectric layer 412 and a wire 411, and may also include a first reference layer 413; the first reference layer 413 and the wire 411 are provided with a dielectric layer 412.

[0168] In other words, the first structure 41 of this application can adopt not only a stripline structure but also a microstrip line structure. Microstrip line structures are small in size and light in weight, making them suitable for applications with high requirements for size and weight; in addition, microstrip line structures are simple in structure, highly reliable, and suitable for environments with long-term stable operation.

[0169] When the first structure 41 adopts a microstrip line structure, in one possible way, Figure 14 is a schematic diagram of the structure of the first structure 41 provided in the embodiment of this application. As shown in Figure 14, the side of the conductor 411 away from the first reference layer 413 may also have a dielectric layer 412.

[0170] In other words, the side of the conductor 411 facing away from the first reference layer 413 may also have a dielectric layer 412, that is, the dielectric layer 412 is located on opposite sides of the conductor 411, and the conductor 411 is surrounded by the dielectric layer 412. Alternatively, in other embodiments, as shown in FIG13, the dielectric layer 412 may only be located on one side of the conductor 411, and the other side of the conductor 411 is air.

[0171] When there are dielectric layers 412 on both sides of the conductor 411, the electromagnetic field distribution around the conductor 411 becomes more symmetrical. This symmetry helps reduce electromagnetic wave radiation and leakage, improving the electromagnetic compatibility performance of the transmission line. Furthermore, the double-sided dielectric layer 412 structure provides better support and protection for the conductor 411, enhancing its mechanical stability and helping to prevent deformation or damage under external forces, thus improving circuit reliability. Additionally, microstrip lines with a double-sided dielectric layer 412 structure are easier to integrate and connect with other circuit components, simplifying manufacturing and processing, and reducing production costs and complexity.

[0172] When the first structure 41 adopts a microstrip line structure, in one possible implementation, FIG15 is a structural schematic diagram of the first structure 41 provided in the embodiment of this application. Referring to FIG15, the wire 411 may include a coupled first wire 4111 and second wire 4112, which are used to transmit differential signals.

[0173] In other words, when the first structure 41 adopts a microstrip line structure, the first structure 41 can also adopt a differential structure form.

[0174] For example, the first conductor 4111 and the second conductor 4112 are arranged at intervals along the first direction a. The size of the first conductor 4111 in the first direction a is larger than the size of the first conductor 4111 in the second direction b. The size of the second conductor 4112 in the first direction a is larger than the size of the second conductor 4112 in the second direction b. The first direction a is parallel to the first reference layer 413, and the second direction b is parallel to the arrangement direction of the first reference layer 413 and the dielectric layer 412.

[0175] That is, when the first structure 41 adopts a microstrip line structure, the first structure 41 can adopt a narrow-side coupling form. The spacing between the differential pairs of the narrow-side coupling is smaller, the coupling is tighter, the signal is not easily affected by external interference, and it helps to reduce crosstalk between adjacent differential pairs.

[0176] Figure 16 is one of the structural schematic diagrams of the interconnect structure 40 provided in the embodiment of this application, Figure 17 is a top view of the interconnect structure 40 in Figure 16, and Figure 18 is another structural schematic diagram of the interconnect structure 40 provided in the embodiment of this application. Referring to Figures 16 to 18, in one possible implementation, the first structure 41 may include multiple first structures 41, and the multiple first structures 41 may be arranged in an array.

[0177] That is, the interconnection structure 40 of this application may include only one first structure 41, or it may include multiple first structures 41. Here, "multiple" in this application refers to two or more. Multiple first structures 41 may be two first structures 41, three first structures 41, five first structures 41, or more first structures 41.

[0178] Multiple first structures 41 can be arranged in an array, as shown in Figures 16 and 17.

[0179] Any one of the plurality of first structures 41 can be a microstrip line structure or a stripline structure; any one of the plurality of first structures 41 can be used for single-ended signal transmission or differential signal transmission, and this application does not impose any restrictions on this.

[0180] The interconnect structure 40 employs multiple first structures 41, enabling it to process multiple signals in parallel, thereby improving signal processing efficiency and throughput. This is advantageous for applications requiring simultaneous processing of large amounts of data (such as high-speed data transmission and image processing). Arranging multiple first structures 41 in an array allows for higher circuit density and integration within a limited space, helping to reduce the size and weight of the circuit structure and improve its portability and reliability.

[0181] Furthermore, for example, when multiple first structures 41 are arranged in an array, the reference layers of two adjacent first structures 41 can be shared. For instance, the reference layers of two first structures 41 stacked along the second direction b can be shared (i.e., the second reference layer 414 of one first structure 41 can be shared with the first reference layer 413 of the other first structure 41).

[0182] In one possible implementation, there is a dielectric layer 412 and a plurality of power layers 42 between two adjacent first structures 41, the plurality of power layers 42 being located within the dielectric layer 412 between the two adjacent first structures 41; the plurality of power layers 42 are arranged at intervals.

[0183] This application, by setting up multiple power layers 42, enables more flexible and efficient power distribution. Different power layers 42 can be assigned to different power supply voltages, thereby meeting the needs of multiple power supplies in complex systems. Assigning multiple power layers 42 to multiple power supply voltages also helps to reduce the length and impedance of power supply paths, improving the efficiency of power distribution.

[0184] The specific number of power layers 42 is not limited in this application and may include one, two, three, or more. The specific number of power layers 42 can be determined according to actual power requirements.

[0185] Furthermore, in one possible implementation, multiple power layers 42 can be arranged at intervals along a second direction b, which is parallel to the arrangement direction of the first reference layer 413 and the second reference layer 414.

[0186] Alternatively, in another possible implementation, multiple power layers 42 can be arranged at intervals along a first direction a, which is parallel to the first reference layer 413. This allows for more uniform power distribution, avoiding voltage drops and power noise problems caused by excessively long power paths or uneven distribution. It helps ensure that all parts of the circuit receive a stable and consistent power supply voltage, improving circuit performance and reliability. Furthermore, the co-location of multiple power layers 42 on the same layer facilitates power management. During design, different power regions can be divided on the same layer according to actual needs, providing independent power supplies for different circuit modules or functional units, thus enabling more refined power management and control.

[0187] In one possible implementation, the carrier plate 10 may include multiple receiving holes 11, and the interconnect structure 40 may also include multiple interconnect structures 40; the multiple interconnect structures 40 are disposed one-to-one in the multiple receiving holes 11.

[0188] In other words, the receiving hole 11 on the carrier board 10 is not limited to one; multiple receiving holes 11 can be provided according to signal transmission requirements. The specific number of receiving holes 11 is not limited in this application and can be determined according to actual needs.

[0189] The plurality of receiving holes 11 can be arranged at intervals along a direction parallel to the surface of the carrier plate 10, that is, the plurality of receiving holes 11 can be arranged at intervals along the first direction a.

[0190] Each accommodating hole 11 can be equipped with an interconnect structure 40, allowing the carrier board 10 to support multiple interconnect structures 40. These multiple interconnect structures 40 can transmit signals in parallel, increasing signal channels and thus improving signal transmission efficiency and throughput, which helps meet the needs of high-speed data transmission and complex signal processing. Furthermore, arranging multiple accommodating holes 11 on the carrier board 10 and providing an interconnect structure 40 within each accommodating hole 11 enables more complex circuit layouts and higher wiring density, facilitating the integration of more functions within a limited space, thereby meeting the miniaturization and high-performance requirements of modern electronic products.

[0191] In this embodiment, the circuit structure 100 can be a packaging substrate 310, a circuit board 200, or other physical boards used for signal transmission. This application does not impose any restrictions.

[0192] For example, in one possible implementation, as shown in Figure 3, the circuit structure 100 can be a packaging substrate 310, and the carrier board 10 can be a core board layer 311.

[0193] That is, receiving holes 11 can be opened on the core board layer 311, and interconnection structure 40 can be embedded in the core board layer 311 and fixed inside the core board layer 311.

[0194] The circuit structure 100 may also include a second circuit layer 30, which is located on the side of the core board layer 311 opposite to the first circuit layer 20.

[0195] That is, the circuit structure 100 may include a second circuit layer 30 in addition to the first circuit layer 20. The second circuit layer 30 is located on the side of the core board layer 311 away from the first circuit layer 20.

[0196] The first line layer 20 can be one or more layers, and the second line layer 30 can also be one or more layers; this application does not impose any restrictions on this.

[0197] When the circuit structure 100 includes a first circuit layer 20 and a second circuit layer 30, one end of the conductor 411 can be connected to the first circuit layer 20, and the other end of the conductor 411 can be electrically connected to electronic devices through the second circuit layer 30.

[0198] The end of the first circuit layer 20 away from the conductor 411 can also be connected to other electronic devices, so that signal interconnection between different electronic devices can be achieved through the packaging substrate 310.

[0199] Figure 19 is a schematic diagram of the package substrate 310 when one part uses plated vias and the other part uses the interconnect structure 40 of this application. Referring to Figure 19, the core layer 311 of the package substrate 310 has a thickness of 1200 μm. The solder ball size is 300 μm and the ball pitch is 0.5 mm. The circuit board 200 uses High Density Interconnect (HDI) technology, and the high-speed vias can achieve a stub-free design.

[0200] In Figure 19, part of the core layer 311 of the packaging substrate 310 adopts a plated hole scheme, and part adopts the interconnect structure 40 scheme of this application. As a comparative group of this application, the plated hole scheme has a drilling diameter of 150 μm and a hole pad of 250 μm for the plated holes in the core layer 311.

[0201] Figure 20 compares the insertion loss obtained when the package substrate 310 uses plated via interconnects and when it uses the interconnect structure 40 of this application. Referring to Figure 20, the solid line represents the insertion loss curve obtained using the solution of this application, and the dashed line represents the insertion loss curve obtained using the conventional solution. It can be seen that the conventional solution has a cavity resonance point (i.e., point m2) in the core layer 311 near 56 GHz. The solution provided by this application can completely eliminate the cavity resonance point in the core layer 311 near 56 GHz. Furthermore, the bandwidth of the conventional solution is 106 GHz (refer to point m4 in Figure 20), while the bandwidth of the solution provided by this application can be increased from 106 GHz to 135 GHz (refer to point m3 in Figure 20). In addition, the solution provided by this application has better insertion loss ripple within the bandwidth compared to the conventional solution.

[0202] In future 448Gbps applications, there are potential modulation methods such as four-level pulse amplitude modulation (PAM4) and six-level pulse amplitude modulation (PAM6). Based on a passive bandwidth requirement of 1.2 times the Nyquist frequency, these would require passive channel bandwidths of 134GHz and 108GHz respectively. Therefore, the solution proposed in this application can effectively achieve future 448Gbps electrical interconnect transmission.

[0203] Figure 21 is a comparison of return loss obtained when the package substrate 310 uses plated via interconnects and when it uses the interconnect structure 40 of this application. Referring to Figure 21, the solid line in Figure 21 represents the return loss curve obtained using the solution of this application, and the dashed line represents the return loss curve obtained using the conventional solution. It can be seen that in the frequency range of 60GHz to 135GHz, the return loss of the plated via solution is between -19.10dB and -6.55dB, while the return loss of the solution using this application is between -23.96dB and -12.18dB. In the frequency range of 60GHz to 135GHz, the conventional plated via solution of this application optimizes the return loss by 5dB to 10dB.

[0204] For example, in one possible implementation, the circuit structure 100 can also be a circuit board 200.

[0205] At this point, the receiving hole 11 is formed on the circuit board 200. The receiving hole 11 can penetrate all layers of the circuit board 200, or it can penetrate some layers of the circuit board 200.

[0206] When the circuit structure 100 is a circuit board 200, different electronic devices on the circuit board can be interconnected through the interconnection structure 40 within the circuit board 200.

[0207] Furthermore, regardless of whether the circuit structure 100 is a circuit board 200 or a packaging substrate 310, multiple receiving holes 11 can be provided to improve signal transmission efficiency.

[0208] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit structure, characterized in that, The circuit structure includes: A carrier plate having receiving holes; The first circuit layer is located on one surface of the carrier board; An interconnection structure located within the accommodating hole; A connection structure, wherein the interconnection structure is fixedly connected to the carrier plate via the connection structure; The interconnect structure includes a wire, one end of which is connected to the first circuit layer, and the other end of which is used for electrical connection to electronic devices.

2. The circuit structure according to claim 1, characterized in that, The interconnection structure includes a first structure; The first structure includes a dielectric layer and the wire, the wire being connected to the dielectric layer.

3. The circuit structure according to claim 2, characterized in that, The first structure further includes a first reference layer and a second reference layer; the dielectric layer is located between the first reference layer and the second reference layer, and the wire is located within the dielectric layer; The dielectric layer has a ground hole, one end of which is connected to the first reference layer and the other end of which is connected to the second reference layer.

4. The circuit structure according to claim 3, characterized in that, The first structure further includes a third reference layer, which is located within the dielectric layer and between the first reference layer and the second reference layer; The borehole is connected to the third reference layer.

5. The circuit structure according to claim 3, characterized in that, The first structure further includes multiple third reference layers and multiple fourth reference layers, and the wires include multiple first wires and multiple second wires; The plurality of third reference layers and the plurality of fourth reference layers are all located within the dielectric layer, and the plurality of third reference layers are located between the first reference layer and the plurality of fourth reference layers; Along a first direction, the third reference layer and the first conductor are alternately and spaced apart, and the first direction is parallel to the first reference layer; Along the first direction, the fourth reference layer and the second conductor are alternately and spaced apart; The first conductor is configured corresponding to the fourth reference layer, and the second conductor is configured corresponding to the third reference layer.

6. The circuit structure according to claim 3 or 4, characterized in that, The conductor includes a coupled first conductor and a second conductor, which are parallel and spaced apart. The first wire and the second wire are used to transmit differential signals.

7. The circuit structure according to claim 6, characterized in that, The first wire and the second wire are arranged along a first direction, the size of the first wire in the first direction is larger than the size of the first wire in the second direction, and the size of the second wire in the first direction is larger than the size of the second wire in the second direction; The first direction is parallel to the first reference layer, and the second direction is parallel to the arrangement direction of the first reference layer and the second reference layer.

8. The circuit structure according to claim 6, characterized in that, The first wire and the second wire are arranged along a second direction, wherein the size of the first wire in the first direction is greater than the size of the first wire in the second direction, and the size of the second wire in the first direction is greater than the size of the second wire in the second direction; The first direction is parallel to the first reference layer, and the second direction is parallel to the arrangement direction of the first reference layer and the second reference layer.

9. The circuit structure according to claim 2, characterized in that, The first structure further includes a first reference layer; the dielectric layer is located between the first reference layer and the conductor.

10. The circuit structure according to claim 9, characterized in that, The conductor has the dielectric layer on the side opposite to the first reference layer.

11. The circuit structure according to claim 9 or 10, characterized in that, The conductor includes a coupled first conductor and a second conductor, which are used to transmit differential signals; The first wire and the second wire are arranged at intervals along a first direction, the size of the first wire in the first direction is larger than the size of the first wire in the second direction, and the size of the second wire in the first direction is larger than the size of the second wire in the second direction; The first direction is parallel to the first reference layer, and the second direction is parallel to the arrangement direction of the first reference layer and the dielectric layer.

12. The circuit structure according to any one of claims 3-11, characterized in that, The first structure includes multiple structures, which are arranged in an array.

13. The circuit structure according to claim 12, characterized in that, Between two adjacent first structures, there is a dielectric layer and a plurality of power layers, wherein the plurality of power layers are located within the dielectric layer between two adjacent first structures; Multiple power supply layers are arranged at intervals.

14. The circuit structure according to claim 13, characterized in that, The plurality of power layers are arranged at intervals along a first direction, which is parallel to the first reference layer.

15. The circuit structure according to any one of claims 1-14, characterized in that, The connection structure is adhesive.

16. The circuit structure according to any one of claims 1-15, characterized in that, The accommodating holes include multiple types, and the interconnection structure includes multiple types; The interconnecting structures are disposed one-to-one within the accommodating holes.

17. The circuit structure according to any one of claims 1-16, characterized in that, The circuit structure is a packaging substrate, and the carrier board is a core board layer; The circuit structure further includes a second circuit layer, which is located on the side of the core board layer opposite to the first circuit layer. One end of the conductor is connected to the first circuit layer, and the other end of the conductor is electrically connected to the electronic device through the second circuit layer.

18. The circuit structure according to any one of claims 1-16, characterized in that, The circuit structure is a circuit board.

19. An electronic device packaging structure, characterized in that, include: Electronic devices; The circuit structure as described in any one of claims 1-18, wherein the circuit structure is a packaging substrate, and the electronic device is connected to the packaging substrate.

20. An electronic device, characterized in that, include: Circuit board; The electronic device packaging structure as described in claim 19 is connected to the circuit board.

21. The electronic device according to claim 20, characterized in that, The circuit board is the circuit structure described in any one of claims 1-18.

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