Semiconductor device and manufacturing method therefor
By etching highly differentiated semiconductor layers on an SOI substrate and depositing silicon nitride waveguides using LPCVD, the process contradiction between photodetectors and silicon nitride waveguides was resolved, achieving a high-bandwidth, low-loss integration effect.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- WUHAN XINXIN SEMICON MFG CO LTD
- Filing Date
- 2025-12-09
- Publication Date
- 2026-06-25
AI Technical Summary
In the existing technology, there are process contradictions in the integration of photodetectors and silicon nitride waveguides. High-temperature processes can damage the performance of the absorption layer, while additional etching or bonding steps lead to increased structural complexity and cost.
Using an SOI substrate, the semiconductor layer in the detector region is etched to make the height higher than that in the waveguide region, forming a first waveguide and an insulating dielectric layer. Then, a semiconductor absorption layer is formed in the detector region. Silicon nitride is deposited using LPCVD and annealed to avoid high-temperature damage.
The integration of photodetectors and waveguides was achieved, optimizing structural redundancy space, increasing detector bandwidth, and reducing waveguide transmission loss.
Smart Images
Figure CN2025141072_25062026_PF_FP_ABST
Abstract
Description
Semiconductor devices and manufacturing methods thereof Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] In silicon photonics chips, waveguides need to have low transmission loss characteristics (commonly using silicon nitride materials), while photodetectors require semiconductor materials with high absorption efficiency (such as Ge, InGaAs, etc.). However, there is an inherent contradiction in the process requirements of these two types of devices: silicon nitride waveguides require high-temperature processes (such as LPCVD deposition and annealing at >1000℃) to reduce optical loss; semiconductor absorption layers (such as Ge) cannot withstand high temperatures, and subsequent processes must be controlled at low temperatures (usually <500℃), otherwise it will lead to lattice defects or interface failure. In traditional solutions, if the detector is fabricated first and then the waveguide is made, the high-temperature process will damage the performance of the absorption layer; if the waveguide is fabricated first and then the detector is integrated, the detector requires additional etching or bonding steps, leading to increased structural complexity and cost. How to integrate photodetectors with silicon nitride waveguides is an urgent problem to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can realize the integration of photodetectors and waveguides.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0005] An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprising a detector region and a waveguide region;
[0006] The semiconductor layer is etched so that the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region;
[0007] A first waveguide is formed in the semiconductor layer of the waveguide region;
[0008] An insulating dielectric layer and a second waveguide are formed, the insulating dielectric layer covering the semiconductor layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide;
[0009] A semiconductor absorption layer is formed in the insulating dielectric layer on the semiconductor layer of the detector region.
[0010] Optionally, the upper surface of the semiconductor absorption layer is higher than or equal to the upper surface of the second waveguide.
[0011] Optionally, the second waveguide is made of silicon nitride, which is deposited using LPCVD process and then annealed.
[0012] Optionally, before forming the semiconductor absorber layer in the insulating dielectric layer on the semiconductor layer of the detector region, the method of manufacturing the semiconductor device further includes:
[0013] The insulating dielectric layer is etched to expose a portion of the semiconductor layer in the detector region;
[0014] A first doped region and a second doped region are formed in the semiconductor layer of the exposed detector region, the first doped region and the second doped region being spaced apart and having opposite doping types.
[0015] Optionally, the step of forming the semiconductor absorber layer in the insulating dielectric layer on the semiconductor layer includes:
[0016] A semiconductor absorption layer is formed on the exposed semiconductor layer of the detector region, and the semiconductor absorption layer extends onto the insulating dielectric layer;
[0017] The semiconductor absorber layer above the upper surface of the insulating dielectric layer is removed using a chemical mechanical polishing process.
[0018] Optionally, the method for manufacturing the semiconductor device further includes:
[0019] A third doped region and a fourth doped region are formed in the semiconductor layer on both sides of the semiconductor absorption layer. The third doped region is connected to the first doped region, and the fourth doped region is connected to the second doped region. The third doped region and the first doped region have the same doping type, and the fourth doped region and the second doped region have the same doping type. The doping concentrations of the third doped region and the fourth doped region are greater than the doping concentrations of the first doped region and the second doped region, respectively.
[0020] Optionally, the method for manufacturing the semiconductor device further includes:
[0021] A conductive plug is formed, which is used to electrically lead out the first doped region and the second doped region or the third doped region and the fourth doped region.
[0022] Optionally, the SOI substrate further includes a modulator region and a coupler region, and the method for manufacturing the semiconductor device further includes, prior to forming the insulating dielectric layer and the second waveguide:
[0023] A modulator is formed in the semiconductor layer of the modulator region, and a coupler is formed in the semiconductor layer of the coupler region.
[0024] The present invention also provides a semiconductor device, comprising:
[0025] The SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer. The SOI substrate includes a detector region and a waveguide region, wherein the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region.
[0026] A first waveguide is formed in the semiconductor layer of the waveguide region;
[0027] A semiconductor absorption layer is formed on the semiconductor layer in the detector region;
[0028] An insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide.
[0029] Optionally, the upper surface of the semiconductor absorption layer is higher than or equal to the upper surface of the second waveguide.
[0030] Optionally, the upper surface of the semiconductor layer in the detector region is located between the upper and lower surfaces of the second waveguide.
[0031] Optionally, the semiconductor device further includes: a first doped region and a second doped region, formed at intervals in the semiconductor layer below the semiconductor absorption layer, wherein the first doped region and the second doped region have opposite doping types.
[0032] Optionally, the semiconductor device further includes:
[0033] The third doped region and the fourth doped region are respectively formed in the semiconductor layer on both sides of the semiconductor absorption layer. The third doped region is connected to the first doped region, and the fourth doped region is connected to the second doped region. The third doped region and the first doped region have the same doping type, and the fourth doped region and the second doped region have the same doping type. The doping concentration of the third doped region and the fourth doped region is greater than the doping concentration of the first doped region and the second doped region, respectively.
[0034] Optionally, the semiconductor device further includes:
[0035] A conductive plug is used to electrically lead out the first doped region and the second doped region, or the third doped region and the fourth doped region.
[0036] Optionally, the SOI substrate further includes a modulator region and a coupler region, and the semiconductor device further includes:
[0037] A modulator is formed in the semiconductor layer of the modulator region;
[0038] A coupler is formed in the semiconductor layer of the coupler region.
[0039] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0040] 1. A method for manufacturing a semiconductor device according to the present invention includes: providing an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer, the SOI substrate including a detector region and a waveguide region; etching the semiconductor layer such that the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region; forming a first waveguide in the semiconductor layer of the waveguide region; forming an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide; and forming a semiconductor absorption layer in the insulating dielectric layer on the semiconductor layer of the detector region. This enables the integration of a photodetector and a waveguide.
[0041] 2. The semiconductor device of the present invention includes: an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer, the SOI substrate including a detector region and a waveguide region, the semiconductor layer height of the detector region being higher than the semiconductor layer height of the waveguide region; a first waveguide formed in the semiconductor layer of the waveguide region; a semiconductor absorption layer formed on the semiconductor layer of the detector region; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide. This enables the integration of a photodetector and a waveguide. Attached Figure Description
[0042] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0043] Figures 2a to 2l are schematic diagrams of a device according to an embodiment of the manufacturing method of the semiconductor device shown in Figure 1.
[0044] The reference numerals in Figures 1 to 21 are explained as follows: 101-lower substrate; 102-buried insulating layer; 103-semiconductor layer; 11-first insulating dielectric layer; 111-first insulating layer; 112-second insulating layer; 12-second waveguide; 121-groove; 122-waveguide material layer; 13-semiconductor absorption layer; 131-opening; 141-first doped region; 142-second doped region; 151-third doped region; 152-fourth doped region; 16-second insulating dielectric layer; 17-conductive plug; 171-through hole; A1-detector region; A2-modulator region; A3-waveguide region; A4-coupler region. Detailed Implementation
[0045] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0046] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG1, as can be seen from FIG1, the method for manufacturing the semiconductor device includes:
[0047] Step S1: Provide an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprising a detector region and a waveguide region;
[0048] Step S2: Etch the semiconductor layer so that the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region;
[0049] Step S3: Form a first waveguide in the semiconductor layer of the waveguide region;
[0050] Step S4: Form an insulating dielectric layer and a second waveguide, wherein the insulating dielectric layer covers the semiconductor layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide;
[0051] Step S5: Form a semiconductor absorption layer in the insulating dielectric layer on the semiconductor layer of the detector region.
[0052] The manufacturing method of the semiconductor device provided in this embodiment will be described in detail below with reference to Figures 2a to 2l, which are longitudinal cross-sectional schematic diagrams.
[0053] According to step S1, referring to Figure 2a, an SOI (Semiconductor-On-Insulator) substrate is provided. The SOI substrate includes a lower substrate 101, an insulating buried layer 102 and a semiconductor layer 103 from bottom to top. The SOI substrate includes a detector region A1 and a waveguide region A3.
[0054] The detector region A1 is used to form a photodetector, and the waveguide region A3 is used to form a waveguide.
[0055] In one embodiment, the SOI substrate may further include a modulator region A2 and a coupler region A4, wherein the modulator region A2 is used to form a modulator and the coupler region A4 is used to form a coupler.
[0056] The photodetector and the modulator are active devices, while the first waveguide and the coupler are passive devices.
[0057] It should be noted that the SOI substrate may include not only modulators and couplers, but also other active and / or passive devices.
[0058] In one embodiment, the upper surfaces of the semiconductor layer 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are flush.
[0059] The semiconductor layer 103 can be made of semiconductor materials such as silicon.
[0060] Following step S2, referring to Figure 2b, the semiconductor layer 103 is etched so that the height of the semiconductor layer 103 in the detector region A1 is higher than the height of the semiconductor layer 103 in the waveguide region A3. This ensures that the height of the semiconductor absorption layer 13 subsequently formed on the semiconductor layer 103 in the detector region A1 does not need to be excessive, while still ensuring that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the subsequently formed second waveguide 12.
[0061] The height of the semiconductor layer 103 in the detector region A1 is higher than that in the waveguide region A3, which allows the subsequently formed semiconductor absorption layer 13 to be raised, optimizing the overall structure and providing greater redundancy space for subsequent device structure design.
[0062] In one embodiment, the height of the semiconductor layer 103 in the detector region A1 is also higher than the height of the semiconductor layer 103 in the modulator region A2 and the coupler region A4.
[0063] That is, by etching away a portion of the thickness of the semiconductor layer 103 surrounding the detector region A1, the upper surfaces of the semiconductor layer 103 of the waveguide region A3, the modulator region A2, and the coupler region A4 are lower than the upper surface of the semiconductor layer 103 of the detector region A1.
[0064] According to step S3, referring to Figure 2c, a first waveguide is formed in the semiconductor layer 103 of the waveguide region A3.
[0065] In one embodiment, prior to the subsequent formation of the first insulating dielectric layer 11 and the second waveguide 12, the method of manufacturing the semiconductor device further includes: forming a modulator in the semiconductor layer 103 of the modulator region A2, and forming a coupler in the semiconductor layer 103 of the coupler region A4.
[0066] In one embodiment, the semiconductor layer 103 surrounding the detector region A1 is patterned by etching, as shown in FIG2c, such that the semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are spaced apart, and the first waveguide, the modulator, and the coupler are formed. In one embodiment, the surfaces of the highest points of the semiconductor layers 103 of the modulator region A2, the waveguide region A3, and the coupler region A4 are flush after the patterning process.
[0067] In one embodiment, after patterning, the semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are interconnected and / or coupled at other locations, so that optical signals can be transmitted between the semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0068] The first waveguide is not limited to any type, and can be at least one of the following: ridge waveguide (as shown in Figure 2c, the longitudinal section of the ridge waveguide is convex), strip waveguide (as shown in Figure 2c, the longitudinal section of the strip waveguide is rectangular), slot waveguide, and grating waveguide.
[0069] The type of modulator is not limited. For example, the longitudinal section of the modulator can be a shape with two grooves (as shown in Figure 2c) or a convex shape.
[0070] The type of coupler is not limited; for example, the coupler can be the grating coupler shown in Figure 2c.
[0071] According to step S4, an insulating dielectric layer (defined as the first insulating dielectric layer 11 to distinguish it from other insulating dielectric layers) and a second waveguide 12 are formed. The first insulating dielectric layer 11 covers the semiconductor layer 103, and the second waveguide 12 is formed in the first insulating dielectric layer 11 above the first waveguide.
[0072] In one embodiment, the first insulating dielectric layer 11 further covers the gap between the patterned semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0073] The first insulating dielectric layer 11 covers the semiconductor layer 103, which enables the first insulating dielectric layer 11 and the insulating buried layer 102 to wrap the semiconductor layer 103, thereby preventing optical signals from leaking out of the semiconductor layer 103.
[0074] In one embodiment, the step of forming the first insulating dielectric layer 11 and the second waveguide 12 may include: as shown in FIG2d, forming the first insulating layer 111 to cover the patterned semiconductor layer 103 and the gap between the semiconductor layer 103 of the detector region A1, the modulator region A2, the waveguide region A3 and the coupler region A4; and then etching at least the first insulating layer 111 above the waveguide region A3 to form a groove 121 in the first insulating layer 111 at least above the waveguide region A3. Then, as shown in FIG2e, a waveguide material layer 122 is formed on the first insulating layer 111, and the waveguide material layer 122 fills the groove 121; then, as shown in FIG2f, the waveguide material layer 122 is etched to form a second waveguide 12 located above the first waveguide; then, as shown in FIG2g, a second insulating layer 112 is formed on the first insulating layer 111, and the second insulating layer 112 covers the second waveguide 12. The first insulating layer 111 and the second insulating layer 112 constitute a first insulating dielectric layer 11. In other embodiments, other methods can be used to form the first insulating dielectric layer 11 and the second waveguide 12.
[0075] The upper surface of the semiconductor layer 103 in the detector region A1 is located between the upper and lower surfaces of the second waveguide 12 to prevent the height of the semiconductor layer 103 in the detector region A1 from being too low, which would require the height of the subsequently formed semiconductor absorption layer 13 to be very high so that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12, thereby preventing the semiconductor absorption layer 13 from being too high and causing a reduction in the bandwidth of the detector.
[0076] In one embodiment, the second waveguide 12 is formed inside the first insulating dielectric layer 11 above the first waveguide, that is, the first insulating dielectric layer 11 does not expose the second waveguide 12, so that the first insulating dielectric layer 11 can protect the second waveguide 12 in subsequent processes and prevent the second waveguide 12 from being damaged.
[0077] The first insulating dielectric layer 11 can be made of insulating materials such as silicon oxide.
[0078] The second waveguide 12 is formed above the first waveguide, and optical signals can be transmitted between the second waveguide 12 and the first waveguide.
[0079] The transmission loss of the second waveguide 12 for optical signals is less than that of the first waveguide. The second waveguide 12 is preferably made of silicon nitride.
[0080] When the second waveguide 12 is made of silicon nitride, it is preferable to use LPCVD (Low Pressure Chemical Vapor Deposition) process to deposit the silicon nitride and then anneal the silicon nitride.
[0081] In one embodiment, the process temperature for depositing the silicon nitride can be greater than 600°C, and the process temperature for annealing can be greater than 1000°C.
[0082] Compared to the deposition of silicon nitride using PECVD (Plasma Enhanced Chemical Vapor Deposition), the silicon nitride deposition process using LPCVD in this embodiment has a higher process temperature, and there is also an annealing process with a higher process temperature after deposition, which results in better quality silicon nitride (e.g., higher density), fewer defects in silicon nitride, and thus less loss when optical signals are transmitted in silicon nitride.
[0083] Since the second waveguide 12, made of silicon nitride, is formed using LPCVD and annealing processes before the subsequent formation of the semiconductor absorption layer 13, it is possible to avoid damage to the semiconductor absorption layer 13 due to excessively high process temperatures.
[0084] The second waveguide 12 is spaced apart from the first waveguide by a certain distance; in one embodiment, the distance between the second waveguide 12 and the first waveguide can be...
[0085] In one embodiment, the height of the second waveguide 12 can be
[0086] According to step S5, referring to FIG2j, a semiconductor absorption layer 13 is formed in the first insulating dielectric layer 11 on the semiconductor layer 103 of the detector region A1.
[0087] In one embodiment, the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12.
[0088] Preferably, the semiconductor absorber layer 13 can be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 13 can be made of Si, GeAs, or InP, etc.
[0089] In one embodiment, the semiconductor absorption layer 13 is undoped, that is, the semiconductor absorption layer 13 is in an intrinsic state.
[0090] The height of the semiconductor absorption layer 13 needs to be controlled within a certain range to avoid excessively high heights, which would result in an excessively long path for the optical signal during transmission within the layer, thereby preventing excessively long transmission times and frequency reduction, and ultimately reducing the detector's bandwidth. In one embodiment, the height of the semiconductor absorption layer 13 can be located at...
[0091] In one embodiment, as shown in FIG2h, before forming the semiconductor absorption layer 13 in the first insulating dielectric layer 11 on the semiconductor layer 103 of the detector region A1, the method of manufacturing the semiconductor device further includes:
[0092] The first insulating dielectric layer 11 is etched to form an opening 131 that exposes a portion of the semiconductor layer 103 of the detector region A1; wherein the opening 131 exposes the semiconductor layer 103 in the middle region of the detector region A1.
[0093] A first doped region 141 and a second doped region 142 are formed in the semiconductor layer 103 of the exposed detector region A1. The first doped region 141 and the second doped region 142 are spaced apart and have opposite doping types.
[0094] In one embodiment, the step of forming the semiconductor absorber layer 13 in the first insulating dielectric layer 11 on the semiconductor layer 103 includes:
[0095] As shown in FIG2i, a semiconductor absorption layer 13 is formed on the semiconductor layer 103 of the exposed detector region A1, and the semiconductor absorption layer 13 extends to the first insulating dielectric layer 11; that is, the semiconductor absorption layer 13 fills the opening 131.
[0096] As shown in Figure 2j, the semiconductor absorber layer 13 above the upper surface of the first insulating dielectric layer 11 is removed using a chemical mechanical polishing process.
[0097] If the upper surface of the semiconductor absorption layer 13 is lower than the upper surface of the second waveguide 12, the second waveguide 12 will also be ground when the semiconductor absorption layer 13, which is higher than the upper surface of the first insulating dielectric layer 11, is removed by chemical mechanical polishing, resulting in damage to the second waveguide 12. Therefore, by defining that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12, damage to the second waveguide 12 can be avoided when grinding the semiconductor absorption layer 13.
[0098] In one embodiment, the method of manufacturing the semiconductor device further includes:
[0099] As shown in Figure 2j, a second insulating dielectric layer 16 is formed on the first insulating dielectric layer 11 and the semiconductor absorption layer 13;
[0100] As shown in Figure 2k, the second insulating dielectric layer 16 and the first insulating dielectric layer 11 are etched to form vias 171 that expose the semiconductor layer 103 on both sides of the semiconductor absorption layer 13.
[0101] An ion implantation process and an annealing process are performed to form a third doped region 151 and a fourth doped region 152 in the semiconductor layer 103 on both sides of the semiconductor absorber layer 13, respectively. The third doped region 151 is connected to the first doped region 141, and the fourth doped region 152 is connected to the second doped region 142. The doping type of the third doped region 151 is the same as that of the first doped region 141, and the doping type of the fourth doped region 152 is the same as that of the second doped region 142. The doping concentrations of the third doped region 151 and the fourth doped region 152 are greater than the doping concentrations of the first doped region 141 and the second doped region 142, respectively.
[0102] As shown in FIG21, conductive material is filled into the through hole 171 to form a conductive plug 17 in the second insulating dielectric layer 16 and the first insulating dielectric layer 11 on the third doped region 151 and the fourth doped region 152.
[0103] The first doped region 141 and the second doped region 142 can be electrically connected through the third doped region 151 and the fourth doped region 152, respectively.
[0104] In other embodiments, the first doped region 141 and the second doped region 142 may be located in the semiconductor layer 103 of the detector region A1 on both sides of the semiconductor absorption layer 13 and extend below the semiconductor absorption layer 13. The third doped region 151 and the fourth doped region 152 are respectively formed in the first doped region 141 and the second doped region 142 on both sides of the semiconductor absorption layer 13, so that the first doped region 141 and the second doped region 142 can be electrically connected through the third doped region 151 and the fourth doped region 152 respectively. In this embodiment, the step of forming the first doped region 141, the second doped region 142, the third doped region 151, and the fourth doped region 152 may include: forming an opening 131 that exposes the entire upper surface of the semiconductor layer 103 of the detector region A1; forming the first doped region 141 and the second doped region 142 spaced apart in the exposed semiconductor layer 103 of the detector region A1; then forming a third insulating dielectric layer (not shown) to fill the opening 131; then etching the third insulating dielectric layer to form another opening (not shown) that exposes a portion of the first doped region 141 and a portion of the second doped region 142 and the semiconductor layer 103 between them; Then, a semiconductor absorber layer 13 is formed to fill the opening; then, a second insulating dielectric layer 16 is formed on the first insulating dielectric layer 11, the semiconductor absorber layer 13, and the third insulating dielectric layer; then, the second insulating dielectric layer 16 and the third insulating dielectric layer are etched to form vias 171 that expose the first doped region 141 and the second doped region 142 on both sides of the semiconductor absorber layer 13, respectively; then, an ion implantation process is performed to form a third doped region 151 and a fourth doped region 152 in the first doped region 141 and the second doped region 142 on both sides of the semiconductor absorber layer 13, respectively; then, conductive material is filled into the vias 171 to form a conductive plug 17.
[0105] The conductive plug 17 is used to electrically lead out the first doped region 141 and the second doped region 142 or the third doped region 151 and the fourth doped region 152.
[0106] In one embodiment, prior to forming the conductive plug 17, a metal silicide layer (not shown) may be formed on the surfaces of the third doped region 151 and the fourth doped region 152 to reduce the contact resistance between the third doped region 151 and the fourth doped region 152 and the conductive plug 17, respectively.
[0107] When the first doped region 141 and the third doped region 151 are P-type doped and the second doped region 142 and the fourth doped region 152 are N-type doped, the first doped region 141, the semiconductor absorption layer 13, and the second doped region 142 form a horizontal PIN junction; when the first doped region 141 and the third doped region 151 are N-type doped and the second doped region 142 and the fourth doped region 152 are P-type doped, the first doped region 141, the semiconductor absorption layer 13, and the second doped region 142 form a horizontal NIP junction.
[0108] As can be seen from the above, by thinning the thickness of the semiconductor layer 103 surrounding the detector region A1, the height of the semiconductor layer 103 in the detector region A1 is made higher than the height of the semiconductor layer 103 in the waveguide region A3. Furthermore, the upper surface of the semiconductor absorption layer 13 on the semiconductor layer 103 in the detector region A1 after chemical mechanical polishing is not lower than the upper surface of the second waveguide 12. This allows the height of the semiconductor absorption layer 13 to be controlled within a certain range (e.g., its height is located at...). This not only improves the bandwidth of the photodetector, but also allows for the fabrication of a low-loss second waveguide 12 using a higher process temperature before forming the semiconductor absorption layer 13 (e.g., using LPCVD and annealing processes to form a second waveguide 12 made of silicon nitride), thereby enabling the high-bandwidth photodetector and the low-loss second waveguide 12 to be integrated into the same process.
[0109] In summary, this invention provides a method for manufacturing a semiconductor device, comprising: providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer, the SOI substrate comprising a detector region and a waveguide region; etching the semiconductor layer such that the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region; forming a first waveguide in the semiconductor layer of the waveguide region; forming an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide; and forming a semiconductor absorption layer in the insulating dielectric layer on the semiconductor layer of the detector region. The semiconductor device manufacturing method provided by this invention enables the integration of a photodetector and a waveguide.
[0110] An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer, the SOI substrate including a detector region and a waveguide region, the semiconductor layer height of the detector region being higher than the semiconductor layer height of the waveguide region; a first waveguide formed in the semiconductor layer of the waveguide region; a semiconductor absorption layer formed on the semiconductor layer of the detector region; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide.
[0111] The semiconductor device provided in this embodiment will now be described in detail with reference to FIG21.
[0112] The SOI (Semiconductor-On-Insulator) substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103. The SOI substrate includes a detector region A1 and a waveguide region A3. The height of the semiconductor layer 103 in the detector region A1 is higher than the height of the semiconductor layer 103 in the waveguide region A3. This allows the height of the semiconductor absorption layer 13 formed on the semiconductor layer 103 in the detector region A1 to be less than excessive, while ensuring that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12.
[0113] The height of the semiconductor layer 103 in the detector region A1 is higher than that in the waveguide region A3, which allows the subsequently formed semiconductor absorption layer 13 to be raised, optimizing the overall structure and providing greater redundancy space for subsequent device structure design.
[0114] The detector region A1 is used to form a photodetector, and the waveguide region A3 is used to form a waveguide.
[0115] The semiconductor layer 103 can be made of semiconductor materials such as silicon.
[0116] The first waveguide is formed in the semiconductor layer 103 of the waveguide region A3.
[0117] In one embodiment, the SOI substrate may further include a modulator region A2 and a coupler region A4, and the semiconductor device further includes: a modulator formed in the semiconductor layer 103 of the modulator region A2; and a coupler formed in the semiconductor layer 103 of the coupler region A4.
[0118] The photodetector and the modulator are active devices, while the first waveguide and the coupler are passive devices.
[0119] It should be noted that the SOI substrate may include not only modulators and couplers, but also other active and / or passive devices.
[0120] In one embodiment, the height of the semiconductor layer 103 in the detector region A1 is also higher than the height of the semiconductor layers 103 in the modulator region A2 and the coupler region A4. That is, the upper surfaces of the semiconductor layers 103 in the waveguide region A3, the modulator region A2, and the coupler region A4 are lower than the upper surface of the semiconductor layer 103 in the detector region A1.
[0121] In one embodiment, the first waveguide, the modulator, and the coupler are obtained by patterning the semiconductor layer 103 surrounding the detector region A1. The upper surface of the semiconductor layer 103 in the detector region A1 is higher than the highest surface of the semiconductor layers 103 in the modulator region A2, the waveguide region A3, and the coupler region A4. Furthermore, the semiconductor layers 103 in the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are spaced apart. In another embodiment, the semiconductor layers 103 in the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4 are interconnected and / or coupled at other locations, enabling optical signals to be transmitted among the semiconductor layers 103 in the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0122] The first waveguide is not limited to any type, and can be at least one of the following: ridge waveguide (as shown in Figure 2l, the longitudinal section of the ridge waveguide is convex), strip waveguide (as shown in Figure 2l, the longitudinal section of the strip waveguide is rectangular), slot waveguide, and grating waveguide.
[0123] The type of modulator is not limited. For example, the longitudinal section of the modulator can be a shape with two grooves (as shown in Figure 2l) or a convex shape.
[0124] The type of coupler is not limited; for example, the coupler can be the grating coupler shown in Figure 21, etc.
[0125] The semiconductor absorption layer 13 is formed on the semiconductor layer 103 of the detector region A1.
[0126] In one embodiment, the semiconductor absorber layer 13 may be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 13 may be made of Si, GeAs, or InP, etc.
[0127] In one embodiment, the semiconductor absorption layer 13 is undoped, that is, the semiconductor absorption layer 13 is in an intrinsic state.
[0128] The height of the semiconductor absorption layer 13 needs to be controlled within a certain range to avoid excessively high heights, which would result in an excessively long path for the optical signal during transmission within the layer, thereby preventing excessively long transmission times and frequency reduction, and ultimately reducing the detector's bandwidth. In one embodiment, the height of the semiconductor absorption layer 13 can be located at...
[0129] The insulating dielectric layer covers the semiconductor layer 103 and the semiconductor absorption layer 13, and the second waveguide 12 is formed in the insulating dielectric layer above the first waveguide.
[0130] In one embodiment, the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12.
[0131] The insulating dielectric layer also covers the gap between the semiconductor layer 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4.
[0132] The insulating dielectric layer covers the semiconductor layer 103, which enables the insulating dielectric layer and the insulating buried layer 102 to encapsulate the semiconductor layer 103, thereby preventing optical signals from leaking out of the semiconductor layer 103.
[0133] The insulating dielectric layer may include a multilayer structure. In the embodiment shown in FIG21, the insulating dielectric layer includes a first insulating dielectric layer 11 and a second insulating dielectric layer 16. The first insulating dielectric layer 11 includes a stacked first insulating layer 111 and a second insulating layer 112. The first insulating layer 111 covers the semiconductor layer 103 and the gaps between the semiconductor layers 103 of the detector region A1, the modulator region A2, the waveguide region A3, and the coupler region A4. At least a groove (i.e., groove 121 in FIG2d) is formed in the first insulating layer 111 above the waveguide region A3. The second waveguide 12 is formed in the groove 121 above the first waveguide. The second insulating layer 112 covers the second waveguide 12 and the first insulating layer 111. The semiconductor absorption layer 13 is formed in the first insulating dielectric layer 11 on the semiconductor layer 103 of the detector region A1. The second insulating dielectric layer 16 covers the first insulating dielectric layer 11 and the semiconductor absorption layer 13. It should be noted that the composition of the insulating dielectric layer is not limited to the embodiment shown in FIG21.
[0134] If the upper surface of the semiconductor absorption layer 13 is lower than the upper surface of the second waveguide 12, the second waveguide 12 will also be ground when the semiconductor absorption layer 13, which is higher than the upper surface of the first insulating dielectric layer 11, is removed by chemical mechanical polishing, resulting in damage to the second waveguide 12. Therefore, by defining that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12, damage to the second waveguide 12 can be avoided when grinding the semiconductor absorption layer 13.
[0135] The insulating dielectric layer can be made of insulating materials such as silicon oxide.
[0136] The upper surface of the semiconductor layer 103 in the detector region A1 is located between the upper and lower surfaces of the second waveguide 12 to prevent the height of the semiconductor layer 103 in the detector region A1 from being too low, which would require the height of the semiconductor absorption layer 13 to be very high so that the upper surface of the semiconductor absorption layer 13 is not lower than the upper surface of the second waveguide 12, thereby preventing the bandwidth of the detector from being reduced due to the excessive height of the semiconductor absorption layer 13.
[0137] The second waveguide 12 is formed above the first waveguide, and optical signals can be transmitted between the second waveguide 12 and the first waveguide.
[0138] The transmission loss of the second waveguide 12 for optical signals is less than that of the first waveguide. The second waveguide 12 is preferably made of silicon nitride.
[0139] When the second waveguide 12 is made of silicon nitride, it is preferable to use LPCVD (Low Pressure Chemical Vapor Deposition) process to deposit the silicon nitride and then anneal the silicon nitride.
[0140] In one embodiment, the process temperature for depositing the silicon nitride can be greater than 600°C, and the process temperature for annealing can be greater than 1000°C.
[0141] Compared to the deposition of silicon nitride using PECVD (Plasma Enhanced Chemical Vapor Deposition), the silicon nitride deposition process using LPCVD in this embodiment has a higher process temperature, and there is also an annealing process with a higher process temperature after deposition, which results in better quality silicon nitride (e.g., higher density), fewer defects in silicon nitride, and thus less loss when optical signals are transmitted in silicon nitride.
[0142] The second waveguide 12, made of silicon nitride, can be formed using LPCVD and annealing processes before the semiconductor absorption layer 13 is formed, thus avoiding damage to the semiconductor absorption layer 13 due to excessively high process temperatures.
[0143] The second waveguide 12 is spaced apart from the first waveguide by a certain distance; in one embodiment, the distance between the second waveguide 12 and the first waveguide can be...
[0144] In one embodiment, the height of the second waveguide 12 can be
[0145] In one embodiment, the semiconductor device further includes a first doped region 141 and a second doped region 142, which are formed at intervals in the semiconductor layer 103 below the semiconductor absorption layer 13, wherein the first doped region 141 and the second doped region 142 have opposite doping types.
[0146] In one embodiment, the semiconductor device further includes:
[0147] The third doped region 151 and the fourth doped region 152 are respectively formed in the semiconductor layer 103 on both sides of the semiconductor absorption layer 13. The third doped region 151 is connected to the first doped region 141, and the fourth doped region 152 is connected to the second doped region 142. The doping type of the third doped region 151 is the same as that of the first doped region 141, and the doping type of the fourth doped region 152 is the same as that of the second doped region 142. The doping concentrations of the third doped region 151 and the fourth doped region 152 are greater than those of the first doped region 141 and the second doped region 142, respectively.
[0148] Conductive plugs 17 are formed in the insulating dielectric layer on the third doped region 151 and the fourth doped region 152.
[0149] The first doped region 141 and the second doped region 142 can be electrically connected through the third doped region 151 and the fourth doped region 152, respectively.
[0150] In other embodiments, the first doped region 141 and the second doped region 142 may be located in the semiconductor layer 103 of the detector region A1 on both sides of the semiconductor absorption layer 13 and extend below the semiconductor absorption layer 13. The third doped region 151 and the fourth doped region 152 are respectively formed in the first doped region 141 and the second doped region 142 on both sides of the semiconductor absorption layer 13, so that the first doped region 141 and the second doped region 142 can be electrically connected through the third doped region 151 and the fourth doped region 152 respectively.
[0151] The conductive plug 17 is used to electrically lead out the first doped region 141 and the second doped region 142 or the third doped region 151 and the fourth doped region 152.
[0152] In one embodiment, a metal silicide layer (not shown) may be formed between the third doped region 151 and the fourth doped region 152 and the conductive plug 17, respectively, to reduce the contact resistance between the third doped region 151 and the fourth doped region 152 and the conductive plug 17.
[0153] When the first doped region 141 and the third doped region 151 are P-type doped and the second doped region 142 and the fourth doped region 152 are N-type doped, the first doped region 141, the semiconductor absorption layer 13, and the second doped region 142 form a horizontal PIN junction; when the first doped region 141 and the third doped region 151 are N-type doped and the second doped region 142 and the fourth doped region 152 are P-type doped, the first doped region 141, the semiconductor absorption layer 13, and the second doped region 142 form a horizontal NIP junction.
[0154] As can be seen from the above, since the height of the semiconductor layer 103 in the detector region A1 is higher than the height of the semiconductor layer 103 in the waveguide region A3, and the upper surface of the semiconductor absorption layer 13 on the semiconductor layer 103 in the detector region A1 is not lower than the upper surface of the second waveguide 12, the height of the semiconductor absorption layer 13 can be controlled within a certain range (e.g., the height is located at...). This not only improves the bandwidth of the photodetector, but also allows for the fabrication of a low-loss second waveguide 12 using a higher process temperature before forming the semiconductor absorption layer 13 (e.g., using LPCVD and annealing processes to form a second waveguide 12 made of silicon nitride), thereby enabling the high-bandwidth photodetector and the low-loss second waveguide 12 to be integrated into the same process.
[0155] In summary, this invention provides a semiconductor device comprising: an SOI substrate, the SOI substrate including, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer, the SOI substrate including a detector region and a waveguide region, the semiconductor layer height of the detector region being higher than the semiconductor layer height of the waveguide region; a first waveguide formed in the semiconductor layer of the waveguide region; a semiconductor absorption layer formed on the semiconductor layer of the detector region; an insulating dielectric layer and a second waveguide, the insulating dielectric layer covering the semiconductor layer and the semiconductor absorption layer, the second waveguide being formed in the insulating dielectric layer above the first waveguide. The semiconductor device provided by this invention enables the integration of a photodetector and a waveguide.
[0156] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprising a detector region and a waveguide region; The semiconductor layer is etched so that the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region; A first waveguide is formed in the semiconductor layer of the waveguide region; An insulating dielectric layer and a second waveguide are formed, the insulating dielectric layer covering the semiconductor layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide; A semiconductor absorption layer is formed in the insulating dielectric layer on the semiconductor layer of the detector region.
2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The upper surface of the semiconductor absorption layer is higher than or equal to the upper surface of the second waveguide.
3. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The second waveguide is made of silicon nitride, which is deposited using LPCVD process and then annealed.
4. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, Before forming the semiconductor absorber layer in the insulating dielectric layer on the semiconductor layer of the detector region, the method of manufacturing the semiconductor device further includes: The insulating dielectric layer is etched to expose a portion of the semiconductor layer in the detector region; A first doped region and a second doped region are formed in the semiconductor layer of the exposed detector region, the first doped region and the second doped region being spaced apart and having opposite doping types.
5. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The step of forming the semiconductor absorber layer in the insulating dielectric layer on the semiconductor layer includes: A semiconductor absorption layer is formed on the exposed semiconductor layer of the detector region, and the semiconductor absorption layer extends onto the insulating dielectric layer; The semiconductor absorber layer above the upper surface of the insulating dielectric layer is removed using a chemical mechanical polishing process.
6. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that, The method for manufacturing the semiconductor device further includes: A third doped region and a fourth doped region are formed in the semiconductor layer on both sides of the semiconductor absorption layer. The third doped region is connected to the first doped region, and the fourth doped region is connected to the second doped region. The third doped region and the first doped region have the same doping type, and the fourth doped region and the second doped region have the same doping type. The doping concentrations of the third doped region and the fourth doped region are greater than the doping concentrations of the first doped region and the second doped region, respectively.
7. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The method for manufacturing the semiconductor device further includes: A conductive plug is formed, which is used to electrically lead out the first doped region and the second doped region.
8. The method for manufacturing a semiconductor device as claimed in claim 6, characterized in that, The method for manufacturing the semiconductor device further includes: A conductive plug is formed, which is used to electrically lead out the third doped region and the fourth doped region.
9. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The SOI substrate further includes a modulator region and a coupler region, and the method for manufacturing the semiconductor device further includes, prior to forming the insulating dielectric layer and the second waveguide: A modulator is formed in the semiconductor layer of the modulator region, and a coupler is formed in the semiconductor layer of the coupler region.
10. A semiconductor device, characterized in that, include: The SOI substrate includes, from bottom to top, a lower substrate, an insulating buried layer, and a semiconductor layer. The SOI substrate includes a detector region and a waveguide region, wherein the height of the semiconductor layer in the detector region is higher than the height of the semiconductor layer in the waveguide region. A first waveguide is formed in the semiconductor layer of the waveguide region; A semiconductor absorption layer is formed on the semiconductor layer of the detector region; An insulating dielectric layer and a second waveguide, wherein the insulating dielectric layer covers the semiconductor layer of the waveguide region, the semiconductor layer of the detector region, and the semiconductor absorption layer, and the second waveguide is formed in the insulating dielectric layer above the first waveguide.
11. The semiconductor device as claimed in claim 10, characterized in that, The upper surface of the semiconductor absorption layer is higher than or equal to the upper surface of the second waveguide.
12. The semiconductor device as claimed in claim 10, characterized in that, The upper surface of the semiconductor layer in the detector region is located between the upper and lower surfaces of the second waveguide.
13. The semiconductor device as claimed in claim 10, characterized in that, The semiconductor device further includes a first doped region and a second doped region, which are formed at intervals in the semiconductor layer below the semiconductor absorption layer, wherein the first doped region and the second doped region have opposite doping types.
14. The semiconductor device as claimed in claim 13, characterized in that, The semiconductor device further includes: The third doped region and the fourth doped region are respectively formed in the semiconductor layer on both sides of the semiconductor absorption layer. The third doped region is connected to the first doped region, and the fourth doped region is connected to the second doped region. The third doped region and the first doped region have the same doping type, and the fourth doped region and the second doped region have the same doping type. The doping concentration of the third doped region and the fourth doped region is greater than the doping concentration of the first doped region and the second doped region, respectively.
15. The semiconductor device as claimed in claim 13, characterized in that, The semiconductor device further includes: A conductive plug is used to electrically lead out the first doped region and the second doped region.
16. The semiconductor device as claimed in claim 14, characterized in that, The semiconductor device further includes: Conductive plugs are used to electrically lead out the third doped region and the fourth doped region.
17. The semiconductor device as claimed in claim 10, characterized in that, The SOI substrate further includes a modulator region and a coupler region, and the semiconductor device further includes: A modulator is formed in the semiconductor layer of the modulator region; A coupler is formed in the semiconductor layer of the coupler region.
18. The semiconductor device as claimed in claim 10, characterized in that, The semiconductor device further includes a conductive plug that is electrically connected to the semiconductor layer of the detector region.
19. The semiconductor device as claimed in claim 10, characterized in that, The lower surface of the second waveguide is lower than the upper surface of the semiconductor layer of the detector region.