Quantum device and method for producing a quantum device

Abstract

The invention relates to a method for producing a quantum device (100), the method comprising: - providing and producing, on a face of a substrate: o semiconductor portions and a semiconductor central region arranged between the portions and separated from each of the portions by dielectric regions; then o depositing a gate stack; then o depositing a hard mask covering a gate conductor, then patterning the hard mask to form an opening vertically in line with the central region; - producing a mask comprising a pattern that defines gates and a pattern that comprises a coupling electrode (140) extending in the central region and between the dielectric regions; then - etching the gate stack and the central region according to the pattern of the mask, the remaining portions of the gate stack forming the gates and a remaining portion of the central region forming the coupling electrode.

Description

DESCRIPTION TITLE: Quantum device and method for realizing a quantum device

[0001] The present application claims priority from French patent application number 24 / 14987, filed on December 20, 2024, entitled "Quantum device and method for realizing a quantum device", which is incorporated by reference to the fullest extent permitted by law. technical field

[0002] This description relates generally to the field of quantum information and quantum electronic devices, and in particular to the fabrication or realization of a quantum device with quantum bits (also called "quantum bits" or qubits). Previous technique

[0003] In the approach considered, qubits are formed by quantum dots that confine elementary charges (electrons or holes) within a semiconductor. Quantum information is, for example, encoded on the spin of these charges. The confinement of elementary charges is achieved within the semiconductor in the three spatial dimensions (length, width, and height) of the quantum dots. This confinement can be achieved structurally, for example, by alternating materials along at least one spatial dimension, and / or electrostatically, for example, by applying an electric potential to the portion of conductive material in which the quantum dots are to be formed.

[0004] Charge detection can be achieved through capacitive coupling between the quantum dot containing the information and another quantum dot for detection, both formed within the same semiconductor region. Tunneling coupling between the two quantum dots is unavoidable in this configuration. Such detection can be implemented using two grids positioned directly opposite each other and covering the same semiconductor region in which the quantum dots are formed. In this case, the grids must be positioned relative to each other at a distance that is neither too great to prevent detection nor too small to avoid unwanted charge exchange between the quantum dots. Therefore, the fabrication of such grids is challenging.

[0005] Alternatively, non-invasive charge detection can be achieved by embedding the detection quantum dot in a separate portion of semiconductor material from the information-containing quantum dot, with these semiconductor portions separated by a dielectric material. A drawback of this solution is that, in the presence of this dielectric, the capacitive coupling between the quantum dots can decrease significantly if they are too far apart, thus reducing the detection sensitivity. Therefore, achieving strong capacitive coupling between the quantum dots requires a small distance between them, which is difficult to achieve with the dielectric material separating the semiconductor portions.

[0006] US document 2023 / 0177376 A1 proposes a suitable structure for implementing non-invasive charge detection, in which capacitive coupling between two The quantum dots formed in two neighboring semiconductor nanowires are enhanced by the presence of a coupling element between these nanowires, with the electrical potential of this coupling element left floating. In this paper, the coupling element partially covers the nanowires, which can lead to the formation of parasitic quantum dots in the portions of the nanowires covered by the coupling element. Furthermore, the alignment between the gates and the coupling element is challenging to achieve. Summary of the invention

[0007] There is a need to propose a quantum device, as well as a method for realizing such a quantum device, suitable for implementing non-invasive charge detection and not presenting at least some of the disadvantages of existing methods.

[0008] One embodiment overcomes all or part of the drawbacks of known quantum device fabrication methods and proposes a method for fabricating a quantum device, comprising at least: provision of a substrate including one face, then fabrication on the face of the substrate: • of at least two semiconductor portions and at least one central semiconductor region disposed between the portions and separated from each of the portions by dielectric insulating regions, then • deposition of a grid stack comprising at least one grid dielectric covered by at least one grid conductor, then • deposition of at least one hard mask covering the grid conductor, then structuring of the hard mask to form at least one opening directly above the central region; - fabrication of a mask comprising a pattern defining at least two grids and a pattern comprising at least one coupling electrode extending in the central region, between the dielectric insulation regions; then, - engraving of the grid stack and central region according to the pattern of the mask such that remaining portions of the grid stack form the grids and at least a remaining portion of the central region forms the coupling electrode.

[0009] According to a particular embodiment, the pattern of the mask defines the grids such that they do not cover the semiconductor portions, or that they do not cover the upper faces of the semiconductor portions.

[0010] According to a particular embodiment, the portions and the central region are made by etching a semiconducting layer of the substrate, or by oxidizing parts of the semiconducting layer of the substrate such that unoxidized parts of the semiconducting layer form the portions and the central region.

[0011] According to a particular embodiment, the substrate is of the SOI type and the semiconductor layer corresponds to the surface semiconductor layer of the substrate, or in which the semiconductor layer forms a semiconductor heterostructure.

[0012] According to a particular embodiment, the central region has a rectangular shape in a plane parallel to the face of the substrate, and / or the portions form nanowires.

[0013] According to a particular embodiment, the hard mask structure is implemented according to an engraving pattern whose edges are positioned vertically above the regions insulating dielectrics alongside which the central region is arranged.

[0014] According to a particular embodiment, the pattern of the mask used for engraving the grid stack and the central region defines, on parts of each of the portions, several grids intended to be arranged parallel to each other.

[0015] According to a particular embodiment, the pattern of the mask used for the etching of the grid stack and the central region comprises at least one part defining the coupling electrode and which is aligned with at least one other part of the mask defining at least one pair of grids, or the pattern of the mask used for the etching of the grid stack and the central region comprises several parts defining several coupling electrodes and which are each aligned with other parts of the mask defining pairs of grids.

[0016] According to a particular embodiment, the pattern of the mask used for the etching of the grid stack and the central region defines several distinct coupling electrodes spaced apart from each other.

[0017] According to a particular embodiment, the process further comprises, after the etching of the grid stack and the central region, the fabrication of dielectric spacers against the side walls of the grids.

[0018] According to one embodiment, the dielectric spacers, or dielectric portions, are made so as to cover the semiconducting portions.

[0019] According to a particular embodiment, the process further comprises, after the etching of the grid stack and the central region, a semiconductor epitaxy at least from the coupling electrode semiconductor.

[0020] According to a particular embodiment, the process further comprises, after the etching of the grid stack and the central region, at least one silicification of at least a part of the grids and the coupling electrode.

[0021] According to a particular embodiment, the process further comprises, after the silicification of the grids and the coupling electrode, the creation of electrical contacts coupled to the grids.

[0022] According to a particular embodiment, at least one of the grids covers at least part of one of the semiconductor portions, or at least one of the grids does not cover the semiconductor portions.

[0023] According to a particular embodiment, the coupling electrode is arranged opposite the lateral faces of the semiconductor portions.

[0024] According to a particular embodiment, the grid stack is etched such that the same number of grids at least partially cover each of the semiconductor portions.

[0025] A quantum device is also proposed, comprising at least: - a substrate, - two semiconductor portions arranged on one face of the substrate, - grids configured to electrostatically control quantum dots formed in semiconductor portions, - at least one coupling electrode disposed on the substrate face, electrically isolated from each of the semiconductor portions by dielectric insulating regions, extending into a central region arranged between the dielectric isolation regions, and configured so that its electrical potential is floating, and in which the coupling electrode is arranged opposite the lateral faces of the semiconductor portions.

[0026] According to a particular embodiment, the grids do not cover the semiconductor portions, or do not cover the upper faces of the semiconductor portions.

[0027] According to a particular embodiment, the semiconductor portions are arranged, relative to the face of the substrate, at the same level as the coupling electrode.

[0028] According to a particular embodiment, the coupling electrode extends parallel to an elongation direction of each of the grids, and preferably in a manner aligned with respect to one of the grids.

[0029] According to a particular embodiment, the coupling electrode extends opposite parts of the semiconductor portions intended to form several pairs of quantum dots.

[0030] According to a particular embodiment, the quantum device further comprises at least one semiconductor charge carrier reservoir connected to at least one end of the semiconductor portions.

[0031] According to a particular embodiment, the coupling electrode does not cover the upper faces of the semiconductor portions.

[0032] According to a particular embodiment, the coupling electrode comprises at least one conductive material, for example at least one of the following materials: metal, silicide, doped semiconductor.

[0033] According to a particular embodiment, the charge carrier reservoir is part of at least one semiconductor portion extending perpendicularly to a direction of elongation of the semiconductor portions.

[0034] According to a particular embodiment, a portion of the dielectric spacers is positioned directly above the dielectric insulation regions.

[0035] In one particular embodiment, at least one of the grids is configured to form information-storing quantum dots in at least one of the semiconductor portions. In another particular configuration, at least one of the grids is configured to form charge-sensing quantum dots in the other semiconductor portion.

[0036] According to a particular embodiment, the coupling electrode is configured to increase the capacitive coupling between at least one pair of quantum dots, each formed in one of the semiconductor portions. Brief description of the drawings

[0037] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which:

[0038] - Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14 represent steps in an example of a process for realizing a quantum device according to a particular embodiment;

[0039] - Figure 15 and Figure 16 represent examples of variants of a quantum device obtained in implementing a manufacturing process according to a particular embodiment;

[0040] - Figure 17, Figure 18, Figure 19, Figure Figures 20, 21 and 22 represent steps in an example of a process for realizing a quantum device according to another particular embodiment;

[0041] - Figure 23 and Figure 24 represent examples of variants of a quantum device obtained by implementing a manufacturing process according to another embodiment. Description of the implementation methods

[0042] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may possess identical structural, dimensional, and material properties. In the figures, to facilitate their interpretation, the different elements and material layers are not shown at the same scale relative to one another.

[0043] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various peripheral elements of the quantum device, other than those described below, are not detailed.

[0044] Unless otherwise specified, when referring to two elements connected together, this means directly connected without any intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0045] In the description that follows, when referring to absolute positional qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative positional qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientational qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, this refers to the orientation of the figures. However, these terms do not imply the actual position and orientation of the quantum device during its use.

[0046] Unless otherwise indicated, the ranges of values ​​shown include the limits of those ranges.

[0047] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0048] An example of a process for realizing a quantum device 100 is described below in relation to figures 1 to 14.

[0049] The device 100 is made from a semiconductor substrate 102. In the described embodiment, the substrate 102 is a silicon-on-insulator (SOI) substrate. In this example, the substrate 102 comprises a support layer 103, for example, made of silicon; a buried dielectric layer 104, or BOX (Buried Oxide), for example, made of SiO2; and a semiconducting surface layer 106, for example, made of silicon. The thickness of the surface layer 106 is, for example, between 5 nm and 20 nm. In Figure 1, view a) is a perspective view of the substrate 102, and view b) is a cross-sectional view parallel to the axis AA visible in view a).

[0050] Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate in which the surface semiconductor layer 106 comprises a semiconductor other than silicon. According to another variant, the substrate 102 may be a bulk substrate comprising a thick layer of semiconductor.

[0051] According to another variant, the surface layer 106 could correspond to a semiconductor heterostructure comprising, for example, a SiGe layer sandwiched between two silicon layers. Other types of semiconductor heterostructures are possible.

[0052] At least two semiconductor portions 108 and at least one central semiconductor region 110, disposed between the portions 108 and separated from the portions 108 by dielectric insulating regions 112, are made at a face 114 of the substrate 102. In the described embodiment, the portions 108 and the region 110 are formed from the surface layer 106. Moreover, the face 114 of the substrate 102 corresponds, in this example, to the main face of the substrate 102 formed by the surface layer 106.

[0053] According to a first example, portions 108 and region 110 are formed by etching the surface layer 106 according to the pattern corresponding to portions 108 and region 110. According to a second example, corresponding to that shown in Figure 2, portions 108 and region 110 can be formed by oxidizing parts of layer 106 such that the unoxidized parts of layer 106 form portions 108 and region 110. The dielectric insulation regions 112 correspond to oxidized parts of layer 106.

[0054] In the described embodiment, each of the portions 108 forms a semiconductor nanowire. These nanowires extend along a principal direction such that they are oriented parallel to each other. Each nanowire has, for example, a length (dimension parallel to the nanowire's principal direction and parallel to the X-axis in Figure 2) between 100 nm and 2000 nm, and a width (dimension perpendicular to the nanowire's length and parallel to the plane formed by the face 114 of the substrate 102, and parallel to the Y-axis in Figure 2) between 20 nm and 100 nm. Alternatively, other shapes, dimensions, and arrangements of the portions 108 are possible. Furthermore, the device 100 may comprise more than two portions 108.

[0055] In the described embodiment, region 110 has a rectangular shape in a plane parallel to face 114. Alternatively, this shape of region 110 may be non-rectangular. Furthermore, a length of region 110 parallel to the length of the nanowires formed by portions 108 may be equal to that of each nanowire, and a width (dimension parallel to the width of the nanowires) of region 110 may be between 20 nm and 2000 nm.

[0056] In the described embodiment, the insulating dielectric regions 112 extend along a principal direction parallel to the nanowires formed by the portions 108. Each of the insulating dielectric regions 112 has, for example, a length (dimension parallel to the principal direction of the insulating dielectric region 112, and parallel to the X-axis in Figure 2) equal to that of the nanowire formed by the portion against which the region 112 is positioned, for example, between 20 nm and 2000 nm, and a width (dimension perpendicular to the length of the insulating dielectric region 112 and parallel to the plane formed by the face 114 of the substrate 102, and parallel to the Y-axis in Figure 2). Figure 2) ranging from 2 nm to 50 nm. Alternatively, other shapes, dimensions, and arrangements of the insulating dielectric regions 112 are possible. Furthermore, the device 100 may have more than two insulating dielectric regions 112.

[0057] In the example described, the step(s) implemented to create the portions 108, the central region 110, and the dielectric insulation regions 112 also create reservoirs of semiconductor charge carriers 116 connected to the ends of the nanowires formed by the portions 108. For this purpose, the etching or oxidation pattern implemented includes that of the reservoirs 116 so that remaining portions of the layer 106 (unetched or unoxidized portions) form these reservoirs 116. In the device 100 obtained at the end of the fabrication process, the reservoirs 116 serve as charge carrier reservoirs for the quantum dots formed in the portions 108, both for those used for information storage and those used for charge detection.

[0058] In one embodiment variant, it is possible that a single reservoir 116 is made and connected to only one end of the nanowires formed by the portions 108.

[0059] In Figure 2, view a) corresponds to a perspective view of the assembly obtained at the end of this stage of realization of the portions 108, the regions 110 and the reservoirs 116, and view b) corresponds to a cross-sectional view parallel to the axis AA visible on view a).

[0060] Alternatively, the ends of the nanowires formed by the portions 108 can be free, i.e., not connected to charge carrier reservoirs. An example of portions 108 forming nanowires and a central region 110 obtained according to such a variant is shown in Figure 3, which represents a top view of the face 114 of the substrate 102 at which portions 108 and region 110 are made.

[0061] A grid stack 118 comprising at least one grid dielectric 120 covered by at least one grid conductor 122, and at least one hard mask 124 covering the grid conductor 122, is deposited on the face side 114 of the substrate 102, covering in particular the portions 108, the central region 110, the insulating dielectric regions 112, and any reservoirs 116. According to one embodiment, the grid dielectric 120 comprises, for example, SiO3 or a high-permittivity dielectric such as HfO3, the grid conductor 122 comprises a TiN / polysilicon bilayer, and the hard mask 124 comprises a semiconductor nitride such as Si3N4 or a SiO2 / Si3N4 bilayer. The thicknesses of the layers of the grid stack 118 are, for example: - grid dielectric 120: between 2 nm and 40 nm, or between 2 nm and 10 nm, and for example equal to 5 nm; - TiN of grid conductor 122: between 2 nm and 20 nm, for example equal to 5 nm; - polysilicon of grid conductor 122: between 5 nm and 50 nm, for example equal to 25 nm; - hard mask 124: between 20 nm and 50 nm, for example equal to 40 nm.

[0062] In Figure 4, view a) corresponds to a perspective view of the assembly obtained after the deposit of the grid stack 118 and view b) corresponds to a cross-sectional view parallel to the axis AA visible in view a).

[0063] A structuring of the hard mask 124 is then implemented. For this, in the example described, a first part of the hard mask 124, positioned directly above the central region 110, is engraved. A first mask 126 is created on the grid stack 118. In the example shown on In Figure 5, the first mask 126 is made by depositing layers 128, 130 and 132 comprising SiOC (layer 128), SiARC (layer 130) and a resin (layer 132). The pattern of the first mask 126 is defined in layer 132, and is such that edges 134 of this pattern are positioned vertically above edges of the dielectric insulating regions 112 next to which the central region 110 is positioned. In other words, remaining portions of layer 132 are arranged above the dielectric insulation regions 112, portions 108 (and reservoirs 116 in the example described) as well as the regions of substrate 102 located outside the part in which the central region 110 is arranged. In Figure 5, view a) corresponds to a perspective view of the assembly obtained after the realization of the first mask 126 and view b) corresponds to a cross-sectional view parallel to the axis AA visible in view a).

[0064] An etching process is then implemented such that the pattern of the first mask 126 is etched, or transferred, into the hard mask 124. As a result of this etching, the layers of the first mask 126 have been consumed or selectively removed, and the first part of the hard mask 124 arranged vertically above the region 110 is removed, forming an opening 127 through the hard mask 124 vertically above the central region 110. In this example, edges 129 of the opening 127 are arranged vertically above edges of the dielectric insulation regions 112 next to which the central region 110 is arranged. This engraving is stopped on the grid conductor 122. In figure 6, view a) corresponds to a perspective view of the assembly obtained at the end of the engraving of the first part of the hard mask 124 and view b) corresponds to a cross-sectional view parallel to the axis AA visible in view a).

[0065] A second mask 136 comprising an etching pattern defining at least two grids 138 covering for example each at least a part of one of the portions 108, and at least one coupling electrode 140 extending in the central region 110, between the dielectric regions 112, is then produced. The coupling electrode(s) 140 are described as floating because their electrical potential is intended to be floating during the use of the device 100. In the described embodiment, the material layers 131, 133, and 135 used to create the second mask 136 are similar in nature to the layers 128, 130, and 132 used to create the first mask 126. As can be seen in Figure 6, the material of layer 131 fills the volume of the opening 127 formed by the previous etching in the hard mask 124. The pattern of the second mask 136 is defined in layer 135.In Figure 7, view a) corresponds to a perspective view of the assembly obtained at the end of this step, view b) corresponds to a cross-sectional view along axis AA visible on view a), view c) corresponds to a cross-sectional view along axis BB visible on view a), view d) corresponds to a cross-sectional view along axis CC visible on view a) and view e) corresponds to a cross-sectional view along axis DD visible on view a) of a part of the assembly obtained.

[0066] In the described embodiment, the pattern of the second mask 136 includes, on parts of each of the sections 108, the patterns of several grids 138 intended to be arranged parallel to each other (one pattern defining eight grids on each section 108 in the example of Figure 7). Furthermore, in the described example, the pattern of the second mask 136 also includes the patterns of several distinct coupling electrodes 140 spaced apart from each other (one pattern defining two coupling electrodes). (see the example in Figure 7). Furthermore, in the example described, the pattern of the second mask 136 defines the pattern of each of the coupling electrodes 140 such that it is aligned with the pattern of one of the grids 138 covering each of the portions 108.

[0067] In the example of Figure 7, two straight portions of the layer 135 each define the pattern of two grids 138 and one of the coupling electrodes 140 aligned with these grids 138. Each of the other remaining portions of the layer 135 defines the pattern of one of the other grids 138 such that the ends of these other grids are arranged vertically above the edges of the dielectric regions 112 next to which the region 110 is arranged.

[0068] An engraving of the grid stack 118 and the central region 110 according to the pattern of the second mask 136 is then implemented such that remaining portions of the grid stack 128 form the grids 138 and one or more remaining portions of the region 110 form the coupling electrode(s) 140 in the central region 110 and extending between the dielectric insulation regions 112.

[0069] Figure 8 shows the structure obtained after the first part of this etching, during which the materials of layers 131, 133, and 135 are consumed or selectively removed during this first part of etching the hard mask 124. This etching is stopped at the grid conductor 122, except in regions where the hard mask 124 had already been etched (previous etching carried out according to the pattern of the first mask 126) and which are not covered by the second mask 136. In these regions, the grid conductor 122 is partially or totally consumed by this etching. In Figure 8, the different views are similar to those in Figure 7.

[0070] Figure 9 represents the structure obtained at the end of this etching process, during which the grid conductor 122, not protected by the hard mask 124, is etched. The etching is stopped on the grid dielectric 120 for regions not previously etched, and on the grid dielectric 120 or on the semiconductor layer 106 for regions included in the pattern of the first mask 126 or the second mask 136 only (i.e., on the coupling electrodes 140 and, in this example, on the reservoirs 116), or on the buried dielectric 104 of the substrate 102 for regions included in the pattern of the first mask 126 and in the pattern of the second mask 136. This second part of the etching process allows the patterns of the masks 126 and 136 to be transferred into the grid conductor 122.

[0071] As an alternative to the steps described above, the second mask 136 can be such that the resulting grids 138 do not cover the semiconductor portions 108.

[0072] Removing the grid dielectric 120 is optional, depending on its thickness. If the thickness is sufficiently small, the sub-ideal selectivity of the spacer etching and / or the surface preparation chemistry performed before epitaxy may consume the grid dielectric 120.

[0073] In Figure 9, the different views are similar to those in Figures 7 and 8. In this example, the grid engraving can be completed in such a way as to consume layer 120.

[0074] Thus, the previous engraving stages are implemented in the presence of four types of regions: those exposed through the motif of the first mask 126 only, those exposed through the motif of the second mask 136 only, those exposed through the motifs of the first and second masks 126, 136, and those that are not exposed by the patterns of the first and second masks 126, 136. In the example described, at the end of these engravings, the coupling electrode(s) 140 are found to be arranged opposite lateral faces of the semiconductor portions 108.

[0075] Dielectric spacers 142 are then made against the lateral sides of the grids 138. For example, these dielectric spacers 142 are obtained by implementing one or more conformal deposits of dielectric materials, followed by an anisotropic etching step removing the deposited materials except against the lateral walls of the grids 138. In the example of figure 10 (with view a) corresponding to a perspective view of the assembly obtained at the end of this step and view b) corresponding to a cross-sectional view along the CC axis visible in view a), these dielectric spacers 142 fill the spaces between the grids 138.

[0076] A selective semiconductor epitaxy is then implemented from the semiconductor parts not covered by another material, i.e. the semiconductor of the coupling electrode(s) 140 and, in this example, that of the reservoirs 116. In Figure 11, view a) corresponds to a perspective view of the assembly obtained at the end of this step, view b) corresponds to a cross-sectional view along the CC axis visible on view a), and view c) corresponds to a cross-sectional view along the DD axis visible on view a).

[0077] The remaining portions of the hard mask 124, which are present here on the grids 138, are then removed. This removal is achieved, for example, by engraving the hard mask 124. In Figure 12, view a) corresponds to a perspective view of the resulting assembly. at the end of this step and view b) corresponds to a cross-sectional view along the CC axis visible in view a).

[0078] The grids 138 and the coupling electrode(s) 140 are then silicified. In the example described, this silicification is also performed on the semiconductor of the reservoirs 116. In Figure 13, the silicide portions are designated by reference numeral 144. In Figure 13, the different views are similar to those in Figures 7 to 9.

[0079] The device 100 is completed by making electrical contacts 146 coupled to the grids 138 and, in the example described, to the reservoirs 116. These electrical contacts 146 are made on the silicide portions 144 of the grids 138 and the reservoirs 116.

[0080] In device 100, no electrical contact is made on the coupling electrode(s) 140 whose electrical potential is intended to be floating, i.e. undefined by applying an electrical potential on the coupling electrode(s) 140.

[0081] In the embodiment example described previously in connection with figures 1 to 14, two coupling electrodes 140 are made to increase the capacitive coupling between two quantum dots formed in one of the portions 108 and two other quantum dots formed in the other of the portions 108, i.e. two pairs of quantum dots.

[0082] Alternatively, it is possible that only one of the two coupling electrodes 140 previously described is made, or that a larger number of coupling electrodes 140 are made.

[0083] According to another variant, it is possible that all quantum dots have their capacitive coupling with another quantum dot that is enhanced by the coupling electrodes 140. In such a variant, each of the quantum dots to be formed in the portions 108 is aligned with one of the coupling electrodes 140. Such a configuration is shown schematically in Figure 15 for three pairs of quantum dots, symbolically designated by the reference numeral 148, and for which one of the coupling electrodes is arranged between each pair of quantum dots. In this configuration, as in the previously described embodiment, the coupling electrodes 140 rest on an insulator, corresponding to the buried dielectric 104 in this example.

[0084] In the embodiment described above in connection with Figures 1 to 14, the first mask 126 and the etching used to form the aperture 127 are made before the second mask 136 and the etching forming the grids 138 and the coupling electrode(s) 140. Alternatively, the second mask 136 and the etching forming the grids 138 and the coupling electrode(s) 140 can be made before the first mask 126 and the etching used to form the aperture 127. According to another variant, the second mask 136 can be made before the structuring of the hard mask 124.

[0085] In the examples described above, each of the coupling electrodes 140 has a rectangular shape in a plane parallel to plane 114.

[0086] In the examples described above, each coupling electrode 140 is used to increase the capacitive coupling between a pair of quantum dots 148, each formed in one of the portions 108. Alternatively, the coupling electrode 140, or one of the coupling electrodes 140, may be common to several pairs of quantum dots 148. An example of such a variant is shown schematically in Figure 16, in which the electrode of coupling 140 shown is common to three pairs of quantum dots 148 controlled by six distinct grids 138.

[0087] In the examples described above, the shape of the coupling electrode 140 or of each of the coupling electrodes 140 is the same at each of the dielectric insulation regions 112. Alternatively, it is possible to have several coupling electrodes 140 whose cross-sections are of different dimensions along the axis parallel to the length of the nanowires formed by the portions 108.

[0088] In the previously described embodiment, the portions 108 are coupled to regions 116 forming load-bearing reservoirs, or source and drain regions, common to both portions 108. Alternatively, these load-bearing reservoirs can be formed by elements other than the regions 116, common or not to the portions 108.

[0089] In the embodiment described above, the coupling element(s) whose electrical potential is left floating do not cross the 108 portions, i.e. are not made on part of the 108 portions, thus avoiding any risk of formation of parasitic quantum dot in the 108 portions by the coupling electrode(s) 140.

[0090] An example of a method for realizing a quantum device 100 according to another embodiment variant is described below in relation to figures 17 to 22. In this other embodiment variant, the grids 138 of the device 100 do not cover the semiconductor portions 108.

[0091] To implement this device 100, the steps previously described in connection with figures 1 to 6 are implemented, as in the examples previously described.

[0092] The second mask 136, comprising the etching pattern defining the grids 138 so that they do not cover the semiconductor portions 108, and the coupling electrode(s) 140 extending into the central region 110, is then fabricated. Thus, the grids 138 will be fabricated such that no part of the grids 138 will be positioned directly above the semiconductor portions 108.

[0093] In this alternative embodiment, the pattern of the second mask 136 is adjusted so as not to cover the semiconductor portions 108. In this example, the portions of this second mask 136 defining the coupling electrodes 140 are separate from those defining the grids 138. No portion of the second mask 136 covers the semiconductor portions 108; that is, no portion of the second mask 136 is positioned directly above the semiconductor portions 108. The layer(s) of material used to form the second mask 136 are, for example, similar or identical to those previously described in connection with Figure 7.In Figure 17, view a) corresponds to a perspective view of the assembly obtained at the end of this step, view b) corresponds to a cross-sectional view along axis AA visible on view a), view c) corresponds to a cross-sectional view along axis BB visible on view a), view d) corresponds to a cross-sectional view along axis CC visible on view a) and view e) corresponds to a cross-sectional view along axis DD visible on view a) of a part of the assembly obtained.

[0094] In the described embodiment, the pattern of the second mask 136 includes the patterns of several grids 138 intended to be arranged parallel to each other. Furthermore, in the described example, the pattern of the second mask 136 also includes the patterns of several distinct coupling electrodes 140, spaced apart from each other and from the grids 138. In addition, in the example described, the pattern of the second mask 136 defines the pattern of each of the coupling electrodes 140 such that it is aligned with the pattern of two grids 138.

[0095] An engraving of the grid stack 118 and the central region 110 according to the pattern of the second mask 136 is then implemented such that remaining portions of the grid stack 128 form the grids 138 and one or more remaining portions of the region 110 form the coupling electrode(s) 140 in the central region 110 and extending between the dielectric insulation regions 112.

[0096] Figure 18 shows the structure obtained after the first part of this etching, during which the materials of layers 131, 133, and 135 are consumed or selectively removed during this first part of the etching of the hard mask 124. This etching is stopped at the grid conductor 122, except in regions where the hard mask 124 had already been etched (previous etching carried out according to the pattern of the first mask 126) and which are not covered by the second mask 136. In these regions, the grid conductor 122 is partially or totally consumed by this etching. In Figure 18, the different views are similar to those in Figure 17.

[0097] Figure 19 shows the structure obtained at the end of this etching process, during which the grid conductor 122, unprotected by the hard mask 124, is etched. The etching is stopped on the grid dielectric 120 for regions not previously etched, and on the grid dielectric 120 or the semiconductor layer 106 for regions included in the pattern of the first mask 126 or the second mask 136 only (i.e., on the coupling electrodes 140 and, in this example, on the reservoirs 116), or on the buried dielectric 104 of the substrate 102 for regions included in the pattern of the first mask 126 and in the pattern of the second mask 136. This second part of engraving allows the patterns of masks 126 and 136 to be transferred into the grid conductor 122.

[0098] Removing the grid dielectric 120 is optional, depending on its thickness. If the thickness is sufficiently small, the sub-ideal selectivity of the spacer etching and / or the surface preparation chemistry performed before epitaxy may consume the grid dielectric 120.

[0099] In Figure 19, the different views are similar to those in Figures 17 and 18. In this example, the grid engraving can be completed in such a way as to consume layer 120.

[0100] Thus, as in the embodiment described above, the previous etching steps are carried out in the presence of four types of regions: those exposed through the pattern of the first mask 126 only, those exposed through the pattern of the second mask 136 only, those exposed through the patterns of the first and second masks 126, 136, and those which are not exposed by the patterns of the first and second masks 126, 136. In the example described, at the end of these etchings, the coupling electrode(s) 140 are arranged opposite lateral faces of the semiconductor portions 108.

[0101] Dielectric portions 150 are then formed against the lateral flanks of the grids 138 and so as to cover the semiconducting portions 108. For example, these dielectric portions 150 are obtained by implementing one or more conformal depositions of dielectric material (x)(s), for example SiO2 and / or SiN (see Figure 20 in which the deposited dielectric material(s) are designated by reference numeral 152), followed by lithography with a mask 154 covering the semiconductor portions 108, followed by etching of the dielectric material(s) 152 and removal of the mask 154. The remaining portions of the dielectric material(s) 152 form the dielectric portions 150. This embodiment of the dielectric portions 150 ensures complete coverage of the semiconductor portions 108 regardless of the distance between the semiconductor portions 108 and the grids 138. Depending on the etching conditions, spacers may form between the grids 138, which is not problematic.

[0102] The following steps of resuming epitaxy, removing hard mask, silicification and making electrical contacts can then be carried out in a similar manner to the manufacturing process previously described, in connection with figures 11 to 13.

[0103] Alternatively, it is possible to make the dielectric portions 150 such that they also cover at least part of the grids 138. Such an alternative embodiment of the device 100 is visible in figure 23.

[0104] Alternatively, dielectric spacers 142 covering the semiconductor portions 108 may be made instead of the dielectric portions 150. Such an embodiment of the device 100 is shown in Figure 24. This alternative can be implemented when the dielectric spacers 142 are sufficiently wide to cover the semiconductor portions 108, which are sufficiently narrow so as not to be too far from the grids 138 and can thus be covered by the dielectric spacers 142.

[0105] The variants previously described for the device 100 comprising grids 138 covering at least part of the semiconductor portions 108 can be applied to device 100 comprising grids 138 not covering the semiconductor portions 108.

[0106] The fact that the gates 138 do not cover the semiconductor portions 108 reduces the capacitive coupling between the quantum dots formed in the semiconductor portions 108 and these gates 138. This reduction in coupling increases the capacitive coupling between the coupling electrodes 140 and the quantum dots, which ultimately improves the detection of the read qubit and thus enhances the performance of the device 100. Furthermore, the fact that the gates 138 do not cover the semiconductor portions 108 reduces the risk of contamination of the active channel by the gate metal.

[0107] In all embodiments, the presence of one or more coupling electrodes 140, whose electrical potential is floating, between the quantum dots 148, in close proximity to them, allows for better capacitive coupling between the quantum dots 148 compared to a configuration in which the quantum dots are separated by the same distance but without the presence of this metallic element. The coupling electrode(s) 140 are not connected to the nanowires 108, which allows the device 100 to implement non-invasive charge detection.

[0108] In the various embodiments, one of the portions 108 can be used to form quantum dots 148 for information storage, and the other portion 108 can be used to form quantum dots used for charge detection. Alternatively, both portions 108 can be used to form quantum dots 148 for information storage.

[0109] In all the embodiment examples, the two lithography-etching processes used allow for an over-etching in the semiconductor layer 106 where the The patterns of the two masks used overlap, and thus precisely define the portions 108, the coupling electrode(s) 140, the dielectric isolation regions 112 and the possible reservoirs 116.

[0110] In the described process, self-alignment between the grids and the coupling electrode is achieved.

[0111] With the described process, the quantum device 100 can be realized in a single semiconductor nanowire.

[0112] With the described process, it is possible to choose the number of dielectric isolation regions formed in the quantum device 100.

[0113] The process described above allows the realization of at least one coupling electrode disposed opposite the lateral sides of the semiconductor portions and which does not cover the upper faces of the semiconductor portions, thus avoiding the formation of parasitic quantum dots.

[0114] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0115] Finally, the practical implementation of the described embodiments and variations is within the reach of a skilled professional, based on the functional specifications provided above. For example, the precise nature of the deposition and engraving steps implemented can be chosen according to, in particular, the material(s) to be deposited or engraved, as well as the thicknesses of the material to be deposited or engraved.

Claims

29 DEMANDS 1. Quantum device (100), comprising at least: - a substrate (102), - two semiconductor portions (108) arranged on one face (114) of the substrate (102), - grids (138) configured to electrostatically control quantum dots formed in the semiconductor portions (108), - at least one coupling electrode (140) disposed on the face (114) of the substrate, electrically isolated from each of the semiconducting portions (108) by dielectric isolation regions (112), extending into a central region (110) disposed between the dielectric isolation regions (112), and configured so that its electrical potential is floating, and in which the coupling electrode (140) is disposed opposite lateral faces of the semiconducting portions (108).

2. Quantum device (100) according to claim 1, in which the grids (138) do not cover the semiconductor portions (108).

3. Quantum device (100) according to any one of the preceding claims, wherein the semiconductor portions (108) are arranged, with respect to the face (114) of the substrate (102), at the same level as the coupling electrode (140). 30 4. Quantum device (100) according to any one of the preceding claims, wherein the coupling electrode (140) extends parallel to an elongation direction of each of the grids (138), and preferably in a manner aligned with respect to one of the grids (138).

5. Quantum device (100) according to any one of the preceding claims, wherein the coupling electrode (140) extends opposite parts of the semiconductor portions (108) intended to form several pairs of quantum dots.

6. Quantum device (100) according to any one of the preceding claims, further comprising at least one semiconductor charge carrier reservoir (116) connected to at least one end of the semiconductor portions (108).

7. Quantum device (100) according to any one of the preceding claims, wherein the coupling electrode (140) does not cover the upper faces of the semiconductor portions (108).

8. Quantum device (100) according to any one of the preceding claims, wherein the coupling electrode (140) comprises at least one conductive material, for example at least one of the following materials: metal, silicide, doped semiconductor.

9. A method for realizing a quantum device (100), comprising at least: providing a substrate (102) comprising a face (114), then fabricating on the face (114) of the substrate (102): o at least two semiconductor portions (108) and at least one central semiconductor region (110) disposed between the semiconductor portions (108) and separated from each of the semiconductor portions (108) by dielectric isolation regions (112), then o depositing a grid stack (118) comprising at least one grid dielectric (120) covered by at least one grid conductor (122), then o depositing at least one hard mask (124) covering the grid conductor (122), then structuring the hard mask (124) to form at least one opening (127) directly above the central region (110); - fabrication of a mask (136) comprising a pattern defining at least two grids (138) and a pattern comprising at least one coupling electrode (140) extending in the central region (110), between the dielectric insulation regions (112); then, - engraving of the grid stack (118) and of the central region (110) according to the pattern of the mask (136) such that remaining portions of the grid stack (118) form the grids (138) and at least a remaining portion of the central region (110) forms the coupling electrode (140).

10. Method according to claim 9, wherein the pattern of the mask (136) defines the grids (138) such that they do not cover the semiconductor portions (108).

11. A method according to any one of claims 9 or 10, wherein the semiconducting portions (108) and the central region (110) are made by etching a semiconducting layer (106) of the substrate (102), or by oxidizing parts of the semiconducting layer (106) of the substrate (102) such that unoxidized parts of the semiconducting layer (106) form the semiconducting portions (108) and the central region (110).

12. Method according to claim 11, wherein the substrate (102) is of the SOI type and the semiconducting layer (106) corresponds to the semiconducting surface layer of the substrate (102), or wherein the semiconducting layer (106) forms a semiconducting heterostructure.

13. A method according to any one of claims 9 to 12, wherein the central region (110) has a rectangular shape in a plane parallel to the face (114) of the substrate (102), and / or wherein the semiconducting portions (108) form nanowires.

14. A method according to any one of claims 9 to 13, wherein the structuring of the hard mask (124) is 33 implemented according to an engraving pattern in which the edges (134) are arranged vertically above the dielectric insulation regions (112) next to which the central region (110) is arranged.

15. A method according to any one of claims 9 to 14, wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) defines, on portions of each of the semiconductor portions (108), several grids (138) intended to be arranged parallel to each other 16. Method according to claim 15, wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) comprises at least one part defining the coupling electrode (140) and which is aligned with at least one other part of the mask (136) defining at least one pair of grids (138), or wherein the pattern of the mask (136) used for etching the grid stack (118) and the central region (110) comprises several parts defining several coupling electrodes (140) and which are each aligned with other parts of the mask (136) defining pairs of grids (138).

17. A method according to any one of claims 9 to 16, wherein the pattern of the mask (136) used for engraving the grid stack (118) and the central region (110) defines several distinct coupling electrodes (140) spaced apart from each other. 34 18. Method according to any one of claims 9 to 17, further comprising, after engraving the grid stack (118) and the central region (110), an embodiment of dielectric spacers (142) or dielectric portions (150) against side walls of the grids (138).

19. Method according to claims 10 and 18, wherein the dielectric spacers (142) or the dielectric portions (150) are made so as to cover the semiconducting portions (108).

20. A method according to any one of claims 9 to 19, further comprising, after etching the grid stack (118) and the central region (110), a semiconductor epitaxy at least from the coupling electrode semiconductor (140).

21. A method according to any one of claims 9 to 20, further comprising, after the etching of the grid stack (118) and the central region (110), at least a silicification of at least a part of the grids (138) and the coupling electrode (140).

22. Method according to claim 21, further comprising, after silicification of the grids (138) and of the coupling electrode (140), the making of electrical contacts (146) coupled to the grids (138). 35 23. A method according to any one of claims 9 to 22, wherein at least one of the grids (138) covers at least a part of one of the semiconductor portions (108), or wherein at least one of the grids (138) does not cover the semiconductor portions (108).

24. A method according to any one of claims 0 to 23, wherein the coupling electrode (140) is arranged opposite lateral faces of the semiconducting portions (108).

25. A method according to any one of claims 9 to 24, wherein the grid stack (118) is etched such that the same number of grids (138) cover at least part of each of the semiconductor portions (108).

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