Photolithographic methods

Abstract

A photolithographic method of forming a tapered via channel in an integrated circuit, IC. The tapered via channel extends through an insulator layer sandwiched between a first conductive layer and a second conductive layer. The insulator layer comprises a photopatternable material. The tapered via channel comprises a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer. The method comprises depositing a layer of the photopatternable material onto the first conductive layer, and exposing the photopatternable material using a photomask comprising a feature corresponding to the upper opening of the tapered via channel. The exposing is arranged to facilitate tapering of the via channel.

Description

PHOTOLITHOGRAPHIC METHODSTECHNICAL FIELD

[0001] The present disclosure concerns photolithographic methods. More particularly, but not exclusively, the present disclosure concerns photolithographic methods of forming a tapered via channel in an integrated circuit.BACKGROUND

[0002] Vias are used to electrically connect first electrical circuitry and / or components on a first side of an electrical insulator (dielectric) with second electrical circuitry and / or components on a second side of the electrical insulator. Vias typically take the form of a perforation through the electrical insulator that is filled with an electrical conductor, for example a channel through a silicon layer with a copper, aluminium or tungsten plug in the channel.

[0003] Manufacturing vias can be complex and expensive. As an example, a via through silicon using copper plugs typically requires more than 10 processing steps requiring etch-stop layers etc.

[0004] It is an object of the present disclosure to provide improved methods for manufacturing vias. In particular, it is an object of the present disclosure to provide methods for manufacturing vias with a significant reduction in the number of processing steps.SUMMARY

[0005] A first aspect of the present disclosure relates to a photolithographic method of forming a tapered via channel in an integrated circuit, IC, the tapered via channel extending through an insulator layer sandwiched between a first conductive layer and a second conductive layer, the insulator layer comprising a photopatternable material, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, the method comprising: depositing a layer of the photopatternable material onto the first conductive layer; and exposing thephotopatternable material using a photomask comprising a feature corresponding to the upper opening of the tapered via channel, wherein the exposing is arranged to facilitate / cause tapering of the via channel. The method may further comprise developing the photopatternable material.

[0006] A second aspect of the present disclosure relates to a photolithographic method of forming a tapered via channel in an integrated circuit. The tapered via channel extends through an insulator layer which is sandwiched between a first conductive layer and a second conductive layer. The insulator layer comprises a photopatternable material. The tapered via channel comprises a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer. The method comprises depositing a layer of the photopatternable material onto the first conductive layer and exposing the photopatternable material using a photomask comprising a feature corresponding to the upper opening of the tapered via channel. During the exposing, the first conductive layer causes at least a portion of light from the exposing to be reflected into the photopatternable material, such that adjacent the first conductive layer, laterally inward extending regions of the photopatternable material become exposed, resulting in the lower opening of the via channel being smaller than the upper opening of the via channel, such that the via channel is tapered.

[0007] A third aspect of the present disclosure relates to a photolithographic method of forming a tapered via channel in an integrated circuit. The tapered via channel extends through an insulator layer which is sandwiched between a first conductive layer and a second conductive layer. The insulator layer comprises a photopatternable material. The tapered via channel comprises a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer. The method comprises depositing a layer of the photopatternable material onto the first conductive layer and exposing the photopatternable material using a photomask comprising a feature corresponding to an upper opening of the tapered via channel. The exposing is arranged to cause rounding of the via channel sidewalls adjacent the upper opening of the viachannel, such that the lower opening is smaller than the upper opening, thereby tapering the via channel.

[0008] A fourth aspect of the present disclosure relates to a photolithographic method of forming a tapered via channel in an integrated circuit. The tapered via channel extends through an insulator layer which is sandwiched between a first conductive layer and a second conductive layer. The insulator layer comprises a photopatternable material. The tapered via channel comprises a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer. The method comprises depositing a layer of the photopatternable material onto the first conductive layer and exposing the photopatternable material using a photomask comprising a feature corresponding to an upper opening of the tapered via channel. During the exposing, the first conductive layer causes at least a portion of light from the exposing to be reflected into the photopatternable material, such that adjacent the first conductive layer, laterally inward extending regions of the photopatternable material become exposed. In addition, the exposing is arranged to cause rounding of the via channel sidewalls adjacent the upper opening of the via channel, such that the lower opening of the via channel is smaller than the upper opening of the via channel, such that the via channel is tapered.

[0009] A fifth aspect of the present disclosure relates to an integrated circuit comprising a tapered via channel extending through an insulator layer which is sandwiched between a first conductive layer and a second conductive layer, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, wherein the insulator layer comprises a photopatternable material. The integrated circuit may be a flexible integrated circuit.

[0010] It will of course be appreciated that features described in relation to one aspect of the present disclosure may be incorporated into other aspects of the present disclosure. For example, the method of the present disclosure may incorporate any of the features described with reference to the apparatus of the present disclosure and vice versa.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 shows a side view of layers of an integrated circuit (IC) according to the present disclosure;

[0012] Figures 2(a) to 2(d) show a tapered via according to the present disclosure;

[0013] Figure 3 shows a partially formed via according to the present disclosure, in which adjacent to a first conductive layer, laterally inward extending regions of a photopatternable material become exposed to UV light;

[0014] Figure 4 shows a partially formed via according to the present disclosure in which the via sidewalls are rounded adjacent an upper opening of the via;

[0015] Figures 5(a) and 5(b) show rounding of the via sidewalls according to the present disclosure by performing a first exposure using a first photomask followed by a second exposure using a second photomask; and

[0016] Figures 6(a) and 6(b) show rounding of the via sidewalls according to the present disclosure using a patterned or gradient photomask.DETAILED DESCRIPTION

[0017] Figure 1 shows a schematic side view of layers of an integrated circuit (IC) 100 according to the present disclosure. The IC 100 comprises devices (not shown), such as transistors, capacitors, resistors etc., within first layers 102 which are formed in a front end of line (FEOL) process. The FEOL process is followed by a back end of line process (BEOL) during which second layers 104 are deposited. In the illustrated example, the second layers 104 include a first inter-metal dielectric layer 108 and a second inter-metal dielectric layer 110. The individual devices and / or circuits in the first layers 102 are interconnected using vias 112 and metal tracking 114 to form the final integrated circuit. A passivation layer 106 may be deposited above the second layers 104, with further metal tracking 114 layers and / or external contact (redistribution) layers above, and connected by further vias in, the passivation layer 106.

[0018] Figures 2(a) to 2(d) show a via 200 according to the present disclosure. Figure 2(a) is a top-down view, whereas Figures 2(b) and 2(c) are cross-sectional views.The via 200 comprises a tapered via channel 202 extending through an insulator layer 204. The insulator layer 204 comprises a photopatternable material. The insulator layer is sandwiched between a first conductive layer 212 and a second conductive layer 214. The tapered via channel 202 comprises a lower opening 208 at the boundary between the insulator layer 204 and the first conductive layer 212; and an upper opening 206 at the boundary between the insulator layer 204 and the second conductive layer 214. Figure 2(b) shows the via 200 before deposition of the second conductive layer 214, whereas Figure 2(c) shows the via after deposition of the second conductive layer 214. The second conductive layer 214 coats the sidewalls 210 of the via channel 202 and is in electrical contact with the exposed surface of the first conductive layer 212. This forms a completed conductive via 200 through the insulator layer 204, electrically connecting two layers of an integrated circuit. Figure 2(d), shows a top-down view of the completed via of Figure 2(c). It should be noted that a perimeter of metal in the first conductive layer 212, shown with dashed lines, is provided around the lower opening 208, and another perimeter of metal is provided in the second conductive layer 214 around the upper opening 206.

[0019] The present inventors appreciated that it is desirable for the via channel 202 to be tapered in such a manner that the lower opening 208 of the via channel 202 is smaller than the upper opening 206 of the via channel 202. By smaller, it should be understood that the lower opening 208 may have a smaller cross-section than the upper opening 206, whilst retaining the same general cross-sectional shape as the upper opening 206, which may be rectangular, square, hexagonal or circular, for example. By tapering the via channel 202 in this manner, the subsequent coating of the via sidewalls 210 with the second conductive layer 214 may be completed more successfully and with fewer processing steps. For example, the tapering of the via channel 202 may allow the second conductive layer 214 to adhere better to the sidewalls 210. The tapering of the via channel 202 may allow easier formation of a conformal layer over the sidewalls 210 and the lower opening 208. This may allow the use of faster and / or lower cost deposition methods for the second conductive layer 214. Such methods may include physical vapor deposition (PVD) and sputtering. However, it should be appreciated that more conventional methods such as chemical vapor deposition (CVD) may also be used fordeposition of the second conductive layer 214. Accordingly, the present disclosure provides simple methods for forming a tapered via channel 202 through an insulator layer 204 in an integrated circuit, without the complexity of conventional processes, such as the damascene processes.

[0020] With the above in mind, Figure 3 illustrates schematically a partially formed via 200 according to the present disclosure (where reference numerals common with Figures 2(a) to 2(d) refer to corresponding features). Since the insulator layer 204 comprises a photopatternable material, a photolithographic process is used for formation of the tapered via channel 202. After deposition of the photopatternable material 204 onto the first conductive layer 212, the photopatternable material is exposed to ultraviolet (UV) light 218 in which a photomask 216 is employed which comprises a feature corresponding to the upper opening 206 of the tapered via channel 202. It should be appreciated that the photomask 216 may not be a physical mask, but rather the projection of a reticle onto the surface of the photopatternable material 204. In Figure 3, the photopatternable material may be a negative photopatternable material, which means that regions exposed to UV light become insoluble and hence remain after a developing process, whereas the regions of the photopatternable material not exposed to UV light remain soluble and hence are removed in a developing process. As such, the photomask 216 is arranged to block UV light from exposing the photopatternable material in the region corresponding to the desired upper opening 206 of the tapered via channel 202.

[0021] The present inventors appreciated that the first conductive layer 212 may cause at least a portion 218’ of the exposure light 218 to be reflected or scattered back into the photopatternable material 204. This may occur, for example, if no bottom anti- reflective coating (BARC) is applied to the upper surface of the first conductive layer 212 prior to deposition of the layer of photopatternable material 204. This means that adjacent to the first conductive layer 212, laterally inward extending regions 220 (or ‘feet’) of the photopatternable material become exposed to UV light, whereas in the absence of the first conductive layer 212, these laterally inward extending regions 220 would not be exposed to UV light, i.e. they would remain substantially unilluminated. For a negative photopatternable material 204, this causes the laterally inward extending regions 220 to become insoluble. As a result, after developing the photopatternable material 204 toremove unexposed regions, the lower opening 208 of the via channel 202 is smaller (i.e. has smaller cross-sectional area) than the upper opening 206 of the via channel. In other words, the via channel 202 is tapered. Once the developing step has been completed, the upper surface of photopatternable material 204, the exposed surface of the first conductive layer 212 at the lower opening 208 of the via channel 202, and the side walls 210 of the tapered via channel 202 are typically coated with a second conductive layer 214, thereby forming a conductive via 200 through the insulator layer 204. In this manner, the via 200 is formed in a single photolithography step and no etch stop layers or the like are required. Priorto coating the side walls 210 of the tapered via channel 202, an optional cleaning process, for example a dry etching process, may be performed to remove any debris from the tapered via channel 202.

[0022] Figure 4 illustrates schematically a partially formed via 200 according to the present disclosure (where reference numerals common with Figures 2(a) to 2(c) refer to corresponding features). As with Figure 3, the insulator layer 204 comprises a photopatternable material, and therefore a photolithographic process may be used for formation of the tapered via channel 202. After deposition of the photopatternable material onto the first conductive layer 212, the photopatternable material is exposed to ultraviolet (UV) light 218 in which a photomask 216 is employed which comprises a feature corresponding to the upper opening 206 of the tapered via channel 202. In Figure 4, the photopatternable material may be a negative photopatternable material which means that regions exposed to UV light become insoluble and hence remain after a developing process, whereas the regions of the photopatternable material not exposed to UV light remain soluble and hence are removed in a developing process. As such, the photomask 216 is arranged to block UV light from exposing the photopatternable material in the region corresponding to the desired upper opening 206 of the tapered via channel 202.

[0023] The present inventors appreciated that the exposing process may be arranged to cause rounding of the via sidewalls 210 adjacent the upper opening 206 of the via channel 202, such that the lower opening 208 is smaller than the upper opening 206, thereby tapering the via channel 202. The rounding of the via sidewalls 210 may be caused by reducing the exposure to UV light 218 of laterally outward extending regions 222 of the photopatternable material 204 adjacent the upper opening 206 of the viachannel 202, compared to the exposure adjacent the lower opening 208 of the via channel.

[0024] Such rounding may be achieved in different ways. With reference to Figures 5(a) and 5(b), one option may be to perform a first exposure 218’ using a first photomask 216’ (as depicted in Figure 5(a)) followed by a second exposure 218” using a second photomask 216” (as depicted in Figure 5(b)). However, it should be appreciated that the method may extend to using more than two photomasks to achieve the desired tapered via channel profile. The first and second photomasks together define the upper opening 206 of the tapered via channel 202. The first and second exposures 218’, 218” and first and second photomasks 216’, 216” may be arranged such that regions 222 of the photopatternable material 204 adjacent the upper opening 206 of the via channel 202 have a higher dissolution rate than corresponding regions of the photopatternable material 204 vertically below said regions 222 and adjacent the lower opening 208 of the via channel 202. The first photomask 216’ may have a smaller cross-sectional area than the second photomask 216”. Alternatively, or in addition, the second exposure 218” may be performed at a higher intensity and / or duration than the first exposure 218’.

[0025] With reference to Figures 6(a) and 6(b), An alternative way of achieving / promoting rounding at the upper opening 206 of the via channel 202 may be to use a patterned or gradient photomask 216. Figure 6(a) is a side view whereas Figure 6(b) is a top-down view. The patterned photomask 216 may a plurality of slits or a checkerboard pattern which is arranged to produce a diffraction pattern in the exposure light 218 within the photopatternable material 204.

[0026] It should be appreciated that the via opening 202 may be formed using a process that combines any of the concepts described with reference to Figures 3 to 6.

[0027] The photopatternable material 204 may be a negative photopatternable material, such as an epoxy-based negative photopatternable material. One such material is SU-8, though the skilled person will appreciate that alternatives exist. On the other hand, the photopatternable material 204 may be a positive photopatternable material. The skilled person understands that the photomasks 216, 216’, 216” shown in Figures 3 to 6 may need to be adapted when using a positive photopatternable material 204 for the insulator layer 204. For example, the photomask may be required to produce shadowwhere the illustrated photomasks permit transmission of UV light 218 and vice versa. The skilled person appreciates that for a positive photopatternable material 204, the developing step removes the exposed regions of the material, as opposed to the unexposed regions. The photopatternable material may be a photoresist material.

[0028] The insulator layer 204 may be a pre-metal dielectric layer, a first intermetal dielectric layer 108, a second intermetal dielectric layer 110, or any other insulating layer through which an electrical connection is desired to be made. The upper opening of the via channel 202 may have a diameter in the range 0.3 to 1.0 microns, although it should be appreciated that the methods disclosed herein extend to vias of arbitrary size, as limited only by the intrinsic properties of the dielectric material and / or the capability of the lithography apparatus, for example.

[0029] An integrated circuit comprising vias 200 as disclosed herein may be a flexible integrated circuit. In accordance with the present disclosure a “flexible integrated circuit” (flexible IC or flexIC) is a type of integrated circuit that is designed to be flexible and conformable, allowing it to bend, twist, and conform to non-flat or irregular surfaces. Unlike traditional rigid ICs, which are typically made on silicon wafers and are inflexible, flexible ICs, in accordance with the present disclosure, are fabricated on flexible substrates using appropriate materials and thin-film processes. The substrate is typically formed of an appropriate flexible polymer material. Nevertheless, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, mechanical, optical, biological and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. The flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0030] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides,polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0031] Where a metal oxide based material is used, the substrate may comprise one or more metal oxides selected from: AI2O3, SiOxNy, Si O2, SisN4, or any other suitable metal oxide. Where a resin based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU- 8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless- steel or any other suitable insulator-coated metal.

[0032] Additionally or alternatively, a flexible IC may not include the flexible substrate, which, for example, may be removed during a manufacturing step.

[0033] Whilst the present disclosure has been described and illustrated with reference to particular examples, it will be appreciated by those of ordinary skill in the art that the present disclosure lends itself to many different variations not specifically illustrated herein. By way of example only, certain possible variations will now be described.

[0034] Where in the foregoing description, integers or elements are mentioned which have known, obvious or foreseeable equivalents, then such equivalents are herein incorporated as if individually set forth. Reference should be made to the claims for determining the true scope of the present disclosure, which should be construed so as to encompass any such equivalents. It will also be appreciated by the reader that integers or features of the present disclosure that are described as preferable, advantageous, convenient or the like are optional and do not limit the scope of the independent claims.Moreover, it is to be understood that such optional integers or features, whilst of possible benefit in some aspects of the present disclosure, may not be desirable, and may therefore be absent, in other aspects.

Claims

Claims1. A photolithographic method of forming a tapered via channel in an integrated circuit, IC, the tapered via channel extending through an insulator layer sandwiched between a first conductive layer and a second conductive layer, the insulator layer comprising a photopatternable material, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, the method comprising: depositing a layer of the photopatternable material onto the first conductive layer; and exposing the photopatternable material using a photomask comprising a feature corresponding to the upper opening of the tapered via channel, wherein the exposing is arranged to facilitate tapering of the via channel.

2. The method according to claim 1 , wherein during the exposing, the first conductive layer causes at least a portion of light from the exposing to be reflected into the photopatternable material, such that adjacent the first conductive layer, laterally inward extending regions of the photopatternable material become exposed, resulting in the lower opening of the via channel being smaller than the upper opening of the via channel, such that the via channel is tapered.

3. The method according to claim 1 or 2, further comprising developing the photopatternable material to remove unexposed regions.

4. The method according to any preceding claim, further comprising depositing the second conductive layer onto the insulator layer.

5. The method according to claim 4, wherein during depositing of the second conductive layer, the second conductive layer coats the side walls of the tapered via channel and coats an exposed portion of the first conductive layer at the lower opening of the via channel, such that the second conductive layer is in electrical contact with the first conductive layer.

6. The method according to claim 4 or 5, further comprising prior to depositing the second conductive layer, performing dry etching to remove debris from the tapered via channel.

7. The method according to any preceding claim, wherein the exposing is arranged to cause rounding of the via channel sidewalls adjacent the upper opening of the via channel, thereby tapering the via channel.

8. The method according to claim 7, wherein the rounding is caused by reducing the exposure of laterally outward extending regions of the photopatternable material adjacent the upper opening of the via channel compared to the exposure adjacent the lower opening of the via channel.

9. The method according to claim 7 or 8, wherein the exposing comprises performing a first exposure using a first photomask followed by a second exposure using a second photomask, the first and second photomasks together defining the upper opening of the tapered via channel.

10. The method according to claim 9, wherein the first and second exposures are arranged such that a region of the photopatternable material adjacent the upper openingof the via channel has a higher dissolution rate than a region of the photopatternable material adjacent the lower opening of the via channel.11 . The method according to claim 9 or 10, wherein the first photomask has a smaller area than the second photomask.

12. The method according to any one of claims 9 to 11 , wherein the second exposure step is performed at a higher intensity and / or duration than the first exposure step.

13. The method according to claim 7 or 8, wherein the exposing comprises using a patterned or gradient photomask.

14. The method according to claim 13, wherein the patterned photomask comprises a plurality of slits or a checkerboard pattern above the intended upper opening of the via channel, the slits or checkerboard pattern being arranged to produce a diffraction pattern in the exposure light.

15. The method according to any preceding claim, wherein the photopatternable material is a negative photopatternable material.

16. The method according to claim 15, wherein the photopatternable material is an epoxy-based negative photopatternable material.

17. The method according to claim 16, wherein the negative photopatternable material is SU-8.

18. The method according to any preceding claim, wherein the insulator layer is a premetal dielectric layer, a first intermetal dielectric layer, or a second intermetal dielectric layer.

19. The method according to any preceding claim, wherein the upper opening of the via channel has a diameter in the range 0.3 to 1.0 microns.

20. The method according to any preceding claim, wherein the tapered via channel has a square cross section.

21. The method according to any preceding claim, wherein the integrated circuit is a flexible integrated circuit.

22. A photolithographic method of forming a tapered via channel in an integrated circuit, IC, the tapered via channel extending through an insulator layer sandwiched between a first conductive layer and a second conductive layer, the insulator layer comprising a photopatternable material, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, the method comprising: depositing a layer of the photopatternable material onto the first conductive layer; and exposing the photopatternable material using a photomask comprising a feature corresponding to an upper opening of the tapered via channel, wherein the exposing is arranged to cause rounding of the via channel sidewalls adjacent the upper opening of the via channel, such that the lower opening is smaller than the upper opening, thereby tapering the via channel.

23. A photolithographic method of forming a tapered via channel in an integrated circuit, IC, the tapered via channel extending through an insulator layer sandwiched between a first conductive layer and a second conductive layer, the insulator layer comprising a photopatternable material, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, the method comprising: depositing a layer of the photopatternable material onto the first conductive layer; and exposing the photopatternable material using a photomask comprising a feature corresponding to the upper opening of the tapered via channel, wherein: during the exposing, the first conductive layer causes at least a portion of light from the exposing to be reflected into the photopatternable material, such that adjacent the first conductive layer, laterally inward extending regions of the photopatternable material become exposed; and the exposing is arranged to cause rounding of the via channel sidewalls adjacent the upper opening of the via channel, such that the lower opening of the via channel is smaller than the upper opening of the via channel, such that the via channel is tapered.

24. An integrated circuit comprising a tapered via channel extending through an insulator layer which is sandwiched between a first conductive layer and a second conductive layer, the tapered via channel comprising a lower opening at the boundary between the insulator layer and the first conductive layer and an upper opening at the boundary between the insulator layer and the second conductive layer, wherein the insulator layer comprises a photopatternable material.

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