A multi-stage power converter

Abstract

A power converter includes a first converter stage and a second converter stage. The first converter stage has a plurality of power switches of a first type. The second converter stage has a plurality of power switches of a second type. A first controller controls the first converter stage; and a second controller controls the second converter stage.

Description

[0001] A MULTI-STAGE POWER CONVERTER

[0002] Technical Field

[0003] The present disclosure relates to a multi-stage power converter and in particular to a multi-stage power converter with improved efficiency.

[0004] Background

[0005] Power electronics are a critical element of electric motors which corresponds to 50% of energy consumption globally.

[0006] To improve efficiency of power electronics research has focused on finding a replacement for silicon insulated gate bipolar transistors (Si 1GBT) and power MOSFET. The comparison of Si 1GBT, SiC,GaN in terms of cost, ease of manufacturing, high power efficiency, and high switching frequency efficiency has been reported in the literature.

[0007] Current power inverters for driving a 3-phase motor are typically optimized to operate at high power levels. Such systems are limited to a specific range of applications.

[0008] It is an object of the disclosure to address one or more of the above mentioned limitations.

[0009] Summary

[0010] According to a first aspect of the disclosure, there is provided a power converter comprising a first converter stage comprising a plurality of power switches of a first type; a second converter stage comprising a plurality of power switches of a second type; a first controller configured to control the first converter stage; and a second controller configured to control the second converter stage.

[0011] For instance the power switches of the first converter stage may all be of the first type, and the power switches of the second converter stage may all be of the second type.

[0012] Optionally, the first type of power switches comprises unipolar switches and the second type of power switches comprises bipolar switches.

[0013] For instance, unipolar switches may include metal-oxide-semiconductor field-effect transistor [MOSFETs], Junction Field Effect Transistor (JFETs) and High-electron-mobility transistor (HEMTs). Bipolar switches may include diodes, bipolar junction transistor [BJTs], thyristors, insulated-gate bipolar transistor (IGBTsJ.

[0014] Optionally, the power switches of the first type have a first size, and the power switches of the second type have a second size.

[0015] Optionally, both the first type of power switches and the second type of power switches are unipolar switches or both the first type of power switches and the second type of power switches are unipolar switches.

[0016] For instance, the first stage and the second stage may be implemented with (SiC) MOSFETs power switches but having different sizes for the first stage and the second stage, respectively.

[0017] Optionally, the first controller and the second controller operate the first converter stage and the second converter stage based on a load threshold. For instance, the load threshold may be a predetermined value. Optionally, the first stage is configured to optimise efficiency for operation below the load threshold; and the second converter stage is configured to optimize power for operation above the load threshold.

[0018] Optionally, the first controller and the second controller are configured to operate the first and second converter stages in parallel.

[0019] Optionally, the power switches of the first stage are implemented as silicon (Si) MOSFETs, silicon carbide (SiC) MOSFETs or gallium nitride (GaN) HEMTs; and the power switches of the second stage are implemented as BJTs, silicon IGBTs or insulated gate turn off thyristors (IGTOs).

[0020] Optionally, the power switches of the first stage are implemented as SiC MOSFETs and the power switches of the second stage are implemented as Si IGBTs.

[0021] Optionally, the power switches of the first stage are implemented as SiC MOSFETs and the power switches of the second stage are implemented as insulated gate turn off thyristor (IGTOs).

[0022] Optionally, the power switches of the first stage are implemented as GaN HEMTs and the power switches of the second stage are implemented as Si IGBTs.

[0023] Optionally, the power switches of the first stage are implemented as GaN HEMTs and the power switches of the second stage are implemented as insulated gate turn off thyristor (IGTOs).

[0024] Optionally, the first and second converter stages form a DC / AC converter. Optionally, the first converter stage is an inverter, and the second converter stage is an inverter.

[0025] Optionally, the first converter stage comprises one or more inductors forming a first switched mode converter stage, the second converter stage comprises one or more inductors forming a second switched mode converter stage.

[0026] Optionally, the one or more inductors form a filter circuit.

[0027] Optionally, the power converter comprises a first filter circuit having inductors designed for intermittent operation, and a second filter circuit having inductors designed for continuous operation.

[0028] For instance, the first filter may be designed for operation at relatively high currents and the second filter may be designed for operation at relatively low currents.

[0029] Optionally, the first controller is configured to generate a first set of control signals to control the first converter stage; and the second controller is configured to generate a second set of control signals to control the second converter stage.

[0030] Optionally, at least one of the first controller and the second controller comprises a processor adapted to execute an artificial intelligence algorithm configured to generate a correction signal to adjust the first and / or second set of control signals.

[0031] For instance the Al algorithm may include a Machine Learning (ML) algorithm or an Artificial Neural Network (ANN). For instance, the artificial neural network may be trained in-situ during the operation of the circuit in a circular fashion, alternating such that one set of data is collected, the second set of data is used for training, and third set of data is applied to the control which was previously collected and used for training during the previous time period.

[0032] Optionally, the artificial intelligence algorithm is configured to predict a change in load current and to start operating one of the converter stage based on the prediction.

[0033] Optionally, the artificial intelligence algorithm is configured to learn nonlinear characteristics of the power switches present in the first and second converter stages.

[0034] According to a second aspect of the disclosure, there is provided a control system for controlling an apparatus, the control system comprising a driving stage comprising a power converter according to the first aspect.

[0035] According to a third aspect of the disclosure, there is provided a system comprising the control system according to the second aspect; and an apparatus coupled to the driving stage of the control system.

[0036] Optionally, the apparatus comprises a motor or an energy grid.

[0037] According to a fourth aspect of the disclosure, there is provided a power system for use with one or more computational units of a data center, the power system comprising: a plurality of energy sources coupled to a bus via a corresponding power converter according to the first aspect; and a grid interface configured to couple the bus to an energy grid; wherein the grid interface is configured to identify if the energy grid is in a critical state associated with a high energy demand, and upon detection of the critical state to send signals to the plurality of power converters to deliver power to the energy grid.

[0038] Optionally, the grid interface comprises a resistive load.

[0039] For instance, the grid interface may be configured to use the resistive load to control the total power flowing between the data center and the energy grid. The grid interface may also be used to disconnect the data center from the energy grid.

[0040] Optionally, the power system comprises a system controller comprising a processor adapted to execute an artificial intelligence algorithm configured to receive data from the one or more computational units and from one or more power converters.

[0041] For instance, the data may be used by the artificial intelligence algorithm to generate one or more control signals to stabilize the grid.

[0042] Optionally, wherein the second type of power switches are arranged in a full bridge configuration formed of a first half bridge coupled to a second half bridge; and wherein the first type of power switches form a third half-bridge coupled in parallel with the second half bridge.

[0043] For instance, the first half bridge, the second half bridge and the third half bridge may form a DC / AC converter.

[0044] Optionally, the power converter comprises a controller circuit adapted to control the power switches of the power converter, wherein the first controller and the second controller are combined in the controller circuit and wherein the controller circuit comprises a gate driver coupled to voltage loop circuit, wherein the voltage loop comprises an adjuster configured to provide a duty cycle signal to maintain modulation within + / -100%; and wherein the gate driver comprises a current limiter configured to perform a duty cycle scaling that can be applied to each half bridge independently .

[0045] For instance, if a measured current of the half bridge (in absolute value) is 25% above a given threshold; the duty cycle is multiplied by 1 / 1.25 that is 0.8; hence reducing the duty cycle by 25% for the corresponding half-bridge.

[0046] Optionally, wherein the gate driver is configured to compare a current of the second half bridge with a first set of threshold values, to compare a current of the third half bridge with a second set of threshold values, and to compare the load current with a third set of threshold values, and to operate the power converter in different modes or with different functionalities based on the comparisons.

[0047] Optionally, wherein the different modes comprise one or more of a safe mode, a short mode, an active mode and a reset mode.

[0048] Optionally, wherein the gate driver comprises a state machine configured to determine the operation of each half bridge.

[0049] For instance, the state machine may be a finite state machine FSM.

[0050] Optionally, wherein the current limiter is configured to provide short circuit protection by maintaining the load current at a pre-determined value until a short circuit condition is eliminated.

[0051] For instance, the short circuit condition may be identified when the load current is above a threshold value (lth8). The controller may be configured to maintain an absolute value of the load current substantially equal to the threshold value (lth8).

[0052] Description of the drawings

[0053] The disclosure is described in further detail below by way of example and with reference to the accompanying drawings, in which: figure 1A is a diagram of an inverter circuit according to the prior art; figure IB is a diagram illustrating the general configuration of an inverter connecting a DC power supply to a three phase load such a 3-phase motor; figure 1C is a diagram of a power converter circuit with a current mode control loop according to the prior art; figure 2 is a diagram of a power converter according to the disclosure; figure 3 is an example implementation of the power converter of figure 2 connected to a 3 phase motor; figure 4 is a diagram of a dual inverter connected to two filters; figure 5A is a plot illustrating an exemplary output waveform for a power converter of the disclosure; figure 5B is a plot illustrating another exemplary output waveform for a power converter of the disclosure; figure 5C is a plot illustrating the operation of the power converter of figure 3; figure 6A is a plot showing the power loss for the example of figure 5B; figure 6B is a plot showing the power loss as a function of current for the example of figure 5B; figure 6C is a plot showing the power loss as a function of current for the example of figure 5B for three different implementations; figure 6D is a plot showing the contribution of each inverter to the overall current as the output power is increased; figure 7 shows the power loss as a function of time for the power converter of figure 3 with optimized sized switches; figure 8 is a plot comparing the total loss of the power converter of figure 3 for three different implementations of the power switches and for increasing current transient; figure 9A is an example implementation of the power converter of figure 2 connected to an energy grid; figure 9B is a modified version of the power converter of figure 9A; figure 9C is an extension of the power converter of figure 9A; figure 9D is an extension of the power converter of figure 9B; figure 10 is a diagram of control system with two controllers and two inverters; figure 11 is a diagram illustrating a dual inverter with dual current mode inner loops according to the disclosure; figure 12 is a diagram of a dual inverter coupled to a motor according to the disclosure; figure 13 is a table summarizing input, outputs and operation for different implementations of the power converter of figure 2; figure 14 is a diagram of a data center system; figure 15 is a diagram of an active filter connected to an energy grid; figure 16 is a diagram of a DC / AC converter according to the disclosure; figure 17 is a diagram of a controller for controlling the DC / AC converter of figure 16; figure 18A is a diagram of a state machine for the gate driver of figure 17; figure 18B is a table defining various current thresholds for use by the state machine of figure 18A; figure 19 is a plot illustrating operation of the DC / AC converter of figure 16 during a short circuit protection mode; figure 20 is a schematic diagram of the DC / AC of figure 16 coupled to several loads connected to different circuit breakers.

[0054] Description

[0055] Figure 1A is a diagram of an inverter circuit according to the prior art. The inverter 100 is an 1GBT inverter having a driver coupled to a transistor circuit formed of three pairs of transistors labelled 1GBTA(H) / 1GBTA(L), 1GBTB(H) / 1GBTB(L), 1GBTC(H) / IGBTC(L). Each pair is connected to a DC voltage from a DC voltage supply. Depending on the application the DC voltage can be relatively high, for instance 500V. The power inverter circuit 100 may be used for a driving a 3-phase motor.

[0056] Figure IB is a diagram illustrating the general configuration of an inverter connecting a DC power supply to a three phase load such a 3-phase motor.

[0057] Figure 1C is a diagram of a power converter circuit with a current mode control loop according to the prior art.

[0058] In many applications the power electronic converter is controlled by multiple nested feedback loops. The innermost loop is commonly a current mode loop which means that the PWM duty cycle is controlled by feedback of the inductor current so as to control the inductor current to a desired value. This desired value is the output of the next outermost feedback loop.

[0059] For example, in a grid forming or off-grid inverter, the outer loop acts to make the output voltage at the inverter’s terminals equal to a reference voltage waveform, for example a sine wave at 50 or 60Hz. If the output voltage diverges from the desired value, an error signal is generated, causing the inner loop to dispense current of the appropriate magnitude and sign to correct the output voltage error. The current mode inner loop adds some cost and complexity but is commonly used in inverters because it brings the following advantages.

[0060] Inverters are traditionally classified as either voltage source or current source. In a voltage source inverter (VS1), the switching devices are connected to a source of DC voltage with a low impedance, such as a battery or capacitor. The AC output of the inverter also appears as a voltage source (a 3-phase AC voltage source). As such it will deliver very large currents into a short circuit, and needs overcurrent protection.

[0061] In a current source inverter (CS1), the switching devices are fed from a source of DC current with a high impedance at the frequencies of interest. Traditionally a large inductor is used in series with the DC supply. The AC output of this inverter appears as a current source. It is not harmed by short circuits, but will deliver a very high voltage into an open circuit, so needs over voltage protection.

[0062] The current source inverter has fallen out of popularity as it is harder to control and protect than the VS1. It is now only used in the very largest inverters in HVDC power transmission.

[0063] A VS1 with current mode inner loop combines the advantages of the VS1 and CS1. It is protected against both short and open circuits, and the output impedance can be controlled to a voltage source, current source, or anything in between, by changing the transfer functions of the loop filters. This is useful for parallel operation with other inverters or with the electrical grid in grid forming applications.

[0064] Figure 2 is a diagram of a DC / AC power converter according to the disclosure. The power converter 200 includes two converter stages and two controllers. The first converter stage 210 has a plurality of power switches of a first type. The second converter stage 220 has a plurality of power switches of a second type different from the first type. The first controller 230 is provided to control the first converter stage while the second controller 240 is provided to control the second converter stage.

[0065] For instance, the first type of power switches may be bipolar switches, and the second type may be unipolar switches. Power semiconductor switches can be classified into two groups. Unipolar devices such as metal-oxide- semiconductor field-effect transistor [MOSFETs], Junction Field Effect Transistor (JFETs) and High-electron-mobility transistor (HEMTs), use electrons as the current carriers. This conduction mechanism makes the device resistive when turned on. Doubling the current doubles the voltage drop and quadruples the conduction losses. At low currents the voltage drop tends to zero.

[0066] Bipolar devices use both electrons and holes as carriers. Examples are diodes, bipolar junction transistor [BJTs], thyristors, insulated-gate bipolar transistor (IGBTsJ. These have a voltage drop that varies as the log of current, which makes them more efficient than unipolar devices at high currents, but less efficient at low currents. To a first approximation the voltage drop is a constant, and doubling the current only doubles the losses.

[0067] The first and second controllers 230, 240 may be designed to operate the first and the second stages 210, 220 based on a load threshold or power output threshold.

[0068] The first converter stage may be configured to optimise efficiency for operation below the load threshold, while the second converter stage is configured to optimize power for operation above the load threshold. In this way the first and second converters may be used in parallel with active current control to maximise the overall efficiency. One converter stage optimised for high efficiency at lower load currents and the second converter stage optimised for high efficiency at high load currents.

[0069] The converter optimised for efficiency may use power switches with a unipolar conduction mechanism such as silicon (Si) MOSFETs, silicon carbide (SiC) MOSFETs or gallium nitride (GaN) HEMTs.

[0070] The converter optimised for high power may use power switches with a bipolar conduction mechanism such as BJTs, silicon IGBTs, gate turn off (GTO) thyristor, or insulated gate turn off thyristor IGTOs (a hybrid of the 1GBT and the gate turn off thyristor).

[0071] While the disclosure provides implementation details for a DC / AC converter, a similar architecture can be implemented for DC / DC converters with the following difference in implementation. DC / AC controller output voltage across the load (which is mostly inductive load) is sinusoidal and the three- phase implementation consists of 120 degrees phase shifted sinusoidal load currents. DC / DC controller output voltage across the load (which is mostly resistive or capacitive) is constant except for the ripple voltage due to current variations. For the DC / DC controller the reference current for the inner loop is generated to keep output voltage constant.

[0072] Figure 3 is an example implementation of the power converter of figure 2 connected to a 3 phase motor. The power converter 300 has a first converter stage 310 having six power switches S1-S6. The switches SI and S2 are coupled to inductor LI at switching node XI. The switches S3 and S4 are coupled to inductor L2 at switching node X2. The switches S5 and S6 are coupled to inductor L3 at switching node X3. The second converter stage 320 has six power switches S7-S17. The switches S7 and S8 are coupled to the inductor LI at switching node X4. The switches S9 and S10 are coupled to the inductor L2 at switching node X5. The switches Sil and S12 are coupled to the inductor L3 at switching node X6.

[0073] A 3 phase motor 305 is coupled to the power converter 300 at nodes X4, X5 and X6. The switches S1-S6 may be selected to achieve a better efficiency at lower currents and higher frequencies, while the switches S7-S12 may be selected to achieve high power delivery. The inductors LI, L2 and L3 between these two sets of switches are used between the converters to isolate them from each other at the switching frequency.

[0074] In this example the first stage 310 that is towards the DC supply is the nominal stage for efficiency at low load current, while the second stage 320 towards the load, is the boost stage for power at higher load current.

[0075] It will be appreciated that the arrangement of the nominal and boost stages may be swapped, so that the boost stage is first (towards the DC supply), and nominal stage is second towards the load. Each arrangement has its own advantage, as follows:

[0076] For high power (boost) first, nominal stage second: In the case where both stages share the output load all the time, this configuration will allow higher frequency components to be added by the second (nominal) stage without additional filtering between the two stages. This configuration will not allow the high power (boost) to be turned off (both sides of the inductors in between converters need to be actively switched at all time, even if there is no power flow).

[0077] For efficiency first, high power second: In the case where the high power converter will be turned off during lower mode, the efficiency converter will drive inductors between the two converters. The capacitance of the second converter (which will appear as a parasitic capacitance of switching devices when they are turned off, as well as discrete capacitors that might be added) works with the inductors to provide an additional stage of filtering. The overall response of the efficiency converter will include this additional LC which will be a design consideration. This configuration is better if the boost converter is expected to be off most of the time.

[0078] Figure 4 is a diagram of a dual inverter connected to two filters. The first inverter 410 may be designed to provide a nominal power required and the second inverter 420 to provide additional boost power. Each filter (450, 460) may be optimized for the corresponding inverter. For instance, the dual inverter architecture can be designed to reduce the size of the filter components.

[0079] In this case the combined power delivered is more than the power that can be delivered by each inverter and the corresponding filter. The optimization of each inverter can also be done taking advantage of different types of switches having different power losses at higher frequencies or higher currents (switching losses and conduction losses).

[0080] One of the filters can be omitted as shown in figure 3 in which one filter is provided by the inductors present in the motor itself.

[0081] In another implementation one or more filters are used between the converters to isolate them from each other at the switching frequency (See inductors LI, L2, L3 in figure 3). The filter may include one or more inductors.

[0082] The high power inductor(s) positioned between the high power stage and the load (for instance 460 after 420) may be implemented with low inductance and a small core made of inexpensive material such as iron powder or air. It is designed for intermittent operation and would overheat if the high power converter ran continuously. The efficiency converter inductor(s) positioned between the nominal stage and the load (for instance 450 after 410) is / are designed for continuous operation at lower currents. It has higher inductance and uses a high quality and low loss core.

[0083] Figure 5A is a plot illustrating an exemplary output waveform for a power converter of the disclosure. In this example, the output of the power converter, also referred to as target waveform 530a, is provided by the combination of two waveforms 510a, 520a generated by the first converter stage and the second converter stage, respectively.

[0084] The second converter stage has power switches of a first type selected to generate a target waveform for power, also referred to as PowerWaveform 520a and defined as PowerWaveform = sin(theta)-SecondaryWaveform.

[0085] The first converter stage has power switches of a second type selected to generate a waveform for efficiency. The waveform 510a is an artificially generated third harmonic of the target waveform with conditional statement to enable the output waveform when the sign of the third harmonic is the same as the sign of the fundamental frequency.

[0086] In this example the magnitude of the second waveform 510a is divided by three (compared with the first waveform 520a) to prevent the Boost inverter from reversing power flow at lower currents.

[0087] SecondaryWaveform 510a = sin(3*theta) / 3, if sign(sin(theta))==sign(sin(3*theta))

[0088] 0, if sign(sin(theta)) .NE. sign(sin(3*theta)) So, in this example the target sinusoidal waveform output is a combination of higher order harmonics and fundamental frequency (sin(theta)).

[0089] Figure 5B is a plot illustrating another exemplary output waveform for a power converter of the disclosure. In this example, the output (target) waveform 530b, is obtained by the combination of a boost waveform 520b, generated by the second converter stage (boost stage) and a nominal waveform 510b generated by the first converter stage (nominal stage).

[0090] The boost waveform and the nominal waveform are defined based on a secondary waveform is expressed as:

[0091] SecondaryWaveform = sin(3*theta) / 3 , if sign(sin(theta)) == sign(sin(3*theta))

[0092] 0 , if sign(sin(theta)) .NE. sign(sin(3*theta))

[0093] The BoostWaveform is defined as:

[0094] BoostWaveform = sin(theta) / 2-SecondaryWaveform

[0095] The NominalWaveform is defined as:

[0096] NominalWaveform = sin(theta) / 2+SecondaryWaveform

[0097] The second converter stage (boost stage) may be implemented using large Si 1GBT switches for the boost power (1GBT has better loss optimization at higher currents). The first converter stage (nominal stage) may be implemented using smaller SiC (or GaN) switches for the nominal power delivery. In this way the overall power loss of the power converter can be reduced. In an alternative embodiment the power switches of both converter stages (nominal and boost) could be both implemented with SiC power switches but having different sizes for different stages. For example, large power switches for the boots stage and small power switches for the nominal stage.

[0098] Figure 5C is a plot illustrating the operation of the power converter of figure 3. The plot includes the output waveform 510c of the first (nominal) stage 310, the output waveform 520c of the second (boost) stage 320, and the combined output waveform 530c of both stages.

[0099] Between the time tO and tl the power converter operates in a low load mode. The power output is delivered by the first stage (nominal inverter) 310. After time tl, the power converter operates in a high load mode. The power output is delivered by both the first stage (nominal inverter) 310 and the second stage 320 (boost inverter). The contribution of the second stage increases as the load increases.

[0100] Figure 6A shows the power loss for the example of figure 5B. As described above with respect to figure 5B, the boost stage is implemented using Si 1GBT power switches and nominal stage is implemented using SiC power switches.

[0101] Figure 6B shows the power loss as a function of current for the example of figure 5B.

[0102] Figure 6C shows the power loss as a function of current for the example of figure 5B with the first converter stage (boost stage) implemented using Si 1GBT switches, and with the second converter stage (nominal stage) implemented using smaller SiC (or GaN) switches. In this example the size of the switches are chosen to match conduction losses at 50% of maximum current target for different type of switches used as boost and nominal converters. Figure 6D shows the contribution of each inverter to the overall current as the output power is increased. This corresponds to the waveforms from Figure 5B. Compared with the prior art converter of figure 1A, the dual inverter of figure 3 has 12 switches instead of 6.

[0103] If the circuit of figure 3 and the circuit of figure 1A were implemented with power switches having the same size, the switching power losses would double for the circuit of figure 3. By reducing the size of the power switches by 50% (half the size) the conduction losses would increase and the efficiency gains from lower conduction power losses would diminish.

[0104] This problem is addressed by introducing a power output threshold for the second stage 320 (boost inverter) to contribute to the output. The switches S1-S6 of the first stage 310 (nominal inverter) are sized such that the total power loss (i.e the switching losses which are decreased plus the conduction losses which are increased with smaller switch sizes) is the same or better for the nominal inverter 310 when operating at lower currents below the power output threshold. In this case the total power loss is the sum of switching losses which are decreased and the conduction losses which are increased with smaller switch sizes.

[0105] Figure 7 shows the power loss as a function of time for the power converter of figure 3 with optimally sized switches. The waveform 710 shows the conduction power loss of the first (nominal) stage 310. The waveform 720 shows the conduction power loss of the second (boost) stage 320. The waveform 730 shows the total power loss including both the conduction and the switching power losses for the two stages.

[0106] Between the times tO and tl the power converter operates in a low load mode. The power output is delivered by the first stage (nominal inverter) 310. After time tl, the power converter operates in a high load mode. The power output is delivered by both the first stage (nominal inverter) 310 and the second stage 320 (boost inverter). The data are shown for four discrete power steps.

[0107] Figure 8 is a plot comparing the total loss of the power converter of figure 3 for three different implementations of the power switches and for increasing current transient. The data are shown for four discrete power steps.

[0108] The waveform 810 shows the total power loss including both the conduction and the switching power losses when the first stage and the second stage are both implemented using only 1GBT transistors.

[0109] The waveform 820 shows the total power loss including both the conduction and the switching power losses when the first stage and the second stage are both implemented using only SiC transistors.

[0110] The waveform 730 (already presented in figure 7) shows the total power loss including both the conduction and the switching power losses the first stage and the second stage are implemented using the optimized configuration in which the boost stage is larger for lower conduction loss and the nominal stage is optimized for smaller switching losses but have higher conduction loss.

[0111] When compared to SiC only or Si 1GBT only solution, this optimized version can deliver lower total power loss for all four discrete power steps.

[0112] The waveforms provided are the output of filter. The gate drive switching waveforms are square waves with switching frequency chosen appropriately for the corresponding switching device type (Si 1GBT, SiC, GaN, etc.). The switching losses are calculated using the square wave gate drive signals as well as the output waveforms charging and discharging of the parasitic capacitance at the output of the switching devices.

[0113] Figure 9A is an example implementation of the power converter of figure 2 connected to a grid. In this example the power converter 900a is used as power inverter interface to the grid. The efficiency switches S1-S6 provide the SecondaryWaveform via the inductors LI, L2 and L3 that also provide a filter function between these two sets of switches.

[0114] The second set of inductors LI' L2' L3' filter the boost inverter output and provide a second stage of filtering for the nominal inverter.

[0115] The nominal inverter may be implemented to have faster switching than the boost inverter. The inductors isolate the high frequency components of the switching waveforms from the load (motor or grid) which will reduce switching losses (because the capacitance of the load and boost inverter doesn't have to be charged / discharged with each switching event) and help with EML

[0116] As the nominal inverter is designed for lower current operation, it needs a higher value of filter inductance to achieve the desired percentage of ripple current. With the topology of figure 9a, both sets of inductors contribute to filtering the nominal inverter output, the effective value of inductance is LI + LI' when the nominal inverter is working by itself.

[0117] Figure 9B is a modified version of the power converter of figure 9A. In this example the efficiency switches S1-S6 are connected to the grid in a dual inverter architecture with each having a separate filter. The grid 905 may be implemented as a star-delta transformer connected to transmission lines. Figure 9C is an extension of the power converter of figure 9A. In this example each converter stage has four legs (four half-bridge) connected to four inductors L1-L4, and LI’ to L4, respectively.

[0118] Figure 9D is an extension of the power converter of figure 9B.

[0119] Not shown in figures 9A-9D is additional filtering that may be required between power converter and grid or distribution system, to meet regulatory limits for EMI.

[0120] Figure 10 is a diagram of a control system with two controllers and two inverters. The control system 1000 has two controllers 1030 and 1040 coupled to a driving stage 1090 that includes a first and a second path, respectively. The first path has a first modulator 1011 and a first driver 1012. The second path has a second modulator 1021 and a second driver 1022.

[0121] Two DC / AC inverters 1010 and 1020 are provided. The DC / AC inverter 1010 is coupled to the apparatus or equipment 1005 via a 3-phase filter 1013. Similarly, the DC / AC inverter 1020 is coupled to the apparatus or equipment 1005 via a 3-phase filter 1023.

[0122] The first controller 1030 is a provided with a first supplementary controller 1031. Similarly, the second controller 1040 is provided with a second supplementary controller 1041. The first and second supplementary controllers may be implemented as processors.

[0123] The sensing unit 1050 is provided to measure a plurality of parameters of the equipment 1005. The first supplementary controller 103 receives the parameters from the sensing unit 1050 and executes an artificial intelligence algorithm for generating at least one correction signal to adjust the control signals sent to modulator 1011. Similarly, the second supplementary controller 1041 receives the parameters from the sensing unit 1050 and executes an artificial intelligence algorithm for generating at least one correction signal to adjust the control signals sent to modulator 1021. The supplementary controllers may be coupled to communicate with each other. This may be used to perform synchronization functions.

[0124] The supplementary controllers can receive all the internal signals of the controller as well as the system platform level instructions that are not directly related to the controller. For instance, the system instructions may be used to predict corresponding changes in the equipment 1005 or other external conditions that might impact the operation of the equipment 1005. The supplementary controller can also receive instructions from the system platform independent of the controller. The supplementary controllers may also receive the gain functions, as well as parameters from other sources, including environmental parameters.

[0125] The supplementary controllers may also be referred to as supplementary Al controllers. The artificial intelligence Al algorithm may be implemented in different ways. For instance, the artificial intelligence algorithm used in supplementary controller may include one or more machine learning (ML) algorithms or artificial neural network (ANN). The ML algorithm(s) might combine linear regression, and classification with multiple neural networks. The ML algorithm may also combine supervised and unsupervised learning. Predetermined pattern recognition may be generated by supervised learning during the design phase of the device. The machine learning functions may be used for inferencing, classification, pattern recognition and may make use of the transfer function of the system.

[0126] In this example the controllers 1030 and 1040 are configured to separate “high power” and “high frequency” components of the desired waveform. This may be achieved by splitting higher harmonics or by the method described in Figure 11 below.

[0127] The supplementary controllers 1031 and 1041 are used to correct the system response of each controller to eliminate the overall error of the system during transients, during anomalies, and due to mismatch of response from different types of switches used in the corresponding set of 6 switches.

[0128] The artificial intelligence algorithm used in the supplementary controller ( for instance, an artificial neural network (ANN)) may be used to predict the need for a sudden high output current and start the high power converter 1020 in advance, to compensate the finite time taken for its inductor current to ramp up.

[0129] The Al algorithm may also be configured to learn the load profile and adjusts the thresholds for starting and stopping the high power converter 1020 for optimum efficiency.

[0130] The Al algorithm may be configured to learn nonlinear characteristics of the power switches, inductors, and electric motor windings so as to maintain optimum efficiency in view of differences between power switches due to variations in manufacturing (process corner / batch to batch variations).

[0131] The artificial neural network may be trained in different fashion, for instance it may be trained during a start-up operation and optionally for a set period after stable operation is achieved. For example, the artificial neural network may be trained in-situ during the operation of the circuit in a circular fashion, alternating such that one set of data is collected, the second set of data is used for training, and third set of data is applied to the control which was previously collected and used for training during the previous time period, as described in W02022 / 038338, incorporated herein by reference. In an alternative embodiment only one supplementary controller is provided in one of the controllers.

[0132] Figure 11 is a diagram illustrating a dual inverter with dual current mode inner loops according to the disclosure. The diagram and description relate to a single phase half bridge inverter as this is the simplest case. The same modification is applicable to three phase, four leg or six phase inverters by using multiple copies of it. For the purposes of this discussion, they can be considered as 3, 4 or 6 separate half bridge inverters connected to a common DC bus and having voltage references for their outer control loops that are synchronised with each other. For example, in a 3 phase inverter, the voltage references could be sine waves of 50 or 60Hz frequency and phases of 0, 120 and 240 degrees.

[0133] Considering the half bridge inverter and its filter inductor, a second half bridge and filter inductor are added. One half bridge and inductor is optimised for efficient operation at low currents, the other for efficient operation at high currents. Each half bridge is provided with an independent PWM circuit, current sensor, and current mode inner loop.

[0134] The output of the existing outer loop (the desired current) now drives the two inner loops through two nonlinear function blocks. These functions could take any form as needed to optimise the overall efficiency of the system.

[0135] In this example the efficiency bridge has a function that is linear from zero current up to a threshold, and then saturates at the threshold value. The power bridge has a function that is zero up to the same threshold, then linear above the threshold, and then saturates at another higher value, which is the maximum safe current it can pass without damage. Additionally, when the desired current is within the zero portion of the power bridge’s transfer function, the power bridge PWM is disabled to avoid switching losses.

[0136] The sum of these two nonlinear functions is a straight line from zero to the maximum safe current, so the modification does not change the behaviour of the inner loop, as far as the outer loop is concerned. This means that any existing control scheme in the prior art can be used for the outer loops.

[0137] Figure 12 is a diagram of a dual inverter coupled to a motor according to the disclosure.

[0138] For background, in the prior art, motor control applications typically do not use current mode inner loops as described with reference to figure 1C. Instead, the motor current is controlled by current sensors and feedback loops, but the control is done in a rotating reference frame using the Park and Clarke transforms. The output is the desired motor voltages in the rotating reference frame, these are transformed to the stationary reference frame and output using PWM or space vector modulation. This scheme is known in the prior art as field oriented control (FOC) and allows vector control of the motor current using relatively modest digital processing power and only 2 current sensors for a 3 phase motor. It is used in many applications including electric vehicle traction motors.

[0139] If the control system described in figure 11 with inner current loops were applied to this application, the number of current sensors would increase from 2 to 6 and the bandwidth and accuracy requirements on them would also be stricter, hence increasing the overall cost of the system.

[0140] In the embodiment of figure 12, two separate 3 phase inverters are used, each with 6 switching devices. The inverter optimised for high power is connected directly to the motor, and the efficiency inverter is connected through 3 filter inductors. Two current sensors are used on two of the motor connections, as in the FOC scheme.

[0141] The motor control algorithm contains two variables, Id and Iq, also known as direct and quadrature axis currents. These are in the rotating reference frame, and as such, DC values that do not alternate with time. The total RMS current in the motor and inverter is equal to the square root of (1 dA2 + lqA2).

[0142] The control algorithm is based on the motor total RMS current as defined above. To save computation, other current measurements such as peak or rectified average could be used instead of RMS. When the current is below the maximum that the efficiency inverter can handle, the efficiency inverter is active and the high power inverter is idle with all switching devices turned off. When the current is greater than the efficiency inverter can handle, all of its switching devices are turned off, and the PWM signals are redirected to the high power inverter. The PWM switching frequency can also be changed at this time, to suit whichever inverter is currently active.

[0143] Because only one inverter is active at a time, “sharing” of current is possible using only 2 current sensors. All the current is assumed to flow in whichever inverter is currently active.

[0144] Various methods can be used to make sure the switchover does not happen too frequently. For example, hysteresis may be added to the switching threshold, so the threshold for switching from efficiency to power is higher than the threshold for switching from power back to efficiency. Alternatively, the artificial neural network might be used to modify the threshold or even generate the switchover signal.

[0145] Figure 13 is a table summarizing input, outputs and operation for different implementations of the power converter of figure 2. The DC / DC supply can have different size multi-leg implementation where the switch sizes and inductor can be optimized for a specified current rating. Since the output voltage of inductors is maintained at DC voltage each phase can operate independently. In a multi-phase operation, a single phase can provide the required current until other phases are required. For low power operation a single pulse can be applied to any of the phases without effecting the other nodes such that the inductor is charged and discharged completely with each pulse. This complete charge / discharge cycle forms the basis of PFM (pulse frequency modulation) and the frequency of the pulses determines the average current delivered to the output capacitor. When the frequency of the PFM is equal or greater than the 1 / time-period of the charge / discharge cycle, the inductor no longer discharges completely, and this is also the optimum point for PWM operation. For DC / DC converters PFM is used to avoid negative current flow during low power operation (it also reduces the switching losses by maintaining the switching to be proportional to number of charge / discharge cycles at low power operation). PFM mode is possible since at any given point Vin / Vout ratio is constant (at least as a target. Note that there are special considerations for starting from Vout=0 before reaching Vout=Vtarget).

[0146] The multi-stage power converter and control system of the disclosure may be used in a variety of applications, including and not limited to the control of motors, energy grid, or data center to name a few.

[0147] Electric power systems operation and control has been mainly determined by legacy synchronous machines (rotational inertia and stabilizing control mechanisms). The increase in percentage of renewable energy sources that connect to the grid by power converter and the associated challenges are widely reported in literature. The main impact of these challenges on the power converter controller is the requirement to design for both linear and nonlinear system response to replicate the synchronous machine behavior with power converters.

[0148] The control system of the disclosure with supplementary controller as shown in figure 10, enables real-time system response correction to nonlinear transient load changes and fault conditions.

[0149] The use of the dual power converter of the disclosure in multiple power converters within a complex power system would allow optimization of the combined system.

[0150] Figure 14 is a diagram of a power system connected to a computational unit of a data center. A data center may include several computational units. In this example a computational unit 1410 is connected to an energy grid 1405 via a local electric bus 1401 also referred to as microgrid. In the system computational units would appear as resistance / capacitance loads. . The bus / microgrid 1401 is connected to the grid 1405 via a smart grid interface 1440 which may be provided as part of an electrical substation that includes a star-delta transformer. The smart grid interface 1440 may be configured to provide various sensing, protection and control functions.

[0151] A renewable energy source 1420 is connected to the bus 1401 via a power converter 1422. Similarly, a battery storage 1430 is connected to the bus 1401 via a power converter 1432. The power converters 1422 and 1432 may be implemented using a dual inverter as described in figures 9a or 9b. In addition, the controllers controlling the inverters may also include a supplementary controller (supplementary Al controllers as described in figure 10). A standby diesel generator (not shown) may be provided and connected to bus 1401. In operation, the smart grid interface 1440 senses the current and power flowing between the grid 1405 and the bus 1401 where several other electrical equipment in the data center are connected.

[0152] The smart grid interface 1440 may also be configured to control a circuit breaker (not shown) for disconnecting the bus 1401 from the grid 1405 if required. In this case smart grid interface 1440 would sense the voltage (magnitude, phase and frequency) on both the grid and data center sides of the circuit breaker. This information would be communicated to the supplementary controllers of the power converters 1422 and 1432 and optionally to the computational unit 1410.

[0153] The smart grid interface 1440 may also contain a resistive load bank and controller for it, to absorb accidental / unwanted backfeed to the grid 1405.

[0154] The resistive load may be used to perform serai functionalities as follows: For instance, it may be used to control the total power flowing between data center and grid. It may also be used to prevent or limit accidental backfeed of power into the grid in cases where it was restricted or forbidden by the electrical utility. It may be used to disconnect the data center from the grid so it can operate as an island if attempts to stabilise the grid fail and it goes down.

[0155] The smart grid interface may be adapted to monitor grid voltage and frequency while operating as an island, and resynchronise with and reconnect to the grid when it becomes stable again.

[0156] A system controller may also be provided to coordinate the various energy sources and loads present in the system 1400 to achieve an optimal outcome. In the present example the system controller may be used to coordinate the energy source 1420, the energy storage 1430, the power converters 1422, 1432 and the computational unit 1410, to achieve an optimal outcome.

[0157] For instance, the smart grid interface may identify that the energy grid 1405 is in a critical state associated with a high energy demand. When the critical state is identified the system controller sends a signal to the power converters 1422, 1432 so that they act as a source to send power to the grid 1405, and therefore stabilize the grid. In addition, the system controller may also send a signal to the computational unit 1410 and converter 1412 to reduce their energy demand (i.e reducing or slowing the workload of the computational unit). Therefore 1420 / 1422 and 1430 / 1432 may act as a source for a specific period of time to stabilize the energy grid 1405.

[0158] The supplementary controllers present in 1422 and 1432 may be used to capture various data, for instance during a transient event. This has been described in patent application W02023017241 incorporated herewith by reference. Such data may be used by the smart grid interface 1440 and the system control to decide when to send the signals to 1422, 1432, 1412 and 1410 to stabilize the grid 1405.

[0159] The system controller might also receive automated dispatching data from the electrical utility. The system controller may include a processor adapted to execute an artificial intelligence algorithm configured to receive data from the one or more computational units 1410 and from one or more power converters 1422, 1432. The data may be used by the artificial intelligence algorithm to generate one or more control signals to stabilize the grid. The system controller may be implemented as part of the smart grid interface 1440, but could also be implemented independently.

[0160] Figure 15 is a diagram of an active filter connected to an energy grid. The DC source voltage across the capacitor C shown in figure 15 can be different for each inverter based on the high voltage operation characteristics of the corresponding switching devices used. In one embodiment, the gate driver of the switching devices are connected to controller with supplementary control containing artificial intelligence components for handling the nonlinear aspects of the dual inverter especially during transient conditions. This may be used for load balancing and reduction of harmonics.

[0161] Figure 16 is diagram of a DC / AC converter. In this example the DC / AC converter 1600 receives a 400V DC input and provides 230V rms at the output. The converter 1600 may be referred to as a high voltage hybrid power module (HVHPM). The hybrid terminology refers to the use of two different types of switches such as Insulated Gate Bipolar Transistor 1GBT power devices and Silicon carbide (SiC) MOSFETs.

[0162] The converter 1600 includes six switches M1-M6. The first half bridge HB1 has a first switch Ml coupled to a second switch M2 at node A. The second half bridge HB2 has a third switch M3 coupled to a fourth switch M4 at node B. The third half bridge HB3 has a fifth switch M5 coupled to a sixth switch M6 at node C. The switches Ml and M2 of the first half bridge, and the switches M3 and M4 of the second half bridge may be implemented using Si 1GBT devices. The switches M5 and M6 of the third half bridge may be implemented as Silicon carbide (SiC) MOSFETs or GaN MOSFETs for instance 650V GaN devices. A first inductor LI is provided between the node B of the second bridge, and the output node D. A second inductor L2 is provided between the node C of the third bridge and the output node D. The first, second and third half bridges are configured to receive a DC voltage (in this case a high voltage of 400V DC) at switch Ml, M3 and M5, respectively.

[0163] In this example, the first half bridge switches at 50Hz and may be referred to as the slow bridge SLB. The second half bridge is referred to as high power bridge HPB typically running at 50kHz with an inductor LI that is nominally ImilliHenry. In this example M3-M4 are implemented using Si 1GBT devices which are more efficient at lower frequencies and higher currents. The third half bridge is referred to as the efficiency bridge EFB typically running at 100kHz - 250kHz with an inductor L2 that is nominally 470microHenry. In this example M5-M6 are implemented with unipolar devices which have lower switching losses and can be operated with higher frequencies and smaller inductors. They are especially more efficient at lower currents.

[0164] Figure 17 is diagram of a controller for controlling the DC / AC converter 1600 of figure 16. The controller 1700 includes a gate driver 1710 coupled to a voltage loop circuit 1720. The gate driver 1710 has a current limiter (not shown) configured to implement a current limiter function also referred to as duty cycle scaling based on a one or more measured currents that may include the high-power bridge current 1HP through LI, the efficiency bridge current 1EF through L2, and the load current 1LOAD.

[0165] The voltage loop circuit 1720 includes a first combiner 1721, a Proportional Integral Pl controller 1722, a second combiner 1723, a divider 1724 and an adjuster 1725 for adjusting the duty cycle of the half bridges. The first combiner 1721 receives a reference sinusoidal signal (SI), the measured load voltage of the converter (S2) and an adjustment signal UE1 (S3) providing correction signal from Ultra Edge block with artificial intelligence. The first combiner generates an output signal, also referred to as error signal S4 = S1+S3-S2.

[0166] The Pl controller 1722 receives the error signal S4 and outputs a signal S5 to correct the error. The signal S5 has two components: a proportional component and an integral component so that S5 = ProportionalGain x S4 + Gainl x lntegral(S4). RESET is for the integral component (it starts from zero when RESET). The set point S4 changes in real time. The second combiner 1723 receives the reference sinusoidal signal SI, the signal S5 and an adjustment signal UE2 (S6) providing correction signal from Ultra Edge block with artificial intelligence. The second combiner 1723 then generates the output signal S7=S1+S5+S6.

[0167] The divider 1724 receives S7 and generates the signal S8 by dividing S7 by the supply voltage VDC (nominally 400V in the example of figure 16), hence normalizing the voltage signal S7. This normalizes the duty cycle with respect to VDC. For example, when S8=l the Duty Cycle is 100%. Ml OFF M2 ON, M3 ON M4 OFF and VLOAD = VDC. When Duty Cycle = -1, Ml ON M2 OFF, M3 OFF M4 ON and VLOAD = -VDC.

[0168] The adjuster 1725 receives the signal S8 and provides a duty cycle signal S9 to the gate driver 1710. The signal S9 is a sinusoidal signal having a value that varies between -1 and +1. The signal S9 governs the duty cycle based on the outer voltage control loop and the adjustments from Ultra Edge and other considerations to keep the duty cycle within + / -100% (common duty cycle for all half bridges before the current limiter function is applied). For instance, 0.5 means 50% modulation where M2 is ON M3 / M4 has 50% duty cycle. Similarly, -0.5 means Ml is ON M3 / M4 toggles with 50% duty cycle. The adjuster 1725 is used to guarantee that the duty cycle stays within + / - 100% modulation. The gate driver 1710 performs pulse width modulation function and generates the gate signals for the power devices Ml, M2, M3, M4, M5, M6. The gate driver 1710 comprises a state machine, for instance a finite state machine FSM that determines the operation of each half-bridge and a current limiter implementing a current limiter function (duty cycle scaling) that can be applied to each half bridge independently. If the measured current is above the current limit by xx% (i.e. O.xx); the duty cycle S9 is multiplied by 1 / 1. xx for the corresponding half bridge. The current limiter reduces the duty cycle by 1 / 1. xx (true for both positive and negative duty cycles) when absolute value of half-bridge current is above the threshold by xx%. The current limiter function can be implemented digitally.

[0169] Figure 18A is a diagram of a state machine for the gate driver 1710 of figure 17. Different modes of operation are determined by various current thresholds.

[0170] Figure 18B is a table defining the various current thresholds. The table list 10 thresholds also referred to as flags labelled 0 to 9. The gate driver is configured to compare a current of the second half bridge with a first set of threshold values. See current 1HP compared with the current thresholds lth7, lcc3 and led (when half-bridge currents have opposite signs and they are above these threshold values; a flag condition occurs). The gate driver is also configured to compare a current of the third half bridge with a second set of threshold values. See current 1EF compared with led, lcc3, lth6. The gate driver is also configured to compare the load current with a third set of threshold values. See load compared with lth8, 1th 5 and lth2. The gate driver operates the power converter in different modes or with different functionalities based on the above comparisons as described in the table of figure 18B.

[0171] The duty cycle scaling is implemented within specific operating states for controlling the current of each half bridge independently. This is achieved by multiplying the duty cycle S9 with a coefficient corresponding to the required current correction. If the absolute value of the measured current is 25% above the threshold; the duty cycle is multiplied by 1 / 1.25 (that is 0.8; hence reducing the duty cycle by 25% for the corresponding half-bridge). It should be noted that the controller makes up for the reduced current by increasing the overall duty cycle, which results in increased current for the half bridge that is not being controlled. Additional modes are implemented for protection and short circuit handling as described below. For instance, flag 8 corresponds to ILOAD > Ith8. In this case the driver implements a short circuit protection.

[0172] The driver can operate the converter 1600 in four modes referred to as short mode, safe mode, active mode and reset mode. The operation of the state machine is explained using shorthand notation as follows. HiZ: refers to high impedance where both the high side and low side switches are OFF regardless of the value of Duty Cycle. Act: refers to ACTIVE mode where the high side and low side switches are turned ON and OFF according to the output of the pulse width modulation. This can be bipolar mode or unipolar mode depending on the value of the duty cycle and other design considerations.

[0173] In nominal operation, the switches M5 and M6 are running at a faster switching frequency (N times the nominal switching frequency of M3 and M4, nominally 50kHz). Accordingly, the L2 inductor value can be smaller than the LI inductor value based on design considerations. For instance, L2 may have an inductance of 500|iH and LI of ImH.

[0174] The switches Ml and M2 run at the same frequency as the reference voltage signal Vref (nominally 50Hz or 60Hz). The gate drive signals can be generated using unipolar mode or bipolar mode modulation. In unipolar mode, M2 is ON and Ml is OFF when duty cycle output of voltage loop is greater than or equal to zero. Ml is ON and M2 is OFF when duty cycle output of voltage loop (signal S9) is less than zero. For values of S9 around zero, bipolar mode modulation can be used where Ml and M2 are running at 50% duty cycle and other half bridge duty cycle is adjusted as (50% + / - DutyCycle_Voltage_loop).

[0175] Figure 19 is a plot showing the waveforms of the load current ILOAD 1910, the voltage load 1920, and the supply voltage VDC 1930 during the short circuit protection mode when the flag_8 in figure 18A is enabled. The current limit is configured to a pre-determined value to trip the circuit breaker (nominally + / -30A depending on the circuit breaker specification) when short circuit is encountered. As shown in Figure 19, the 230V rms output returns to normal operation as soon as the circuit breaker is tripped. The short circuit (connection to ground that short circuit the load) occurs at time tl. Between the times tl and t2 the load current increases sharply in amplitude. At time t2 the circuit breaker opens and the load current 1910 and load voltage 1920 return to their previous values.

[0176] Figure 20 is a schematic diagram of a DC / AC converter as shown in figure 16 coupled to several loads connected to different circuit breakers. The loads on a different circuit breaker return to normal operation as soon as the circuit breaker connected to the short circuit opens. Sufficient current is provided to the circuit breaker to ensure the trip happens in a very short time. A sufficient voltage should be maintained across the short until the circuit breaker trips. During the short operation the DC / AC converter maintains specified current across the load as shown in Figure 19. The system allows minimal impact on the remaining loads that are not on the same circuit breaker as the short. The short circuit functionality permits the DC / AC inverter to continue delivering power to the other load(s) without major disruption.

[0177] A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the above description of the specific embodiments is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described.

Claims

CLAIMS1. A power converter comprising a first converter stage comprising a plurality of power switches of a first type; a second converter stage comprising a plurality of power switches of a second type; a first controller configured to control the first converter stage; and a second controller configured to control the second converter stage.

2. The power converter as claimed in claim 1, wherein the first type of power switches comprises unipolar switches and wherein the second type of power switches comprises bipolar switches.

3. The power converter as claimed in claim 1, wherein the power switches of the first type have a first size, and the power switches of the second type have a second size.

4. The power converter as claimed in claim 3, wherein both the first type of power switches and the second type of power switches are unipolar switches or wherein both the first type of power switches and the second type of power switches are unipolar switches.

5. The power converter as claimed in claim 1, wherein the first controller and the second controller operate the first converter stage and the second converter stage based on a load threshold.

6. The power converter as claimed in claim 3, wherein the first stage is configured to optimise efficiency for operation below the loadthreshold; and wherein the second converter stage is configured to optimize power for operation above the load threshold.

7. The power converter as claimed in claim 1, wherein the first controller and second controller are configured to operate the first and second converter stages in parallel.

8. The power converter as claimed in claim 1, wherein the power switches of the first stage are implemented as silicon (Si) MOSFETs, silicon carbide (SiC) MOSFETs or gallium nitride (GaN) HEMTs; and wherein the power switches of the second stage are implemented as BJTs, silicon IGBTs or insulated gate turn off thyristors (IGTOs).

9. The power converter as claimed in claim 1, wherein the power switches of the first stage are implemented as SiC MOSFETs and wherein the power switches of the second stage are implemented as Si IGBTs.

10. The power converter as claimed in claim 1, wherein the power switches of the first stage are implemented as SiC MOSFETs and wherein the power switches of the second stage are implemented as insulated gate turn off thyristors (IGTOs).

11. The power converter as claimed in claim 1, wherein the power switches of the first stage are implemented as GaN HEMTs and wherein the power switches of the second stage are implemented as Si IGBTs.

12. The power converter as claimed in claim 1, wherein the power switches of the first stage are implemented as GaN HEMTs andwherein the power switches of the second stage are implemented as insulated gate turn off thyristors (IGTOs).

13. The power converter as claimed in claim 1, wherein the first and second converter stages form a DC / AC converter.

14. The power converter as claimed in claim 1, wherein the first converter stage is an inverter and wherein the second converter stage is an inverter.

15. The power converter as claimed in claim 1, wherein the first converter stage comprises one or more inductors forming a first switched mode converter stage, wherein the second converter stage comprises one or more inductors forming a second switched mode converter stage.

16. The power converter as claimed in claim 15, wherein the one or more inductors form a filter circuit.

17. The power converter as claimed in claim 16, comprising a first filter circuit having inductors designed for intermittent operation, and a second filter circuit having inductors designed for continuous operation.

18. The power converter as claimed in claim 1, wherein the first controller is configured to generate a first set of control signals to control the first converter stage; and wherein the second controller is configured to generate a second set of control signals to control the second converter stage.

19. The power converter as claimed in claim 18, wherein at least one of the first controller and the second controller comprises aprocessor adapted to execute an artificial intelligence algorithm configured to generate a correction signal to adjust the first and / or second set of control signals.

20. The power converter as claimed in claim 19, wherein the artificial intelligence algorithm is configured to predict a change in load current and to start operating one of the converter stage based on the prediction.

21. The power converter as claimed in claim 19, wherein the artificial intelligence algorithm is configured to learn nonlinear characteristics of the power switches present in the first and second converter stages.

22. A control system for controlling an apparatus, the control system comprising a power converter as claimed in claim 1.

23. A system comprising the control system as claimed in claim 22; and an apparatus coupled to a driving stage of the control system.

24. The system as claimed in claim 23, wherein the apparatus comprises a motor or an energy grid.

25. A power system for use with one or more computational units of a data center, the power system comprising: a plurality of energy sources coupled to a bus via a corresponding power converter as claimed in claim 1; and a grid interface configured to couple the bus to an energy grid; wherein the grid interface is configured to identify if the energy grid is in a critical state associated with a high energy demand, andupon detection of the critical state to send signals to the plurality of power converters to deliver power to the energy grid.

26. The power system as claimed in claim 25, wherein the grid interface comprises a resistive load.

27. The power system as claimed in claim 25, comprising a system controller comprising a processor adapted to execute an artificial intelligence algorithm configured to receive data from the one or more computational units and from one or more power converters.

28. The power converter as claimed in claim 2, wherein the second type of power switches are arranged in a full bridge configuration formed of a first half bridge coupled to a second half bridge; and wherein the first type of power switches form a third half-bridge coupled in parallel with the second half bridge.

29. The power converter as claimed in claim 28, comprising a controller circuit adapted to control the power switches of the power converter, wherein the first controller and the second controller are combined in the controller circuit and wherein the controller circuit comprises a gate driver coupled to voltage loop circuit, wherein the voltage loop comprises an adjuster configured to provide a duty cycle signal to maintain modulation within + / - 100%; and wherein the gate driver comprises a current limiter configured to perform a duty cycle scaling that can be applied to each half bridge independently.

30. The power converter as claimed in claim 29, wherein the gate driver is configured to compare a current of the second half bridge with a first set of threshold values, to compare a current of thethird half bridge with a second set of threshold values, and to compare the load current with a third set of threshold values, and to operate the power converter in different modes or with different functionalities based on the comparisons.

31. The power converter as claimed in claim 30, wherein the different modes comprise one or more of a safe mode, a short mode, an active mode and a reset mode.

32. The power converter as claimed in claim 30, wherein the gate driver comprises a state machine configured to determine the operation of each half bridge.

33. The power converter as claimed in claim 30, wherein the current limiter is configured to provide short circuit protection by maintaining the load current at a pre-determined value until a short circuit condition is eliminated.

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