Semiconductor device and semiconductor device manufacturing method

Abstract

The present disclosure makes it possible to provide a semiconductor device and semiconductor device manufacturing method that can suppress variations in etching depth during PEC etching. The semiconductor device includes a substrate, a channel layer and a barrier layer stacked sequentially on the substrate, and a gate electrode. The barrier layer has a lower semiconductor layer, an intermediate semiconductor layer stacked on the lower semiconductor layer, and an upper semiconductor layer stacked on the intermediate semiconductor layer. The lower semiconductor layer has a higher band gap energy than the upper semiconductor layer. The intermediate semiconductor layer has a higher band gap energy than the lower semiconductor layer. The gate electrode is formed on the intermediate semiconductor layer exposed from an opening provided in the upper semiconductor layer.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device and a method for manufacturing a semiconductor device to which PEC (Photoelectrochemical) etching is applied.

[0002] For base stations of mobile communication, devices such as GaN-HEMT (GaN-High Electron Mobility Transistor) characterized by high breakdown voltage and high output density are widely used.

[0003] In such a device, a recess gate structure in which the barrier layer directly under the gate electrode is dug down only in the vicinity of the gate electrode has been proposed. With the recess gate structure, it is possible to achieve both high-frequency operation and high output density of the device, which are generally in a trade-off relationship.

[0004] Non-Patent Document 1 discloses a technique of applying wet etching called PEC etching to a GaN-based semiconductor layer. In this technique, an excitation light having an energy exceeding the bandgap is irradiated to the GaN-based semiconductor layer to generate electron-hole pairs, and Ga is oxidized by holes. Further, wet etching is performed to remove the Ga oxide on the surface, thereby digging down the GaN-based semiconductor layer. Thereby, damage-free etching is realized.

[0005] "PEC (Photoelectrochemical) etching of GaN crystals", Sumitomo Chemical Technical Journal, 2020.

[0006] However, in the method of Non-Patent Document 1, in order to perform PEC etching of the semiconductor layer to a desired depth, condition management such as the concentration of the chemical solution, the etching time, and the intensity of the excitation light is required. In a method relying on such condition management, there is a concern about manufacturing variations in the etching depth.

[0007] In order to solve the above problems, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of suppressing variations in etching depth in PEC etching.

[0008] A first aspect of the present disclosure is preferably a semiconductor device comprising a substrate, a channel layer and a barrier layer sequentially laminated on the substrate, and a gate electrode, wherein the barrier layer has a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer, the lower semiconductor layer having a higher bandgap energy than the upper semiconductor layer, the intermediate semiconductor layer having a higher bandgap energy than the lower semiconductor layer, and the gate electrode being formed on the intermediate semiconductor layer exposed through an opening in the upper semiconductor layer.

[0009] A second embodiment is preferable to be a semiconductor device comprising: a substrate; a channel layer and a barrier layer sequentially laminated on the substrate; an insulating film formed on the barrier layer; an insulating injection region; a first gate electrode and a second gate electrode, wherein the barrier layer has a lower semiconductor layer; an intermediate semiconductor layer laminated on the lower semiconductor layer; and an upper semiconductor layer laminated on the intermediate semiconductor layer, the lower semiconductor layer having a higher bandgap energy than the upper semiconductor layer, the intermediate semiconductor layer having a higher bandgap energy than the lower semiconductor layer, the first gate electrode being formed on the intermediate semiconductor layer within an opening that penetrates the insulating film and the upper semiconductor layer and exposes the intermediate semiconductor layer, and the second gate electrode being formed on the upper semiconductor layer within an opening provided in the insulating film and exposing the upper semiconductor layer, and the region including the first gate electrode and the region including the second gate electrode being separated by the insulating injection region that penetrates from the barrier layer to the substrate.

[0010] Furthermore, a third embodiment is preferably a method for manufacturing a semiconductor device, comprising the steps of: laminating a channel layer on a substrate; laminating a barrier layer on the channel layer, the barrier layer having a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer; removing the upper semiconductor layer at the position where the gate electrode is to be formed by photoelectrochemical etching using excitation light having an energy equal to or greater than the band gap energy of the upper semiconductor layer and equal to or less than the band gap energy of the intermediate semiconductor layer, thereby exposing the intermediate semiconductor layer; and forming the gate electrode on the exposed intermediate semiconductor layer.

[0011] A fourth embodiment includes the steps of: laminating a channel layer on a substrate; laminating a barrier layer on the channel layer having a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer; forming an insulating injection region penetrating from the barrier layer to the substrate, and separating the upper semiconductor layer into a first region and a second region in a plan view; forming a first electrode on the upper semiconductor layer in the first region; forming a second electrode on the upper semiconductor layer in the second region; forming an insulating film that exposes at least a part of the first electrode and covers the second electrode; selectively proceeding etching only in the first region by photoelectrochemical etching using excitation light having an energy greater than or equal to the band gap energy of the upper semiconductor layer and less than or equal to the band gap energy of the intermediate semiconductor layer, thereby removing the upper semiconductor layer at the position where the first gate electrode is to be formed and exposing the intermediate semiconductor layer; and forming the first gate electrode on the exposed intermediate semiconductor layer in the first region. Preferably, the method for manufacturing a semiconductor device includes the step of forming a second gate electrode on the upper semiconductor layer in the second region.

[0012] In this disclosure, the intermediate semiconductor layer functions as an etching stopper layer in PEC etching. The etching depth is controlled by the thickness of the upper semiconductor layer removed by PEC etching. Therefore, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress variations in etching depth in PEC etching.

[0013] This figure illustrates the recess gate structure of a conventional semiconductor device relating to a comparative example of this disclosure. This figure illustrates conventional PEC etching of a GaN-based semiconductor layer relating to a comparative example of this disclosure. This is a cross-sectional view showing a semiconductor device relating to Embodiment 1 of this disclosure. This is a cross-sectional view showing a method for manufacturing a semiconductor device relating to Embodiment 1 of this disclosure. This is a cross-sectional view showing a semiconductor device relating to Embodiment 1 of this disclosure. This is a cross-sectional view showing a semiconductor device relating to Embodiment 3 of this disclosure. This is a cross-sectional view showing a method for manufacturing

[0014] Before describing the present disclosure, we will explain the comparative examples. The same reference numerals are used for components that are common to or correspond to the present disclosure. Here, we will mainly explain the differences from the present disclosure, and the explanation of components that are common to or correspond to the present disclosure will be given in the description of the present disclosure.

[0015] <Comparative Example> Figure 1 is a diagram illustrating a recess gate structure 5 of a conventional semiconductor device 500 according to a comparative example of the present disclosure. In the conventional semiconductor device 500, a buffer layer 2, a channel layer 3, and a barrier layer 40 which is a GaN-based semiconductor layer are stacked in order on the upper surface of the substrate 1. A recess gate structure 5 is formed on the surface of the barrier layer 40. Within the recess gate structure 5, a T-shaped gate electrode 6 is formed on the barrier layer 40.

[0016] Generally, to improve the high-frequency characteristics of a transistor, it is necessary to shorten the gate length (Lg) of the gate electrode 6 to reduce the electron channel travel time. However, simply shortening the gate length (Lg) causes so-called short-channel effects, such as a decrease in transconductance (gm), an increase in drain conductance (gd), and a decrease in threshold voltage (Vth). To prevent the occurrence of short-channel effects, it is necessary not only to shorten the gate length (Lg) but also to reduce the thickness (d) of the barrier layer 40 under the gate electrode 6 to lower the aspect ratio (Lg / d).

[0017] However, in GaN-based transistors, 2DEG is induced by spontaneous polarization and piezoelectric polarization in the barrier layer 40. Therefore, if the barrier layer 40 is thinned, the concentration of 2DEG decreases, and the power density of the transistor decreases. In other words, in GaN-based transistors, there is a trade-off between high frequency and high power density.

[0018] As shown in Figure 1, in the recessed gate structure 5, the barrier layer 40 is thinned only near the gate electrode 6. This makes it possible to lower the aspect ratio (Lg / d). Also, in the recessed gate structure 5, since only a portion of the barrier layer 40 is excavated, the overall thickness of the barrier layer 40 can be secured to maintain a concentration of 2DEG. Therefore, GaN-based transistors with the recessed gate structure 5 can achieve both high-frequency operation and high power density.

[0019] Because GaN-based semiconductor layers are chemically stable, recess gate structures 5, as shown in Figure 1, are generally formed by dry etching. However, applying dry etching to GaN-based semiconductor layers presents two challenges. The first challenge is the concern of damage to the GaN-based semiconductor layer due to the use of high-energy plasma, and the contamination of the GaN-based semiconductor layer with etching gas. The second challenge is the need to control conditions such as dry etching power and etching time in order to etch the GaN-based semiconductor layer to the desired depth.

[0020] Figure 2 illustrates a conventional PEC etching process for a GaN-based semiconductor layer according to a comparative example of this disclosure. Here, we will describe the case where the barrier layer 40 described in Figure 1 is PEC etched.

[0021] In conventional PEC etching, electron-hole pairs are generated in the barrier layer 40 by irradiating it with excitation light 7 with energy exceeding the band gap. The generated holes 9 have strong oxidizing power and oxidize the Ga contained in the barrier layer 40. Furthermore, the barrier layer 40 is deepened by removing the Ga oxide 16 on the surface of the barrier layer 40 by wet etching. This forms a recess gate structure 5 in the barrier layer 40.

[0022] On the other hand, electrons 8 generated by light irradiation pass through the 2DEG surface beneath the barrier layer 40 to the source-drain electrode (hereinafter referred to as SD electrode) 11 and are released into the wet etching solution. In particular, in wet etching using a solution capable of generating sulfuric acid radicals, the sulfuric acid radicals in the solution consume electrons 8, so electrons 8 can be spontaneously transferred to the solution without connecting the SD electrode 11 to an external circuit.

[0023] Since PEC etching is a wet etching process, damage to the barrier layer 40 and contamination of the barrier layer 40 with etching gas, which were concerns with dry etching, cannot occur. Therefore, the first problem with dry etching has already been solved by the conventional PEC etching process described in Figure 2.

[0024] However, conventional PEC etching requires precise control of conditions such as chemical concentration, etching time, and excitation light intensity to etch the barrier layer 40 to the desired depth. This is common to the second challenge of dry etching. In other words, conventional PEC etching cannot solve the second challenge. Methods that rely on condition control raise concerns about manufacturing variations in etching depth. Since the etching depth of the barrier layer 40 is related to the threshold voltage (Vth) of the transistor, there is a strong demand for a technology that can suppress variations in etching depth in PEC etching of GaN-based semiconductor layers.

[0025] Embodiments of the present disclosure will be described below with reference to the drawings. The same or corresponding components will be denoted by the same reference numerals, and repetition of the description may be omitted.

[0026] Embodiment 1 Figure 3 is a cross-sectional view showing a semiconductor device 100 according to Embodiment 1 of the present disclosure. A buffer layer 2, a channel layer 3, and a barrier layer 4 are sequentially stacked on the upper surface of the substrate 1. Here, we assume that the semiconductor device 100 is a high-frequency compatible GaN-HEMT and will explain the constituent materials of each layer, but if there are other applicable materials, they will be explained in addition.

[0027] While SiC is assumed for substrate 1, other materials such as Si, sapphire, or diamond substrates may also be used.

[0028] Buffer layer 2 is assumed to be GaN or AlGaN, but it may also be a single or multiple layers of a group III nitride semiconductor such as AlN, InGaN, or AlInGaN.

[0029] The channel layer 3 is assumed to be a single layer of GaN or AlGaN, but it may also be composed of a group III nitride semiconductor such as InGaN or AlInGaN.

[0030] The barrier layer 4 comprises a lower barrier layer 4-a, an intermediate barrier layer 4-c, and an upper barrier layer 4-b, each composed of AlGaN.

[0031] The lower barrier layer 4-a has a higher band gap energy than the upper barrier layer 4-b. In general, it is known that in AlGaN, the band gap energy increases as the Al composition ratio increases. That is, the Al composition ratio in the lower barrier layer 4-a is adjusted to be higher than the Al composition ratio in the upper barrier layer 4-b.

[0032] The intermediate barrier layer 4-c is thinner than the lower barrier layer 4-a and the upper barrier layer 4-b. The intermediate barrier layer 4-c has a higher band gap energy than the lower barrier layer 4-a. In other words, the Al composition ratio in the intermediate barrier layer 4-c is adjusted to be even higher than that in the lower barrier layer 4-a.

[0033] A heterobarrier is formed at the interface between the lower barrier layer 4-a and the channel layer 3. Because the lower barrier layer 4-a has a larger band gap than the channel layer 3, a 2DEG surface is formed on the channel layer 3 side near the interface.

[0034] One of the source and drain electrodes, the SD electrode 11, is formed on the upper barrier layer 4-b. An opening is provided in the upper barrier layer 4-b next to the SD electrode 11, exposing the intermediate barrier layer 4-c.

[0035] The gate electrode 6 is formed on the intermediate barrier layer 4-c, which is exposed through an opening in the upper barrier layer 4-b. In other words, in this embodiment, the opening in the upper barrier layer 4-b that exposes the intermediate barrier layer 4-c is the recessed gate structure 5. The material of the gate electrode 6 is, for example, Ni, TiN, Pt, Pd, Cu, Ta, TaN, W, WSi, Al, Au, Ti, etc.

[0036] Figures 4 and 5 are cross-sectional views showing a method for manufacturing a semiconductor device 100 according to Embodiment 1 of the present disclosure. First, as shown in Figure 4, an epitaxial wafer is formed on a substrate 1 by sequentially stacking a buffer layer 2, a channel layer 3, a lower barrier layer 4-a, an intermediate barrier layer 4-c, and an upper barrier layer 4-b. Furthermore, an SD electrode 11 is formed on the upper barrier layer 4-b.

[0037] Next, a resist 13 is applied to the upper barrier layer 4-b and the SD electrode 11. Furthermore, by patterning the resist 13, an opening is created in the resist 13 at the position where the recess gate structure 5 is to be formed, exposing the upper barrier layer 4-b.

[0038] Next, as shown in Figure 5, the upper barrier layer 4-b is PEC etched using the resist 13 as a mask. In the PEC etching of this embodiment, first, excitation light 7 with a band gap energy greater than or equal to the band gap energy of the upper barrier layer 4-b and less than or equal to the band gap energy of the intermediate barrier layer 4-c is irradiated from above the resist 13. The excitation light 7 that penetrates from the parts not masked by the resist 13 is absorbed by the upper barrier layer 4-b, generating electron-hole pairs, but is transmitted through the intermediate barrier layer 4-c without being absorbed.

[0039] Furthermore, wet etching is performed to remove the Ga oxide 16 generated on the surface of the upper barrier layer 4-b, thereby excavating the upper barrier layer 4-b. The electrons 8 generated in the upper barrier layer 4-b pass through the 2DEG surface below the lower barrier layer 4-a to the SD electrode 11 and are released into the wet etching solution. In this embodiment, it is preferable to use a chemical solution capable of generating sulfuric acid radicals in order to spontaneously move the electrons 8 into the chemical solution. However, known chemical solutions used in PEC etching can be used.

[0040] On the other hand, wet etching does not proceed in the intermediate barrier layer 4-c, where the excitation light 7 is not absorbed. In other words, the intermediate barrier layer 4-c acts as an etching stopper layer.

[0041] Furthermore, by forming the gate electrode 6 on the intermediate barrier layer 4-c exposed by wet etching, the semiconductor device 100 shown in Figure 3 can be obtained.

[0042] Thus, in this embodiment, the intermediate barrier layer 4-c functions as an etching stopper layer. The etching depth of the barrier layer 4 is controlled by the thickness of the upper barrier layer 4-b that is removed by PEC etching. Therefore, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress variations in etching depth during PEC etching.

[0043] For example, in conventional examples, a GaN layer is provided as a sacrificial layer on top of the barrier layer 40 shown in Figure 1, and a recess gate structure 5 is formed by PEC etching of the GaN layer. However, providing a thick GaN layer on top of the barrier layer 40 significantly increases the contact resistance of the SD electrode 11, resulting in a degradation of the characteristics of the GaN-based transistor. In addition, the generation of two-dimensional hole gas (2DHG) between the GaN layer provided as a sacrificial layer and the barrier layer 40 also degrades the characteristics. In contrast, in this disclosure, the recess gate structure 5 can be formed on the barrier layer 4 itself while suppressing variations in etching depth.

[0044] In addition, a structure in which the barrier layer 4 has a two-layer structure of an upper barrier layer 4-b and a lower barrier layer 4-a, and the lower barrier layer 4-a serves as an etching stopper layer is conceivable. In that case, it is necessary to increase the Al composition ratio of the lower barrier layer 4-a. However, it is considered that the Al composition ratio in the lower barrier layer 4-a affects the concentration of 2DEG immediately below the lower barrier layer 4-a, and as a result, the design freedom of the 2DEG concentration is lost. By sharing the role as an etching stopper layer with the intermediate barrier layer 4-c and the role of 2DEG generation with the lower barrier layer 4-a as in this embodiment, it is possible to suppress the variation in etching depth while ensuring the design freedom of the 2DEG concentration.

[0045] <Modification 1> Although the lower barrier layer 4-a is not very thick, it is considered that the Al composition ratio in the intermediate barrier layer 4-c also affects the 2DEG concentration. From the viewpoint of reducing the influence, it is desirable to make the thickness of the intermediate barrier layer 4-c thinner. More specifically, it is desirable that the intermediate barrier layer 4-c is thinner than the lower barrier layer 4-a and the upper barrier layer 4-b. However, the thickness of the intermediate barrier layer 4-c is not limited, and it does not necessarily have to be thinner than the lower barrier layer 4-a and the upper barrier layer 4-b.

[0046] <Modification 2> The barrier layer 4 is not limited to AlGaN, and may be composed of a group III nitride semiconductor such as AlInGaN, for example. Also in this case, the bandgap energy can be adjusted by adjusting the composition of Al, for example. This is common to all the following embodiments.

[0047] <Modification 3> In FIGS. 4 and 5, it was described that the SD electrode 11 is formed on the upper barrier layer 4-b. Also in PEC etching, it was described that the electrons 8 are released from the SD electrode 11 into the chemical solution. However, the electrode formed to release the electrons 8 into the chemical solution does not necessarily have to be the SD electrode 11. For example, an electrode that can be removed after PEC etching may be formed. This is common to all the following embodiments.

[0048] Embodiment 2 Since the cross-sectional view of the semiconductor device 100 in this embodiment is the same as FIG. 3 in Embodiment 1, the drawing is omitted. Hereinafter, the points of change from Embodiment 1 will be described.

[0049] In this embodiment, the bandgap energy of the intermediate barrier layer 4-c in Embodiment 1 gradually increases from top to bottom of the intermediate barrier layer 4-c. That is, the Al composition ratio in the intermediate barrier layer 4-c gradually increases from top to bottom of the intermediate barrier layer 4-c. Note that it should be noted that the magnitude relationship of the bandgap energies in the lower barrier layer 4-a, the intermediate barrier layer 4-c, and the upper barrier layer 4-b is the same as in Embodiment 1.

[0050] In this embodiment, by selecting the wavelength of the excitation light 7 in PEC etching, it becomes possible to adjust the etching depth of the intermediate barrier layer 4-c. Thereby, slight manufacturing variations in the thickness of the upper barrier layer 4-b can be absorbed in a subsequent process, and the depth of the recess gate structure 5 can be brought closer to a desired value. As a result, variations in the etching depth can be further suppressed compared to Embodiment 1. Further, by selecting the wavelength of the excitation light 7, it becomes possible to manufacture a plurality of semiconductor devices 100 having different designed threshold voltages from the same epitaxial wafer.

[0051] Embodiment 3 The semiconductor device 200 in this embodiment has first and second regions each operable as an independent semiconductor element formed on the same substrate 1. Hereinafter, the points of change from Embodiment 1 will be described.

[0052] FIG. 6 is a cross-sectional view showing the semiconductor device 200 according to Embodiment 3 of the present disclosure. A buffer layer 2, a channel layer 3, a lower barrier layer 4-a, an intermediate barrier layer 4-c, and an upper barrier layer 4-b are sequentially stacked on the upper surface of the substrate 1. Further, an insulating implantation region 14 penetrating from the upper barrier layer 4-b to the substrate 1 is formed. The insulating implantation region 14 separates from the upper barrier layer 4-b to the substrate 1 into a first region 10 and a second region 20.

[0053] A first SD electrode 11-1 and a first gate electrode 6-1 are formed in the first region 10. A second SD electrode 11-2 and a second gate electrode 6-2 are formed in the second region 20. The first region 10 and the second region 20 can each operate as independent semiconductor elements, and their leakage currents are contained by the insulating injection region 14.

[0054] An insulating film 15 is formed on the upper barrier layer 4-b and the insulating injection region 14. This insulating film 15 covers the side of the first SD electrode 11-1. This insulating film 15 also covers the top and side of the second SD electrode 11-2.

[0055] The first gate electrode 6-1 is formed on the intermediate barrier layer 4-c within an opening that penetrates the insulating film 15 and the upper barrier layer 4-b, exposing the intermediate barrier layer 4-c. On the other hand, the second gate electrode 6-2 is provided in the insulating film 15 and is formed on the upper barrier layer 4-b within an opening that exposes the upper barrier layer 4-b.

[0056] Thus, in the semiconductor device 100 of this embodiment, of the first gate electrode 6-1 and the second gate electrode 6-2 formed on the upper barrier layer 4-b, only the first gate electrode 6-1 is formed within the recessed gate structure 5.

[0057] Figures 7 and 8 are cross-sectional views showing a method for manufacturing a semiconductor device 200 according to Embodiment 3 of the present disclosure. First, as shown in Figure 7, an epitaxial wafer is formed on a substrate 1 by sequentially stacking a buffer layer 2, a channel layer 3, a lower barrier layer 4-a, an intermediate barrier layer 4-c, and an upper barrier layer 4-b. Furthermore, an insulating injection region 14 is formed that penetrates from the upper barrier layer 4-b to the substrate 1.

[0058] Furthermore, in the first region 10, which is one of the regions separated by the insulating injection region 14, the first SD electrode 11-1 is formed on the upper barrier layer 4-b. Next, in the second region 20, which is the other region separated by the insulating injection region 14, the second SD electrode 11-2 is formed on the upper barrier layer 4-b. Furthermore, an insulating film 15 is formed to cover the upper barrier layer 4-b, the insulating injection region 14, the first SD electrode 11-1, and the second SD electrode 11-2.

[0059] Furthermore, the insulating film 15 is processed to form openings for the first gate electrode 6-1 and the second gate electrode 6-2, exposing the upper barrier layer 4-b. Further processing of the insulating film 15 exposes the upper part of the first SD electrode 11-1.

[0060] Furthermore, a resist 13 is applied to the insulating film 15, the upper barrier layer 4-b exposed from the insulating film 15, and the first SD electrode 11-1 and the second SD electrode 11-2. Then, the resist 13 is removed from the openings in the insulating film 15 for the first gate electrode 6-1 and the second gate electrode 6-2 to expose the upper barrier layer 4-b.

[0061] Next, as shown in Figure 8, the upper barrier layer 4-b is PEC etched using the resist 13 as a mask. In this embodiment, excitation light 7 with a band gap energy greater than or equal to that of the upper barrier layer 4-b and less than or equal to that of the intermediate barrier layer 4-c is irradiated onto the resist 13.

[0062] In PEC etching, electrons 8 generated by the excitation light 7 are released from the SD electrode 11 into the chemical solution, where they are consumed, forming a circuit and allowing etching to proceed. If the SD electrode 11 is covered with an insulating film 15, electrons 8 are not released into the chemical solution, a circuit is not formed, and therefore etching does not proceed. Furthermore, electrons 8 generated in one of the first region 10 and the second region 20 are not allowed to penetrate the other by the insulating injection region 14, so the PEC etching in the first region 10 and the second region 20 proceeds independently.

[0063] In other words, in the first region 10, a portion of the first SD electrode 11-1 is exposed from the insulating film 15, so etching proceeds and the upper barrier layer 4-b is removed. On the other hand, in the second region 20, the second SD electrode 11-2 is covered by the insulating film 15, so etching does not proceed.

[0064] Furthermore, in the first region 10, a first gate electrode 6-1 is formed on the intermediate barrier layer 4-c exposed by wet etching. Also, in the second region 20, a second gate electrode 6-2 is formed on the upper barrier layer 4-b. This results in the semiconductor device 200 shown in Figure 6.

[0065] In this embodiment, at least a portion of the first SD electrode 11-1 is exposed from the insulating film 15, the second SD electrode 11-2 is covered with the insulating film 15, and then PEC etching is performed on the upper barrier layer 4-b. This makes it possible to remove the upper barrier layer 4-b only in the first region 10. As a result, of the first gate electrode 6-1 and the second gate electrode 6-2 formed on the upper barrier layer 4-b, only the first gate electrode 6-1 can be formed within the recessed gate structure 5. This makes it possible to provide multiple semiconductor elements with different threshold voltages (Vth) on the same substrate 1.

[0066] As described above, this disclosure provides a semiconductor device and a method for manufacturing a semiconductor device that can suppress variations in etching depth during PEC etching.

[0067] This disclosure is not limited to the embodiments described above, and various modifications can be made during implementation without departing from its essence. Furthermore, each embodiment and its modifications may be combined as appropriate, and the combined effects can be obtained in such cases.

[0068] <Correspondence with terms used in the claims> The lower barrier layer 4-a is referred to as the lower semiconductor layer in the claims. The upper barrier layer 4-b is referred to as the upper semiconductor layer in the claims. The intermediate barrier layer 4-c is referred to as the intermediate semiconductor layer in the claims.

[0069] 1: Substrate, 2: Buffer layer, 3: Channel layer, 4: Barrier layer, 4-a: Lower barrier layer, 4-b: Upper barrier layer, 4-c: Intermediate barrier layer, 5: Recessed gate structure, 6: Gate electrode, 6-1: First gate electrode, 6-2: Second gate electrode, 7: Excitation light, 8: Electron, 9: Hole, 10: First region, 11: SD electrode, 11-1: First SD electrode, 11-2: Second SD electrode, 13: Resist, 14: Insulation injection region, 15: Insulating film, 16: Ga oxide, 20: Second region, 40: Barrier layer, 100: Semiconductor device, 200: Semiconductor device, 500: Conventional semiconductor device

Claims

1. A semiconductor device comprising a substrate, a channel layer and a barrier layer sequentially laminated on the substrate, and a gate electrode, wherein the barrier layer has a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer, the lower semiconductor layer has a higher band gap energy than the upper semiconductor layer, the intermediate semiconductor layer has a higher band gap energy than the lower semiconductor layer, and the gate electrode is formed on the intermediate semiconductor layer exposed through an opening provided in the upper semiconductor layer.

2. A semiconductor device comprising: a substrate; a channel layer and a barrier layer sequentially laminated on the substrate; an insulating film formed on the barrier layer; an insulating injection region; a first gate electrode and a second gate electrode, wherein the barrier layer comprises a lower semiconductor layer; an intermediate semiconductor layer laminated on the lower semiconductor layer; and an upper semiconductor layer laminated on the intermediate semiconductor layer, the lower semiconductor layer having a higher bandgap energy than the upper semiconductor layer, the intermediate semiconductor layer having a higher bandgap energy than the lower semiconductor layer, the first gate electrode being formed on the intermediate semiconductor layer within an opening that penetrates the insulating film and the upper semiconductor layer and exposes the intermediate semiconductor layer, the second gate electrode being formed on the upper semiconductor layer within an opening provided in the insulating film and exposing the upper semiconductor layer, and the region including the first gate electrode and the region including the second gate electrode being separated by the insulating injection region that penetrates from the barrier layer to the substrate.

3. The semiconductor device according to claim 1 or 2, wherein the bandgap energy of the intermediate semiconductor layer gradually increases from top to bottom of the intermediate semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the lower semiconductor layer, the intermediate semiconductor layer, and the upper semiconductor layer are composed of the same group III nitride semiconductor, and their composition ratios are different.

5. A method for manufacturing a semiconductor device, comprising: a step of laminating a channel layer on a substrate; a step of laminating a barrier layer on the channel layer, the barrier layer having a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer; a step of removing the upper semiconductor layer at the position where the gate electrode is to be formed by photoelectrochemical etching using excitation light having an energy equal to or greater than the band gap energy of the upper semiconductor layer and equal to or less than the band gap energy of the intermediate semiconductor layer, thereby exposing the intermediate semiconductor layer; and a step of forming the gate electrode on the exposed intermediate semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of forming an electrode on the upper semiconductor layer for releasing electrons generated in the photoelectrochemical etching to the outside, prior to the photoelectrochemical etching step.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the electrode is a source electrode or a drain electrode.

8. A step of laminating a channel layer on a substrate; a step of laminating a barrier layer having a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer on the channel layer; a step of forming an insulating injection region penetrating from the barrier layer to the substrate, and separating the upper semiconductor layer into a first region and a second region in a plan view; a step of forming a first electrode on the upper semiconductor layer in the first region; a step of forming a second electrode on the upper semiconductor layer in the second region; a step of forming an insulating film that exposes at least a part of the first electrode and covers the second electrode; a step of selectively proceeding etching only in the first region by photoelectrochemical etching using excitation light having an energy greater than or equal to the band gap energy of the upper semiconductor layer and less than or equal to the band gap energy of the intermediate semiconductor layer, thereby removing the upper semiconductor layer at the position where the first gate electrode is to be formed and exposing the intermediate semiconductor layer; a step of forming the first gate electrode on the intermediate semiconductor layer exposed in the first region. A method for manufacturing a semiconductor device, comprising the step of forming a second gate electrode on the upper semiconductor layer in the second region.

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