Silicon carbide semiconductor device

Abstract

Provided is a silicon carbide semiconductor device comprising a silicon carbide substrate having a first principal surface, an active region, and a terminal region surrounding the active region in a plan view perpendicular to the first principal surface. The silicon carbide substrate includes: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions that have a second conductivity type different from the first conductivity type, that are positioned between the first principal surface and the first semiconductor region, that are in contact with the first semiconductor region, that extend along a first axis parallel to the first principal surface in the active region and the terminal region, and that have end surfaces intersecting the first axis; a plurality of third semiconductor regions that have the first conductivity type, that are positioned between the first principal surface and the first semiconductor region, that are in contact with the first semiconductor region, and that extend along the first axis in the active region and the terminal region; and a fourth semiconductor region that has the first conductivity type, that is positioned between the first principal surface and the first semiconductor region, that is in contact with the first semiconductor region, and that is in contact with the end surfaces of the second semiconductor regions. The second semiconductor regions and the third semiconductor regions are alternately arranged along a second axis parallel to the first principal surface and perpendicular to the first axis, and the fourth semiconductor region contains impurities of the first conductivity type at an effective concentration lower than that in the third semiconductor regions.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide semiconductor device.

[0002] This application claims priority based on Japanese Application No. 2024-221027 filed on December 17, 2024, and incorporates all the descriptions described in the said Japanese application.

[0003] Conventionally, a semiconductor device having a super junction structure has been disclosed.

[0004] Japanese Patent Application Laid-Open No. 2003-273355

[0005] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface, and in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region. The silicon carbide substrate has a first semiconductor region having a first conductivity type, a second conductivity type different from the first conductivity type, located between the first main surface and the first semiconductor region, contacting the first semiconductor region, extending along a first axis parallel to the first main surface within the active region and the termination region, and having end faces intersecting the first axis; a plurality of second semiconductor regions; a plurality of third semiconductor regions having the first conductivity type, located between the first main surface and the first semiconductor region, contacting the first semiconductor region, and extending along the first axis within the active region and the termination region; and a fourth semiconductor region having the first conductivity type, located between the first main surface and the first semiconductor region, contacting the first semiconductor region, and contacting the end faces of the second semiconductor regions. The second semiconductor regions and the third semiconductor regions are arranged alternately along a second axis parallel to the first main surface and perpendicular to the first axis, and the fourth semiconductor region contains impurities of the first conductivity type at an effective concentration lower than that of the third semiconductor region.

[0006] Figure 1 is a schematic diagram showing an overview of the silicon carbide substrate in a silicon carbide semiconductor device according to the first embodiment. Figure 2 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the active region of the silicon carbide semiconductor device according to the first embodiment. Figure 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to the first embodiment. Figure 4 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 5 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the first embodiment. Figure 6 is a cross-sectional view showing the configuration of the termination region of the silicon carbide semiconductor device according to the first embodiment. Figure 7 is a diagram (1) showing an example of the distribution of impurity concentration in the n-type region. Figure 8 is a diagram showing an example of the distribution of effective impurity concentration in the n-type region. Figure 9 is a diagram (2) showing an example of the distribution of impurity concentration in the n-type region. Figure 10 is a cross-sectional view (1) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 11 is a cross-sectional view (2) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 12 is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 13 is a cross-sectional view (part 4) showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. Figure 14 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment.

[0007] [Problems this disclosure aims to solve] In conventional semiconductor devices, further improvement in withstand voltage is difficult.

[0008] This disclosure aims to provide a silicon carbide semiconductor device that can improve voltage resistance.

[0009] [Effects of this disclosure] According to this disclosure, pressure resistance can be improved.

[0010] The implementation methods are described below.

[0011] [Description of Embodiments of the Disclosure] Embodiments of the Disclosure are first listed and described. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, in the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the silicon carbide semiconductor device. Also, from any point, the +Z direction may be referred to as upward, upper side, or up, and the -Z direction may be referred to as downward, lower side, or down.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and, in a plan view perpendicular to the first main surface, having an active region and a terminal region surrounding the active region, wherein the silicon carbide substrate comprises a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type different from the first conductivity type, located between the first main surface and the first semiconductor region, in contact with the first semiconductor region, extending along a first axis parallel to the first main surface within the active region and the terminal region, and having end faces intersecting the first axis, and having a first conductivity type and the first main surface and the first The semiconductor material comprises a plurality of third semiconductor regions located between the semiconductor region and the first semiconductor region, in contact with the first semiconductor region, and extending along the first axis within the active region and the terminal region; and a fourth semiconductor region having the first conductivity type, located between the first main surface and the first semiconductor region, in contact with the first semiconductor region, and in contact with the end face of the second semiconductor region, wherein the second semiconductor region and the third semiconductor region are alternately arranged along a second axis parallel to the first main surface and perpendicular to the first axis, and the fourth semiconductor region contains impurities of the first conductivity type at a lower effective concentration than the third semiconductor region.

[0013] A fourth semiconductor region having a first conductivity type is in contact with the end face of a second semiconductor region having a second conductivity type, and the fourth semiconductor region contains impurities of the first conductivity type at a lower effective concentration than the third semiconductor region, which extends along the first axis, just like the second semiconductor region. Therefore, compared to the case where the fourth semiconductor region contains impurities of the first conductivity type at the same effective concentration as the third semiconductor region, depletion near the end face of the second semiconductor region is promoted, and the electric field acting on the second semiconductor region is mitigated. Consequently, the breakdown voltage can be improved.

[0014] [2] In [1], the fourth semiconductor region may contain the second conductivity type impurity. In this case, the effective concentration of the first conductivity type impurity in the fourth semiconductor region is easier to make lower than the effective concentration of the first conductivity type impurity in the third semiconductor region.

[0015] [3] In [2], the fourth semiconductor region may have a peak concentration of the second conductivity type impurity at a position away from the first main surface. When channeling injection of the second conductivity type impurity is performed during the formation of the fourth semiconductor region, the fourth semiconductor region will have a peak concentration of the second conductivity type impurity at a position away from the first main surface.

[0016] [4] In any of [1] to [3], the minimum effective concentration of the first conductivity type impurity in the fourth semiconductor region may be lower than the minimum effective concentration of the first conductivity type impurity in the first semiconductor region. In this case, the electric field over the second semiconductor region is particularly easy to relax.

[0017] [5] In any of [1] to [4], the third semiconductor region has a fifth semiconductor region in contact with the fourth semiconductor region and a sixth semiconductor region in contact with the fifth semiconductor region, the fifth semiconductor region is located between the fourth semiconductor region and the sixth semiconductor region, and the fifth semiconductor region may contain the first conductivity type impurity at an effective concentration lower than that of the sixth semiconductor region and higher than that of the fourth semiconductor region. In this case, the change in the effective concentration of the first conductivity type impurity in the third semiconductor region is gradual, and the change in the electric field can be gradual.

[0018] [6] In any of [1] to [5], there may be an oxide film provided on the first main surface that overlaps with the entire fourth semiconductor region in a plan view perpendicular to the first main surface. In this case, the electric field applied to the fourth semiconductor region can be relaxed.

[0019] [7] In any of [1] to [5], there may be a silicon oxide film provided on the first main surface that overlaps with the entire fourth semiconductor region in a plan view perpendicular to the first main surface. In this case as well, the electric field applied to the fourth semiconductor region can be mitigated.

[0020] [Embodiments of the Disclosure] (First Embodiment) The first embodiment will be described below. The first embodiment relates to a so-called vertical MOS (metal oxide semiconductor) type field-effect transistor (FET) using silicon carbide. This MOS type FET is an example of a silicon carbide semiconductor device. Figure 1 is a schematic diagram showing an overview of the silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment. Figure 2 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the active region of the silicon carbide semiconductor device according to the first embodiment. Figure 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to the first embodiment. Figure 4 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the first embodiment. Figure 5 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the first embodiment. Figure 6 is a cross-sectional view showing the configuration of the termination region of the silicon carbide semiconductor device according to the first embodiment. Figure 2 corresponds to region II in Figure 1. Figure 3 corresponds to a cross-sectional view along the line III-III in Figure 2. Figure 4 corresponds to region IV in Figure 1. Figure 5 corresponds to a cross-sectional view along the line V-V in Figure 4. Figure 6 corresponds to a cross-sectional view along the line VI-VI in Figure 4. Figure 4 corresponds to a cross-sectional view along the line IV-IV in Figure 5. The plating film 86 is omitted in Figure 5.

[0021] As shown in Figures 1 to 6, the silicon carbide semiconductor device 100 according to the first embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0022] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The first main surface 1 is on the silicon carbide epitaxial layer 40, and the second main surface 2 is on the silicon carbide single crystal substrate 50. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are formed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type). Hereafter, a plan view perpendicular to the first principal plane 1 will simply be referred to as a plan view.

[0023] As shown in Figure 1, the silicon carbide substrate 10 has an active region 110 and an end region 120. The active region 110 has, for example, the shape of a rounded square in plan view. The active region 110 may have the shape of a rounded rectangle in plan view. The end region 120 surrounds the active region 110 in plan view. The end region 120 is provided around the active region 110 in plan view. The end region 120 has a first end region 121 that contacts the active region 110 in a direction parallel to the Y axis, a second end region 122 that contacts the active region 110 in a direction parallel to the X axis, and a third end region 123 that contacts the first end region 121 and the second end region 122. The first termination region 121 is provided on the +Y and -Y sides of the active region 110, the second termination region 122 is provided on the +X and -X sides of the active region 110, and the third termination region 123 is provided at the four corners of the silicon carbide substrate 10.

[0024] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less. The first main surface 1 may be the (0001) surface or a surface inclined by an off-angle of 8° or less in the off-direction.

[0025] The silicon carbide epitaxial layer 40 has an n-type region 19A, an n-type region 19B, an n-type region 15C, an n-type region 15D, an n-type region 15E, a body region 12, a source region 13, a p-type region 14 for superjunctions, a contact region 16, a junction termination extension (JTE) 17, and a contact region 18. The n-type region 19A has a first drift region 11A within the active region 110 and an n-type region 15A within the termination region 120. The n-type region 19B has a second drift region 11B within the active region 110 and an n-type region 15B within the termination region 120. The first main surface 1 is located in the source region 13, contact region 18, contact region 16, JTE 17, n-type region 15C, n-type region 15D, and n-type region 15E. n-type region 19A is an example of a first semiconductor region. n-type region 19B is an example of a third semiconductor region.

[0026] The contact region 16 has a first main surface 1. The contact region 16 is located within the active region 110. The contact region 16 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. In plan view, the contact region 16 has an annular shape. In this disclosure, annular includes single closed curve shapes other than annular or elliptical annular shapes, such as a rounded rectangle.

[0027] JTE17 has a first main surface 1. In a plan view, JTE17 is in contact with the outer edge of the contact region 16. In a plan view, the contact region 16 is located inside JTE17. JTE17 is located within the termination region 120. The boundary between the contact region 16 and JTE17 is the boundary between the active region 110 and the termination region 120. In a plan view, JTE17 is located inside the outer edge of the silicon carbide substrate 10. JTE17 contains p-type impurities such as aluminum (Al) at an effective concentration lower than that of the contact region 16 and has a p-type conductivity.

[0028] The source region 13 has a first main surface 1. In plan view, the source region 13 is located inside the contact region 16. The source region 13 contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0029] The body region 12 is located between the source region 13 and the second main surface 2. The body region 12 is in contact with the source region 13. The lower end surface of the source region 13 and the upper end surface of the body region 12 are in contact with each other. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity).

[0030] The n-type region 15C has a first main surface 1. In plan view, the n-type region 15C is outside the JTE 17. The n-type region 15C is in contact with the JTE 17. The n-type region 15C contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0031] The p-type region 14 is located in the active region 110 and the termination region 120. The p-type region 14 is located between the body region 12, the contact region 16, the JTE 17, the n-type region 15C and the second main surface 2. The p-type region 14 is in contact with the body region 12, the contact region 16, the JTE 17, and the n-type region 15C. The lower end surface of the body region 12, the lower end surface of the contact region 16, the lower end surface of the JTE 17, and the lower end surface of the n-type region 15C are in contact with the upper end surface of the p-type region 14. The p-type region 14 extends along the Y-axis. The p-type region 14 has an end face 20 within the termination region 120. Multiple p-type regions 14 are provided along the X-axis at regular intervals (first pitch P1). The p-type region 14 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The p-type region 14 is an example of a second semiconductor region. The Y-axis is an example of a first axis. The X-axis is an example of a second axis.

[0032] The second drift region 11B is located in the active region 110. The second drift region 11B is located between the body region 12 and the second main surface 2. The second drift region 11B is in contact with the body region 12. The lower end surface of the body region 12 and the upper end surface of the second drift region 11B are in contact with each other. The second drift region 11B is located between adjacent p-type regions 14 along the X-axis. The second drift region 11B is also in contact with the p-type regions 14. The second drift region 11B extends along the Y-axis. Multiple second drift regions 11B are provided along the X-axis at regular intervals (first pitch P1). The second drift region 11B contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The source region 13 and the second drift region 11B are separated from each other by the body region 12. The lower end surface of the second drift region 11B and the lower end surface of the p-type region 14 may or may not be flush.

[0033] The first drift region 11A is located between the second drift region 11B and the p-type region 14 and the second main surface 2. The first drift region 11A is in contact with the second drift region 11B and the p-type region 14. The lower end surface of the second drift region 11B and the lower end surface of the p-type region 14 are in contact with the upper end surface of the first drift region 11A. The first drift region 11A contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The first drift region 11A may be in contact with the silicon carbide single crystal substrate 50. The second drift region 11B contains n-type impurities at a higher concentration than the first drift region 11A.

[0034] The n-type region 15B is located in the terminal region 120. The n-type region 15B is located between the n-type region 15C and the second main surface 2. The n-type region 15B is in contact with the n-type region 15C. The lower end surface of the n-type region 15C and the upper end surface of the n-type region 15B are in contact with each other. The n-type region 15B is located between adjacent p-type regions 14 along the X-axis. The n-type region 15B is also in contact with the p-type region 14 and the second drift region 11B. The n-type region 15B extends along the Y-axis. Multiple n-type regions 15B are provided along the X-axis at regular intervals (first pitch P1). The n-type region 15B contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0035] The n-type region 15D is located in the terminal region 120. The n-type region 15D has a first main surface 1. The n-type region 15D extends along the X-axis. The n-type region 15D is in contact with each end face 20 of the p-type region 14. The n-type region 15D is also in contact with the n-type regions 15B and 15C. The n-type region 15D contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The n-type region 15D is an example of a fourth semiconductor region.

[0036] The n-type region 15E is located in the terminal region 120. The n-type region 15E has a first main surface 1. In plan view, the n-type regions 15D and 15C and the p-type region 14 are located inside the n-type region 15E. In plan view, the outer edge of the silicon carbide substrate 10 is located in the n-type region 15E. The n-type region 15E is in contact with the n-type regions 15D and 15C. The n-type region 15E is also in contact with the p-type region 14. The n-type region 15E contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0037] The n-type region 15A is located in the terminal region 120. The n-type region 15A is located between the n-type regions 15B, 15D, 15E, and p-type region 14 and the second main surface 2. The n-type region 15A is in contact with the n-type regions 15B, 15D, 15E, and p-type region 14. The lower end surfaces of the n-type region 15B, n-type region 15D, n-type region 15E, and p-type region 14 are in contact with the upper end surface of the n-type region 15A. The n-type region 15A is also in contact with the first drift region 11A. The n-type region 15A contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The n-type region 15A may be in contact with the silicon carbide single crystal substrate 50.

[0038] A buffer layer containing n-type impurities such as nitrogen (N) and having an n-type conductivity may be present between the first drift region 11A and the n-type region 15A and the silicon carbide single crystal substrate 50.

[0039] A gate trench 5 is located on the first main surface 1. The gate trench 5 comprises a side surface 3 that penetrates the source region 13 and the body region 12 and reaches the second drift region 11B, and a bottom surface 4 connected to the side surface 3. The gate trench 5 is defined by the side surface 3 and the bottom surface 4. The bottom surface 4 is located in the second drift region 11B. In plan view, the gate trench 5 overlaps with the second drift region 11B. The gate trench 5 extends along the Y-axis. Multiple gate trenches 5 are provided along the X-axis at regular intervals (first pitch P1). The p-type region 14 is separated from the gate trench 5. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ1 of the side surface 3 with respect to the virtual plane 30 including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. Side surface 3 has, for example, a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent electron mobility.

[0040] Along the Z-axis, there is a silicon carbide single crystal substrate 50, a second drift region 11B, and a first drift region 11A between the bottom surface 4 and the second main surface 2, and the conductivity type of the silicon carbide substrate 10 between the bottom surface 4 and the second main surface 2 is n-type.

[0041] The contact region 18 has the first main surface 1. The contact region 18 contacts the source region 13. The contact region 18 also contacts the body region 12. The contact region 18 contains p-type impurities such as aluminum (Al) and has a p-type conductivity type. For example, the contact region 18 is formed simultaneously with the contact region 16, is formed of the same material as the contact region 16, and has the same depth as the contact region 16. The contact region 18 may contact the p-type region 14. The contact region 18, the body region 12, and the p-type region 14 are electrically connected to each other. The contact region 18 is, for example, between adjacent gate trenches 5 along the X axis in a plan view. Between two adjacent gate trenches 5 along the X axis, the contact region 18 and the source region 13 may be alternately provided along the Y axis. Between two adjacent gate trenches 5 along the X axis, the contact region 18 may be intermittently provided along the Y axis.

[0042] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be between adjacent gate trenches 5 along the Y axis. In a plan view, the plurality of gate trenches 5 may be provided in an array.

[0043] The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contains, for example, silicon dioxide (SiO ２ 2). The gate insulating film 81 contacts the second drift region 11B at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the second drift region 11B at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0044] The gate electrode 82 sandwiches the gate insulating film 81 between itself and the body region 12. The gate electrode 82 is on the gate insulating film 81 and sandwiches the gate insulating film 81 between itself and the silicon carbide substrate 10. The gate electrode 82 includes, for example, polycrystalline silicon containing a conductive impurity. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A part of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view, the gate electrode 82 may overlap a plurality of gate trenches 5 arranged along the Y-axis.

[0045] There is also the gate insulating film 81 over the contact region 16, the JTE 17, the n-type region 15C, the n-type region 15D, and the n-type region 15E, and there is an electrode film 85 on the gate insulating film 81 above the contact region 16. For example, the electrode film 85 is formed simultaneously with the gate electrode 82 and is formed of the same material as the gate electrode 82.

[0046] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 contacts the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 contains, for example, silicon dioxide (SiO ２ ). The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface with a continuously changing curvature. The upper surface of the interlayer insulating film 83 may be a curved surface that protrudes in the +Z direction above the gate trench 5.

[0047] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals (first pitch P1) along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is positioned between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. The contact holes 90 reach the source region 13 and the contact region 18.

[0048] Above the contact region 16, an interlayer insulating film 83 is located on the gate insulating film 81 and the electrode film 85. Contact holes 91 reaching the electrode film 85 are formed in the interlayer insulating film 83, and contact holes 92 reaching the contact region 16 are formed in the interlayer insulating film 83 and the gate insulating film 81. The silicon carbide semiconductor device 100 has a gate runner 63 and a source runner 64. For example, the gate runner 63 and the source runner 64 are formed at the same time as the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. In plan view, the gate runner 63 is provided between the source electrode 60 and the source runner 64.

[0049] The laminate 89 of the gate insulating film 81 and the interlayer insulating film 83 is provided on the first main surface 1 and overlaps with the entire n-type region 15D in a plan view. The laminate 89 is an example of an oxide film and is also an example of a silicon oxide film.

[0050] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 that is in contact with the source region 13 and the contact region 18, and a source pad 62 that is in contact with the contact electrode 61. The contact electrode 61 includes, for example, nickel silicide (NiSi). The contact electrode 61 may also include titanium (Ti), aluminum (Al), and silicon (Si). The contact electrode 61 is ohmic-bonded to the source region 13 and the contact region 18.

[0051] The barrier metal film 84 covers the surface of the interlayer insulating film 83. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the contact electrode 61. The barrier metal film 84 contains, for example, titanium nitride (TiN).

[0052] The source pad 62 covers the surface of the barrier metal film 84 and the upper surface of the contact electrode 61. The source pad 62 is in contact with the barrier metal film 84 and the contact electrode 61. The barrier metal film 84 is located between the source pad 62 and the interlayer insulating film 83. The source pad 62 contains, for example, aluminum (Al). The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other.

[0053] The silicon carbide semiconductor device 100 further includes a silicon nitride film 87 and a polyimide film 88. The silicon nitride film 87 covers the upper and side surfaces of the interlayer insulating film 83, and the polyimide film 88 covers the upper and side surfaces of the silicon nitride film 87. The silicon nitride film 87 and the polyimide film 88 have openings that expose a portion of the source electrode 60, and a plating film 86 for the source is formed inside these openings. The silicon nitride film 87 and the polyimide film 88 also have openings (not shown) that expose a portion of a gate electrode (not shown) connected to the gate runner 63, and a plating film (not shown) for the gate is formed inside these openings.

[0054] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the first drift region 11A and the n-type region 15A. The drain electrode 70 includes, for example, nickel silicide (NiSi). The drain electrode 70 may also include titanium (Ti), aluminum (Al), and silicon (Si). The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 50.

[0055] The concentrations of impurities in n-type regions 15A, 15B, 15C, and 15D will be described. Figure 7 shows an example of the distribution of impurity concentrations in n-type regions 15D and 15A. Figure 8 shows an example of the distribution of effective impurity concentrations in n-type regions 15D and 15A. Figure 9 shows an example of the distribution of impurity concentrations in n-type regions 15C, 15B, and 15A. In this disclosure, the effective concentration of n-type (first conductivity type) impurities is the concentration obtained by subtracting the concentration of p-type (second conductivity type) impurities from the concentration of n-type impurities. The effective concentration can be measured, for example, using a scanning capacitance microscope (SCM). The effective concentration of impurities contained in each region is the average value of the effective concentrations of impurities contained in that region. Figures 7 and 8 show an example of the distribution along arrow 26 in Figure 5. Figure 9 shows an example of a distribution along arrow 27 in Figure 6.

[0056] As shown in Figure 7, the concentration of n-type impurities is constant within n-type region 15D and within n-type region 15A. The concentration of n-type impurities in n-type region 15D (A2) is higher than the concentration of n-type impurities in n-type region 15A (A1). Also, as shown in Figure 9, the concentration of n-type impurities is constant within n-type regions 15C and 15B. The concentration of n-type impurities in n-type regions 15C and 15B is equal to the concentration of n-type impurities in n-type region 15D (A2). That is, n-type regions 15D, 15C, and 15B contain n-type impurities at a higher concentration than n-type region 15A. Although not shown, the concentration of n-type impurities in the second drift region 11B is equal to the concentration of n-type impurities in n-type region 15B (A2), and the concentration of n-type impurities in the first drift region 11A is equal to the concentration of n-type impurities in n-type region 15A (A1).

[0057] As shown in Figure 7, the n-type region 15D contains p-type impurities. The n-type region 15D has a peak 29 of p-type impurity concentration located away from the first main surface 1, and the concentration of p-type impurities decreases as it approaches the second main surface 2. For example, the concentration of p-type impurities at peak 29 is higher than the concentration of n-type impurities in the n-type region 15A, and as shown in Figure 8, the minimum effective concentration of n-type impurities in the n-type region 15D is lower than the minimum effective concentration of n-type impurities in the n-type region 15A. Also, as shown in Figure 9, the n-type regions 15C and 15D do not contain p-type impurities. The n-type region 15A does not necessarily have to contain p-type impurities.

[0058] Next, a method for manufacturing the silicon carbide semiconductor device 100 will be described. Figures 10 to 13 are cross-sectional views showing a method for manufacturing the silicon carbide semiconductor device 100 according to the first embodiment.

[0059] First, as shown in Figure 10, a silicon carbide single crystal substrate 50 is prepared, and n-type semiconductor layers 31 and 32 are formed on the silicon carbide single crystal substrate 50. The n-type semiconductor layer 31 contains n-type impurities at the same concentration as the n-type region 19A, and the n-type semiconductor layer 32 contains n-type impurities at the same concentration as the n-type region 19B. The n-type semiconductor layer 31 has an n-type region 19A that includes a first drift region 11A and an n-type region 15A.

[0060] Next, as shown in Figure 11, a p-type region 14 is formed by ion implantation into the n-type semiconductor layer 32. In the ion implantation for forming the p-type region 14, channeling implantation of p-type impurities such as aluminum is performed.

[0061] Next, as shown in Figure 12, ion implantation is performed into the n-type semiconductor layer 32 to form the body region 12, source region 13 (see Figure 3), contact region 16, JTE 17, and contact region 18.

[0062] Next, as shown in Figure 13, an n-type region 15D is formed by ion implantation into the n-type semiconductor layer 32. In the ion implantation for forming the n-type region 15D, channeling implantation of p-type impurities such as aluminum is performed. When forming the n-type region 15D, p-type impurities are ion-implanted at a lower concentration than when forming the p-type region 14. The remaining portion of the n-type semiconductor layer 32 yields a second drift region 11B and n-type regions 15B, 15C, and 15E. The n-type region 15D may be formed before the formation of the body region 12, source region 13, contact region 16, JTE 17, and contact region 18.

[0063] Next, multiple gate trenches 5 are formed. Then, a gate insulating film 81, gate electrode 82, electrode film 85, interlayer insulating film 83, contact electrode 61, barrier metal film 84, source pad 62, silicon nitride film 87, polyimide film 88, and plating film 86 are formed (see Figures 3 and 5).

[0064] In this way, the silicon carbide semiconductor device 100 can be manufactured.

[0065] In the silicon carbide semiconductor device 100, as described above, the n-type region 15D is in contact with the end face 20 of the p-type region 14, and the n-type region 15D contains n-type impurities at a lower effective concentration than the n-type region 19B, which extends along the Y-axis, just like the p-type region 14. Therefore, compared to the case where the n-type region 15D contains n-type impurities at the same effective concentration as the n-type region 19B, depletion near the end face 20 of the p-type region 14 is promoted, and the electric field applied to the p-type region 14 is relaxed. Consequently, the breakdown voltage can be improved.

[0066] If the n-type region 15D contains p-type impurities, the effective concentration of the n-type impurities in the n-type region 15D tends to be lower than the effective concentration of the n-type impurities in the n-type region 19B. If channeling injection of p-type impurities is performed during the formation of the n-type region 15D, the n-type region 15D will have a peak 29 of p-type impurity concentration located away from the first main surface 1.

[0067] When the minimum effective concentration of n-type impurities in n-type region 15D is lower than the minimum effective concentration of n-type impurities in n-type region 15A, the electric field applied to p-type region 14 is particularly easy to relax.

[0068] When the laminated body 89 overlaps with the entire n-type region 15D in a plan view, the electric field acting on the n-type region 15D can be mitigated.

[0069] (Second Embodiment) The second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the configuration of the n-type region within the terminal region 120. Figure 14 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment.

[0070] As shown in Figure 14, in the silicon carbide semiconductor device 200 according to the second embodiment, the n-type region 15B is separated from the n-type region 15D, and the n-type region 19B has an n-type region 15F between the n-type region 15B and the n-type region 15D. The n-type region 15F is located in the terminal region 120. The n-type region 15F is in contact with the n-type region 15D, and the n-type region 15B is in contact with the n-type region 15F. The n-type region 15F is located between the n-type region 15D and the n-type region 15B. The n-type region 15F has a first main surface 1, just like the n-type region 15D. The n-type region 15F is located between adjacent p-type regions 14 along the X-axis, just like the n-type region 15B. Multiple n-type regions 15F are provided along the X-axis at regular intervals (first pitch P1). The n-type region 15F is also in contact with the n-type region 15C. The n-type region 15F contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity.

[0071] The concentration of n-type impurities in n-type region 15F is equal to the concentration of n-type impurities (A2) in n-type regions 15B, 15C, and 15D. n-type region 15F contains p-type impurities at a lower concentration than n-type region 15D. Like n-type region 15D, n-type region 15F has a peak in the concentration of p-type impurities at a position away from the first main surface 1, and the concentration of p-type impurities decreases as it approaches the second main surface 2. n-type region 15F contains n-type impurities at an effective concentration lower than n-type region 15B and higher than n-type region 15D. n-type region 15F is an example of a fifth semiconductor region, and n-type region 15B is an example of a sixth semiconductor region.

[0072] The n-type region 15F can be formed, for example, by channeling p-type impurities into the n-type semiconductor layer 32. When forming the n-type region 15F, p-type impurities are ion-implanted at a lower concentration than when forming the n-type region 15D.

[0073] The other components of the silicon carbide semiconductor device 200 are the same as those of the silicon carbide semiconductor device 100.

[0074] The silicon carbide semiconductor device 200 can achieve the same effect as the silicon carbide semiconductor device 100. Furthermore, since the n-type region 15F contains n-type impurities at an effective concentration lower than that of the n-type region 15B and higher than that of the n-type region 15D, the change in the effective concentration of n-type impurities within the n-type region 19B is more gradual than in the silicon carbide semiconductor device 100, and the change in the electric field can be made more gradual.

[0075] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0076] 1. First main surface 2. Second main surface 3. Side view 4. Bottom view 5. Gate trench 10. Silicon carbide substrate 11A. First drift region 11B. Second drift region 12. Body region 13. Source region 14. p-type region (second semiconductor region) 15A, 15C, 15E. n-type region 15B. n-type region (sixth semiconductor region) 15D. n-type region (fourth semiconductor region) 15F. n-type region (fifth semiconductor region) 16, 18. Contact region 17. Junction termination structure 19A. n-type region (first semiconductor region) 19B. n-type region (third semiconductor region) 20. Edge view 26, 27. Arrow 29. Peak 30. Virtual plane 31, 32. n-type semiconductor layer 40. Silicon carbide epitaxial layer 50. Silicon carbide single crystal substrate 60. Source electrode 61 Contact electrode 62 Source pad 63 Gate runner 64 Source runner 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode film 86 Plating film 87 Silicon nitride film 88 Polyimide film 89 Laminate (oxide film, silicon oxide film) 90, 91, 92 Contact hole 100, 200 Silicon carbide semiconductor device 110 Active region 120 Termination region 121 First termination region 122 Second termination region 123 Third termination region P1 First pitch θ1 Angle X X-axis (second axis) Y Y-axis (first axis) Z Z-axis

Claims

1. A silicon carbide substrate having a first main surface and, in a plan view perpendicular to the first main surface, having an active region and a terminal region surrounding the active region, wherein the silicon carbide substrate comprises: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type different from the first conductivity type, located between the first main surface and the first semiconductor region, in contact with the first semiconductor region, extending along a first axis parallel to the first main surface within the active region and the terminal region, and having end faces intersecting the first axis; a plurality of third semiconductor regions having the first conductivity type, located between the first main surface and the first semiconductor region, in contact with the first semiconductor region, and extending along a first axis within the active region and the terminal region; and a fourth semiconductor region having the first conductivity type, located between the first main surface and the first semiconductor region, in contact with the first semiconductor region, and in contact with the end faces of the second semiconductor regions. The silicon carbide semiconductor device is characterized in that the second semiconductor region and the third semiconductor region are alternately arranged along a second axis parallel to the first main plane and perpendicular to the first axis, and the fourth semiconductor region contains impurities of the first conductivity type at a lower effective concentration than the third semiconductor region.

2. The silicon carbide semiconductor device according to claim 1, wherein the fourth semiconductor region contains an impurity of the second conductivity type.

3. The silicon carbide semiconductor device according to claim 2, wherein the fourth semiconductor region has a peak concentration of the second conductivity type impurity at a position away from the first main surface.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the minimum effective concentration of the first conductivity type impurity in the fourth semiconductor region is lower than the minimum effective concentration of the first conductivity type impurity in the first semiconductor region.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the third semiconductor region comprises a fifth semiconductor region in contact with the fourth semiconductor region and a sixth semiconductor region in contact with the fifth semiconductor region, the fifth semiconductor region is located between the fourth semiconductor region and the sixth semiconductor region, and the fifth semiconductor region contains the first conductivity type impurity at an effective concentration lower than that of the sixth semiconductor region and higher than that of the fourth semiconductor region.

6. A silicon carbide semiconductor device according to any one of claims 1 to 5, comprising an oxide film provided on the first main surface and overlapping the entire fourth semiconductor region in a plan view perpendicular to the first main surface.

7. A silicon carbide semiconductor device according to any one of claims 1 to 5, comprising a silicon oxide film provided on the first main surface and overlapping the entire fourth semiconductor region in a plan view perpendicular to the first main surface.

Images