Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device comprising: a drift region of a first conductivity type provided to a semiconductor substrate equipped with a front surface and a rear surface; a buffer region of the first conductivity type; and a lifetime control region provided in the buffer region. The buffer region may have a first peak of a carrier concentration, a second peak of the carrier concentration, and a valley peak of the carrier concentration provided between the first peak and the second peak in the depth direction of the semiconductor substrate. The lifetime control region may include a lifetime killer and the valley peak. A concentration gradient of the carrier concentration distribution may change critically between a depth position at which the carrier concentration of the valley peak exhibits a minimum value and the depth position of the second peak. A depth position at which the lifetime killer concentration exhibits a maximum peak concentration in the lifetime control region may be located closer to the front surface side than the depth position at which the concentration gradient of the carrier concentration distribution changes critically.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 describes a semiconductor device having a lifetime control region in the buffer region. [Prior Art Documents] [Patent Documents] Patent Document 1 International Publication No. 2022 / 265061 Patent Document 2 International Publication No. 2022 / 107728 General disclosure

[0003] (Problem to be solved) It is preferable to improve the electrical characteristics of semiconductor devices. (Means for solving the problem)

[0004] In a first embodiment of the present invention, a semiconductor device is provided comprising: a drift region of a first conductivity type provided on a semiconductor substrate having a front surface and a back surface; a buffer region of a first conductivity type provided on the back surface side of the semiconductor substrate more than the drift region; and a lifetime control region provided in the buffer region. The buffer region may have a first peak of carrier concentration, a second peak of carrier concentration provided in the depth direction of the semiconductor substrate closer to the front surface of the semiconductor substrate than the first peak, and a trough peak of carrier concentration provided between the first peak and the second peak in the depth direction of the semiconductor substrate. The lifetime control region may have a lifetime killer and the trough peak. The concentration gradient of the carrier concentration distribution may change critically between the depth position where the carrier concentration of the trough peak is at its minimum and the depth position of the second peak. The depth position of the peak concentration where the lifetime killer concentration of the lifetime control region is at its maximum may be located on the front surface side of the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0005] In the above-described semiconductor device, the absolute value of the concentration gradient of the carrier concentration distribution at the depth position where the lifetime killer concentration is maximum may be smaller than the absolute value of the concentration gradient of the carrier concentration distribution on the back side than the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0006] In any of the above semiconductor devices, the absolute value of the concentration gradient of the carrier concentration distribution on the front side relative to the depth position where the concentration gradient of the carrier concentration distribution changes critically may be smaller than the absolute value of the concentration gradient of the carrier concentration distribution on the back side relative to the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0007] In any of the above semiconductor devices, the ratio of the absolute value of the concentration gradient of the carrier concentration distribution on the front side of the device to the absolute value of the concentration gradient of the carrier concentration distribution on the back side of the device to the absolute value of the concentration gradient of the carrier concentration distribution on the back side of the device to the depth position where the concentration gradient of the carrier concentration distribution changes critically may be greater than 1 and less than or equal to 5.

[0008] In any of the above semiconductor devices, the carrier concentration may continuously increase monotonically from the depth position where the carrier concentration distribution of the valley peak shows its minimum value to the depth position where the carrier concentration distribution of the first peak shows its maximum value.

[0009] In any of the above semiconductor devices, the width of the valley peak may be 0.1 μm or more and 2 μm or less in the depth direction of the semiconductor substrate.

[0010] In any of the above semiconductor devices, the width of the valley peak may be 1 μm or less in the depth direction of the semiconductor substrate.

[0011] In any of the above semiconductor devices, the lower limit of the carrier concentration in the valley peak may be greater than the carrier concentration in the drift region.

[0012] In any of the semiconductor devices described above, the first peak may be the peak among the plurality of peaks in the buffer region that is closest to the back surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0013] In any of the semiconductor devices described above, the buffer region may have a third carrier concentration peak located closer to the surface of the semiconductor substrate than the second peak in the depth direction of the semiconductor substrate. The lower limit of the carrier concentration of the valley peak may be greater than the minimum carrier concentration between the second peak and the third peak.

[0014] In any of the semiconductor devices described above, the peak position of the valley peak may be closer to the peak position of the first peak than to the peak position of the second peak in the depth direction of the semiconductor substrate.

[0015] In any of the semiconductor devices described above, the distance between the peak position of the valley peak and the peak position of the first peak in the depth direction of the semiconductor substrate may be less than 1 / 4 times the distance between the peak position of the first peak and the peak position of the second peak.

[0016] In any of the semiconductor devices described above, the peak position of the valley peak may be located at a distance of 0.1 μm or more from the peak position of the second peak toward the back surface in the depth direction of the semiconductor substrate.

[0017] In any of the semiconductor devices described above, the peak position of the valley peak may be located at a distance of 0.1 μm or more from the peak position of the first peak toward the front surface side in the depth direction of the semiconductor substrate.

[0018] In any of the semiconductor devices described above, the valley peak may be provided at a depth of 0.5 μm or more and 2 μm or less from the back surface of the semiconductor substrate.

[0019] In any of the above semiconductor devices, the lifetime control region may be closer to the first peak than to the second peak in the depth direction of the semiconductor substrate.

[0020] In any of the semiconductor devices described above, the depth position of the full width at half maximum in the lifetime control region does not need to overlap with the depth position of the full width at half maximum of the first peak in the depth direction of the semiconductor substrate.

[0021] In any of the above semiconductor devices, the depth position of the half-value width of the lifetime control region may not overlap with the depth position of the half-value width of the second peak in the depth direction of the semiconductor substrate.

[0022] In any of the above semiconductor devices, the semiconductor substrate may be an MCZ substrate.

[0023] In any of the above semiconductor devices, the oxygen chemical concentration in the drift region may be 1E17 cm

[0029] , , , －３ , , , －３ , －３ , －３ , , －３ ,

[0027] , －３ ,

[0028] ,

[0026] , －３ , －３ to 4.5E17 cm －３ or less.

[0024] In any of the above semiconductor devices, the carbon chemical concentration in the drift region may be 1E13 cm －３ or more and 1E14 cm －３ or less.

[0025] In any of the above semiconductor devices, the peak concentration of the lifetime killer concentration in the lifetime control region may be 6E16 cm －３ or more and 4E17 cm －３ or less.

[0026] In any of the above semiconductor devices, the carbon chemical concentration in the drift region may be 1E14 cm －３ or more and 5E15 cm －３ or less.

[0027] In any of the above semiconductor devices, the peak concentration of the lifetime killer concentration in the lifetime control region may be 1E16 cm －３ or more and 6E16 cm －３ or less.

[0028] In any of the above semiconductor devices, the carbon chemical concentration in the drift region may be 5E15 cm －３ or more and 1E16 cm －３ or less.

[0029] In any of the above semiconductor devices, the peak concentration of the lifetime killer concentration in the lifetime control region may be 1E15 cm －３ or more and 1E16 cm －３ or less.

[0030] Any of the above semiconductor devices may include a transistor section and a diode section provided on the semiconductor substrate. The transistor section may have a collector region of a second conductivity type provided on the back surface of the semiconductor substrate. The buffer region may be provided on the transistor section and the diode section.

[0031] A second embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a drift region of a first conductivity type on a semiconductor substrate; providing a buffer region of the first conductivity type on the back side of the semiconductor substrate more than the drift region; and providing a lifetime control region in the buffer region. The buffer region may have a first peak of carrier concentration, a second peak of carrier concentration provided in the depth direction of the semiconductor substrate closer to the front surface of the semiconductor substrate than the first peak, and a trough peak of carrier concentration provided between the first peak and the second peak in the depth direction of the semiconductor substrate. The lifetime control region may have a lifetime killer and the trough peak. The concentration gradient of the carrier concentration distribution may change critically between the depth position where the carrier concentration of the trough peak is at its minimum and the depth position of the second peak. The depth position of the peak concentration where the lifetime killer concentration of the lifetime control region is at its maximum may be located on the front surface side of the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0032] In the above-described method for manufacturing the semiconductor device, the acceleration energy for forming the lifetime control region may be 270 keV or more and 900 keV or less.

[0033] In any of the above methods for manufacturing a semiconductor device, the carbon chemical concentration in the drift region is 1E13cm －３ Above, 1E14cm －３ It may be less than 1E12cm. The dose amount in the lifetime control region is 1E12cm －２ Above 6E12cm －２ The following is acceptable:

[0034] In any of the above methods for manufacturing a semiconductor device, the carbon chemical concentration in the drift region is 1E14cm². －３ Above 5E15cm －３ It may be less than 2E11cm. The dose amount in the lifetime control region is 2E11cm －２ Above 1E12cm －２ It can be less than [amount].

[0035] In any of the above methods for manufacturing a semiconductor device, the carbon chemical concentration in the drift region is 5E15cm －３ Above, 1E16cm －３ The following may apply: The dose amount in the lifetime control region is 2E10cm －２ Above, 2E11cm －２ It can be less than [amount].

[0036] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention.

[0037] An example of a top view of the semiconductor device 100 is shown. An example of the a-a' cross section in Figure 1A is shown. An example of the carrier concentration distribution in the collector region 22, buffer region 20, and drift region 18 is shown. This is an enlarged view of the carrier concentration distribution near the valley peak 65. This shows the carrier concentration distribution of a modified buffer region 20. This shows the carrier concentration distribution of a modified buffer region 20. The doping concentration distribution of the lifetime control region 150 is superimposed on the carrier concentration distribution in Figure 3A. This shows a top view of a modified semiconductor device 100. This shows the b-b' cross section of a modified semiconductor device 100. This is a flowchart of an example of the manufacturing process of the semiconductor device 100. This shows the relationship between switching loss and steady-state loss. This shows the range of variation of switching loss and steady-state loss with respect to changes in carbon chemical concentration. This shows an example of a lifetime killer concentration distribution. This is a schematic correspondence diagram of SR carrier concentration, carrier mobility μ, and normalized recombination center concentration Rn.

[0038] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0039] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0040] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0041] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0042] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0043] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0044] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N Ｄ , the acceptor concentration is N Ａ Therefore, the net doping concentration at any given position is N Ｄ -N Ａ In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0045] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as an electron-supplying donor. In this specification, VOH defects may be referred to as hydrogen donors.

[0046] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type.

[0047] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) method. Alternatively, the carrier concentration measured by broadening resistance (SR) method may be used as the net doping concentration. The carrier concentration measured by CV or SR method may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0048] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0049] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0050] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is also a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0051] Figure 1A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 is a semiconductor chip equipped with a transistor section 70.

[0052] The transistor section 70 is a region obtained by projecting a collector region 22, which is provided on the back surface of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes transistors such as IGBTs.

[0053] Figure 1A shows the region around the chip end, which is the edge side of the semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0054] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by any of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0055] The semiconductor substrate 10 may be an MCZ substrate. An MCZ substrate is a substrate manufactured using the MCZ method. The semiconductor substrate 10 may contain arbitrary carbon and oxygen chemical concentrations. The carbon chemical concentration of the semiconductor substrate 10 will be described later. The carbon and oxygen in the semiconductor substrate 10 may be introduced during the manufacturing of the ingot. The oxygen chemical concentration of the semiconductor substrate 10 is 1E17cm². －３ Above, 4.5E17cm －３ The following may apply: The oxygen chemical concentration of the semiconductor substrate 10 may be the same as the oxygen chemical concentration of the drift region 18. That is, the oxygen chemical concentration of the drift region 18, as described later, may be 1E17cm. －３ Above, 4.5E17cm －３ The following may be the case. For example, the oxygen chemical concentration in a substrate manufactured by the FZ method is 1E15cm². －３ Above, 5E16cm －３ The following applies:

[0056] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 in this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0057] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the gate trench 40 and well region 17.

[0058] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Each electrode may further have a plug portion formed by embedding tungsten or the like in contact with the barrier metal and aluminum or the like within the contact hole.

[0059] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0060] The contact hole 55 connects the gate metal layer 50 to the gate conductive part within the transistor section 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0061] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0062] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0063] The gate trenches 40 are arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The gate trenches 40 in this example may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the alignment direction, and a connecting portion 43 that connects the two extended portions 41.

[0064] Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0065] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example, like the gate trench portion 40, may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31.

[0066] The transistor section 70 in this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extended section 31 between two extended sections 41. Also, the transistor section 70 has two extended sections 31 adjacent to the gate trench section 40.

[0067] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1:1 or 2:4. Also, the transistor portion 70 may have all trench portions as gate trench portions 40 and not have dummy trench portions 30.

[0068] The well region 17 is a region of a second conductivity type located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, of the P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0069] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the stretching direction.

[0070] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0071] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0072] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0073] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0074] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0075] The contact region 15 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0076] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0077] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0078] The buffer region 20 is a first conductivity type region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is greater than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second conductivity type.

[0079] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+. The doping concentration of the collector region 22 is 1.0E17cm². －３ The above is 1.0E19cm －３ The following is acceptable:

[0080] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal.

[0081] The base region 14 is a second conductive region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0082] The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0083] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N+ type. However, the storage region 16 does not necessarily have to be provided.

[0084] Furthermore, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is greater than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1.0E12cm －２ Above, 1.0E13cm －２ The following may be the case. Also, the dose of ion implantation in the accumulation region 16 is 3.0E12cm －２ The above is 6.0E12cm －２ The following is also possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced. Note that E means a power of 10, for example 1.0E12cm －２is 1.0 × 10 １２ cm －２ It means...

[0085] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to cases where the doping region is formed before the trenches are formed. Cases where doping regions are formed between trenches after the trenches are formed are also included in cases where the trenches penetrate a doping region.

[0086] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The upper part of the gate trench portion 40 may be covered by an interlayer insulating film 38.

[0087] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The upper part of the dummy trench portion 30 may be covered by an interlayer insulating film 38.

[0089] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38.

[0090] The lifetime control region 150 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate 10. In one example, the lifetime control region 150 is formed by injecting helium into the semiconductor substrate 10. By providing the lifetime control region 150, the turn-off time can be reduced and the tail current suppressed, thereby reducing losses during switching.

[0091] A lifetime killer is a carrier recombination center. A lifetime killer may be a lattice defect. For example, a lifetime killer may be a vacancy, a double vacancy, a composite defect between these and an element constituting the semiconductor substrate 10, or a dislocation. A lifetime killer may also be a noble gas element such as helium or neon, or a metallic element such as platinum. A lifetime killer may also be a recombination center formed on the injection surface side of the semiconductor substrate 10 after hydrogen ions have been injected into the injection surface. Electron beams may be used to form lattice defects. The lifetime control region 150 is the region where a lifetime killer is formed. In the region where a lifetime killer is formed, the carrier mobility may decrease from the value in the crystalline state. For example, in silicon, the carrier mobility in the crystalline state is approximately 1450 (cm) for electrons at a temperature of 300 K. ２ / Vs), the hole is approximately 450 (cm ２ (Vs)

[0092] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may also be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the concentration of composite defects between these vacancies and the elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime killer concentration may also be the chemical concentration of noble gas elements such as helium and neon, or the chemical concentration of metallic elements such as platinum.

[0093] The lifetime control region 150 is provided on the back surface 23 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the lifetime control region 150 is provided in the buffer region 20. In this example, the lifetime control region 150 is provided on the entire surface of the semiconductor substrate 10 in the XY plane and may be formed without using a mask. The lifetime control region 150 may also be provided on a part of the semiconductor substrate 10 in the XY plane.

[0094] Furthermore, the lifetime control region 150 in this example is formed by ion implantation from the back surface 23 side. This avoids affecting the front surface 21 side of the semiconductor device 100. For example, the lifetime control region 150 is formed by irradiating helium ions from the back surface 23 side. Here, whether the lifetime control region 150 is formed by ion implantation from the front surface 21 side or from the back surface 23 side can be determined by obtaining the state of the front surface 21 side using the SR method or by measuring the leakage current.

[0095] Figure 2 shows an example of the carrier concentration distribution in the collector region 22, buffer region 20, and drift region 18. G100 shows the carrier concentration distribution of semiconductor device 100, and G500 shows the carrier concentration distribution of a comparative semiconductor device.

[0096] The buffer region 20 has multiple carrier concentration peaks. In this example, the buffer region 20 has four carrier concentration peaks: a first peak 61, a second peak 62, a third peak 63, and a fourth peak 64. The buffer region 20 may have two or three peaks, or five or more peaks. The lower end of the buffer region 20 may be the boundary between the collector region 22 and the first peak 61. The upper end of the buffer region 20 may be the boundary between the fourth peak 64 and the drift region 18. The thickness of the buffer region 20 in the depth direction may be 10 μm or more and 30 μm or less. Note that the position of each peak is the position where the carrier concentration shows a maximum value.

[0097] The first peak 61 is located on the front surface 21 side of the collector region 22. The first peak 61 is the peak among the multiple peaks of the buffer region 20 that is closest to the back surface 23 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The first peak 61 may be located at a depth of 0.5 μm or more and 2 μm or less from the back surface 23. The depth position of each peak in the buffer region 20 refers to the depth from the back surface 23 in the depth direction of the semiconductor substrate 10.

[0098] The first peak 61 may be the peak with the highest carrier concentration in the buffer region 20. Carrier peak concentration Cp of the first peak 61 １ It is 1.0E15cm －３ Above, 1.0E17cm －３ The following may be true: 1.0E16cm －３ The above is 5.0E16cm －３ The following may apply: For example, the carrier peak concentration Cp of the first peak 61. １ It is 2.0E16cm －３ The carrier peak concentration refers to the maximum value of the carrier concentration in the carrier concentration distribution. The dopant of the first peak 61 may be phosphorus, arsenic, or hydrogen. In this example, the dopant of the first peak 61 is phosphorus.

[0099] The second peak 62 is located in the depth direction of the semiconductor substrate 10, closer to the front surface 21 of the semiconductor substrate 10 than the first peak 61. The second peak 62 may be located at a depth of 2 μm or more and 7 μm or less from the back surface 23. Carrier peak concentration Cp of the second peak 62 ２ It is 1.0E15cm －３ The above is 2.0E16cm －３ The following may be used: 3.0E15cm －３ The above is 1.0E16cm －３ The following is acceptable:

[0100] The third peak 63 is located in the depth direction of the semiconductor substrate 10, closer to the front surface 21 of the semiconductor substrate 10 than the second peak 62. The third peak 63 may be located at a depth of 7 μm or more and 13 μm or less from the back surface 23. Carrier peak concentration Cp of the third peak 63 ３ This is the carrier peak concentration Cp of the first peak 61. １ It is fine if it is smaller than the second peak 62, and the carrier peak concentration Cp ２ It can be smaller than that.

[0101] The fourth peak 64 is located in the depth direction of the semiconductor substrate 10, closer to the front surface 21 of the semiconductor substrate 10 than the third peak 63. The fourth peak 64 may be located at a depth of 10% to 20% of the substrate thickness of the semiconductor substrate 10 from the back surface 23. Carrier peak concentration Cp of the fourth peak 64 ４ This is the carrier peak concentration Cp of the first peak 61. １ It is fine if it is smaller than the second peak 62, and the carrier peak concentration Cp ２ It can be smaller than that.

[0102] The valley peak 65 is located between the first peak 61 and the second peak 62 in the depth direction of the semiconductor substrate 10. The valley peak 65 may be located at a depth of 0.5 μm or more and 2 μm or less from the back surface 23 of the semiconductor substrate 10. The valley peak 65 will be described later.

[0103] Each peak in the buffer region 20 may be formed by the same dopant or by different dopants. The dopant for each peak in the buffer region 20 may be hydrogen. The first peak 61 may be formed by phosphorus ion implantation, and the other peaks may be formed by hydrogen ion implantation. That is, the dopant for the first peak 61 may be phosphorus, and the dopants for the other peaks may be hydrogen. The hydrogen ion may be a proton, a dutron, or a triton. In this example, the hydrogen ion is a proton.

[0104] First peak 61 carrier peak concentration Cp １ The carrier peak concentration Cp of the first peak 61 may be greater than the peak concentrations of the other peaks. １ This may be smaller than the carrier peak concentration in the collector region 22. Carrier peak concentration Cp of the first peak 61 １ The system may be configured to adjust the hole concentration or hole current injected from the collector region 22, the injection efficiency, etc., when the gate is on.

[0105] The carrier peak concentrations of peaks other than the first peak 61 in the buffer region 20 may decrease toward the front surface 21. Alternatively, the carrier peak concentration of the peak closest to the front surface 21 among the peaks other than the first peak 61 may be greater than or equal to the carrier peak concentration of the adjacent peak on the back surface 23 side of that peak. In this example, the peak closest to the front surface 21 is the fourth peak 64, and the peak adjacent to the back surface 23 side of the fourth peak 64 is the third peak 63. Carrier peak concentration Cp of the fourth peak 64 ４ This is the carrier peak concentration Cp of the third peak 63. ３ It can be smaller than, the same as, or larger than. In this example, the carrier peak concentration Cp of the fourth peak 64. ４ The third peak 63 is the carrier peak concentration Cp ３ Larger.

[0106] The depth position D150 indicates the depth position from the back surface 23 where the carrier concentration is at its minimum at the valley peak 65. The lifetime control region 150 is provided in the depth direction of the semiconductor substrate 10 between the first peak 61 and the second peak 62. This makes it easier to reduce the turn-off loss Eoff while suppressing the increase in leakage current. The lifetime control region 150 may be provided at a depth position of 1 μm or more and 3 μm or less from the back surface 23. The lifetime control region 150 may have one peak or multiple peaks in the lifetime killer concentration distribution. In this example, the lifetime killer concentration distribution of the lifetime control region 150 is a helium chemical concentration distribution with one peak.

[0107] The lifetime control region 150 is the region where lifetime killers are formed. In this example, the lifetime killer is helium represented by the helium chemical concentration 160. Furthermore, the lifetime killer in this example is a lattice defect such as a vacancy or dangling bond in the depth region where the valley peak 65 on the back surface 23 side is formed, which is deeper than the depth position of the helium chemical concentration 160, and these lattice defects are recombination centers. The end of the lifetime control region 150 on the front surface 21 side may be the end of the helium chemical concentration 160 on the front surface 21 side. The end of the lifetime control region 150 on the back surface 23 side may be the end of the valley peak 65 on the back surface 23 side.

[0108] The comparative semiconductor device does not have a valley peak 65 in the buffer region 20. The comparative semiconductor device has a lifetime control region peak at depth position D550. The comparative semiconductor device has a lower limit of carrier concentration between two peaks adjacent to the back surface 23, but does not need to have an inflection point on the front surface 21 side of the lower limit. The inflection point of carrier concentration will be described later. That is, the two peaks adjacent to the back surface 23 of the comparative semiconductor device may be connected. The comparative semiconductor device may have at least one of the carbon chemical concentration and oxygen chemical concentration of the semiconductor substrate 10 different from that of the semiconductor device 100. The comparative semiconductor device has a third peak 63 and a fourth peak 64 that are lower than those of the semiconductor device 100.

[0109] Here, if a lifetime control region 150 is formed in the buffer region 20, the carrier concentration in the buffer region 20 may decrease below the carrier concentration in the drift region 18. The valley peak 65 may be formed by adjusting the positional relationship between each peak in the buffer region 20 and the lifetime control region 150. For example, the valley peak 65 is formed by the effect of helium ion implantation to form the lifetime control region 150.

[0110] The lower limit Cv of the carrier concentration at trough peak 65 may be adjusted according to the position and concentration of each peak in the buffer region 20 and the lifetime control region 150. The lower limit Cv of the carrier concentration at trough peak 65 may be greater than the carrier concentration C18 in the drift region 18. However, the carrier concentration C18 in the drift region 18 may be less than the bulk donor concentration Db in the drift region 18.

[0111] Figure 3A is an enlarged view of the carrier concentration distribution near the valley peak 65. This figure shows the carrier concentration distribution from the back surface 23 of the semiconductor device 100 in Figure 2 at a depth of 0.5 μm to 5.5 μm. This figure shows the carrier concentrations of the first peak 61, the second peak 62, and the valley peak 65.

[0112] Distance L1 is the distance between the peak position of the first peak 61 and the depth position D150 where the carrier concentration of the trough peak 65 is at its minimum in the depth direction of the semiconductor substrate 10. That is, distance L1 is the difference between the depth position of the maximum carrier concentration of the first peak 61 and the depth position of the minimum carrier concentration of the trough peak 65. The peak position of the trough peak 65 may be 0.1 μm or more away from the peak position of the first peak 61 toward the front surface 21 in the depth direction of the semiconductor substrate 10. That is, distance L1 may be 0.1 μm or more. Distance L1 may be 0.2 μm or more, 0.3 μm or more, or 0.5 μm or more. Distance L1 may be 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0113] Distance L2 is the distance between the peak position of the second peak 62 and the peak position of the trough peak 65 in the depth direction of the semiconductor substrate 10. That is, distance L2 is the difference between the depth position of the maximum carrier concentration of the second peak 62 and the depth position of the minimum carrier concentration of the trough peak 65. The peak position D150 of the trough peak 65 may be 0.1 μm or more away from the peak position of the second peak 62 toward the back surface 23 side in the depth direction of the semiconductor substrate 10. That is, distance L2 may be 0.1 μm or more. Distance L2 may be 0.1 μm or more, 0.2 μm or more, 0.5 μm or more, 1.0 μm or more, 1.5 μm or more, or 2.0 μm or more. Distance L2 may be 10 μm or less, 7 μm or less, 5 μm or less, 4 μm or less, or 3 μm or less.

[0114] The distance L12 is the distance between the peak position of the first peak 61 and the peak position of the second peak 62 in the depth direction of the semiconductor substrate 10. That is, the distance L12 is the difference between the depth position of the maximum carrier concentration of the first peak 61 and the depth position of the maximum carrier concentration of the second peak 62.

[0115] Distance L1 may be the same as or different from distance L2. In this example, distance L1 is smaller than distance L2. That is, the peak position of the valley peak 65 may be closer to the peak position of the first peak 61 than to the peak position of the second peak 62 in the depth direction of the semiconductor substrate 10. The peak position of the valley peak 65 may be the position of the lower limit Cv of the valley peak 65. Distance L1 may be 1 / 2 times or less of distance L2, or 1 / 3 times or less. Distance L1 may be less than 1 / 4 times distance L12 in the depth direction of the semiconductor substrate 10. Distance L1 may be less than 1 / 4 times distance L12 and greater than 1 / 20 times distance L12 in the depth direction of the semiconductor substrate 10. Distance L1 may be greater than distance L2. That is, the valley peak 65 may be closer to the second peak 62 than to the first peak 61. Distance L1 may be 2 times or more of distance L2, or 3 times or more.

[0116] The lower limit Cv of the carrier concentration at trough peak 65 may be greater than the minimum value CL of the carrier concentration between the second peak 62 and the third peak 63. The lower limit Cv of the carrier concentration at trough peak 65 may be adjusted according to the position and concentration of the lifetime control region 150. The lower limit Cv of the carrier concentration at trough peak 65 can be adjusted according to the oxygen chemical concentration of the semiconductor substrate 10. That is, the degree of trough peak 65 drop can be adjusted by the oxygen chemical concentration of the semiconductor substrate 10. Increasing the oxygen chemical concentration makes it more difficult for the carrier concentration at the peak of trough peak 65 to decrease. Decreasing the oxygen chemical concentration makes it easier for the carrier concentration at the peak of trough peak 65 to decrease. The oxygen chemical concentration of the semiconductor substrate 10 or the drift region 18 is 1E17cm －３ Above, 4.5E17cm －３ The following is acceptable:

[0117] Between the depth position D150 where the carrier concentration of the valley peak 65 is at its minimum and the depth position of the second peak 62, the concentration gradient of the carrier concentration distribution may change critically. The depth position of the peak concentration where the lifetime killer concentration is at its maximum may be located closer to the front surface 21 than the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0118] The width L65 is the width of the valley peak 65 in the depth direction of the semiconductor substrate 10. The upper end of the valley peak 65 may be the inflection point Pi of the carrier concentration distribution. The upper end of the valley peak 65 refers to the end of the valley peak 65 on the front surface 21 side. The upper end of the valley peak 65 may be the position along the front surface 21 side from the peak of the valley peak 65 where the second derivative of the carrier concentration distribution changes from positive to negative. That is, at the inflection point Pi, the absolute value of the concentration gradient of the carrier concentration distribution of the valley peak 65 decreases critically toward the front surface 21 side. That is, at the inflection point Pi, the absolute value of the concentration gradient of the carrier concentration distribution of the valley peak 65 changes critically. Here, let C1 be the depth position from the back surface 23 of the inflection point Pi. Depth position C1 is the depth position where the concentration gradient of the carrier concentration distribution changes critically.

[0119] The lower end of the valley peak 65 may be located on the back surface 23 side of the peak of the valley peak 65, at a position where it has the same carrier concentration as the upper end of the valley peak 65. The lower end of the valley peak 65 refers to the end on the back surface 23 side of the valley peak 65. The upper end of the valley peak 65 may be closer to the first peak 61 than the midpoint of the distance L2.

[0120] The following describes how to calculate the concentration gradient of the carrier concentration distribution on the valley peak 65 side and the concentration gradient of the carrier concentration distribution on the second peak 62 side, using the inflection point Pi as the boundary.

[0121] Let S1 be the calculation region for the density gradient on the back side, and S2 be the calculation region for the density gradient on the front side. The calculation region S1 for the density gradient on the back side is on the front surface 21 side of the depth position D150 that shows the minimum value of the valley peak 65, and on the back surface 23 side of the depth position C1 of the inflection point Pi. The calculation region S2 for the density gradient on the front side is on the front surface 21 side of the depth position C1 of the inflection point Pi, and on the back surface 23 side of the depth position of the second peak.

[0122] The concentration gradient of the carrier concentration distribution is calculated by plotting the common logarithm of the carrier concentration on the vertical axis of the graph and the linear depth from the back surface on the horizontal axis. It can be calculated by dividing the absolute value of the common logarithmic difference of the carrier concentrations between two points by the absolute value of the difference in linear depth from the back surface. Alternatively, the least squares method can be used to calculate the gradient for multiple measurement points between the two points. In this example, the calculation region S1 for the back surface concentration gradient was set from 1.48 μm to 2.01 μm, and the calculation region S2 for the front surface concentration gradient was set from 2.27 μm to 3.34 μm.

[0123] The absolute value of the concentration gradient in the calculation region S1 of the back side concentration gradient is calculated using the following formula and is 7080 ( / cm). | log １０ (7.34 x 10 １４ [ / cm ３ ]) - log １０ (3.06 x 10 １４ [ / cm ３ ]) | / (2.01 x 10 －４ [cm]-1.48×10 －４ [cm]) When the least squares method was used to improve accuracy, the result was 7079 ( / cm).

[0124] The density gradient of the front-side calculation region S2 is calculated by the following formula and is 3740 ( / cm). |log １０ (2.41×10 １５ [ / cm ３ ]) - log １０ (9.62×10 １４ [ / cm ３ ]) | / (3.34×10 －４ [cm] - 2.27×10 －４ [cm]) When the least squares method is used, it becomes 3831 ( / cm). Using the least squares method can result in higher accuracy.

[0125] The ratio obtained by dividing the absolute value of the back-side density gradient by the absolute value of the front-side density gradient may be greater than 1.0, may be 1.5 or more, and may be 2.0 or more. The ratio obtained by dividing the absolute value of the back-side density gradient by the absolute value of the front-side density gradient may be 5.0 or less, may be 4.0 or less, and may be 3.0 or less. The ratio in this example is 1.8.

[0126] The absolute value of the density gradient of the carrier concentration distribution at the depth position of the peak density where the lifetime killer concentration shows the maximum may be smaller than the absolute value of the density gradient of the carrier concentration distribution on the back surface 23 side than the depth position C1 where the density gradient of the carrier concentration distribution critically changes.

[0127] The absolute value of the density gradient of the carrier concentration distribution on the front surface 21 side than the depth position C1 where the density gradient of the carrier concentration distribution critically changes may be smaller than the absolute value of the density gradient of the carrier concentration distribution on the back surface 23 side than the depth position C1 where the density gradient of the carrier concentration distribution critically changes.

[0128] From the depth position D150 where the carrier concentration distribution of the valley peak 65 shows the minimum value to the depth position where the carrier concentration distribution of the first peak 61 shows the maximum value, the carrier concentration may continuously increase monotonically.

[0129] In this example, the width L65 is greater than the distance L1, but may also be less than the distance L1. Also, in this example, the width L65 is less than the distance L2, but may also be greater than the distance L2. The width L65 may be 10% or more and 80% or less of the distance L12, or 10% or more and 50% or less. In this example, the width L65 is less than 50% of the distance L12. The width L65 may be 0.1 μm or more and 2 μm or less in the depth direction of the semiconductor substrate 10. The width L65 of the valley peak 65 may be 1 μm or less in the depth direction of the semiconductor substrate 10. By reducing the width L65, it becomes easier to reduce the influence of lesser than one of the carbon chemical concentration or oxygen chemical concentration of the semiconductor substrate 10.

[0130] In the lifetime control region 150, the helium represented by the helium chemical concentration 160 among the lifetime killers may be located on the front surface 21 side of the region represented by the valley peak 65. Furthermore, the valley peak 65 may continuously increase monotonically and connect to the first peak 65. By having at least one of these features, it is possible to distribute many recombination centers not only in terms of the depth position of helium, but also in the valley peak 65 on the back surface 23 side. As a result, the carrier concentration distribution of the second peak 62 is stabilized, and recombination centers can be promoted in locations close to the collector region 22 into which holes are injected. As a result, as shown in Figure 6A later, even if the carbon concentration of the semiconductor substrate varies, for example, the helium in the lifetime control region 150 is located on the front surface 21 side of the valley peak 65. This stabilizes the hole current injection efficiency due to the acceptor concentration distribution in the collector region 22 and the donor concentration distribution of the first peak 61, as well as the local transport efficiency of the hole current determined by the lifetime control region 150, thereby significantly reducing variations in electrical characteristics.

[0131] Figure 3B shows the carrier concentration distribution of a modified example of the buffer region 20. In this example, the peak position of the valley peak 65 is located closer to the front surface 21 than the peak position of the valley peak 65 in Figure 3A. In this example, the differences from the carrier concentration distribution in Figure 3A will be explained in particular.

[0132] The valley peak 65 has an inflection point Pi. In this example, the inflection point Pi is located deeper than 2.5 μm from the back surface 23. Thus, the upper end of the valley peak 65 may be closer to the second peak 62 than the midpoint of the distance L2. In this example, the lower limit Cv of the carrier concentration of the valley peak 65 is greater than the minimum value CL of the carrier concentration between the second peak 62 and the third peak 63, and greater than the bulk donor concentration Db of the drift region 18.

[0133] The width L65 may be 10% or more and 80% or less of the distance L12, or 10% or more and 50% or less. In this example, the width L65 is greater than 50% of the distance L12. In this example, the width L65 is 1 μm or more and 2 μm or less in the depth direction of the semiconductor substrate 10.

[0134] Figure 3C shows the carrier concentration distribution of a modified example of the buffer region 20. The valley peak 65 in this example is located on the back surface 23 side compared to the valley peak 65 in Figure 3A. In this example, the differences from the carrier concentration distribution in Figure 3A will be explained in particular.

[0135] The valley peak 65 has an inflection point Pi. In this example, the inflection point Pi is located shallower than 1.5 μm from the back surface 23. Thus, the upper end of the valley peak 65 may be closer to the first peak 61 than the midpoint of the distance L2. In this example, the lower limit Cv of the carrier concentration of the valley peak 65 is greater than the minimum value CL of the carrier concentration between the second peak 62 and the third peak 63, and greater than the bulk donor concentration Db of the drift region 18.

[0136] The width L65 may be 10% or more and 80% or less of the distance L12, or 10% or more and 50% or less. In this example, the width L65 is less than 30% of the distance L12. In this example, the width L65 is 0.1 μm or more and 1 μm or less in the depth direction of the semiconductor substrate 10. By narrowing the width L65 of the valley peak 65 in the semiconductor device 100 of this example, the influence of lesser than one of the carbon chemical concentration or oxygen chemical concentration of the semiconductor substrate 10 can be further reduced.

[0137] Figure 3D overlays the doping concentration distribution in the lifetime control region 150 onto the carrier concentration distribution in Figure 3A.

[0138] The lifetime control region 150 may be located closer to the first peak 61 than to the second peak 62 in the depth direction of the semiconductor substrate 10. The depth position D150 of the lifetime control region 150 may be 1 μm or more and 3 μm or less.

[0139] The lifetime control region 150 may be spaced apart from the first peak 61. The depth position of the full width at half maximum (FWHM) Wh5 of the lifetime control region 150 does not need to overlap with the depth position of the full width at half maximum (FWHM) Wh1 of the first peak 61 in the depth direction of the semiconductor substrate 10. In this example, the full width at half maximum (FWHM) Wh5 is the full width at half maximum (FWHM) of the lifetime control region 150. The full width at half maximum (FWHM) Wh1 may be the full width at half maximum (FWHM) of the first peak 61. The full width at half maximum (FWHM) Wh5 of the lifetime control region 150 may be the full width at half maximum of the concentration distribution of the helium chemical concentration 160.

[0140] The lifetime control region 150 may be spaced apart from the second peak 62. The depth position of the full width at half maximum (FWH5) of the lifetime control region 150 does not need to overlap with the depth position of the full width at half maximum (FWH2) of the second peak 62 in the depth direction of the semiconductor substrate 10. In this example, the full width at half maximum (FWHM) of the second peak 62 is Wh2.

[0141] By reducing the full width at half maximum (FWH5) of the lifetime control region 150, the influence on the peaks of the adjacent buffer region 20 can be reduced. Specifically, by further reducing the FWH5 of the lifetime control region 150, the disappearance of lattice defects in the lifetime control region 150 can be suppressed. In addition, by reducing the FWH5 of the lifetime control region 150, the influence of the carbon chemical concentration of the semiconductor substrate 10 can be more easily reduced. For example, the FWH5 of the lifetime control region 150 is between 0.1 μm and 0.5 μm.

[0142] The killer peak concentration Dp is the peak concentration of the lifetime killer concentration in the lifetime control region 150. The killer peak concentration Dp may be the peak concentration of the helium chemical concentration 160. The killer peak concentration Dp in the lifetime control region 150 is the carrier peak concentration Cp of the first peak 61. １It can be larger than this. The killer peak concentration Dp in the lifetime control region 150 is equal to the carrier peak concentration Cp of the first peak 61. １ It may be more than twice, more than five times, or more than ten times. In one example, the killer peak concentration Dp in the lifetime control region 150 is 3E15cm －３ Above, 1E17cm －３ The following is acceptable:

[0143] Figure 4A shows a modified top view of the semiconductor device 100. The semiconductor device 100 in this example comprises a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 in this example includes a boundary region 90 located at the boundary between the transistor section 70 and the diode section 80.

[0144] The diode section 80 is a region obtained by projecting a cathode region 82, which is provided on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is N+ type. The diode section 80 includes a diode such as a freewheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0145] The boundary region 90 is provided in the transistor section 70 and is adjacent to the diode section 80. The boundary region 90 has a contact region 15. In this example, the boundary region 90 does not have an emitter region 12. In one example, the trench portion of the boundary region 90 is a dummy trench portion 30. In this example, the boundary region 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30.

[0146] The contact holes 54 are located above the base region 14 in the diode section 80. The contact holes 54 are located above the contact region 15 in the boundary region 90. None of the contact holes 54 are located above the well regions 17 located at both ends in the Y-axis direction.

[0147] The mesa portion 91 is provided in the boundary region 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0148] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0149] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portions 71 and 91, but it does not need to be provided in the mesa portion 81.

[0150] Figure 4B shows a cross-section of a modified semiconductor device 100 along the line b-b'. In this example, the semiconductor device 100 includes a lifetime control region 150 in the buffer region 20. The buffer region 20 is provided in the transistor section 70 and the diode section 80.

[0151] The contact area 15 is provided above the base area 14 in the mesa portion 91. The contact area 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the mesa portion 71.

[0152] The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is provided across the entire surface of the transistor section 70 and the diode section 80. However, the storage region 16 does not necessarily have to be provided in the diode section 80.

[0153] The cathode region 82 is located below the buffer region 20 in the diode section 80. The boundary 78 between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is located below the boundary region 90 in this example.

[0154] The lifetime control region 150 is provided in both the transistor portion 70 and the diode portion 80. Thereby, the semiconductor device 100 of this example can accelerate the recovery in the diode portion 80 and further improve the switching loss.

[0155] FIG. 5 is a flowchart showing an example of the manufacturing process of the semiconductor device 100. In step S100, a drift region 18 is provided in the semiconductor substrate 10. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being formed. The semiconductor substrate 10 may be an MCZ substrate. The semiconductor substrate 10 may have arbitrary carbon chemical concentration and oxygen chemical concentration. The carbon chemical concentration and oxygen chemical concentration of the drift region 18 may be the same as the carbon chemical concentration and oxygen chemical concentration of the MCZ substrate which is the semiconductor substrate 10. In step S100, the structure on the front surface 21 side of the semiconductor device 100 may be formed. Also, in step S100, after forming the structure on the front surface 21 side, the back surface 23 side of the semiconductor substrate 10 may be polished to adjust the thickness of the semiconductor substrate 10 according to the required breakdown voltage.

[0156] In step S102, a first peak 61 is formed by ion implantation from the back surface 23 side of the semiconductor substrate 10. In one example, the dopant of the first peak 61 is phosphorus. For example, the dose amount of the dopant of the first peak 61 may be 1.0E12 cm －２ or more, and may be 2.0E12 cm －２ or more. The dose amount of the dopant of the first peak 61 may be 1.0E13 cm －２ or less, and may be 5.0E12 cm －２ or less. In this example, it is 3.0E12 cm －２ . The acceleration energy of the dopant of the first peak 61 may be 500 keV or more, and may be 700 keV or more. The acceleration energy of the dopant of the first peak 61 may be 4000 keV or less, and may be 3000 keV or less. In this example, it is 2000 keV.

[0157] In step S104, the collector region 22 is formed. The collector region 22 may be formed over the entire surface of the back surface 23 of the semiconductor substrate 10. The ion dose for forming the collector region 22 is 2.0E13cm －２ The above is sufficient, and 5.0E13cm －２ The following may apply. Furthermore, the dose of ions required to form the collector region 22 may be 10 to 50 times the dose of ions required to form the first peak 61.

[0158] In step S106, the cathode region 82 is formed. The cathode region 82 may be formed before the collector region 22 is formed. If the semiconductor device 100 does not have a diode portion 80, step S106 may be omitted. In step S108, the region in which impurities have been injected from the back surface 23 side of the semiconductor substrate 10 is heated by laser annealing.

[0159] In step S110, hydrogen ions are implanted to form a buffer region 20. If multiple peaks are to be formed in the buffer region 20, hydrogen ions are implanted multiple times with different acceleration energies. For example, in step S110, a second peak 62, a third peak 63, and a fourth peak 64 are formed.

[0160] As an example, the hydrogen ion dose corresponding to the second peak 62 is 7.0 × 10⁻⁶. １２ cm －２ The acceleration energy is 1100 keV. The dose of hydrogen ions corresponding to the third peak 63 is 1.0 × 10⁻⁶. １３ cm －２ The acceleration energy is 820 keV. The dose of hydrogen ions corresponding to the fourth peak 64 is 3.0 × 10⁻⁶. １４ cm －２ The acceleration energy is 400 keV. In step S112, the semiconductor substrate 10 is heated in an annealing furnace with a nitrogen atmosphere or the like. For example, the annealing temperature is 370 degrees and the annealing time is 5 hours.

[0161] In step S114, helium is ion-implanted from the back surface 23 side of the semiconductor substrate 10 to form a lifetime control region 150. The dose of ions used to form the lifetime control region 150 is 1.0E11cm －２ The above is sufficient, and 3.0E11cm －２ The above is acceptable. The dose of ions required to form the lifetime control region 150 is 5.0E12cm －２ The following may be true: 2.0E12cm －２ The following is acceptable: By making the dose amount in the lifetime control region 150 larger than a predetermined lower limit, the turn-off loss Eoff can be reduced. However, if the dose amount in the lifetime control region 150 is made larger than a predetermined upper limit, variations in characteristics may occur due to lattice defects.

[0162] The dose of ions required to form the lifetime control region 150 may be appropriately changed depending on the carbon chemical concentration of the semiconductor substrate 10. The carbon chemical concentration of the semiconductor substrate 10 may be the same as that of the drift region 18. －３ Above, 1E14cm －３ If it is less than 1E12cm, the dose in the lifetime control region 150 is 1E12cm －２ Above 6E12cm －２ The following is acceptable: The carbon chemical concentration in drift region 18 is 1E14 cm⁻¹. －３ Above 5E15cm －３ If it is less than 2E11cm, the dose in the lifetime control region 150 is 2E11cm －２ Above 1E12cm －２ It may be less than 5E15 cm. The carbon chemical concentration in drift region 18 is 5E15 cm. －３ Above, 1E16cm －３ If the following conditions are met, the dose in the lifetime control region 150 is 2E10cm². －２ Above, 2E11cm －２ It may be less than [value]. By appropriately controlling the carbon chemical concentration in the drift region 18 and the formation conditions of the lifetime control region 150, the characteristics of the semiconductor device 100 can be stabilized.

[0163] The dose of ions required to form the collector region 22 may be 300 to 500 times the dose of ions required to form the lifetime control region 150. The acceleration energy required to form the lifetime control region 150 may be 270 keV to 900 keV. As an example, He ２＋ The dose is 2 × 10 １２ cm －２ The accelerating energy is injected at 700 keV. In step S116, the semiconductor substrate 10 is heated in an annealing furnace with a nitrogen atmosphere or the like.

[0164] Furthermore, the ion dose for forming the lifetime control region 150 may be 0.1 times or more and 10 times or less, 0.5 times or more and 5 times or less, or 0.7 times or more and 3 times or less, the ion dose for forming the first peak 61.

[0165] In step S118, the collector electrode 24 is formed. For example, the collector electrode 24 is formed by sputtering. The collector electrode 24 may be a multilayer electrode in which an aluminum layer, a titanium layer, and a nickel layer are stacked. The semiconductor device 100 can be manufactured through such a process.

[0166] Figure 6A shows the relationship between switching loss and steady-state loss. The vertical axis represents switching loss (Eoff), and the horizontal axis represents steady-state loss (Von). In this example, results from both the example and the comparative example are shown. The units on the vertical and horizontal axes are arbitrary units [a.u.].

[0167] Lx, Mx, and Hx represent the switching loss and steady-state loss of the semiconductor device 100. The carbon chemical concentration of the semiconductor substrate 10 decreases in the order of Lx, Mx, and Hx. That is, Lx is lower in concentration than Mx, and Mx is lower in concentration than Hx. The carbon chemical concentration of the semiconductor substrate 10 may be the same as the carbon chemical concentration of the drift region 18. The semiconductor device 100 in this example has a valley peak 65, and its switching loss and steady-state loss are reduced compared to the semiconductor device of the comparative example. Furthermore, the semiconductor device 100 exhibits small variation in switching loss and steady-state loss even when the carbon chemical concentration changes.

[0168] At low concentrations Lx, the carbon chemical concentration in drift region 18 is 1E13 cm⁻¹. －３ Above, 1E14cm －３ It may be less than . In this case, the killer peak concentration Dp in the lifetime control region 150 is 6E16cm. －３ Above, 4E17cm －３ The following is acceptable: At medium concentration Mx, the carbon chemical concentration in drift region 18 is 1E14 cm⁻¹. －３ Above 5E15cm －３ It may be less than . In this case, the killer peak concentration Dp in the lifetime control region 150 is 1E16cm. －３ Above 6E16cm －３ It may be less than 5. At high concentrations of Hx, the carbon chemical concentration in the drift region 18 is 5E15 cm. －３ Above, 1E16cm －３ The following is acceptable. In this case, the killer peak concentration Dp in the lifetime control region 150 is 1E15cm. －３ Above, 1E16cm －３ It can be less than [amount].

[0169] Lc, Mc, and Hc represent the switching loss and steady-state loss of the comparative semiconductor device. The carbon chemical concentration of the semiconductor substrate 10 decreases in the order of Lc, Mc, and Hc. That is, Lc is at a lower concentration than Mc, and Mc is at a lower concentration than Hc. In the comparative semiconductor device, the variation in switching loss and steady-state loss increases as the carbon chemical concentration changes.

[0170] Thus, while the carbon chemical concentration affects the trade-off between switching loss and steady-state loss, the influence of variations in the carbon chemical concentration of the semiconductor substrate 10 on the trade-off characteristics can be suppressed by appropriately controlling the relationship between each peak in the buffer region 20 and the lifetime control region 150. In this example, the semiconductor device 100 can stabilize its characteristics by adjusting the carbon chemical concentration in the drift region 18 and the conditions of the lifetime control region 150 to form a valley peak 65, thereby reducing variations in characteristics. Turn-off loss can be easily reduced by moving the valley peak 65 away from the back surface 23. On-voltage can be easily reduced by moving the valley peak 65 closer to the back surface 23.

[0171] Figure 6B shows the range of variation in switching loss and steady-state loss with respect to changes in carbon chemical concentration. In this example, the range of variation in characteristics at medium and high concentrations relative to low concentrations is shown.

[0172] In the comparative semiconductor device, the steady-state loss (Von) at a low carbon chemical concentration increased by 3.2% at a medium concentration and by 3.9% at a high concentration. In the comparative semiconductor device, the switching loss (Eoff) at a low carbon chemical concentration decreased by 2.8% at a medium concentration and by 4.2% at a high concentration.

[0173] On the other hand, in semiconductor device 100, the steady-state loss (Von) at a low carbon chemical concentration increases by 1.8% at a medium concentration and by 2.1% at a high concentration. In semiconductor device 100, the switching loss (Eoff) at a low carbon chemical concentration decreases by 0.4% at a medium concentration and by 3.0% at a high concentration.

[0174] Thus, the semiconductor device 100 exhibits small fluctuations in both steady-state losses and switching losses in response to changes in carbon chemical concentration. In this example, the semiconductor device 100 can suppress variations while improving the trade-off between switching losses and steady-state losses by appropriately adjusting the conditions for forming the valley peak 65.

[0175] Figure 7A is a schematic diagram showing the concentration distribution of the killer peak concentration. As shown in Figure 7A, the concentration distribution of the killer peak concentration may follow a Gaussian distribution. In this case, the dose amount (ions / cm²) in the lifetime control region 150 is ２ or atoms / cm ２ ) is the killer peak concentration Dp (atoms / cm³). ３) may be the value obtained by multiplying by the full width at half maximum (FWHM) (cm). The killer peak concentration may be the concentration of recombination centers, the concentration of vacancies, the helium chemical concentration, or the hydrogen chemical concentration. In this example, the killer peak concentration is the helium chemical concentration. In the case of the hydrogen chemical concentration, the killer peak concentration may be the concentration of recombination centers formed on the front side 21 or the back side 23 of the hydrogen chemical concentration. In this case, the concentration distribution of the killer peak concentration may be the concentration distribution measured by positron annihilation, or it may be the carrier concentration distribution by SR measurement and the carrier mobility ratio distribution converted from the carrier concentration distribution by CV measurement or DLTS measurement.

[0176] Figure 7B is a schematic correspondence diagram of SR carrier concentration, carrier mobility μ, and normalized recombination center concentration Rn. In this example, a lifetime killer is formed in the hydrogen ion passage region. As an example, the first peak 61 and second peak 62 of the collector region 22 and buffer region 20 are shown from the back surface 23. The SR carrier concentration is given by N = 1 / (qμρ), where N is the carrier concentration, ρ is the resistivity, μ is the carrier mobility, and q is the elementary charge.

[0177] There are two distribution diagrams: A is the doping concentration distribution, and B is the SR concentration distribution. The region where the doping concentration is shown by a dotted line is the region where many recombination centers are distributed. Since the SR concentration uses the carrier mobility value in the crystalline state, the carrier concentration appears to decrease. Therefore, the value obtained by dividing the SR concentration B by the doping concentration A is the proportion of the carrier concentration that has decreased due to lattice defects. Multiplying this proportion by the carrier mobility in the crystalline state gives the value of the decreased carrier mobility B'. Furthermore, the reciprocal of the value of the decreased carrier mobility B' can be taken, and the value normalized by setting the maximum value of the reciprocal corresponding to the minimum value of the decreased carrier mobility B' to 1 can be used as the normalized recombination center concentration Rn. The normalized recombination center concentration Rn can be used as the normalized lattice defect concentration.

[0178] In regions where the carrier concentration falls below the doping concentration due to lattice defects constituting recombination centers, carrier mobility decreases. Since the actual doping concentration, such as the donor concentration, does not decrease, this apparent decrease in carrier concentration distribution represents the distribution of the rate at which mobility decreases from its crystalline state value. In other words, it is the distribution of the proportion of lattice defect concentrations that are reducing mobility, and the distribution of the proportion of recombination center formation. This allows for adjustment of the on-voltage of the transistor section 70 and the forward voltage of the diode section 80.

[0179] The full width at half maximum (FWHM) of the recombination center concentration is calculated from the normalized recombination center concentration Rn shown in Figure 7B. Additionally, the normalized recombination center concentration Rn, the carrier mobility μ in the crystalline state, and the minimum carrier mobility μ are used. ｍｉｎ , Carrier mobility is at its minimum value μ ｍｉｎ Using the doping concentration Nd at the depth position shown, the maximum recombination center concentration Rn ０ Rn ０ = Nd・(μ ｍｉｎ We may assume that the recombination center concentration Rn is ≠ μ. ０ The integrated concentration (which may correspond to the dose) may be used as the dose for the lifetime control region 150. Recombination center concentration Rn ０ The integral concentration of is Rn ０ Assuming that follows a Gaussian distribution, let Rn(z) be the normalized recombination center concentration distribution, and let Δz be the full width at half maximum (FWHM) of Rn(z). ０ The calculation may also be performed using (z) × Δz. Based on the above, the recombination center concentration and dose amount in the hydrogen ion implantation passage region can be estimated.

[0180] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0181] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0182] 10... Semiconductor substrate, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 17... Well region, 18... Drift region, 20... Buffer region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection portion, 30... Dummy trench portion, 31... Extending portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 40... Gate trench portion, 41... Extending portion, 42... Gate insulating film, 43... Connection portion 44...Gate conductive part, 50...Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 61...First peak, 62...Second peak, 63...Third peak, 64...Fourth peak, 65...Valley peak, 70...Transistor part, 71...Mesa part, 78...Boundary, 80...Diode part, 81...Mesa part, 82...Cathode region, 90...Boundary region, 91...Mesa part, 100...Semiconductor device, 150...Lifetime control region, 160...Helium chemical concentration

Claims

1. A semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate having a front surface and a back surface; a buffer region of a first conductivity type provided on the back surface side of the semiconductor substrate more than the drift region; and a lifetime control region provided in the buffer region, wherein the buffer region has: a first peak of carrier concentration; a second peak of carrier concentration provided in the depth direction of the semiconductor substrate closer to the front surface of the semiconductor substrate than the first peak; and a trough peak of carrier concentration provided in the depth direction of the semiconductor substrate between the first peak and the second peak; the lifetime control region has a lifetime killer and the trough peak; the concentration gradient of the carrier concentration distribution changes critically between the depth position where the carrier concentration of the trough peak is at its minimum and the depth position of the second peak; and the depth position of the peak concentration where the lifetime killer concentration of the lifetime control region is at its maximum is located on the front surface side of the depth position where the concentration gradient of the carrier concentration distribution changes critically.

2. The semiconductor device according to claim 1, wherein the absolute value of the concentration gradient of the carrier concentration distribution at the depth position where the lifetime killer concentration is maximum is smaller than the absolute value of the concentration gradient of the carrier concentration distribution on the back side than the depth position where the concentration gradient of the carrier concentration distribution changes critically.

3. The semiconductor device according to claim 1, wherein the absolute value of the concentration gradient of the carrier concentration distribution on the front side is smaller than the absolute value of the concentration gradient of the carrier concentration distribution on the back side is smaller than the absolute value of the concentration gradient of the carrier concentration distribution on the back side is smaller than the depth position where the concentration gradient of the carrier concentration distribution changes critically.

4. The semiconductor device according to claim 3, wherein the ratio of the absolute value of the concentration gradient of the carrier concentration distribution on the front side of the depth position where the concentration gradient of the carrier concentration distribution critically changes to the absolute value of the concentration gradient of the carrier concentration distribution on the back side of the depth position where the concentration gradient of the carrier concentration distribution critically changes, is greater than 1 and less than or equal to 5.

5. The semiconductor device according to claim 1, wherein the carrier concentration continuously increases monotonically from a depth position where the carrier concentration distribution of the valley peak shows a minimum value to a depth position where the carrier concentration distribution of the first peak shows a maximum value.

6. The semiconductor device according to claim 1, wherein the width of the valley peak is 0.1 μm or more and 2 μm or less in the depth direction of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the width of the valley peak is 1 μm or less in the depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the lower limit of the carrier concentration in the valley peak is greater than the carrier concentration in the drift region.

9. The semiconductor device according to claim 1, wherein the first peak is the peak among a plurality of peaks in the buffer region that is closest to the back surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein the buffer region has a third carrier concentration peak located closer to the surface of the semiconductor substrate than the second peak in the depth direction of the semiconductor substrate, and the lower limit of the carrier concentration of the valley peak is greater than the minimum value of the carrier concentration between the second peak and the third peak.

11. The semiconductor device according to claim 1, wherein the peak position of the valley peak is closer to the peak position of the first peak than the peak position of the second peak in the depth direction of the semiconductor substrate.

12. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the distance between the peak position of the valley peak and the peak position of the first peak is less than 1 / 4 times the distance between the peak position of the first peak and the peak position of the second peak.

13. The semiconductor device according to claim 1, wherein the peak position of the valley peak is located at a distance of 0.1 μm or more from the peak position of the second peak toward the back surface in the depth direction of the semiconductor substrate.

14. The semiconductor device according to claim 1, wherein the peak position of the valley peak is located at a distance of 0.1 μm or more toward the front surface side from the peak position of the first peak in the depth direction of the semiconductor substrate.

15. The semiconductor device according to claim 1, wherein the valley peak is provided at a depth of 0.5 μm or more and 2 μm or less from the back surface of the semiconductor substrate.

16. The semiconductor device according to any one of claims 1 to 15, wherein the lifetime control region is closer to the first peak than to the second peak in the depth direction of the semiconductor substrate.

17. The semiconductor device according to any one of claims 1 to 15, wherein the depth position of the full width at half maximum of the lifetime control region does not overlap with the depth position of the full width at half maximum of the first peak in the depth direction of the semiconductor substrate.

18. The semiconductor device according to any one of claims 1 to 15, wherein the depth position of the full width at half maximum of the lifetime control region does not overlap with the depth position of the full width at half maximum of the second peak in the depth direction of the semiconductor substrate.

19. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor substrate is an MCZ substrate.

20. The oxygen chemical concentration in the drift region is 1E17cm －３ Above, 4.5E17cm －３ The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is as follows:

21. The carbon chemical concentration in the drift region is 1E13cm －３ Above, 1E14cm －３ A semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is less than [amount missing].

22. The peak concentration of the lifetime killer in the lifetime control region is 6E16cm². －３ Above, 4E17cm －３ The semiconductor device according to claim 21, as follows.

23. The carbon chemical concentration in the drift region is 1E14cm －３ Above 5E15cm －３ A semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is less than [amount missing].

24. The peak concentration of the lifetime killer concentration in the lifetime control region is 1E16 cm －３ or more and less than 6E16 cm －３ The semiconductor device according to claim 23.

25. The carbon chemical concentration in the drift region is 5E15cm －３ Above, 1E16cm －３ The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is as follows:

26. The peak concentration of the lifetime killer in the lifetime control region is 1E15cm. －３ Above, 1E16cm －３ The semiconductor device according to claim 25, which is less than [amount missing].

27. A semiconductor device according to any one of claims 1 to 15, comprising a transistor portion and a diode portion provided on the semiconductor substrate, wherein the transistor portion has a second conductivity type collector region provided on the back surface of the semiconductor substrate, and the buffer region is provided on the transistor portion and the diode portion.

28. A method for manufacturing a semiconductor device, comprising the steps of: providing a drift region of a first conductivity type on a semiconductor substrate; providing a buffer region of the first conductivity type on the back side of the semiconductor substrate more than the drift region; and providing a lifetime control region in the buffer region, wherein the buffer region has: a first peak of carrier concentration; a second peak of carrier concentration provided in the depth direction of the semiconductor substrate closer to the front surface of the semiconductor substrate than the first peak; and a trough peak of carrier concentration provided in the depth direction of the semiconductor substrate between the first peak and the second peak; the lifetime control region has a lifetime killer and the trough peak; the concentration gradient of the carrier concentration distribution changes critically between the depth position where the carrier concentration of the trough peak is at its minimum and the depth position of the second peak; and the depth position of the peak concentration where the lifetime killer concentration of the lifetime control region is at its maximum is located on the front surface side of the depth position where the concentration gradient of the carrier concentration distribution changes critically.

29. The method for manufacturing a semiconductor device according to claim 28, wherein the acceleration energy for forming the lifetime control region is 270 keV or more and 900 keV or less.

30. The carbon chemical concentration in the drift region is 1E13cm －３ Above, 1E14cm －３ The dose amount in the lifetime control region is less than 1E12cm －２ Above 6E12cm －２ The method for manufacturing a semiconductor device according to claim 28 or 29, which is as follows:

31. The carbon chemical concentration in the drift region is 1E14cm －３ Above 5E15cm －３ The dose amount in the lifetime control region is less than 2E11cm －２ Above 1E12cm －２ A method for manufacturing a semiconductor device according to claim 28 or 29, wherein the method is less than [amount missing].

32. The carbon chemical concentration in the drift region is 5E15cm －３ Above, 1E16cm －３ The dose amount in the lifetime control region is as follows: 2E10cm －２ Above, 2E11cm －２ A method for manufacturing a semiconductor device according to claim 28 or 29, wherein the method is less than [amount missing].

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