Semiconductor device and manufacturing method

Abstract

A semiconductor device includes a lifetime adjustment region, a plurality of mesa parts, and a second-conductivity-type lower end region provided in contact with the lower end of at least one trench part. The plurality of mesa parts include a first mesa part in which the lifetime adjustment region is provided below, and a second mesa part in which the lifetime adjustment region is not provided below. The difference concentration obtained by subtracting a second doping concentration of the base region of the second mesa part from a first doping concentration of the base region of the first mesa part is greater than zero and no greater than 50 times a third doping concentration of the lower end region.

Description

Semiconductor device and manufacturing method

[0001] The present invention relates to semiconductor devices and methods for manufacturing them.

[0002] Patent Document 1 discloses a technique for "extending parallel to the first transverse direction (X) to form a second conductive type barrier region (105) adjacent to the bottom of the trenches (14, 15, 16) (Claim 1)." Patent Document 2 discloses a semiconductor device comprising a "lifetime adjustment region." Patent Document 3 discloses a semiconductor device comprising a "lifetime control region." [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Unexamined Patent Publication No. 2019-110288 [Patent Document 2] Japanese Unexamined Patent Publication No. 2024-67536 [Patent Document 3] International Publication No. 2020 / 036015 General disclosure

[0003] (Problem to be solved) In semiconductor devices, it is preferable to suppress fluctuations in threshold voltage, etc. (Means for solving the problem)

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. The semiconductor device may include a plurality of trenches arranged in a first direction, each extending from the upper surface to the interior of the semiconductor substrate. Any of the above semiconductor devices may include a lifetime adjustment region provided on the upper surface side of the semiconductor substrate for adjusting the lifetime of carriers. Any of the above semiconductor devices may include a plurality of mesaes sandwiched between two of the trenches in the semiconductor substrate. Any of the above semiconductor devices may include a lower end region of a second conductivity type provided in contact with the lower end of at least one of the trenches. In any of the above semiconductor devices, each of the plurality of mesaes may have a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion in which the lifetime adjustment region is provided below, and a second mesa portion in which the lifetime adjustment region is not provided below. In any of the above semiconductor devices, the difference concentration obtained by subtracting the second doping concentration of the base region of the second mesa portion from the first doping concentration of the base region of the first mesa portion may be greater than 0 and 50 times or less the third doping concentration of the lower end region.

[0005] In any of the above semiconductor devices, the differential concentration may be 0.1 times or more the third doping concentration.

[0006] In any of the above semiconductor devices, the differential concentration may be 30 times or less the third doping concentration.

[0007] In any of the above semiconductor devices, the differential concentration may be equal to the third doping concentration.

[0008] In any of the above semiconductor devices, the first doping concentration may be higher than the third doping concentration.

[0009] In any of the semiconductor devices described above, at least a part of the lower end region and at least a part of the lifetime adjustment region may be arranged to overlap in the depth direction of the semiconductor substrate.

[0010] In any of the semiconductor devices described above, the lower end region and the lifetime adjustment region may be arranged not to overlap in the depth direction of the semiconductor substrate.

[0011] In any of the semiconductor devices described above, the lower end region may not be provided in the trench portion in contact with the first mesa portion.

[0012] In any of the semiconductor devices described above, the first doping concentration may be 1×10 １７ / cm ３ or more and 1×10 １８ / cm ３ or less.

[0013] In any of the semiconductor devices described above, the second doping concentration may be 8×10 １６ / cm ３ or more and 8×10 １７ / cm ３ or less.

[0014] In any of the semiconductor devices described above, the third doping concentration may be 1×10 １５ / cm ３ or more and 2×10 １７ / cm ３ or less.

[0015] In any of the semiconductor devices described above, the doping concentration distribution in the depth direction in the base region of the first mesa portion may have one or more inflection points below the position where the doping concentration shows the maximum value.

[0016] In any of the above semiconductor devices, the plurality of trenches may include a first gate trench with the lifetime adjustment region located below it, and a second gate trench without the lifetime adjustment region located below it. In any of the above semiconductor devices, the lower end region is provided at the lower end of the first gate trench, and the lower end region of the second conductivity type is not provided at the lower end of the second gate trench.

[0017] In any of the above semiconductor devices, the plurality of trenches may include gate trenches and dummy trenches that are adjacent to each other in the first direction. In any of the above semiconductor devices, the lower end region may be in contact with the gate trenches but not with the dummy trenches.

[0018] A second aspect of the present invention provides a method for manufacturing a semiconductor device according to the first aspect. The above manufacturing method may involve forming a plurality of trenches extending from the upper surface to the interior of the semiconductor substrate. In any of the above manufacturing methods, in the step of injecting a first dopant to form the lower end region through at least one of the trenches, the first dopant may also be injected into the first mesa portion.

[0019] In any of the above manufacturing methods, a second dopant of the second conductivity type may be injected into the region where the base region is to be formed in both the first mesa portion and the second mesa portion.

[0020] In any of the above manufacturing methods, the first dopant may be injected into the lower end of at least one of the trenches having a lifetime adjustment region below it and a gate trench portion provided therein. In any of the above semiconductor devices, the first dopant does not need to be injected into the lower end of at least one of the trenches having a gate trench portion and not having a lifetime adjustment region below it.

[0021] The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention.

[0022] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. This is an enlarged view of region D in Figure 1. This is an example of an XZ cross-section of the transistor section 70 shown in Figure 2. This is another example of an XZ cross-section of the semiconductor device 100. This is a diagram illustrating some steps in the manufacturing method of the semiconductor device 100. This is a diagram showing an example of the doping concentration distribution along the s-s' line in Figure 3. This is a diagram showing an example of the doping concentration distribution along the r-r' line in Figure 3. This is a diagram showing another example of the doping concentration distribution in the depth direction in the base region 14 of the first mesa section 61. This is a diagram showing an example of the carrier concentration distribution along the r-r' line. This is a diagram showing another example of an XZ cross-section of the transistor section 70. This is a diagram showing another example of an XZ cross-section of the transistor section 70. This is a diagram illustrating some steps in the manufacturing method of the semiconductor device 100. This is a diagram showing an example of the doping concentration distribution along the r-r' line in Figure 10A. This is a diagram showing an example of the doping concentration distribution along the s-s' line in Figure 10A.

[0023] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0025] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0026] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0028] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region containing impurities is described as either p-type or n-type. In this specification, impurities may specifically refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an n-type conductivity or a p-type conductivity.

[0030] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N Ｄ , the acceptor concentration is N Ａ Therefore, the net doping concentration at any given position is N Ｄ -N Ａ In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0031] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as an electron-supplying donor. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, interstitial Si-H, in which interstitial silicon (Si-i) and hydrogen are bonded in a silicon semiconductor, also functions as an electron-supplying donor. In this specification, VOH defects or interstitial Si-H may be referred to as hydrogen donors.

[0032] In this specification, the semiconductor substrate has n-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacturing of the semiconductor substrate ingot. In this example, the bulk donor is an element other than hydrogen. The bulk donor dopants are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the p-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by one of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). In this example, the ingot is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1 × 10⁻¹⁶ １７ ~7 x 10 １７ / cm ３ The oxygen concentration in a substrate manufactured by the FZ method is 1 × 10⁻⁶. １５ ~5 x 10 １６ / cm ３The oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. In addition, the semiconductor substrate may be a non-doped substrate that does not contain dopants such as phosphorus. In that case, the bulk donor concentration (D0) of the non-doped substrate may be, for example, 1 × 10⁻⁶. １０ / cm ３ The above 5 x 10 １２ / cm ３ The following applies: The bulk donor concentration (D0) of the non-doped substrate is preferably 1 × 10⁻⁶. １１ / cm ３ That concludes the explanation. The bulk donor concentration (D0) of the non-doped substrate is preferably 5 × 10⁻⁶. １２ / cm ３ The following applies. Note that the concentrations in this invention may be values ​​at room temperature. For example, the values ​​at room temperature may be those at 300 K (Kelvin) (approximately 26.9°C).

[0033] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. In this specification, when p type or n type is described in lowercase, it only indicates the conductivity type and does not indicate the magnitude of the doping concentration. Unless otherwise specified, the units used in this specification are the SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0034] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadening resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR may be the value at thermal equilibrium. Furthermore, in the n-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the p-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the n-type region may be referred to as the donor concentration, and the doping concentration in the p-type region may be referred to as the acceptor concentration.

[0035] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. ３ , or, / cm ３ This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0037] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is also a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0038] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0039] The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to one of the edges 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0040] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0041] The active section 160 is provided with a transistor section 70 that includes a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET. In this example, the transistor section 70 includes an IGBT. When the transistor section 70 includes a MOSFET, "emitter" and "collector" in this specification may be read as "source" and "drain". The active section 160 may also be provided with a diode section 80 that includes a diode element such as a freewheeling diode (FWD). In the example of Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined first direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). A boundary region may be arranged between the transistor section 70 and the diode section 80 in the X-axis direction, but it is omitted in Figure 1.

[0042] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". In this specification, a direction different from the first direction in a top view may be referred to as the second direction (Y-axis direction in Figure 1). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have their longitudinal length in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of the mesa section, which will be described later.

[0043] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode portion 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0044] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N+ type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad and cathode pad for the temperature sensing section and a current sensing pad for the current sensing section. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is hatched with diagonal lines.

[0047] The gate wiring in this example has an outer perimeter gate wiring 130 and an active-side gate wiring 131. The outer perimeter gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer perimeter gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer perimeter gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a p-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0048] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like, or a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0049] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0050] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be metal wiring containing aluminum or the like, or wiring formed from a semiconductor such as polysilicon doped with impurities.

[0051] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active portion 160, crossing the active portion 160 approximately in the center in the Y-axis direction. When the active portion 160 is divided by the active gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a pn junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0053] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0054] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. Although omitted in Figure 1, a boundary region 200 is located between the transistor section 70 and the diode section 80 in the X-axis direction. The boundary region 200 is optional. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are located inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131, which are located above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other. In this example, the active gate wiring 131 is a metal wiring.

[0055] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. Contact holes 54 are provided in the interlayer insulating film in this example, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0056] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench 30 through a contact hole (not shown) provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive portion of the dummy trench 30 at the tip or straight portion 29 of the dummy trench 30 in the Y-axis direction. The dummy conductive portion of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive portion.

[0057] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole (not shown) provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0058] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum, etc. Furthermore, it may have a plug portion formed by embedding tungsten or the like in contact with the barrier metal and the aluminum, etc. within the contact hole.

[0059] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0060] Each of the transistor section 70, the diode section 80, and the boundary region 200 has a plurality of trench sections arranged in a first direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the first direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 provided along the first direction. In this example, the diode section 80 does not have gate trench sections 40. In this example, the boundary region 200 has a plurality of dummy trench sections 30 provided along the first direction. In this example, the boundary region 200 does not have gate trench sections 40.

[0061] The gate trench section 40 in this example may have two straight sections 39 (the trench section which is linear along the second direction) extending along a second direction intersecting the first direction, and a tip section 41 connecting the two straight sections 39. In Figure 2, the second direction is the Y-axis direction perpendicular to the first direction (X-axis direction).

[0062] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. Between each of the straight sections 39, there may be one dummy trench section 30, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the second direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0064] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0065] In the first direction, a mesa portion 60 is provided between each trench portion. The mesa portion 60 refers to the region sandwiched between the two trench portions within the semiconductor substrate 10. For example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the second direction (Y-axis direction). The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In this specification, when simply referred to as the mesa portion 60, it refers to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200, respectively.

[0066] Each mesa portion 60 is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the second direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0067] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0068] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the second direction (Y-axis direction) of the trench portion.

[0069] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0070] The diode section 80 and the mesa section 60 of the boundary region 200 do not have an emitter region 12. Base regions 14 and contact regions 15 may be provided on the upper surfaces of the diode section 80 and the mesa section 60 of the boundary region 200. Contact regions 15 may be provided in contact with each base region 14-e in the region sandwiched between the base regions 14-e on the upper surface of the mesa section 60. Base regions 14 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa section 60 of the diode section 80. The base regions 14 may be arranged in the entire region sandwiched between the contact regions 15. The mesa section 60 of the boundary region 200 may have the same structure as the mesa section 60 of the diode section 80, or it may have a different structure. In this example, the mesa section 60 of the boundary region 200 has contact regions 15 provided in the entire region sandwiched between the base regions 14-e. In other words, the area of ​​the contact region 15 of the mesa portion 60 of the boundary region 200 may be larger than the area of ​​the contact region 15 of the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 can be more easily drawn to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0071] In other examples, the mesa region 60 of the boundary region 200 may be a p-type impurity region with a doping concentration similar to or lower than that of the base region 14 of the transistor region 70. The p-type impurity region may occupy the entire mesa region 60 of the boundary region 200, and other regions may be provided in the mesa region 60 of the boundary region 200. By providing a p-type impurity region with a doping concentration lower than that of the base region 14 in the mesa region 60 of the boundary region 200, hole injection from the mesa region 60 of the boundary region 200 can be suppressed, and the reverse recovery loss can be reduced.

[0072] The mesa portion 60 of the boundary region 200 may be provided with an n-type impurity region with a doping concentration similar to or lower than that of the emitter region 12. However, in this case, the gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. Since the n-type impurity region of the mesa portion 60 of the boundary region 200 is not in contact with the gate trench portion 40, the boundary region 200 does not have a greater current flowing through it than the transistor portion 70. As a result, the injection of holes from the mesa portion 60 of the boundary region 200 is suppressed, and the reverse recovery loss can be reduced.

[0073] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is located in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be located in the center of the mesa portion 60 in the first direction (X-axis direction).

[0074] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0075] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the p-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, and the cathode region 82, thereby improving pressure resistance. In this example, the end of the cathode region 82 in the Y-axis direction is positioned further from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may be positioned between the well region 11 and the contact hole 54.

[0076] Figures 3A and 3B show an example of an XZ cross-section of the transistor section 70 shown in Figure 2. This cross-section passes through the emitter region 12 and the collector region 22. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 refer to the two surfaces of the semiconductor substrate 10 with the largest area.

[0077] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. The emitter electrode 52 may have a titanium-containing barrier metal in the portion that contacts the upper surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer, or it may have a laminated structure of a titanium nitride layer and a titanium layer. The emitter electrode 52 may have a plug portion made of tungsten or the like that is filled inside the contact hole 54.

[0079] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 may be provided in the transistor portion 70, the diode portion 80, and the boundary region 200, respectively.

[0080] In this example, the multiple mesa sections 60 of the transistor section 70 include a first mesa section 61 and a second mesa section 62. The first mesa section 61 is a mesa section 60 with a lifetime adjustment region 206 provided below it, and the second mesa section 62 is a mesa section 60 without a lifetime adjustment region 206 provided below it. The lifetime adjustment region 206 will be described later.

[0081] In the first mesa portion 61 and the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14.

[0082] In the XZ cross-section passing through the contact region 15 shown in Figure 2, the contact region 15 is provided in place of the emitter region 12. The contact region 15 may extend to a deeper position than the emitter region 12. Also, in the boundary region 200, the contact region 15 may be provided in place of the emitter region 12. In the diode section 80, the base region 14 may be provided in place of the emitter region 12. The base region 14 of the diode section 80 functions as the anode region. The doping concentration of the base region 14 of the diode section 80 may be the same as, or less than, the doping concentration of the base region 14 of the second mesa section 62. The doping concentration of the base region 14 of the diode section 80 may be the same as, or less than, the doping concentration of the base region 14 of the first mesa section 61. In the region where a p-type region such as the base region 14 or the contact region 15 is in contact with the emitter electrode 52, a plug region (not shown), which is a high-concentration P++-type region, may be formed over the entire area or selectively to be very shallow. By forming a plug region, the contact resistance with the emitter electrode 52 can be reduced and the carrier distribution can be adjusted.

[0083] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration in the emitter region 12 is higher than that in the drift region 18.

[0084] The base region 14 is provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. The base region 14 may be provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the first mesa portion 61 and the second mesa portion 62.

[0085] In the first mesa section 61 and the second mesa section 62, an N+ type storage region 16 may be provided between the base region 14 and the drift region 18. The storage region 16 may cover the entire lower surface of the base region 14. The storage region 16 is a region with a higher doping concentration than the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The doping concentration of the storage region 16 may be 10 times or more, 50 times or more, or 100 times or more than the doping concentration of the drift region 18. The lower end of the storage region 16 may be located above the lower end of the trench section, while it may be located below the lower end of the trench section and below the lower surface of the lower end region 210, which will be described later. The storage region 16 may or may not be provided in at least a part of the mesa section 60 of the boundary region 200. The storage region 16 may or may not be provided in at least a portion of the mesa portion 60 of the diode portion 80.

[0086] In the transistor section 70, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. In addition, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is almost flat. The buffer section 20 may also be provided in the diode section 80 and the boundary section 200.

[0087] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0088] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0089] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than that of the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that act as donors and acceptors in each region are not limited to the examples described above.

[0090] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. The collector region 22 of the boundary region 200 may have the same doping concentration as the boundary region 200 of the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be the boundary position in the X-axis direction between the diode section 80 and the boundary region 200. In another example, in the boundary region 200, part or all of the collector region 22 may be replaced with the cathode region 82. When the cathode region 82 is provided on the lower surface of the boundary region 200, the region sandwiched between the base regions 14-e in which the contact region 15 and the base region 14 are alternately arranged may be considered as the diode section 80, and the region sandwiched between the base regions 14-e in which the contact region 15 is arranged throughout may be considered as the boundary region 200. When the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 may be considered as part of the diode section 80.

[0091] Of the gate trenches 40 that are in contact with the emitter region 12, the gate trench 40 that is closest to the diode 80 in the X-axis direction is set as the boundary position in the X-axis direction between the transistor 70 and the boundary region 200 (or diode 80). The central position of this gate trench 40 in the X-axis direction may be set as the boundary position in the X-axis direction between the transistor 70 and the boundary region 200 (or diode 80). Of the two trenches in contact with the emitter region 12 that are closest to the diode 80 in the X-axis direction, the trench on the diode 80 side may be a dummy trench 30. In this case, the dummy trench 30 may be set as the boundary position in the X-axis direction between the transistor 70 and the boundary region 200 (or diode 80).

[0092] An emitter region 12 may be provided in the boundary region 200. However, in that case, the gate trench portion 40 is not provided in the boundary region 200. Also, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. That is, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may be provided in the boundary region 200. However, in that case, the emitter region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0093] The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0094] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. The multiple trenches are arranged in the X-axis direction, and each extends from the upper surface 21 of the semiconductor substrate 10 into the interior. In this example, each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12 and the contact region 15 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Even when doping regions are formed between the trenches after the trenches have been formed, the trenches are still included in the statement that they penetrate the doping regions.

[0095] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with a dummy trench section 30, but the gate trench section 40 is not provided. However, the boundary between the boundary region 200 and the transistor section 70 may have a gate trench section 40, or a dummy trench section 30.

[0096] The boundary region 200 is a buffer structure for arranging the different structures of the transistor section 70 and the diode section 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be short. For example, one or more mesa sections 60 may be provided in the boundary region 200, or the boundary region 200 may not be provided at all. Here, the number of mesa sections refers to the number of mesa sections arranged in a line in the X-axis direction.

[0097] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0098] The gate conductive portion 44 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0099] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0100] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0101] The transistor section 70 in this example is provided on the upper surface 21 side of the semiconductor substrate 10 and includes a lifetime adjustment region 206 for adjusting the carrier lifetime. The upper surface 21 side refers to the region from the center of the semiconductor substrate 10 to the upper surface 21 in the Z-axis direction. The lifetime adjustment region 206 in this example is located below the lower end of the trench section.

[0102] In this example, the lifetime adjustment region 206 is a region where the lifetime of charge carriers is locally small. Charge carriers are electrons or holes. Charge carriers are sometimes simply referred to as carriers. In this example, the lifetime adjustment region 206 is formed by injecting charged particles such as helium ions from the upper surface 21 side of the semiconductor substrate 10.

[0103] In this example, the concentration distribution of helium, etc., in the depth direction of the semiconductor substrate 10 may have a shape that extends from the lifetime adjustment region 206 to the upper surface 21 of the semiconductor substrate 10. That is, from the lifetime adjustment region 206 to the upper surface 21, the concentration of helium, etc. ( / cm³) ３ The concentration of helium, etc., at the upper surface 21 may decrease monotonically. On the other hand, in the direction from the lifetime adjustment region 206 toward the lower surface 23, the concentration of helium, etc., may have a shape that resembles a trailing edge. However, the concentration of helium, etc., decreases more steeply toward the lower surface 23 than toward the upper surface 21.

[0104] The concentration of helium, etc., on the lower surface 23 is lower than the concentration of helium, etc., on the upper surface 21. The concentration of helium, etc., on the upper surface 21 may be below the detection limit, or it may be zero. The lifetime adjustment region 206 may be formed by injecting charged particles such as helium ions from the lower surface 23 side of the semiconductor substrate 10.

[0105] By implanting charged particles such as helium ions into the semiconductor substrate 10, lattice defects 204, such as vacancies, are formed near the implantation site. These lattice defects 204 generate recombination centers. The lattice defects 204 may mainly consist of vacancies, such as single-atom vacancies (V) or double-atom vacancies (VV), but may also consist of dislocations, interstitial atoms, or transition metals.

[0106] For example, atoms adjacent to a vacancy have a dangling bond. In a broad sense, lattice defects 204 may also include donors and acceptors, but in this specification, lattice defects 204 mainly consisting of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, lattice defects 204 may be referred to simply as recombination centers or lifetime killers, as they are recombination centers that contribute to carrier recombination.

[0107] Lifetime killers may be formed by implanting helium ions into the semiconductor substrate 10. The helium chemical concentration may be used as the density of lattice defects 204. Note that lifetime killers formed by implanting helium ions may be terminated by hydrogen present in the buffer region 20, so the depth position of the density peak of the lifetime killers may not coincide with the depth position of the helium chemical concentration peak. In addition, when implanting hydrogen ions into the semiconductor substrate 10, lifetime killers may be formed in the hydrogen ion passage region on the implantation surface side of the range.

[0108] Lattice defects 204 are an example of lifetime killers. In Figure 3A, etc., lattice defects 204 at the injection site of charged particles are schematically shown with an "x". In regions where many lattice defects 204 remain, carriers are trapped by the lattice defects 204, so the lifetime of the carriers is shortened. By adjusting the lifetime of the carriers, the characteristics of the diode section 80, such as the reverse recovery time and reverse recovery loss, can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime adjustment region 206.

[0109] When a lifetime adjustment region 206 is formed by irradiation with a highly penetrating particle beam such as an electron beam, lattice defects are formed substantially uniformly from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10. In this case as well, the region on the upper surface 21 side of the semiconductor substrate 10 where lattice defects are formed may be considered as the lifetime adjustment region 206.

[0110] The lifetime adjustment region 206 is provided in a part of the transistor section 70 in the X-axis direction. As described above, the mesa section 60 with the lifetime adjustment region 206 provided below is designated as the first mesa section 61, and the mesa section 60 without the lifetime adjustment region 206 is designated as the second mesa section 62. The first mesa section 61 may be a section in which the lifetime adjustment region 206 is provided in at least a part of the area overlapping with the mesa section 60 in a top view. The first mesa section 61 may be a section in which the lifetime adjustment region 206 is provided in more than half of the area overlapping with the mesa section 60 in a top view.

[0111] The lifetime adjustment region 206 may also be provided in the diode section 80. If the semiconductor device 100 has a boundary region 200, the lifetime adjustment region 206 may also be provided in the boundary region 200. The lifetime adjustment region 206 may be provided over the entire diode section 80 in the X-axis direction. The lifetime adjustment region 206 may also be provided over the entire boundary region 200. The lifetime adjustment region 206 may be provided in the end region of the transistor section 70 in the X-axis direction. In the case of a transistor section 70 sandwiched between two diode sections 80 in the X-axis direction, the lifetime adjustment region 206 may be provided in the regions at both ends of the transistor section 70 in the X-axis direction. The lifetime adjustment region 206 does not have to be provided in the center of the transistor section 70 in the X-axis direction.

[0112] The lifetime adjustment region 206 provided in the diode section 80 may extend to a portion of the transistor section 70. For example, the lifetime adjustment region 206 of the diode section 80 and the lifetime adjustment region 206 of the transistor section 70 may be located at the same depth.

[0113] The semiconductor device 100 in this example includes a p-type lower end region 210 provided in contact with the lower end of at least one trench portion. The doping concentration of the lower end region 210 may be lower or higher than that of the base region 14. An n-type region may be provided between the lower end region 210 and the base region 14. In this example, a storage region 16 and a drift region 18 are provided between the lower end region 210 and the base region 14. The lower end region 210 may be provided in contact with the lower end of any gate trench portion 40. The lower end region 210 may be provided continuously across two or more trench portions aligned in the X-axis direction. In a single transistor portion 70, there may be only one lower end region 210 in the X-axis direction, or multiple lower end regions 210 may be provided discretely in the X-axis direction. The lower end region 210 does not have to cover the entire lower end of the trench section. There may be areas in a single trench section where the lower end region 210 is not provided, or there may be trench sections where the lower end region 210 is not provided. Providing the lower end region 210 can mitigate electric field concentration at the lower end of the trench section.

[0114] The lower end region 210 may be formed by implanting p-type dopant ions from the upper surface 21 side of the semiconductor substrate 10. The lower end region 210 may be located at a different depth than the lifetime adjustment region 206. In this example, the lifetime adjustment region 206 is located at a deeper position than the lower end region 210. "Deep" means being close to the center of the semiconductor substrate 10 in the Z-axis direction.

[0115] In this example, the lower end region 210 and the lifetime adjustment region 206 are arranged so as not to overlap in the depth direction of the semiconductor substrate 10. That is, the lower end region 210 is arranged separately from the lifetime adjustment region 206 in the X-axis direction. The two trench portions in contact with the first mesa portion 61 do not necessarily have a lower end region 210. At least one mesa portion 60 in the transistor portion 70 does not necessarily have to have either a lifetime adjustment region 206 or a lower end region 210.

[0116] In other examples, the range in the X-axis direction where the lower end region 210 is provided and the range in the X-axis direction where the lifetime adjustment region 206 is provided may overlap. At least one mesa region 60 in the transistor region 70 may be provided with both the lifetime adjustment region 206 and the lower end region 210.

[0117] In the example shown in Figure 3A, the lower end region 210 is positioned away from the lifetime adjustment region 206 in the X-axis direction. Of the second mesa portion 62, those in which the lower end region 210 is provided in at least a part of the lower region are designated as the second mesa portion 62-1, and those in which the lower end region 210 is not provided are designated as the second mesa portion 62-2. In this specification, when the term "second mesa portion 62" is used, it refers to both the second mesa portion 62-1 and the second mesa portion 62-2. In this example, one or more second mesa portions 62-2 are positioned between the first mesa portion 61 and the second mesa portion 62-1.

[0118] The doping concentration in the base region 14 of the first mesa portion 61 is defined as the first doping concentration. The doping concentration in the base region 14 of the second mesa portion 62 is defined as the second doping concentration. The doping concentration in the lower end region 210 is defined as the third doping concentration. In this example, the first doping concentration is higher than the second doping concentration. For example, the difference concentration obtained by subtracting the second doping concentration from the first doping concentration is greater than 0 and less than or equal to twice the third doping concentration.

[0119] The differential concentration may be 0.5 times or more, 0.7 times or more, or 0.9 times or more of the third doping concentration. The differential concentration may be 1.5 times or less, 1.3 times or less, 1.1 times or less, or 1 time or less of the third doping concentration. The differential concentration may be equal to the third doping concentration.

[0120] As described above, the lifetime adjustment region 206 is formed when charged particles are irradiated from the upper surface 21. On the other hand, energy levels are formed in the gate insulating film 42 through which the charged particles have passed, and the threshold voltage in the first mesa portion 61 (the voltage at which the transistor turns on and the voltage at which the transistor turns off) may fall below the threshold voltage in the second mesa portion 62. When the threshold voltage falls, the turn-on and turn-off timings of the first mesa portion 61 and the second mesa portion 62 are out of sync, and current may concentrate in one of the mesa portions 60, reducing its withstand capability.

[0121] In this example, the first doping concentration of the base region 14 of each first mesa portion 61 is set higher than the second doping concentration of the base region 14 of the second mesa portion 62. The higher the doping concentration of the base region 14, the higher the gate voltage required to form the channel region with the conductivity type inverted in the base region 14, and the higher the threshold voltage. This compensates for the decrease in threshold voltage caused by the formation of the lifetime adjustment region 206.

[0122] In the semiconductor device 100 of this example, the difference between the first doping concentration and the second doping concentration is set to a value corresponding to the third doping concentration in the lower end region 210. This makes it possible to manufacture the semiconductor device 100 using a simple process.

[0123] Figure 3B shows another example of the XZ cross-section of the semiconductor device 100. The structure of the lower end region 210 of this example differs from the example described in Figure 3A. The other structures are the same as those described in Figure 3A.

[0124] In the semiconductor device 100 of this example, the lower end region 210 is not formed to extend across to the adjacent element trench. In this example, multiple lower end regions 210 are discretely arranged in the X-axis direction. Each lower end region 210 is in contact with the lower end of the element trench. A drift region 18 may be provided between two adjacent lower end regions 210. The region between two adjacent lower end regions 210 may be located below the second mesa portion 62. Even in this case, the presence of the lower end region 210 allows for control of the carrier distribution when the transistor portion 70 is energized, thereby obtaining good characteristics. In other examples, the lower end region 210 does not have to be provided below all element trenches in the X-axis direction range where the lower end region 210 is provided. The lower end region 210 is provided at the lower end of at least one gate trench portion 40, but does not have to be provided at the lower end of at least one dummy trench portion 30. For example, the lower end region 210 may be provided only below the gate trench portion 40.

[0125] Figure 4 is a diagram illustrating some steps in the manufacturing method of the semiconductor device 100. In step S1002, a plurality of trenches 45 are formed, extending from the upper surface 21 to the interior of the semiconductor substrate 10. The plurality of trenches correspond to the plurality of trench sections described in Figures 1 to 3B. Each trench is a hollow groove provided on the upper surface 21 of the semiconductor substrate 10. A trench section can be formed by providing an insulating film and a conductive part inside the trench.

[0126] In step S1002, a p-type first dopant for forming the lower end region 210 (see Figure 3A or 3B) is injected through at least one trench 45. In this example, the trenches 45 that do not form the lower end region 210 are filled with a mask 230 such as a resist. The trenches 45 that form the lower end region 210 are not filled with a mask 230. The upper surface of the second mesa portion 62 is also covered with a mask 230. In this state, the first dopant ions are injected into the entire active portion 160 or transistor portion 70, thereby injecting the first dopant into the lower end of at least one trench 45 and the upper surface of the first mesa portion 61 to form the first injection region 231. The dose amount of the first dopant for each first injection region 231 is ( / cm²). ２ ) may be the same. When injecting the first dopant, a film such as an oxide film may be formed on the upper surface 21 of the first mesa portion 61 and the inner wall of the trench 45. These films may be removed in a later process, or they may remain until the semiconductor device 100 is completed.

[0127] In step S1004, a p-type second dopant is injected into the areas where the base region 14 is to be formed in both the first mesa portion 61 and the second mesa portion 62. In this example, an insulating film is formed in each trench 45, and a conductive portion is filled to form each trench portion. After forming the trench portions, the second dopant ions are injected into the entire active portion 160 or transistor portion 70. This allows the second injection region 232 to be formed in the first mesa portion 61 and the second mesa portion 62, using the trench portions as a mask. The first dopant and the second dopant may be of the same element or of different elements. The second injection region 232 may be formed to a deeper position than the first injection region 231. When injecting the second dopant, a film such as an oxide film may be formed on the upper surface 21 of the first mesa portion 61. This film may be removed in a later step, or it may remain until the semiconductor device 100 is completed. Furthermore, this step is not limited to this, and the formation of the trench may be performed after the injection of the second dopant. Alternatively, step S1004 may be performed first, followed by step S1002. That is, the first dopant may be injected after the second dopant, and in this case, the formation of the trench 45 may be performed before or after the injection of the second dopant.

[0128] Although not shown in step S1004 of Figure 4, after forming the first injection region 231 and the second injection region 232, the semiconductor substrate 10 is heat-treated to diffuse and activate the first dopant and the second dopant. This forms the lower end region 210 and the base region 14. Since the first mesa portion 61 is provided with the first injection region 231 and the second injection region 232, the doping concentration of the base region 14 of the first mesa portion 61 is higher than the doping concentration of the base region 14 of the second mesa portion 62.

[0129] Although not shown in step S1004 of Figure 4, in this example, the emitter region 12 and the storage region 16 are formed in the respective mesa portions 60. In addition, an interlayer insulating film 38 is formed on the upper surface 21 of the semiconductor substrate 10, and contact holes 54 are formed in the interlayer insulating film 38. Furthermore, an emitter electrode 52 is formed above the interlayer insulating film 38.

[0130] In step S1008, a lifetime adjustment region 206 is formed below the first mesa portion 61. In this example, the lifetime adjustment region 206 is formed after the emitter electrode 52 is formed. A mask 240, such as a resist, is formed on the emitter electrode 52. The mask 240 covers the area other than the first mesa portion 61. The semiconductor substrate 10 is heat-treated by irradiating it with a charged particle beam such as helium from above the mask 240. This allows the lifetime adjustment region 206 to be formed.

[0131] As described above, irradiation with charged particle beams lowers the threshold voltage of the first mesa portion 61. On the other hand, increasing the doping concentration of the base region 14 of the first mesa portion 61 raises the threshold voltage of the first mesa portion 61. Therefore, the variation in threshold voltage between the first mesa portion 61 and the second mesa portion 62 can be reduced.

[0132] Figure 5 shows an example of the doping concentration distribution along the s-s' line in Figure 3A. The s-s' line is a straight line parallel to the Z-axis that passes through the second mesa region 62-1 from the emitter region 12 to the lower end region 210.

[0133] In this example, the emitter region 12, base region 14, storage region 16, and lower end region 210 are formed by locally implanting dopant ions. Each region has a bell-shaped peak or maximum point in the doping concentration distribution. In Figure 5, the doping concentration in the drift region 18 is denoted as Dd. The doping concentration Dd may be the same as the bulk donor concentration of the semiconductor substrate 10, or it may be higher than the bulk donor concentration.

[0134] Let D2 be the second doping concentration in the base region 14 of the second mesa portion 62-1. Also, let D3 be the third doping concentration in the lower end region 210. In this example, the doping concentration in each region is the maximum value of the doping concentration in that region. The second doping concentration D2 may be higher than, the same as, or lower than the third doping concentration D3.

[0135] Figure 6 shows an example of the doping concentration distribution along the r-r' line in Figure 3A. The r-r' line is a straight line parallel to the Z-axis that passes through the first mesa region 61 from the emitter region 12 to a part of the drift region 18.

[0136] The doping concentration distribution in the emitter region 12 and the storage region 16 in this example is the same as in the example in Figure 5. Also, the drift region 18 in this example does not have a lower end region 210. In Figure 6, the doping concentration distribution in the base region 14 in the second mesa section 62-1 is shown by a dashed line. The base region 14 in the first mesa section 61 and the base region in the second mesa section 62-1 may be provided in the same depth range.

[0137] Let D1 be the first doping concentration in the base region 14 of the first mesa portion 61. In this example, the first doping concentration D1 is higher than the third doping concentration D3. Let ΔD be the difference in concentration between the first doping concentration D1 and the second doping concentration D2. As described above, the difference in concentration ΔD is greater than 0 and 50 times or less the third doping concentration D3 (see Figure 5). As explained in Figure 4, the base region 14 of the first mesa portion 61 is formed by the diffusion of the first injection region 231 and the second injection region 232. Therefore, the difference in concentration ΔD is a value corresponding to the doping concentration of the first injection region 231 and a value corresponding to the third doping concentration D3.

[0138] For example, in step S1002 shown in Figure 4, the first dopant may be injected while an oxide film is present on at least one of the inner walls of the first mesa portion 61 and the trench 45. In this case, depending on the presence and thickness of the oxide film, there may be a difference in the doping concentration of the first injection region 231 of the first mesa portion 61 and the doping concentration of the first injection region 231 at the lower end of the trench 45. For example, if a thick oxide film is present on the upper surface of the first mesa portion 61, the doping concentration of the first injection region 231 of the first mesa portion 61 will be lower. As a result, the differential concentration ΔD may be lower than the third doping concentration D3. Also, if a thick oxide film is present on the inner wall of the trench 45, the doping concentration of the first injection region 231 at the lower end of the trench 45 will be lower. As a result, the differential concentration ΔD may be higher than the third doping concentration D3. For this reason, the differential concentration ΔD will fluctuate within a range of, for example, 50 times or less of the third doping concentration D3. Alternatively, by controlling the thickness of the oxide film as described above, the differential concentration ΔD can be adjusted to a range of, for example, 50 times or less of the third doping concentration D3.

[0139] The third doping concentration D3 may be 0.01 times or more the second doping concentration D2. Increasing the third doping concentration D3 increases the differential concentration ΔD, making it easier to adjust the magnitude of the first doping concentration D1. The third doping concentration D3 may be 0.02 times or more the second doping concentration D2, and may also be 0.05 times or more. The third doping concentration D3 may be less than the second doping concentration D2.

[0140] For example, the first doping concentration D1 is 1 × 10⁻⁶ １７ / cm ３ The above is 1 x 10 １８ / cm ３ The following applies: The first doping concentration D1 is 2 × 10⁻⁶ １７ / cm ３ The above is sufficient, or 3 x 10 １７ / cm ３ The above is also acceptable. The first doping concentration D1 is 9 × 10 １７ / cm ３ The following may be used: 8 x 10 １７ / cm ３ The following is also acceptable.

[0141] For example, the second doping concentration D2 is 8 × 10 １６ / cm ３ The above 8 x 10 １７ / cm ３ The following applies: The second doping concentration D2 is 9 × 10 １６ / cm ３ The above is sufficient. 1 x 10 １７ / cm ３ The above is also acceptable. The second doping concentration D2 is 7 × 10 １７ / cm ３ The following is also acceptable: 6 x 10 １７ / cm ３ The following is also acceptable.

[0142] For example, the third doping concentration D3 is 1 × 10⁻⁶ １５ / cm ３ The above is 2 x 10 １７ / cm ３ The following applies: The third doping concentration D3 is 2 × 10⁻⁶ １５ / cm ３ The above is sufficient, or 3 x 10 １５ / cm ３ The above is also acceptable. The third doping concentration D3 is 1 × 10⁻⁶ １７ / cm ３ The following may be used: 9 x 10 １６ / cm ３ The following is also acceptable.

[0143] Figure 7 shows another example of the doping concentration distribution in the depth direction in the base region 14 of the first mesa 61. This doping concentration distribution has one or more inflection points 114 below the position where the doping concentration shows its maximum value D1 (i.e., on the lower surface 23 side). Let Z1 be the depth position where the doping concentration shows its maximum value D1, and Z2 be the depth position of the inflection point 114. An inflection point is the point where the sign of the second derivative changes when the doping concentration is second-orderly differentiated with respect to the depth position.

[0144] In the example described in Figure 4, the base region 14 of the first mesa portion 61 is formed by the diffusion of dopants from the first injection region 231 and the second injection region 232. The diffusion distribution of the dopant from the first injection region 231 and the diffusion distribution of the dopant from the second injection region 232 each have a bell-shaped form. Therefore, the base region 14 has a shape that is a superposition of the two bell-shaped distributions. For this reason, for example, if the injection position of the first dopant is located on the upper surface 21 side than the injection position of the second dopant, the doping concentration distribution of the base region 14 may have an inflection point 114.

[0145] The number of inflection points in the doping concentration distribution in the base region 14 of the second mesa section 62 is either zero or less than the number of inflection points 114 in the base region 14 of the first mesa section 61. In this example, there is one inflection point 114 in the base region 14 of the first mesa section 61, and zero inflection points in the base region 14 of the second mesa section 62.

[0146] The distance ΔZ from position Z1 to position Z2 is determined according to the width W3 in the depth direction of the lower end region 210. The width W3 of the lower end region 210 may be the full width at half maximum (FWHM) of the lower end region 210. The distance ΔZ may be less than or equal to the width W3, or less than or equal to half of the width W3. The distance ΔZ may be one-quarter or more of the width W3.

[0147] Figure 8 shows an example of the carrier concentration distribution along the r-r' line in Figure 3A. The carrier concentration distributions in the emitter region 12, base region 14, and storage region 16 are similar to the doping concentration distribution shown in Figure 6.

[0148] The carrier concentration in at least a portion of the drift region 18 below the first mesa section 61 may be lower than the bulk donor concentration. The carrier concentration in the drift region 18 may decrease as it moves away from the base region 14. For example, in the region from the base region 14 to the lifetime adjustment region 206, the carrier concentration in the drift region 18 may decrease as it moves away from the base region 14. In regions where charged particles have passed, the carrier lifetime decreases, so the carrier concentration decreases. On the other hand, as shown by the dashed line in Figure 8, the carrier concentration in the drift region 18 of the second mesa section 62 may be higher than that of the drift region 18 of the first mesa section 61.

[0149] In other examples, the carrier concentration in at least a portion of the drift region 18 below the first mesa section 61 may be higher than the bulk donor concentration. If hydrogen is present in this region, hydrogen donors may be generated by the hydrogen and defects caused by the passage of charged particles. In this case, the doping concentration and carrier concentration in this region will be higher than the bulk donor concentration. Furthermore, the doping concentration and carrier concentration in this region will be higher than the doping concentration and carrier concentration in the drift region 18 below the second mesa section 62. Also, as shown in Figures 5 and 6, the drift region 18 below the first mesa section 61 and the drift region 18 below the second mesa section 62 may have the same doping concentration distribution and carrier concentration distribution, except for the region where the lower end region 210 or the lifetime adjustment region 206 is provided.

[0150] Figure 9A shows another example of the XZ cross-section in the transistor section 70. In this example of the transistor section 70, the arrangement of the lower end region 210 and the lifetime adjustment region 206 differs from that of the example in Figure 3A. The other structures are the same as those in the example in Figure 3A.

[0151] In this example, at least a portion of the lower end region 210 and at least a portion of the lifetime adjustment region 206 are arranged to overlap in the depth direction of the semiconductor substrate 10. In the example of Figure 9A, a mesa portion 60 provided with both the lifetime adjustment region 206 and the lower end region 210 is designated as the first mesa portion 61-1, and a mesa portion 60 provided with the lifetime adjustment region 206 but without the lower end region 210 is designated as the first mesa portion 61-2. One or more first mesa portions 61-1 may be provided between the first mesa portion 61-2 and the second mesa portion 62-1.

[0152] Figure 9B shows another example of the XZ cross-section in the transistor section 70. The semiconductor device in this example differs from the example described in Figure 9A in the structure of the lower end region 210. The other structures are the same as those described in Figure 9A.

[0153] In the semiconductor device 100 of this example, similar to the example in Figure 3B, the lower end region 210 is not formed to extend into the adjacent element trench. Even in such a case, the presence of the lower end region 210 allows for control of the carrier distribution when the transistor 70 is energized, thereby obtaining good characteristics.

[0154] In the above and subsequent explanations, the doping concentration of the base region 14 of the first mesa portion 61 in contact with the gate trench portion 40 may be ΔD higher than the concentration of the base region 14 of the second mesa portion 62 in contact with the gate trench portion 40. In mesa portions 60 where a channel is not formed, such as when sandwiched between dummy trench portions 30, or in mesa portions 60 where the channel is not connected to the emitter region 12 and there is no electron injection, the doping concentration of the base region 14 may not be limited to this.

[0155] The first and second doping concentrations may be the doping concentrations of the base region 14 at the location in contact with the trench. For example, the first doping concentration may be the doping concentration of the base region 14 at the location in contact with the gate trench 40 in the first mesa 61. Similarly, the second doping concentration may be the doping concentration of the base region 14 at the location in contact with the gate trench 40 in the second mesa 62.

[0156] Figure 10A shows another example of the XZ cross-section of the transistor section 70. The semiconductor device 100 in this example differs from the example described in Figure 9A in the lower end region 210. The other structures are the same as those described in Figure 9A.

[0157] A gate trench section 40 in which a lifetime adjustment region 206 is provided below is designated as the first gate trench section 40-1. A gate trench section 40 in which a lifetime adjustment region 206 is not provided below is designated as the second gate trench section 40-2. Multiple first gate trench sections 40-1 and multiple second gate trench sections 40-2 may be provided.

[0158] A lower end region 210 may be provided at the lower end of at least one first gate trench section 40-1. A lower end region 210 may not be provided at the lower end of at least one second gate trench section 40-2. A lower end region 210 may be provided at the lower ends of multiple first gate trench sections 40-1. A lower end region 210 may not be provided at the lower ends of multiple second gate trench sections 40-2. In this example, a lower end region 210 is provided at the lower end of all first gate trench sections 40-1. Also, a lower end region 210 is not provided at the lower end of any of the second gate trench sections 40-2.

[0159] At least one lower end region 210 may be arranged to overlap with the lifetime adjustment region 206 in the depth direction. Multiple lower end regions 210 may be arranged to overlap with the lifetime adjustment region 206 in the depth direction. Lower end regions 210 may be provided only in positions that overlap with the lifetime adjustment region 206 in the depth direction. The lower end region 210 may be a lower end region 210 provided at the lower end of the gate trench portion 40. In the semiconductor device 100 of this example, all lower end regions 210 and the lifetime adjustment region 206 are arranged to overlap with the semiconductor substrate 10 in the depth direction.

[0160] At least one lower end region 210 may be in contact with the gate trench portion 40 but not with the dummy trench portion 30. At a position overlapping with the lifetime adjustment region 206 in the depth direction, at least one lower end region 210 may be in contact with the gate trench portion 40 but not with the dummy trench portion 30. In this example, the lower end region 210 is provided only below the gate trench portion 40 and is not formed at the lower end of the dummy trench portion 30. For example, the configuration of this example can be achieved by injecting the first dopant into the trench 45 that will become the gate trench portion 40, but not into the trench 45 that will become the dummy trench portion 30, and by not diffusing the lower end region 210 to the dummy trench portion 30. In this example, the lower end region 210 does not diffuse to adjacent trench portions and is not formed spanning across to adjacent dummy trench portions 30. However, the lower end region 210 may diffuse to adjacent trench portions. The lower end region 210 may extend to the center of the mesa portion 60 in the X-axis direction, or it may extend to a point before the center of the mesa portion 60 in the X-axis direction.

[0161] Figure 10B is a diagram illustrating some steps in the manufacturing method of the semiconductor device 100 shown in Figure 10A. In step S2002, a plurality of trenches 45 are formed from the upper surface 21 to the interior of the semiconductor substrate 10. The plurality of trenches 45 correspond to the plurality of trench sections described in Figure 10A. Each trench 45 is a hollow groove provided on the upper surface 21 of the semiconductor substrate 10. A trench section can be formed by providing an insulating film and a conductive part inside the trench 45.

[0162] In step S2002, a p-type first dopant for forming the lower end region 210 is injected through at least one trench 45. In step S2002, the first dopant may be injected into the lower end of at least one trench 45 having a lifetime adjustment region 206 below it. Having a lifetime adjustment region 206 below it means that the lifetime adjustment region 206 is formed below it when the semiconductor device 100 is completed. That is, this includes cases in which the lifetime adjustment region 206 is formed below it in a process after step S2002. The trench 45 may be a trench 45 that provides a gate trench portion 40. In step S2002, the first dopant may be injected into multiple trenches 45, or the first dopant may be injected into all of the trenches 45.

[0163] In step S2002, the first dopant does not need to be injected into the lower end of at least one trench 45 that does not have a lifetime adjustment region 206 below it. Not having a lifetime adjustment region 206 below it means that a lifetime adjustment region 206 is not formed below it when the semiconductor device 100 is completed. In other words, it means that a lifetime adjustment region 206 is not formed below it even in a step after step S2002. The trench 45 may be a trench 45 that has a gate trench portion 40. In step S2002, the first dopant does not need to be injected into multiple trenches 45, and the first dopant does not need to be injected into all of the trenches 45.

[0164] In this example, the trenches 45 that do not form the lower end region 210 are filled with a mask 230 such as a resist. The trenches 45 that form the lower end region 210 are not filled with the mask 230. That is, the trenches 45 that become the gate trench portion 40 adjacent to the first mesa portion 61 are not filled with the mask 230, while the other trenches 45 are filled with the mask 230. Also, in step S1002 explained using Figure 4, the upper surface of the second mesa portion 62 was covered with the mask 230, and the upper surface of the first mesa portion 61 was exposed without being covered with the mask 230. However, in this example, the gate trench portion 40 side of the first mesa portion 61 is exposed without being covered with the mask 230, while the dummy trench portion 30 side is covered with the mask 230. In this state, by injecting the first dopant ions into the entire active portion 160 or transistor portion 70, the first dopant is injected into the lower end of the trench 45, which becomes the gate trench portion 40 adjacent to the first mesa portion 61, and into the upper surface of the first mesa portion 61 on the gate trench portion 40 side, thereby forming the first injection region 231.

[0165] In step S2004, a p-type second dopant is injected into the regions where the base region 14 is to be formed in both the first mesa portion 61 and the second mesa portion 62. Step S2004 may be the same as step S1004 described with reference to Figure 4.

[0166] In step S2008, a lifetime adjustment region 206 is formed below the first mesa portion 61. Step S2008 may be the same as step S1008 described with reference to Figure 4. As described above, irradiation with charged particle beams lowers the threshold voltage of the first mesa portion 61. On the other hand, increasing the doping concentration of the base region 14 of the first mesa portion 61 raises the threshold voltage of the first mesa portion 61. Therefore, the variation in threshold voltage between the first mesa portion 61 and the second mesa portion 62 can be reduced. In this example as well, the relationship of the difference concentration, etc., described above may hold.

[0167] In the example shown in Figures 10A and 10B, the lower end region 210 does not diffuse to the adjacent element trench (dummy trench 30). Similarly, the first dopant injected into the gate trench 40 side of the first mesa 61 does not diffuse to the adjacent element trench (dummy trench 30). Therefore, the doping concentration of the base region 14 on the gate trench 40 side of the first mesa 61 may be higher than the doping concentration of the base region 14 on the dummy trench 30 side. That is, the peak of the doping concentration of the base region 14 on the dummy trench 30 side of the first mesa 61 may be greater than or equal to the peak D2 of the doping concentration of the base region 14 of the second mesa 62, and less than or equal to the peak D1 of the doping concentration of the base region 14 on the gate trench 40 side of the first mesa 61. However, the first dopant of the first mesa 61 may diffuse to the adjacent element trench. Even in that case, a concentration gradient may occur along the X-axis direction of the first mesa portion 61. That is, the doping concentration in the base region 14 on the gate trench portion 40 side of the first mesa portion 61 may be higher than the doping concentration in the base region 14 on the dummy trench portion 30 side.

[0168] Figure 10C shows an example of the carrier concentration distribution along the r-r' line in Figure 10A. The r-r' line in Figure 10A is a line that extends in the Z-axis direction from the gate trench 40-1 side of the center of the first mesa 61-1 in the X-axis direction, and passes through the emitter region 12, base region 14, storage region 16, and lower end region 210. The carrier concentration distribution in the emitter region 12, base region 14, and storage region 16 is similar to the doping concentration distribution shown in Figure 8 or Figure 6.

[0169] A lower end region 210 is formed below the gate trench portion 40-1 of the first mesa portion 61-1. The peak of the doping concentration in the base region 14 is D1. Furthermore, due to irradiation with charged particle beams, etc., the carrier concentration in the drift region 18 may be lower than the bulk donor concentration, as in Figure 8.

[0170] Figure 10D shows an example of the carrier concentration distribution along the s-s' line in Figure 10A. The s-s' line in Figure 10A is a line that extends in the Z-axis direction from the gate trench 40-2 side of the center of the second mesa 62-2 in the X-axis direction, and passes through the emitter region 12, the base region 14, and the storage region 16. The carrier concentration distribution in the emitter region 12, the base region 14, and the storage region 16 is the same as the doping concentration distribution shown in Figure 5.

[0171] A lower end region 210 is not formed below the gate trench portion 40-2 of the second mesa portion 62-2. The doping concentration peak in the base region 14 is D2.

[0172] As explained above using Figure 10B, when forming the mask 230 for forming the first injection region 231, if the mask 230 is formed to cover up to the center of the mesa portion 60, as explained using Figures 10A, 10C, and 10D, the lower end region 210 that contacts the gate trench portion 40 may be provided in the area that overlaps with the lifetime adjustment region 206 in a top view, and may not be provided in the area where the lifetime adjustment region 206 does not exist.

[0173] A trench section with a lower end region 210 is designated as the first trench section, and a trench section without a lower end region 210 is designated as the second trench section. In Figure 10A, the first trench section is the first gate trench section 40-1, which is located in a position overlapping with the lifetime adjustment region 206, and the second trench section is a trench section other than the first gate trench section 40-1.

[0174] The doping concentration of the base region 14 at the position in contact with the first trench may be higher than the doping concentration of the base region 14 at the position in contact with the second trench. For example, when manufacturing using the mask 230 shown in Figure 10B, the first dopant is also injected into the first trench side of the first mesa portion 61 adjacent to the first trench, so the doping concentration of the base region 14 at the position in contact with the first trench becomes higher.

[0175] In Figure 10A, a lower end region 210 may be provided at the lower end of at least one second gate trench portion 40-2. For example, a lower end region 210 may be formed at the lower end of a gate trench portion 40 that is sandwiched between second mesa portions 62 where the channel is not connected to the emitter region 12 and no electrons are injected. In this case, even if the doping concentration of the base region 14 of the second mesa portion 62 is high, the threshold voltage problem will not occur.

[0176] In the example shown in Figures 10A and 10B, when two dummy trench sections 30 are arranged adjacent to each other in a position overlapping with the lifetime adjustment region 206, the doping concentration of the base region 14 of the first mesa section 61 sandwiched between the two dummy trench sections 30 may be lower than the first doping concentration and equal to the second doping concentration. In other words, the first dopant does not need to be injected into the first mesa section 61. To put it another way, the doping concentration of the base region 14 of at least one first mesa section 61 may be lower than the first doping concentration and equal to the second doping concentration. The same may be true in the example shown in Figure 4 when the first dopant is not injected into the first mesa section 61.

[0177] In the example shown in Figure 4, when two dummy trench sections 30 are arranged adjacent to each other in a position that does not overlap with the lifetime adjustment region 206, the doping concentration of the base region 14 of the second mesa section 62 sandwiched between the two dummy trench sections 30 may be higher than the second doping concentration and equal to the first doping concentration. That is, the first dopant may be injected into the second mesa section 62. In other words, the doping concentration of at least one second mesa section 62 may be higher than the second doping concentration and equal to the first doping concentration. In the above explanation, we have dealt with a mesa section 60 sandwiched between two dummy trench sections 30, but the doping concentration of the base region 14 in contact with the dummy trench section 30 may be similar. For example, if the first injection region 231 in contact with the dummy trench section 30 does not diffuse to the adjacent gate trench section 40, the same concentration relationship as above may occur.

[0178] In the example shown in Figure 10B, the first injection region 231 formed on the upper surface 21 of the first mesa portion 61 is injected to a range further away in the X-axis direction from the gate trench portion 40 than the first injection region 231 formed at the lower end of the adjacent gate trench portion 40. Therefore, the first injection region 231 of the first mesa portion 61 may diffuse to a position further away in the X-axis direction from the gate trench portion 40 than the first injection region 231 of the gate trench portion 40.

[0179] In Figure 10A, the lower end region 210 is provided only at the lower end of the gate trench portion 40 that is in contact with the first mesa portion 61, but the lower end region 210 may also be formed at the lower end of the dummy trench portion 30 in the area that overlaps with the lifetime adjustment region 206. The first dopant of the first injection region 231 injected into the lower end of the gate trench portion 40 in step S2002 may diffuse to form the lower end region 210, and the trench 45 that becomes the dummy trench portion 30 and the dummy trench portion 30 side of the adjacent first mesa portion 61 may also be exposed without forming a mask 230 so that the first injection region 231 is provided.

[0180] The lower end region 210 may diffuse and connect with the lower end region 210 provided at the lower end of an adjacent trench section. For example, in Figure 10A, the lower end region 210 may also be formed at the lower end of the dummy trench section 30, and the lower end region 210 of the gate trench section 40 and the lower end region 210 of the dummy trench section 30 may be connected. In other examples, the lower end region 210 may not diffuse, and the lower end region 210 of the gate trench section 40 may be separated from the lower end region 210 of the dummy trench section 30.

[0181] In another example, in step S2002, the trench 45 which will become the dummy trench portion 30 and the dummy trench portion 30 side of the adjacent first mesa portion 61 may be exposed to form the first injection region 231, the other areas may be covered with a mask 230, and the first dopant in the first injection region 231 may diffuse to the gate trench portion 40. In other words, it is not necessary to form the first injection region 231 at the lower end of at least one first gate trench portion 40-1. Furthermore, when using the mask 230 in the example of Figure 4, the mesa portion 60 and trench to which the first dopant is injected can be arbitrarily selected. Therefore, even if the first injection region 231 is not formed at the lower end of the gate trench portion 40, a configuration can be achieved in which the doping concentration of the base region 14 of the first mesa portion 61 in contact with the gate trench portion 40 is ΔD higher than the concentration of the base region 14 of the second mesa portion 62 in contact with the gate trench portion 40, regardless of the degree of diffusion of the first injection region 231.

[0182] In Figure 10A, the lower end region 210 is provided only at the lower end of the gate trench portion 40 that is in contact with the first mesa portion 61, but the lower end region 210 may also be formed at the lower end of the dummy trench portion 30 in a range that does not overlap with the lifetime adjustment region 206. In step S2002, it is preferable to manufacture the product in such a way that the dummy trench portion 30 side of the second mesa portion 62 and the first dopant of the first injection region 231 injected into the dummy trench portion 30 do not diffuse to the gate trench portion 40 side.

[0183] The semiconductor device 100 shown in Figure 10A may also be manufactured by the manufacturing method described using Figure 4. That is, in step S1002, the entire first mesa portion 61 in contact with the trench 45 (which becomes the gate trench portion 40) having a first injection region 231 at its lower end may be exposed without being covered by the mask 230, while the other mesa portions 60 may be covered by the mask 230. Even in this case, the doping concentration of the base region 14 of the first mesa portion 61 is higher than that of the base region 14 of the second mesa portion 62, and the gate trench portion 40 in contact with the first mesa portion 61 has a lower end region 210 at its lower end, while the gate trench portion 40 in contact with the second mesa portion 62 does not have a lower end region 210 at its lower end.

[0184] In the manufacturing method shown in Figure 10B, a case is described in which two gate trench sections 40 are arranged adjacent to each other, a first injection region 231 is formed at the lower end of the gate trench section 40, and a first injection region 231 is not formed at the lower end of the dummy trench section 30. When the first dopant injected into the upper surface 21 of the first mesa section 61 diffuses to the end of the first mesa section 61, the doping concentration of the base region 14 of the first mesa section 61 sandwiched between the two gate trench sections 40 becomes higher than the doping concentration of the base region 14 of the first mesa section 61 sandwiched between the gate trench section 40 and the dummy trench section 30. However, the difference in doping concentrations may be smaller than the difference between the first doping concentration and the second doping concentration. Regardless of which of the above doping concentrations is taken as the first doping concentration, the above-described relationship of the first doping concentration may hold.

[0185] In the manufacturing method shown in Figure 10B, the first injection region 231 may be formed over the entire upper surface 21 of at least one first mesa portion 61 (referred to as a double-sided mesa portion). In other words, the first injection region 231 may be formed at the lower ends of both trench portions flanking the first mesa portion 61. In the other first mesa portion 61 (referred to as a single-sided mesa portion), the cut in the mask 230 may be located so that the first injection region 231 is formed over approximately half the area of ​​the first mesa portion 61 in the X-axis direction. When the first injection region 231 diffuses to the end of the first mesa portion 61, the doping concentration of the base region 14 of the single-sided mesa portion (single-sided doping concentration) becomes smaller than the doping concentration of the base region 14 of the double-sided mesa portion (double-sided doping concentration). However, the difference between the single-sided doping concentration and the double-sided doping concentration may be smaller than the difference between the first doping concentration and the second doping concentration. Regardless of whether the first doping concentration is a one-sided doping concentration or a two-sided doping concentration, the above-described relationship for the first doping concentration may still hold true.

[0186] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0187] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0188] 10... Semiconductor substrate, 11... Well region, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 18... Drift region, 20... Buffer region, 21... Top surface, 22... Collector region, 23... Bottom surface, 24... Collector electrode, 29... Straight section, 30... Dummy trench section, 31... Tip section, 32... Dummy insulating film, 34... Dummy conductive section, 38... Interlayer insulating film, 39... Straight section, 40... Gate trench section, 41... Tip section, 42... Gate insulating film, 44... Gate conductive section, 45... Trench, 52... Emitter electrode, 54 ...Contact hole, 60...Mesa section, 61...First mesa section, 62...Second mesa section, 70...Transistor section, 80...Diode section, 81...Extension region, 82...Cathode region, 90...Edge termination structure section, 100...Semiconductor device, 114...Inflection point, 130...Outer gate wiring, 131...Active side gate wiring, 160...Active section, 162...Edge, 164...Gate pad, 200...Boundary region, 204...Lattice defect, 206...Lifetime adjustment region, 210...Lower end region, 230...Mask, 231...First injection region, 232...Second injection region, 240...Mask

Claims

1. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type, comprising: a plurality of trench portions arranged in a first direction and each extending from the upper surface to the interior of the semiconductor substrate; a lifetime adjustment region provided on the upper surface side of the semiconductor substrate for adjusting the lifetime of carriers; a plurality of mesa portions sandwiched between two of the trench portions in the semiconductor substrate; and a lower end region of a second conductivity type provided in contact with the lower end of at least one of the trench portions, wherein each of the plurality of mesa portions has a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate, and the plurality of mesa portions include a first mesa portion with the lifetime adjustment region provided below it and a second mesa portion without the lifetime adjustment region provided below it, wherein the difference concentration obtained by subtracting the second doping concentration of the base region of the second mesa portion from the first doping concentration of the base region of the first mesa portion is greater than 0 and 50 times or less the third doping concentration of the lower end region.

2. The semiconductor device according to claim 1, wherein the differential concentration is 0.1 times or more the third doping concentration.

3. The semiconductor device according to claim 1, wherein the differential concentration is 30 times or less the third doping concentration.

4. The semiconductor device according to claim 1, wherein the differential concentration is equal to the third doping concentration.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first doping concentration is higher than the third doping concentration.

6. The semiconductor device according to any one of claims 1 to 4, wherein at least a portion of the lower end region and at least a portion of the lifetime adjustment region are arranged to overlap in the depth direction of the semiconductor substrate.

7. The semiconductor device according to any one of claims 1 to 4, wherein the lower end region and the lifetime adjustment region are arranged without overlapping in the depth direction of the semiconductor substrate.

8. The semiconductor device according to any one of claims 1 to 4, wherein the trench portion in contact with the first mesa portion is not provided with the lower end region.

9. The first doping concentration is 1 × 10 １７ / cm ３ The above is 1 x 10 １８ / cm ３ The semiconductor device according to any one of claims 1 to 4 below.

10. The second doping concentration is 8 × 10 １６ / cm ３ The above 8 x 10 １７ / cm ３ The semiconductor device according to any one of claims 1 to 4 below.

11. The third doping concentration is 1×10 １５ / cm ３ or more and 2×10 １７ / cm ３ or less. The semiconductor device according to any one of claims 1 to 4.

12. The semiconductor device according to any one of claims 1 to 4, wherein the doping concentration distribution in the depth direction in the base region of the first mesa portion has one or more inflection points below the position where the doping concentration shows the maximum value.

13. The semiconductor device according to any one of claims 1 to 4, wherein the plurality of trench portions include a first gate trench portion in which the lifetime adjustment region is provided below, and a second gate trench portion in which the lifetime adjustment region is not provided below, and the lower end of the first gate trench portion is provided with the lower end region, and the lower end of the second gate trench portion is not provided with the lower end region of the second conductivity type.

14. The semiconductor device according to any one of claims 1 to 4, wherein the plurality of trench portions include gate trench portions and dummy trench portions provided adjacent to each other in the first direction, and the lower end region is in contact with the gate trench portions but not with the dummy trench portions.

15. A method for manufacturing a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, wherein the semiconductor device comprises a plurality of trench portions provided in a first direction and each extending from the upper surface to the interior of the semiconductor substrate, a lifetime adjustment region provided on the upper surface side of the semiconductor substrate for adjusting the lifetime of carriers, a plurality of mesa portions sandwiched between two of the trench portions in the semiconductor substrate, and a lower end region of a second conductivity type provided in contact with the lower end of at least one of the trench portions, each of the plurality of mesa portions having a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate, the plurality of mesa portions including a first mesa portion with the lifetime adjustment region provided below it and a second mesa portion without the lifetime adjustment region provided below it, and the manufacturing method comprising forming a plurality of trenches provided from the upper surface to the interior of the semiconductor substrate, A manufacturing method comprising the step of injecting a first dopant to form the lower end region through at least one trench, wherein the first dopant is also injected into the first mesa portion.

16. The manufacturing method according to claim 15, wherein a second dopant of the second conductivity type is injected into the region in which the base region is to be formed in both the first mesa portion and the second mesa portion.

17. The manufacturing method according to claim 15 or 16, wherein the first dopant is injected into the lower end of at least one trench having a lifetime adjustment region below it and a gate trench portion, and the first dopant is not injected into the lower end of at least one trench having a gate trench portion that does not have a lifetime adjustment region below it.

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