Diamond semiconductor device, semiconductor module, and diamond semiconductor device production method

Abstract

Provided is a diamond semiconductor device comprising a trench part on a front surface, the diamond semiconductor device comprising: a diamond layer; an epitaxial layer of diamond provided on the diamond layer; a front surface-side insulating film provided over the epitaxial layer; and a front surface-side electrode provided on the front surface-side insulating film. The front surface-side insulating film includes a first insulating film provided inside a trench of the trench part, a first buried insulating film provided on the inner side of the first insulating film inside the trench, and a second insulating film provided over the first buried insulating film inside the trench. The front surface-side electrode is provided on the inner side of the second insulating film inside the trench.

Description

Diamond semiconductor device, semiconductor module, and method for manufacturing a diamond semiconductor device.

[0001] The present invention relates to a diamond semiconductor device, a semiconductor module, and a method for manufacturing a diamond semiconductor device.

[0002] Patent Document 1 discloses a diamond semiconductor device having a trench structure. [Prior Art Documents] [Patent Documents] Patent Document 1 Japanese Unexamined Patent Publication No. 2017-092398 General disclosure

[0003] (Problem to be solved) It is desirable to improve the reliability of diamond semiconductor devices. (Means for solving the problem)

[0004] In a first embodiment of the present invention, a diamond semiconductor device having a trench portion on its front surface is provided, comprising: a diamond layer; a diamond epitaxial layer provided on the diamond layer; a front-side insulating film provided above the epitaxial layer; and a front-side electrode provided on the front-side insulating film, wherein the front-side insulating film comprises: a first insulating film provided inside the trench of the trench portion; a first embedded insulating film provided inside the first insulating film within the trench; and a second insulating film provided above the first embedded insulating film within the trench; and the front-side electrode provided inside the second insulating film within the trench.

[0005] A second embodiment of the present invention provides a semiconductor module comprising a diamond semiconductor device.

[0006] In a third aspect of the present invention, there is provided a method for manufacturing a diamond semiconductor device having a trench portion on a front surface, the method comprising: forming a trench on the front surface of a diamond layer; forming a diamond epitaxial layer inside the trench; forming a first insulating film inside the epitaxial layer; forming a first buried insulating film inside the first insulating film; etching a part of the first insulating film; forming a second insulating film above the first buried insulating film inside the trench; and forming the front surface side electrode inside the second insulating film inside the trench.

[0007] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

[0008] An example of the configuration of a diamond semiconductor device 100 is shown. It is an enlarged view of the vicinity of the trench portion 50 in FIG. 1A. An example of a top view of the diamond semiconductor device 100 is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 1A is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 1A is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 1A is shown. A modified example of the diamond semiconductor device 100 is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 4A is shown. A modified example of the diamond semiconductor device 100 is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 5A is shown. An example of a method for manufacturing the diamond semiconductor device 100 in FIG. 5A is shown. A modified example of the diamond semiconductor device 100 is shown. A modified example of the diamond semiconductor device 100 is shown. A modified example of the diamond semiconductor device 100 is shown. An example of a method for manufacturing a comparative example diamond semiconductor device 500 is shown. An outline of the configuration of a semiconductor module 200 is shown.

[0009] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

[0010] Figure 1A shows an example of the configuration of a diamond semiconductor device 100. The diamond semiconductor device 100 in this example is an example of a semiconductor device that functions as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The diamond semiconductor device 100 includes a diamond layer 15. The diamond layer 15 has a support layer 10 and a doped region 20. The diamond layer 15 has the support layer 10 on the back surface 12 side and the doped region 20 on the front surface 11 side. The diamond semiconductor device 100 in this example includes a trench portion 50 on the front surface 11.

[0011] The support layer 10 may be a P-type substrate made of diamond. The doping concentration of the P-type dopant in the support layer 10 may be 1×10 １９ cm －３ or more. The doping concentration of the support layer 10 may be 3×10 １９ cm －３ or more and 5×10 ２１ cm －３ or less. The support layer 10 may contain a P-type dopant. The P-type dopant may be a group III element such as boron (B), aluminum (Al), or gallium (Ga). The support layer 10 in this example is P+, but is not limited to this. The diamond semiconductor device 100 in this example has a gate structure on the front surface 11 side.

[0012] In this specification, one side in the direction parallel to the depth direction of the support layer 10 is referred to as "up" and the other side as "down". Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other as the lower surface. The directions of "up", "down", "front", and "back" are not limited to the gravitational direction or the mounting direction to the substrate or the like when mounting the semiconductor device.

[0013] In this specification, technical matters may be described using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, the orthogonal axes parallel to the upper and lower surfaces of the support layer 10 are the X-axis and Y-axis. Also, the axis perpendicular to the upper and lower surfaces of the support layer 10 is the Z-axis. The Z-axis direction is the depth direction of the support layer 10. In this specification, the top view refers to the viewpoint seen from the positive side to the negative side in the Z-axis direction.

[0014] In this specification, the doping concentration of a dopant may be the concentration of the intentionally introduced dopant. That is, the doping concentration of the dopant may not include the doping concentration of impurities remaining unintentionally. The dopant may be introduced during epitaxial growth or may be implanted after growth.

[0015] The doped region 20 is provided above the support layer 10. The doped region 20 in this example includes both a region containing an N-type dopant and a region containing a P-type dopant. The N-type dopant may be a Group V element such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga).

[0016] The doped region 20 may be a region epitaxially grown on the support layer 10. The doped region 20 may be formed by a microwave-excited plasma chemical vapor deposition method (MPCVD: Microwave Plasma Chemical Vapor Deposition). The N-type dopant and the P-type dopant may be introduced during epitaxial growth or may be introduced by other methods such as ion implantation after epitaxially growing a non-doped diamond layer. The doped region 20 in this example has a first doped layer 21, a second doped layer 22, and a third doped layer 23.

[0017] The first doped layer 21 is provided above the support layer 10. The first doped layer 21 in this example is provided in contact with the upper surface of the support layer 10. The first doped layer 21 in this example contains a P-type dopant. The first doped layer 21 in this example is P+. The doping concentration of the first doped layer 21 may be the same as or different from the doping concentration of the support layer 10. The doping concentration of the first doped layer 21 is 3×10 １９ cm －３ or more and 5×10 ２１ cm －３ or less.

[0018] The thickness of the first doped layer 21 may be thinner than the thickness of the support layer 10. The thickness of the first doped layer 21 may be thicker than the thickness of the second doped layer 22 and thicker than the thickness of the third doped layer 23. The first doped layer 21 may be a diamond substrate. That is, the first doped layer 21 may not be a layer epitaxially grown on the support layer 10, but may constitute the support layer 10 and a diamond substrate.

[0019] In this example, the first doped layer 21 is a P+ type region in contact with the epitaxial layer 30. The first doped layer 21 may be in contact with the epitaxial layer 30 provided on the side wall of the trench portion 50, or it may be in contact with the epitaxial layer 30 provided on the bottom surface of the trench portion 50. The upper end of the first doped layer 21 may be provided above the bottom surface of the trench portion 50. The lower end of the first doped layer 21 may be provided below the bottom surface of the trench portion 50.

[0020] The second doping layer 22 is provided above the first doping layer 21. In this example, the second doping layer 22 is provided on the first doping layer 21. The second doping layer 22 contains a P-type dopant. In this example, the second doping layer 22 is P-type. The doping concentration of the P-type dopant in the second doping layer 22 may differ from the doping concentration of the P-type dopant in the first doping layer 21. The doping concentration of the P-type dopant in the second doping layer 22 may be lower than the doping concentration of the P-type dopant in the first doping layer 21. The doping concentration of the second doping layer 22 may be lower than the doping concentration of the first doping layer 21. The doping concentration of the second doping layer 22 is 1 × 10⁻⁶. １６ cm －３ The above 5 x 10 １７ cm －３ The following is acceptable:

[0021] The thickness of the second dope layer 22 may be thinner than the thickness of the support layer 10 and thinner than the thickness of the first dope layer 21. The thickness of the second dope layer 22 may be 0.2 μm or more and 5.0 μm or less. The thickness of the second dope layer 22 may be 0.5 μm or more and 3.0 μm or less. By providing the second dope layer 22 between the front electrode 110 of the trench portion 50 and the first dope layer 21, the dielectric breakdown voltage can be improved. The doping concentration and thickness of the N-type dopant in the second dope layer 22 may be determined considering the dielectric breakdown voltage of the diamond semiconductor device 100, etc.

[0022] The third doping layer 23 is provided above the second doping layer 22. In this example, the third doping layer 23 is provided on the second doping layer 22. In this example, the third doping layer 23 contains an N-type dopant. The doping concentration of the third doping layer 23 is 1 × 10⁻⁶. １７ cm －３ The above is 1 x 10 ２１ cm －３ The following may apply: The doping concentration and thickness of the N-type dopant in the third doping layer 23 may be determined considering the breakdown voltage of the diamond semiconductor device 100. Furthermore, by increasing the doping concentration of the N-type dopant in the third doping layer 23, leakage current in the off state can be more easily suppressed.

[0023] The thickness of the third doping layer 23 may be the same as or different from the thickness of the first doping layer 21 and the second doping layer 22. The thickness of the third doping layer 23 may be thinner than the thickness of the first doping layer 21 and thinner than the thickness of the second doping layer 22. The thickness of the third doping layer 23 may be 0.2 μm or more and 3.0 μm or less.

[0024] The interface 101 is the boundary between the second doped layer 22 and the third doped layer 23. The diamond semiconductor device 100 can improve its dielectric breakdown voltage by mitigating the electric field concentration near the interface 101.

[0025] The epitaxial layer 30 is provided on the diamond layer 15. In this example, the epitaxial layer 30 is provided on the doped region 20, but if the support layer 10 is exposed in the trench T of the trench portion 50, it may also be provided on the support layer 10. The epitaxial layer 30 is made of diamond. The epitaxial layer 30 may be formed after the trench T of the trench portion 50 is formed in the doped region 20. The epitaxial layer 30 is in contact with the first doped layer 21 at the bottom surface of the trench portion 50, but may also be in contact with the support layer 10.

[0026] The trench T may be a depression formed by etching the diamond layer 15. The side walls and bottom surface of the trench T may be made of the diamond layer 15. In this example, the side walls of the trench T are made of a first doped layer 21, a second doped layer 22, and a third doped layer 23. In this example, the bottom surface of the trench T is made of the first doped layer 21.

[0027] The thickness of the epitaxial layer 30 may be 10 nm or more and 500 nm or less. The thickness of the epitaxial layer 30 may be 10 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may be 30 nm or more and 100 nm or less. By making the thickness of the epitaxial layer 30 thinner, the distance over which holes penetrate the epitaxial layer 30 when the diamond semiconductor device 100 is turned on is shortened, and the on-resistance can be reduced.

[0028] The doping concentration of the epitaxial layer 30 is 1 × 10⁻⁶ １３ cm －３ The above is 1 x 10 １６ cm －３ The following may apply: The epitaxial layer 30 may contain an N-type dopant. The N-type dopant may be nitrogen. The doping concentration of the N-type dopant in the epitaxial layer 30 may be lower than that in the doped region 20. The doping concentration of the N-type dopant in the epitaxial layer 30 is 1 × 10⁻⁶. １３ cm －３ The above is 1 x 10 １６ cm －３The following is possible: By reducing the doping concentration of the N-type dopant in the epitaxial layer 30, when holes from the terminal layer 40 flow into the epitaxial layer 30, penetrate the epitaxial layer 30 and flow into the first doping layer 21 and then to the support layer 10, the potential barrier within the epitaxial layer 30 is reduced, thereby reducing the on-resistance.

[0029] The epitaxial layer 30 may contain a P-type dopant. The doping concentration of the P-type dopant in the epitaxial layer 30 may be set to a range that allows the gate to be switched on and off. In one example, the doping concentration of the P-type dopant in the epitaxial layer 30 is 1 × 10⁻⁶. １３ cm －３ The above is 1 x 10 １６ cm －３ The following applies:

[0030] The termination layer 40 is provided on the epitaxial layer 30. In this example, the termination layer 40 is provided between the epitaxial layer 30 and the front-side insulating film 120. The termination layer 40 may be a layer that induces two-dimensional hole gas (2DHG) in the epitaxial layer 30. The conductivity of the termination layer 40 may be low enough to achieve normally-off characteristics. The thickness of the termination layer 40 may be 20 nm or less, or 0.1 nm or more.

[0031] The termination layer 40 may be a hydrogen-terminated layer, a silicon oxide-terminated layer, or may contain both hydrogen-terminated and silicon oxide-terminated regions. The termination layer 40 may be hydrogen-terminated by hydrogen radical irradiation, or silicon oxide-terminated by a reduction reaction of silicon dioxide and diamond in a high-temperature atmosphere.

[0032] The termination layer 40 includes a C-H bond, a C-O bond, a C-Si bond, a C-Si-O bond, a C-F bond, a C-OH bond, a C-N bond, or a C-NH bond. ２It may include at least one type of bond. The terminal layer 40 may have the same bond throughout its entire region, or it may have different bonds in each region. The terminal layer 40 may have the same bond across its entire surface between the epitaxial layer 30 and the front-side insulating film 120. The terminal layer 40 may have C-H bonds across its entire surface between the epitaxial layer 30 and the front-side insulating film 120.

[0033] The termination layer 40 in this example has a first termination portion 41 and a second termination portion 42. The first termination portion 41 is provided between the epitaxial layer 30 and the first insulating film 121. The second termination portion 42 is provided between the epitaxial layer 30 and the second insulating film 122. The surface treatment and bonding types of the first termination portion 41 and the second termination portion 42 may be the same or different. The first termination portion 41 may be a layer that induces a two-dimensional hole gas. The second termination portion 42 may be a layer that induces a two-dimensional hole gas to the extent that the gate electrode 114 can achieve normally-off characteristics.

[0034] The front-side insulating film 120 is provided above the epitaxial layer 30. In this example, the front-side insulating film 120 has a first insulating film 121, a second insulating film 122, and a first embedded insulating film 221. The material of the front-side insulating film 120 is aluminum oxide (Al ２ O ３ ), silicon oxide (SiO ２ ), silicon nitride (SiNx), hafnium oxide (HfO ２ ), hafnium silicate (HfSiO ４ It may contain at least one of ) or boron nitride (BN). The front-side insulating film 120 may be formed by methods such as atomic layer deposition (ALD) or CVD.

[0035] The first insulating film 121 is provided inside the trench T of the trench portion 50. The first termination portion 41 is provided above the epitaxial layer 30. The first insulating film 121 may be provided along the side walls and bottom surface of the trench portion 50. That is, the first insulating film 121 may be provided in a U-shape inside the trench portion 50. The first insulating film 121 may be in contact with the first termination portion 41. In this example, the first insulating film 121 is provided in the trench portion 50 so as to cover the side walls and bottom surface of the first embedded insulating film 221. The first insulating film 121 may be provided below the front surface 11 of the diamond layer 15.

[0036] The second insulating film 122 is provided inside the trench T, above the first embedded insulating film 221. The second termination portion 42 is provided above the epitaxial layer 30. The second insulating film 122 may be in contact with the second termination portion 42. In this example, the second insulating film 122 is provided in the trench portion 50, covering the side wall and bottom surface of the front electrode 110. That is, the second insulating film 122 may be provided in a U-shape inside the trench portion 50. The second insulating film 122 may cover the upper surface of the first embedded insulating film 221.

[0037] In this example, the second insulating film 122 is in contact with the gate electrode 114. As a result, the second insulating film 122 may function as a gate insulating film. The second insulating film 122 has a thickness that can be gate-controlled by the gate electrode 114. The thickness of the second insulating film 122 may be 50 nm or more and 200 nm or less. The thickness of the second insulating film 122 may be 50 nm or more and 100 nm or less. The thickness of the second insulating film 122 may be 10 nm or more and 50 nm or less. The thickness of the second insulating film 122 is, for example, 100 nm.

[0038] The material of the second insulating film 122 is Al ２ O ３ SiO ２ SiNx, HfO ２ , HfSiO ４ Or it may include at least one of BN. ２ O ３The composition does not necessarily have to be Al:O = 2:3. The second insulating film 122 may be a single layer or may have a laminated structure with different materials stacked on top of each other. In this example, the second insulating film 122 is a single layer of Al formed by the ALD method. ２ O ３ That is the case.

[0039] The material of the second insulating film 122 may be the same as the material of the first insulating film 121. The materials of the first insulating film 121 and the second insulating film 122 are Al ２ O ３ It may be so. The material of the second insulating film 122 may be different from the material of the first insulating film 121. In this case, the material of the first insulating film 121 may be Al ２ O ３ It may be the case that the material of the second insulating film 122 is SiO ２ This may be the case. However, the materials of the first insulating film 121 and the second insulating film 122 are not limited to these.

[0040] The front-side electrode 110 is provided above the diamond layer 15. In this example, the front-side electrode 110 is provided on the front-side insulating film 120. In this example, the front-side electrode 110 provided inside the trench T is a gate electrode 114. The front-side electrode 110 may be provided on the second insulating film 122 inside the trench T. The front-side electrode 110 is provided inside the second insulating film 122 inside the trench T. In this example, the front-side electrode 110 inside the trench T is a gate electrode 114, but it may also be a source electrode 116. The front-side electrode 110 inside the trench T may be at a floating potential. The front-side electrode 110 may have any electrode material such as aluminum (Al). The symbol G indicates the region of the front-side electrode 110 that is the gate electrode 114.

[0041] The interior of the trench T in the trench portion 50 may be filled with the front-side insulating film 120 and the front-side electrode 110. Filling the interior of the trench T in the trench portion 50 with the front-side insulating film 120 and the front-side electrode 110 may mean filling the inside of the epitaxial layer 30 and the termination layer 40 formed in the trench T with the front-side insulating film 120 and the front-side electrode 110. In this example, the interior of the trench T is filled with the inside of the epitaxial layer 30 and the termination layer 40 formed in the trench T with the first insulating film 121, the second insulating film 122, the first embedded insulating film 221 and the gate electrode 114.

[0042] The first embedded insulating film 221 is provided inside the trench T, on the inside of the first insulating film 121. The first embedded insulating film 221 may fill the inside of the first insulating film 121. The first embedded insulating film 221 may be provided below the front surface 11 of the diamond layer 15. The bottom surface of the first embedded insulating film 221 may be in contact with the first insulating film 121. The side walls of the first embedded insulating film 221 may be in contact with the first insulating film 121. The top surface of the first embedded insulating film 221 may be in contact with the second insulating film 122. The material of the first embedded insulating film 221 is Al ２ O ３ SiO ２ SiNx, HfO ２ , HfSiO ４ Or it may include at least one of BN. The material of the first embedded insulating film 221 is SiO ２ It may be SiNx. The material of the first embedded insulating film 221 may be the same as or different from the material of the first insulating film 121.

[0043] The gate electrode 114 is provided inside the trench T, above the first embedded insulating film 221. In this example, the gate electrode 114 is provided on the second insulating film 122. The bottom surface of the gate electrode 114 may be in contact with the top surface of the second insulating film 122. The side walls of the gate electrode 114 may be in contact with the second insulating film 122. The gate electrode 114 may also be provided above the front surface 11. In this example, the gate electrode 114 is provided outside the trench T, on the top surface of the second insulating film 122.

[0044] The trench portion 50 is provided extending in the depth direction of the diamond layer 15. The trench portion 50 includes an epitaxial layer 30, a termination layer 40, a front-side electrode 110, and a front-side insulating film 120 provided inside the trench T. The termination layer 40 may be omitted. The lower end of the trench portion 50 may be deeper than the upper end of the first doped layer 21. That is, the trench portion 50 may extend inside the first doped layer 21. The lower end of the trench portion 50 may be deeper than the upper end of the support layer 10.

[0045] The trench width of the trench portion 50 may be 100 nm or more and 10 μm or less. The trench width of the trench portion 50 may be the width of the trench portion 50 at its upper end. In this example, the upper end of the trench portion 50 is the gate electrode 114 at the height of the front surface 11. The depth of the trench T may be 60 nm or more and 20 μm or less. The aspect ratio of the trench portion 50 may be 2 or more and 20 or less.

[0046] The bottom surface of the trench section 50 may be in contact with the first dope layer 21. The entire bottom surface of the trench section 50 may be in contact with the first dope layer 21, or a part of the bottom surface of the trench section 50 may be in contact with the first dope layer 21. The side walls of the trench section 50 may be in contact with the first dope layer 21.

[0047] The contact region 60 is provided above the epitaxial layer 30. The contact region 60 may be provided in contact with the source electrode 116. The contact region 60 may contain a P-type dopant. In this example, the contact region 60 is P+ type, but is not limited to this. The doping concentration of the contact region 60 in this example may be the same as or different from the doping concentration of the support layer 10. The doping concentration of the contact region 60 may be greater than or less than the doping concentration of the support layer 10. The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type dopant may be introduced during epitaxial growth, or it may be introduced by other methods such as ion implantation after epitaxial growth of the undoped diamond layer. The thickness of the contact region 60 may be greater than or less than the thickness of the epitaxial layer 30.

[0048] The source electrode 116 is provided above the diamond layer 15. The source electrode 116 may be provided on the front surface 11 side of the diamond layer 15. The source electrode 116 may be provided on the contact region 60. When viewed from above, the source electrode 116 may be provided in the same region as the contact region 60, or a part of it may be provided in a different region. The source electrode 116 may be a laminated film of titanium (Ti) and gold (Au). The source electrode 116 may be a laminated film of titanium (Ti), platinum (Pt), and gold (Au). A source voltage may be applied to the source electrode 116 provided on the front surface 11 side of the diamond layer 15. The symbol S indicates the region of the source electrode 116.

[0049] The drain electrode 130 is provided on the back surface 12 side of the diamond layer 15. The drain electrode 130 may be provided over the entire back surface 12 or on a part of the back surface 12. The drain electrode 130 may be a laminated film of titanium (Ti) and gold (Au). The drain electrode 130 may be a laminated film of titanium (Ti), platinum (Pt), and gold (Au). In this example, the drain electrode 130 is provided in contact with the back surface 12 of the support layer 10. A drain-source voltage may be applied to the drain electrode 130 provided on the back surface 12 side of the diamond layer 15. The symbol D indicates the region of the drain electrode 130.

[0050] In this example, the diamond semiconductor device 100 is provided with a gate electrode 114 and a source electrode 116 on the front surface 11 side of the diamond layer 15, and a drain electrode 130 on the back surface 12 side of the diamond layer 15. When the diamond semiconductor device 100 is turned on, current flows from the source electrode 116 to the contact region 60 and then to the termination layer 40, causing holes to penetrate the epitaxial layer 30 and move into the support layer 10, and current flows to the drain electrode 130.

[0051] In this example, the case where the diamond semiconductor device 100 is a P-channel field-effect transistor has been described, but the diamond semiconductor device 100 may also be an N-channel field-effect transistor. When the diamond semiconductor device 100 functions as an N-channel field-effect transistor, the P-type dopant may be replaced with an N-type dopant, and vice versa.

[0052] In this example, the diamond semiconductor device 100 can mitigate electric field concentration by providing the front-side electrode 110 near the interface 101 inside the trench T. Furthermore, the dielectric breakdown voltage of the diamond semiconductor device 100 can be improved by separating the front-side electrode 110 of the trench portion 50 from the P+ type first doping layer 21. In addition, by separating the front-side electrode 110 of the trench portion 50 from the bottom surface of the trench T, the doping concentration of the first doping layer 21 in contact with the bottom surface of the trench portion 50 can be increased. This reduces the on-resistance of the diamond semiconductor device 100.

[0053] The diamond semiconductor device 100 in this example includes a second insulating film 122 in addition to a first insulating film 121. In this case, the first embedded insulating film 221 may be etched back after the formation of the first insulating film 121 and the first embedded insulating film 221. If the first insulating film 121 exposed after the etch-back of the first embedded insulating film 221 is used as a gate insulating film, energy levels may be formed on the surface of the gate insulating film. In the diamond semiconductor device 100 in this example, the formation of the second insulating film 122, which functions as a gate insulating film, after the formation of the first insulating film 121 can suppress the formation of energy levels on the surface of the gate insulating film. This makes it easier to reduce the leakage current of the diamond semiconductor device 100 and improve hysteresis.

[0054] Figure 1B is an enlarged view of the vicinity of the trench portion 50 in Figure 1A. This figure shows the XZ cross-section of the diamond semiconductor device 100 near the trench portion 50.

[0055] The thickness D122 of the second insulating film 122 may be the same as or different from the thickness D121 of the first insulating film 121. In this example, the thickness D122 of the second insulating film 122 is the same as the thickness D121 of the first insulating film 121. The thickness D122 of the second insulating film 122 may be a thickness that can be gate-controlled by the gate electrode 114.

[0056] The thickness of the first insulating film 121 on the side walls of the first embedded insulating film 221 may be the same as the thickness of the first insulating film 121 on the bottom surface of the first embedded insulating film 221. However, the thickness of the first insulating film 121 on the side walls of the first embedded insulating film 221 may be different from the thickness of the first insulating film 121 on the bottom surface of the first embedded insulating film 221.

[0057] The thickness of the second insulating film 122 on the side wall of the front electrode 110 may be the same as the thickness of the second insulating film 122 on the bottom surface of the front electrode 110. However, the thickness of the second insulating film 122 on the side wall of the front electrode 110 may be different from the thickness of the second insulating film 122 on the bottom surface of the front electrode 110.

[0058] The depth position Z114 at the lower end of the gate electrode 114 may be the same as the depth position of the interface 101. The difference between the depth position Z114 at the lower end of the gate electrode 114 and the depth position of the interface 101 may be greater than 0.1 μm and less than or equal to 1.0 μm.

[0059] Figure 2 shows an example of a top view of a diamond semiconductor device 100. The top surface of the diamond semiconductor device 100 is provided with a gate electrode 114 and a source electrode 116, but not a drain electrode 130. The drain electrode 130 is provided on the back surface 12 of the diamond semiconductor device 100. The gate electrode 114 and the source electrode 116 may have pads for connecting to the outside of the diamond semiconductor device 100. The trench portion 50 is provided between opposing portions of the source electrode 116. In this example, the diamond semiconductor device 100 has one trench portion 50, but it may also be an integrated device having multiple trench portions 50. The top view of the diamond semiconductor device 100 in this example is just one example and is not limited thereto.

[0060] Figure 3A shows an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 1A. In this example, steps S100 to S112 are shown as an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 1A, but the method for manufacturing the diamond semiconductor device 100 is not limited to this.

[0061] In step S100, a trench T is formed on the front surface 11 of the diamond layer 15. Then, an epitaxial layer 30 of diamond is formed inside the trench T. The epitaxial layer 30 is formed by epitaxial growth on the upper surface of the doped region 20. The epitaxial layer 30 may be formed on the side walls and bottom surface of the trench T. The epitaxial layer 30 may be formed on the upper surface of the mesa portion 152 of the doped region 20. The epitaxial layer 30 may be formed on the upper surface of the third doped layer 23. In this example, the epitaxial layer 30 is formed by the MPCVD method, but is not limited thereto.

[0062] In step S102, a first insulating film 121 is formed inside the epitaxial layer 30. The first insulating film 121 may be formed on the side walls and bottom surface of the trench T. The first insulating film 121 may be formed on the upper surface of the epitaxial layer 30 above the mesa portion 152. The first insulating film 121 may be formed by any method such as ALD or CVD. In this example, the first insulating film 121 is Al ２ O ３ However, it is not limited to this.

[0063] The first termination portion 41 may be formed on the surface of the epitaxial layer 30 before forming the first insulating film 121, or it may be formed after forming the first insulating film 121. The first termination portion 41 may be a layer formed by surface treatment of the epitaxial layer 30. The first termination portion 41 may be a layer of the epitaxial layer 30 that is hydrogen-terminated or a layer that is silicon oxide-terminated. After forming the first insulating film 121, the interface between the first termination portion 41 and the first insulating film 121 may be improved by annealing or the like.

[0064] In step S104, a first embedded insulating film 221 is formed inside the first insulating film 121. The first embedded insulating film 221 may be formed in the trench T so as to fill the inside of the first insulating film 121. The first embedded insulating film 221 may be formed outside the trench T above the first insulating film 121. The first embedded insulating film 221 may be formed by any method such as ALD or CVD. In this example, the first embedded insulating film 221 is made of SiO ２ However, it is not limited to this.

[0065] Figure 3B shows an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 1A. This figure shows the process following step S104 in Figure 3A.

[0066] In step S106, the first embedded insulating film 221 is etched. In this example, only a portion of the first embedded insulating film 221 is etched in the trench T, leaving a portion of the first embedded insulating film 221. In this example, the first embedded insulating film 221 outside the trench T is completely removed by etching, but a portion may be left. When etching the first embedded insulating film 221, the first insulating film 121 may or may not be etched. The first embedded insulating film 221 and the first insulating film 121 may be selectively etched by using different materials. In this example, the first embedded insulating film 221 is dry etched, but wet etching may also be used. The etching of the first embedded insulating film 221 may be reactive ion etching (RIE).

[0067] In step S108, a portion of the first insulating film 121 is etched. In this example, only a portion of the first insulating film 121 is etched in the trench T, leaving a portion of the first insulating film 121 intact. In this example, the first insulating film 121 outside the trench T is completely removed by etching, but a portion may be left intact. In this example, the first insulating film 121 is etched to the same height as the upper surface of the first embedded insulating film 221, but the first insulating film 121 may be etched to a different height from the upper surface of the first embedded insulating film 221. The height of the upper surface of the first insulating film 121 after etching may be higher or lower than the height of the first embedded insulating film 221. In this example, the first insulating film 121 is wet-etched, but dry etching may also be used. After etching the first insulating film 121, the residual may be removed by hydrogen plasma treatment or the like.

[0068] The first insulating film 121 and the first embedded insulating film 221 may be etched simultaneously in the same process. In this case as well, the materials of the first insulating film 121 and the first embedded insulating film 221 may be the same or different.

[0069] Figure 3C shows an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 1A. This figure shows the process following step S108 in Figure 3B.

[0070] In step S110, a second insulating film 122 is formed above the doped region 20. In this example, the second insulating film 122 is formed inside the trench T above the first embedded insulating film 221. The second insulating film 122 may be formed in the trench T on the upper surfaces of the first insulating film 121 and the first embedded insulating film 221. The second insulating film 122 may be formed in the trench T on the sidewalls of the epitaxial layer 30. The second insulating film 122 may be formed by any method such as ALD or CVD. In this example, the second insulating film 122 is Al ２ O ３ However, it is not limited to this.

[0071] The second termination portion 42 may be formed on the surface of the epitaxial layer 30 before forming the second insulating film 122, or it may be formed after forming the second insulating film 122. The second termination portion 42 may be a layer formed by surface treatment of the epitaxial layer 30. The second termination portion 42 may be a layer of the epitaxial layer 30 that is hydrogen-terminated or a layer that is silicon oxide-terminated. The surface treatment of the second termination portion 42 may be the same as or different from the surface treatment of the first termination portion 41. After forming the second insulating film 122, the interface between the second termination portion 42 and the second insulating film 122 may be improved by annealing or the like.

[0072] In step S112, the front-side electrode 110 is formed above the second insulating film 122. In this example, the front-side electrode 110 is formed inside the second insulating film 122 in the trench T. In this example, the inside of the second insulating film 122 in the trench T is filled with the gate electrode 114. In step S112, the contact region 60 and the source electrode 116 may be formed.

[0073] The contact region 60 may be formed by epitaxial growth on the epitaxial layer 30. The contact region 60 may be of the P+ type. The contact region 60 may be omitted. The source electrode 116 may be formed on the contact region 60.

[0074] The contact region 60 and the source electrode 116 may be formed at any time. In this example, the contact region 60 and the source electrode 116 are formed after the step of forming the second insulating film 122. The contact region 60 and the source electrode 116 may be formed before forming the gate electrode 114, or they may be formed after forming the gate electrode 114. The contact region 60 and the source electrode 116 may be formed on the epitaxial layer 30 after the epitaxial layer 30 is formed in step S100. That is, the contact region 60 and the source electrode 116 may be formed before the step of forming the first insulating film 121.

[0075] In this example, the terminal layer 40 was formed by surface treatment of the exposed epitaxial layer 30, but it may also be formed with the front-side insulating film 120 already formed on the epitaxial layer 30. The first terminal portion 41 and the second terminal portion 42 may be formed by annealing in a predetermined gas atmosphere after the second insulating film 122 has been formed. The first terminal portion 41 and the second terminal portion 42 may be formed simultaneously or separately. The second terminal portion 42 may be formed after the first terminal portion 41 has been formed.

[0076] In this example, the second insulating film 122 is formed after the first insulating film 121 and the first embedded insulating film 221 are removed. This suppresses the formation of energy states on the surface of the gate insulating film, thereby improving the reliability of the diamond semiconductor device 100.

[0077] Figure 4A shows a modified example of the diamond semiconductor device 100. This figure is an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100. In this example, the shape of the insulating film 120 on the front side differs from that of the diamond semiconductor device 100 in Figure 1A. In this example, the differences from the diamond semiconductor device 100 in Figure 1A will be explained in particular, but other aspects may be the same as those of the diamond semiconductor device 100 in Figure 1A.

[0078] The upper end T121 of the first insulating film 121 is located at a different depth than the upper end T221 of the first embedded insulating film 221. In this example, the upper end T121 of the first insulating film 121 is located below the upper end T221 of the first embedded insulating film 221. That is, the first insulating film 121 at both ends of the first embedded insulating film 221 may be over-etched. On the side surface of the first embedded insulating film 221, the upper end T121 of the first insulating film 121 is in contact with the second insulating film 122. In this way, even if the upper ends of the first insulating film 121 and the first embedded insulating film 221 are at different positions, the formation of energy levels on the surface of the second insulating film 122, which is the gate insulating film, can be suppressed, thereby improving the reliability of the diamond semiconductor device 100.

[0079] Figure 4B shows an example of a manufacturing method for the diamond semiconductor device 100 shown in Figure 4A. In this example, steps S208 to S212 are shown as an example of a manufacturing method for the diamond semiconductor device 100 shown in Figure 4A, but the manufacturing method for the diamond semiconductor device 100 is not limited to this.

[0080] In step S208, the first embedded insulating film 221 and the first insulating film 121 are formed inside the trench T. The method for forming the first embedded insulating film 221 and the first insulating film 121 may be the same as in steps S100 to S106. However, in this example, the first insulating film 121 is etched more deeply than the upper surface of the first embedded insulating film 221.

[0081] The etching of the first insulating film 121 and the first embedded insulating film 221 may be performed in the same process or in different processes. That is, the first insulating film 121 and the first embedded insulating film 221 may be etched simultaneously in the same process. In this case, the height of the upper edge of the first insulating film 121 may be made lower than the height of the upper edge of the first embedded insulating film 221 due to the difference in etching rates between the first insulating film 121 and the first embedded insulating film 221. Alternatively, the etching of the first insulating film 121 may be performed after etching the first embedded insulating film 221. The etching of the first insulating film 121 and the first embedded insulating film 221 may be performed by dry etching or wet etching. After etching the first insulating film 121 or the first embedded insulating film 221, residuals may be removed by hydrogen plasma treatment or the like.

[0082] In step S210, a second insulating film 122 is formed above the doped region 20. The second insulating film 122 may be formed in the trench T on the upper surfaces of the first insulating film 121 and the first embedded insulating film 221. The second insulating film 122 may be formed in the trench T on the sidewall of the epitaxial layer 30. In this example, the second insulating film 122 fills a depression in the sidewall of the first embedded insulating film 221 created by etching the first insulating film 121. In this example, the second insulating film 122 is in contact with the sidewall of the first embedded insulating film 221. In this example, the second insulating film 122 is made of Al ２ O ３However, it is not limited to this.

[0083] The first termination portion 41 and the second termination portion 42 may be formed after the second insulating film 122 is formed. However, as shown in Figures 3A to 3C, the first termination portion 41 and the second termination portion 42 may be formed in separate processes. The boundary between the first termination portion 41 and the second termination portion 42 may be deeper than the upper end of the first embedded insulating film 221.

[0084] In step S212, the front-side electrode 110 is formed above the second insulating film 122. In this example, the gate electrode 114 is filled inside the second insulating film 122 in the trench T. The contact region 60 in this example is formed after the step of forming the second insulating film 122, but may be formed before the step of forming the first insulating film 121.

[0085] Figure 5A shows a modified example of the diamond semiconductor device 100. This figure is an enlarged view of the vicinity of the trench portion 50 of the diamond semiconductor device 100. In this example, the shape of the insulating film 120 on the front side differs from that of the diamond semiconductor device 100 in Figure 1A. In this example, the differences from the diamond semiconductor device 100 in Figure 1A will be explained in particular, but other aspects may be the same as those of the diamond semiconductor device 100 in Figure 1A.

[0086] The front-side electrode 110 has a first embedded electrode portion 111 and a second embedded electrode portion 112. The first embedded electrode portion 111 and the second embedded electrode portion 112 may be formed simultaneously in the same process. That is, the first embedded electrode portion 111 and the second embedded electrode portion 112 may be formed integrally. The first embedded electrode portion 111 and the second embedded electrode portion 112 may be made of the same material.

[0087] The first embedded electrode portion 111 is provided inside the trench T and inside the second insulating film 122. The first embedded electrode portion 111 has a predetermined width. The width of the first embedded electrode portion 111 is not particularly limited. The width of the first embedded electrode portion 111 is determined according to the trench width of the trench T and the film thickness of other members provided in the trench portion 50.

[0088] The second embedded electrode portion 112 is provided inside the trench T and inside the second insulating film 122. The second embedded electrode portion 112 is provided below the first embedded electrode portion 111 and is spaced further apart from the side wall of the trench T of the trench portion 50 than the first embedded electrode portion 111. The second embedded electrode portion 112 may function as a field plate that mitigates the electric field near the front electrode 110. The side and bottom surfaces of the second embedded electrode portion 112 are in contact with the second insulating film 122.

[0089] The stepped portion 123 is in contact with the upper end and side wall of the first insulating film 121. The stepped portion 123 is part of the second insulating film 122. The second embedded electrode portion 112 is in contact with the stepped portion 123. The upper end of the stepped portion 123 may be at the same height as the interface 101, or it may be at a different height. The upper end of the stepped portion 123 may be in contact with the first embedded electrode portion 111.

[0090] The upper end T221 of the first embedded insulating film 221 is located below the upper end T121 of the first insulating film 121. Here, the upper end T221 of the first embedded insulating film 221 may be the same as the lower end of the second insulating film 122. That is, the lower end of the second insulating film 122 may be located below the upper end T121 of the first insulating film 121.

[0091] Figure 5B shows an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 5A. In this example, steps S308 to S314 are shown as an example of a method for manufacturing the diamond semiconductor device 100 shown in Figure 5A, but the method for manufacturing the diamond semiconductor device 100 is not limited to this.

[0092] In step S308, the first embedded insulating film 221 and the first insulating film 121 are formed inside the trench T. The steps up to step S308 may be the same as those up to step S208. A portion of the first embedded insulating film 221 and a portion of the first insulating film 121 may be removed by wet etching.

[0093] In step S310, the first embedded insulating film 221 is further etched. In the manufacturing method of this example, the step of etching the first embedded insulating film 221 is performed after the step of etching a part of the first insulating film 121. The etching of the first embedded insulating film 221 may be dry etching. The etching of the first embedded insulating film 221 may be reactive ion etching. After etching the first embedded insulating film 221, residuals may be removed by hydrogen plasma treatment or the like.

[0094] The first insulating film 121 and the first embedded insulating film 221 may be etched simultaneously in the same process. In this case, the height of the upper edge of the first insulating film 121 may be made higher than the height of the upper edge of the first embedded insulating film 221 due to the difference in etching rates between the first insulating film 121 and the first embedded insulating film 221. After etching the first insulating film 121 or the first embedded insulating film 221, the residual may be removed by hydrogen plasma treatment or the like.

[0095] Figure 5C shows an example of a manufacturing method for the diamond semiconductor device 100 shown in Figure 5A. This figure shows the process following step S310 in Figure 5B.

[0096] In step S312, a second insulating film 122 is formed above the doped region 20. The step of forming the second insulating film 122 is performed after the step of etching the first embedded insulating film 221. The second insulating film 122 may be formed in the trench T on the upper surfaces of the first insulating film 121 and the first embedded insulating film 221. The second insulating film 122 may be formed in the trench T on the sidewalls of the epitaxial layer 30. In this example, the second insulating film 122 fills the depressions created inside the first insulating film 121 by etching the first embedded insulating film 221. In this example, the second insulating film 122 is in contact with the sidewalls of the first insulating film 121. In this example, the second insulating film 122 is Al ２ O ３ However, it is not limited to this.

[0097] The first termination portion 41 and the second termination portion 42 may be formed after the second insulating film 122 is formed. However, as shown in Figures 3A to 3C, the first termination portion 41 and the second termination portion 42 may be formed in separate processes. The boundary between the first termination portion 41 and the second termination portion 42 may be shallower than the upper end of the first embedded insulating film 221.

[0098] In step S314, the front-side electrode 110 is formed above the second insulating film 122. In this example, the gate electrode 114 is filled inside the second insulating film 122 in the trench T. In this example, the gate electrode 114 is also filled in the recessed area of ​​the second insulating film 122 inside the trench T. In this example, the contact region 60 is formed after the step of forming the second insulating film 122, but it may be formed before the step of forming the first insulating film 121.

[0099] Figure 6 shows a modified example of the diamond semiconductor device 100. In this example, the structure of the trench portion 50 differs from that of the diamond semiconductor device 100 in Figure 1A. In this example, the differences from the diamond semiconductor device 100 in Figure 1A will be explained in particular, while other aspects may be the same as those of the diamond semiconductor device 100 in Figure 1A. In this example, the front-side insulating film 120 has a second embedded insulating film 222.

[0100] The second embedded insulating film 222 is provided inside the trench T, above the first embedded insulating film 221. The bottom surface of the second embedded insulating film 222 may be in contact with the front-side electrode 110 of the trench portion 50. The side walls of the second embedded insulating film 222 may be in contact with the second insulating film 122. In this example, the second embedded insulating film 222 is provided inside the trench T, but it may also be provided outside the trench T.

[0101] The material of the second embedded insulating film 222 may be the same as or different from that of the first embedded insulating film 221. The material of the second embedded insulating film 222 is Al ２ O ３ SiO ２ SiNx, HfO ２ , HfSiO ４Or it may include at least one of BN. The material of the second embedded insulating film 222 is SiO ２ It may be SiNx, and it may be SiNx.

[0102] The front-side electrode 110 is provided inside the trench T between the first embedded insulating film 221 and the second embedded insulating film 222. That is, the front-side electrode 110 may be provided only inside the trench T in an XZ cross section parallel to the trench width direction of the trench portion 50. The front-side electrode 110 may be surrounded by the front-side insulating film 120. In this example, the front-side electrode 110 is a gate electrode 114. In this example, the gate electrode 114 is provided inside the trench T between the first embedded insulating film 221 and the second embedded insulating film 222.

[0103] Within the trench T, the thickness of the front-facing electrode 110 in the depth direction may be the same as or different from the thickness of the first embedded insulating film 221 in the depth direction. Within the trench T, the thickness of the front-facing electrode 110 in the depth direction may be smaller than, but larger than, the thickness of the first embedded insulating film 221 in the depth direction.

[0104] Within the trench T, the thickness of the front-facing electrode 110 in the depth direction may be the same as or different from the thickness of the second embedded insulating film 222 in the depth direction. Within the trench T, the thickness of the front-facing electrode 110 in the depth direction may be smaller than, but larger than, the thickness of the second embedded insulating film 222 in the depth direction.

[0105] The bottom surface of the front-side electrode 110 inside the trench T of the trench portion 50 may be flat. However, the shape of the bottom surface of the front-side electrode 110 is not limited thereto. The bottom surface of the front-side electrode 110 may include a tapered shape, a curved shape, or a combination thereof. The top surface of the front-side electrode 110 inside the trench T may also be flat. The top surface of the first embedded insulating film 221 may also be flat.

[0106] The thickness of the second insulating film 122 at the bottom surface of the front electrode 110 may differ from the thickness of the second insulating film 122 at the side wall of the front electrode 110. In this example, the thickness of the second insulating film 122 at the bottom surface of the front electrode 110 is greater than the thickness of the second insulating film 122 at the side wall of the front electrode 110. However, the thickness of the second insulating film 122 at the bottom surface of the front electrode 110 may be less than the thickness of the second insulating film 122 at the side wall of the front electrode 110.

[0107] Figure 7 shows a modified example of the diamond semiconductor device 100. In this example, the structure of the front-side electrode 110 differs from that of the diamond semiconductor device 100 in Figure 6. In this example, the differences from the diamond semiconductor device 100 in Figure 6 will be explained in particular, but other aspects may be the same as those of the diamond semiconductor device 100 in Figure 6.

[0108] The front-side electrode 110 provided inside the trench T of the trench portion 50 is the source electrode 116. However, the source electrode 116 may also be provided on the contact region 60. By providing the front-side electrode 110 inside the trench T in this way, the electric field concentration near the interface 101 can be mitigated, similar to the case where the gate electrode 114 is provided inside the trench T.

[0109] In this example, the front electrode 110 has a gate electrode 114 outside the trench T. The gate electrode 114 in this example is located above the front surface 11 and is not provided inside the trench T. The gate electrode 114 in this example is provided above the trench portion 50 and the mesa portion 152. The gate electrode 114 in this example is provided above the second insulating film 122. At least a part of the gate electrode 114 is in contact with the upper surface of the second insulating film 122. The gate electrode 114 in this example is also provided on the second embedded insulating film 222.

[0110] The gate electrode 114 may extend from above one side wall of the trench portion 50 to above the other side wall, covering the upper part of the front-side insulating film 120 provided inside the trench T. The gate electrode 114 may cover the entire upper surface of the trench portion 50, or it may cover a part of the upper surface of the trench portion 50.

[0111] Figure 8 shows a modified example of the diamond semiconductor device 100. In this example, the structure of the front-side electrode 110 differs from that of the diamond semiconductor device 100 in Figure 7. In this example, the differences from the diamond semiconductor device 100 in Figure 7 will be explained in detail, while other aspects may be the same as those of the diamond semiconductor device 100 in Figure 7. The diamond semiconductor device 100 in this example includes a floating electrode 118.

[0112] The floating electrode 118 is an example of a front-side electrode 110 provided inside the trench T of the trench portion 50. The floating electrode 118 is at a floating potential. That is, the floating electrode 118 is not set to any arbitrary potential such as source potential or gate potential. By providing the floating electrode 118 inside the trench T in this way, electric field concentration near the interface 101 can be mitigated, similar to the case where the gate electrode 114 is provided inside the trench T.

[0113] Figure 9 shows an example of a method for manufacturing a comparative example diamond semiconductor device 500. In step S500, an epitaxial layer 30, a gate insulating film 520, a buried insulating film 521, and a termination layer 540 are formed in the trench T. In step S502, the buried insulating film 521 is etched to form a region for providing the gate electrode 514. In step S504, the gate electrode 514 is formed above the buried insulating film 521.

[0114] In the manufacturing method described here, the gate insulating film 520 is affected by the etching of the embedded insulating film 521. As a result, energy levels may be formed on the surface of the gate insulating film 520.

[0115] Figure 10 shows an overview of the configuration of the semiconductor module 200. The semiconductor module 200 includes a diamond semiconductor device 100. In this example, the semiconductor module 200 includes a diamond semiconductor device 100 that functions as a MOSFET. The semiconductor module 200 includes a gate terminal 210, a source terminal 220, and a drain terminal 230. The gate terminal 210, source terminal 220, and drain terminal 230 may be external connection terminals for electrically connecting the semiconductor module 200 to the outside.

[0116] The gate terminal 210 is connected to the gate electrode 114 of the diamond semiconductor device 100. The source terminal 220 is connected to the source electrode 116 of the diamond semiconductor device 100. The drain terminal 230 is connected to the drain electrode 130 of the diamond semiconductor device 100. The diamond semiconductor device 100 may be mounted on an insulating substrate of a semiconductor module 200 with the drain electrode 130 facing downwards. The drain electrode 130 may be electrically connected to the drain terminal 230 via metal wiring on the insulating substrate.

[0117] The semiconductor module 200 may have a single diamond semiconductor device 100, or it may have multiple diamond semiconductor devices 100. The semiconductor module 200 may have an inverter circuit. The semiconductor module 200 may have an inverter circuit that combines a P-channel diamond semiconductor device 100 and an N-channel semiconductor element. The N-channel semiconductor element may be an N-channel diamond semiconductor device 100, or it may be another semiconductor element such as GaN or SiC.

[0118] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0119] 10...Support layer, 11...Front surface, 12...Back surface, 15...Diamond layer, 20...Doped region, 21...First doped layer, 22...Second doped layer, 23...Third doped layer, 30...Epitaxial layer, 40...Terminal layer, 41...First termination section, 42...Second termination section, 50...Trench section, 60...Contact region, 110...Front side electrode, 111...First embedded electrode section, 112...Second embedded electrode section, 114...Gate electrode, 116...Source electrode, 118...Floating electrode, 120 ...front side insulating film, 121...first insulating film, 122...second insulating film, 123...step portion, 130...drain electrode, 152...mesa portion, 100...diamond semiconductor device, 101...interface, 200...semiconductor module, 210...gate terminal, 220...source terminal, 221...first embedded insulating film, 222...second embedded insulating film, 230...drain terminal, 500...diamond semiconductor device, 514...gate electrode, 520...gate insulating film, 521...embedded insulating film, 540...termination layer

Claims

A diamond semiconductor device having a trench portion on its front surface, Diamond layer and A diamond epitaxial layer provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned insulating film on the front side is A first insulating film is provided inside the trench of the trench portion, Inside the trench, a first embedded insulating film is provided inside the first insulating film, Inside the trench, a second insulating film is provided above the first embedded insulating film, It has, The front-side electrode is provided inside the trench, on the inside of the second insulating film. Diamond semiconductor device. 　 The first insulating film is provided in the trench portion so as to cover the side walls and bottom surface of the first embedded insulating film. The diamond semiconductor device according to claim 1. 　 The second insulating film is provided in the trench portion so as to cover the side wall and bottom surface of the front electrode. The diamond semiconductor device according to claim 1. 　 The thickness of the second insulating film on the side wall of the front-facing electrode is different from the thickness of the second insulating film on the bottom surface of the front-facing electrode. The diamond semiconductor device according to claim 3. 　 The thickness of the second insulating film on the side wall of the front-facing electrode is the same as the thickness of the second insulating film on the bottom surface of the front-facing electrode. The diamond semiconductor device according to claim 3. 　 The second insulating film covers the upper surface of the first embedded insulating film. The diamond semiconductor device according to claim 1. 　 The material of the second insulating film is the same as the material of the first insulating film. The diamond semiconductor device according to claim 1. 　 The material of the second insulating film is different from the material of the first insulating film. The diamond semiconductor device according to claim 1. 　 The inside of the trench in the trench portion is filled with the surface-side insulating film and the surface-side electrode. The diamond semiconductor device according to claim 1. 　 The front-facing electrode located inside the trench is a gate electrode. The diamond semiconductor device according to claim 1. 　 The front-facing electrode located inside the trench is the source electrode. The diamond semiconductor device according to claim 1. 　 The front-facing electrode located inside the trench is at a floating potential. The diamond semiconductor device according to claim 1. 　 The front-side insulating film has a second embedded insulating film provided above the first embedded insulating film inside the trench. The front-side electrode is provided inside the trench between the first embedded insulating film and the second embedded insulating film. The diamond semiconductor device according to any one of claims 1 to 12. The upper end of the first insulating film is located below the upper end of the first embedded insulating film. On the side surface of the first embedded insulating film, the upper end of the first insulating film is in contact with the second insulating film. The diamond semiconductor device according to any one of claims 1 to 12. 　 The aforementioned front-side electrode is, A first embedded electrode portion of a predetermined width, A second embedded electrode portion is provided below the first embedded electrode portion and is spaced further apart from the side wall of the trench portion than the first embedded electrode portion, has The diamond semiconductor device according to any one of claims 1 to 12. 　 The side and bottom surfaces of the second embedded electrode portion are in contact with the second insulating film. The diamond semiconductor device according to claim 15. 　 The second insulating film has a stepped portion that is in contact with the upper end and side wall of the first insulating film. The second embedded electrode portion is in contact with the stepped portion. The diamond semiconductor device according to claim 15. 　 The upper end of the first embedded insulating film is provided below the upper end of the first insulating film. The diamond semiconductor device according to claim 15. 　 The lower end of the second insulating film is provided below the upper end of the first insulating film. The diamond semiconductor device according to claim 15. 　 A semiconductor module comprising a diamond semiconductor device according to any one of claims 1 to 12. 　 A method for manufacturing a diamond semiconductor device having a trench portion on its front surface, The steps include forming trenches on the surface of the diamond layer, The steps include forming an epitaxial layer of diamond inside the trench, The steps include forming a first insulating film on the inside of the epitaxial layer, The steps include forming a first embedded insulating film inside the first insulating film, The steps include etching a portion of the first insulating film, The steps include forming a second insulating film above the first embedded insulating film inside the trench, The steps include forming the front-side electrode inside the second insulating film within the trench, A method for manufacturing a diamond semiconductor device. 　 The process includes a step of etching a portion of the first insulating film, followed by a step of etching the first embedded insulating film. The step of forming the second insulating film is performed after the step of etching the first embedded insulating film. The method for manufacturing a diamond semiconductor device according to claim 21.

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