Circuit board and semiconductor package

Abstract

This circuit board comprises: a core part comprising a first core layer, a second core layer disposed over the first core layer, and an interlayer insulating layer disposed between the first core layer and the second core layer; an upper build-up structure which is disposed on the upper surface of the core part and comprises a plurality of stacked insulating layers; a lower build-up structure which is disposed on the lower surface of the core part and comprises a plurality of stacked insulating layers; and a core via electrode penetrating the upper surface and lower surface of the core part, wherein the first core layer and the second core layer each have at least one cavity, and the core via electrode is horizontally aligned with the cavity of the first core layer and the cavity of the second core layer.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] Furthermore, regarding mobile products such as smartphones and tablets, the thickness of circuit boards applied to miniaturize finished electronic products is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to one another, which was previously considered only from the perspective of conventional semiconductor packaging.

[0005] Recently, in response to the demand for higher functionality and miniaturization of electronic components, research on embedded circuit boards equipped with cavities capable of embedding electronic devices is actively underway to increase mounting efficiency per unit area.

[0006] Considering the signal transmission length between electronic components embedded within the circuit board and electronic components placed on the surface of the circuit board, the cavity is formed close to the surface of the circuit board. According to the above structure, the placement area of ​​electronic components within the circuit board is asymmetric in the vertical direction of the circuit board, which becomes a disadvantageous factor in improving the warpage of the circuit board.

[0007] Furthermore, recent requirements for printed circuit boards are closely linked to the increasing speed and density in the electronics industry market. To satisfy these demands, many issues must be resolved, including the miniaturization of circuits, excellent electrical characteristics, high reliability, high-speed signal transmission structures, and high functionality.

[0008] In particular, efficient heat dissipation is becoming a very important issue to improve product reliability and prevent malfunctions in sets such as mobile phones, servers, and networks that are becoming faster, consume high power, and simultaneously become denser and smaller. High heat generation temperatures of semiconductor chips are a significant cause of errors such as malfunctions and freezes in the sets.

[0009] To lower the temperature of these semiconductor chips, the technology applied to products so far involves installing a heat sink over the semiconductor chip that generates high heat or operating a cooling fan to forcibly exhaust the high heat generated by the chip.

[0010]

[0011] The present invention provides a circuit board and a semiconductor package that can improve the warpage characteristics of the circuit board in the embedding structure of an electronic device and improve heat dissipation efficiency.

[0012] In addition, the invention provides a circuit board and a semiconductor package capable of improving heat dissipation efficiency in the embedding structure of an electronic device.

[0013]

[0014] A circuit board according to the present embodiment comprises: a core portion including a first core layer, a second core layer disposed on the first core layer, and an interlayer insulating layer disposed between the first core layer and the second core layer; an upper build-up structure disposed on the upper surface of the core portion and including a plurality of stacked insulating layers; a lower build-up structure disposed on the lower surface of the core portion and including a plurality of stacked insulating layers; and a core via electrode penetrating the upper and lower surfaces of the core portion, wherein the first core layer and the second core layer each comprise at least one cavity, and the core via electrode overlaps along the horizontal direction with the cavity of the first core layer and the cavity of the second core layer.

[0015] The core portion may include a first insulating layer disposed between the first core layer and the lower build-up structure, a second insulating layer disposed between the second core layer and the upper build-up structure, a third insulating layer disposed between the interlayer insulating layer and the first core layer, and a fourth insulating layer disposed between the interlayer insulating layer and the second core layer.

[0016] The third insulating layer includes a first protrusion protruding toward the lower build-up structure, and the first protrusion may be disposed within the cavity of the first core layer.

[0017] The fourth insulating layer includes a second protrusion protruding toward the upper build-up structure, and the second protrusion may be disposed within the cavity of the second core layer.

[0018] The cavity of the first core layer and the cavity of the second core layer can be vertically overlapped.

[0019] The cavities of the first core layer are provided in multiple numbers and arranged to overlap in the horizontal direction, and the cavities of the second core layer are provided in multiple numbers and arranged to overlap in the horizontal direction.

[0020] The cavities of the plurality of first core layers and the cavities of the plurality of second core layers can each be vertically overlapped.

[0021] The horizontal width of the cavity of the first core layer may be the same as the horizontal width of the cavity of the second core layer.

[0022] The horizontal width of the cavity of the first core layer may be different from the horizontal width of the cavity of the second core layer.

[0023] The core via electrode can penetrate the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the interlayer insulating layer, the first core layer, and the second core layer as a whole.

[0024]

[0025] Through this embodiment, stress is uniformly distributed based on the vertical direction due to the formation of a plurality of cavities that overlap in the vertical direction within the core part, thereby improving the bending characteristics of the circuit board.

[0026] In addition, there is an advantage in that heat dissipation efficiency can be improved by implementing a heat dissipation structure in the horizontal and vertical directions through the metal parts.

[0027]

[0028] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0029] FIG. 2 is a cross-sectional view of a core via electrode according to a first embodiment of the present invention.

[0030] FIG. 3 is a drawing illustrating a modified example of a core via electrode according to the first embodiment of the present invention.

[0031] FIG. 4 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0032] FIG. 5 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0033] FIG. 6 is a drawing illustrating a modified example of a multiple cavity forming structure according to an embodiment of the present invention.

[0034] FIG. 7 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention.

[0035] FIG. 8 is a drawing for explaining the heat dissipation efficiency of a circuit board according to a fourth embodiment of the present invention.

[0036] FIG. 9 is a drawing illustrating a modified example of a plurality of cavity structure within a circuit board according to the fourth embodiment of the present invention.

[0037] FIGS. 10 to 20 are drawings for explaining the manufacturing process of a circuit board according to an embodiment of the present invention.

[0038] FIG. 21 is a cross-sectional view of a circuit board according to the fifth embodiment of the present invention.

[0039] FIG. 22 is an enlarged view of the core section in FIG. 21.

[0040] FIG. 23 is an enlarged view of a core via electrode according to the fifth embodiment of the present invention.

[0041] FIG. 24 is a drawing illustrating a modified example of a core via electrode according to the fifth embodiment of the present invention.

[0042] FIG. 25 is a drawing illustrating a modified example of a circuit board according to the fifth embodiment of the present invention.

[0043] FIG. 26 is a cross-sectional view of a circuit board according to the 6th embodiment of the present invention.

[0044] FIG. 27 is an enlarged view of the core section in FIG. 26.

[0045] FIG. 28 is an enlarged view of a core via electrode according to the 6th embodiment of the present invention.

[0046] FIG. 29 is a drawing illustrating a modified example of a core via electrode according to the 6th embodiment of the present invention.

[0047] FIG. 30 is a drawing illustrating a modified example of a circuit board according to the 6th embodiment of the present invention.

[0048]

[0049] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0050] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0051] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0052] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0053] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0054] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0055] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0056] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0057] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0058] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0059] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0060] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0061] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0062] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0063] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0064] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a core via electrode according to a first embodiment of the present invention, FIG. 3 is a drawing illustrating a modified example of a core via electrode according to a first embodiment of the present invention, FIG. 4 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 5 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0065] Referring to FIGS. 1 to 3, a circuit board (10) according to the first embodiment of the present invention may include a core portion (100), an upper build-up structure (300), a lower build-up structure (400), and a core via electrode (210).

[0066] The circuit board (10) may include a core portion (100). The core portion (100) may be a component forming the basis of the circuit board (10). Based on the vertical direction of the circuit board (10), the core portion (100) may be positioned in the center.

[0067] The core portion (100) may include a plurality of insulating layers arranged in a vertical direction. When the core portion (100) is implemented with a plurality of insulating layers, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved.

[0068] Each of the multiple insulating layers of the core portion (100) may be any insulating material, such as photocurable and / or thermosetting insulating material. As an example of a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, or a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as the core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the multiple insulating layers of the core portion (100) are photocurable insulating materials, each of the multiple insulating layers of the core portion (100) may be PID (Photo Imageable Dielectric).

[0069] The core portion (100) may include a first core layer (110), a second core layer (130), an interlayer insulating layer (150), a first insulating layer (101), a second insulating layer (102), a third insulating layer (160), and a fourth insulating layer (170). The first core layer (110), the second core layer (130), the interlayer insulating layer (150), the first insulating layer (101), the second insulating layer (102), the third insulating layer (160), and the fourth insulating layer (170) may be arranged in a vertical direction. For example, a first core layer (110) may be disposed on a first insulating layer (101), a third insulating layer (160) may be disposed on the first core layer (110), an interlayer insulating layer (150) may be disposed on the third insulating layer (160), a fourth insulating layer (170) may be disposed on the interlayer insulating layer (150), a second core layer (130) may be disposed on the fourth insulating layer (170), and a second insulating layer (102) may be disposed on the second core layer (130).

[0070] The first core layer (110) may be disposed between the first insulating layer (101) and the third insulating layer (160). The first core layer (110) may have a first thickness in the vertical direction. The first core layer (110) may be a prepreg (PPG) containing glass fibers in a resin. The glass fibers in the first core layer (110) may be implemented as a single layer, but are not limited thereto, and the first core layer (110) may include multiple layers of glass fibers arranged in the vertical direction within the resin.

[0071] The first core layer (110) may include a first cavity (112). The first cavity (112) may have a shape that penetrates from one side of the first core layer (110) to the other side. The first cavity (112) may have a shape that penetrates from the upper surface of the first core layer (110) to the lower surface in a vertical direction. The first cavity (112) may be provided in multiple numbers and arranged along the horizontal direction of the first core layer (110). Multiple first cavities (112) within the first core layer (110) may be arranged spaced apart in the horizontal direction. Multiple first cavities (112) within the first core layer (110) may be arranged to overlap in the horizontal direction. A first electronic element (500), to be described later, may be disposed in the first cavity (112).

[0072] The second core layer (130) may be disposed between the fourth insulating layer (170) and the second insulating layer (102). With respect to the interlayer insulating layer (150) within the core portion (100), the second core layer (130) may be disposed symmetrically in the vertical direction with respect to the first core layer (110). The second core layer (130) may have a first thickness in the vertical direction. The vertical thickness of the second core layer (130) may be the same as the vertical thickness of the first core layer (110). Accordingly, warpage of the core portion (100) may be minimized. The second core layer (130) may be a prepreg (PPG) containing glass fibers in the resin. The glass fibers in the second core layer (130) may be implemented as a single layer, but are not limited thereto, and the second core layer (130) may include multiple layers of glass fibers arranged vertically within the resin.

[0073] The second core layer (130) may include a second cavity (132). The second cavity (132) may have a shape that penetrates from one side of the second core layer (130) to the other side. The second cavity (132) may have a shape that penetrates from the upper surface of the second core layer (130) to the lower surface in a vertical direction. The second cavity (132) may be provided in multiple numbers and arranged along the horizontal direction of the second core layer (130). Multiple second cavities (132) within the second core layer (130) may be arranged spaced apart in the horizontal direction. Multiple second cavities (132) within the second core layer (130) may be arranged to overlap in the horizontal direction. A second electronic element (600), to be described later, may be disposed in the second cavity (132).

[0074] The first cavity (112) and the second cavity (132) may be arranged so that at least a portion of them overlap in the vertical direction. For example, the first cavity (112) and the second cavity (132) may each have the same width in the horizontal direction and may be arranged so that they overlap each other in the vertical direction. Accordingly, with respect to the interlayer insulating layer (150), the stress of the plurality of core layers (110, 130) is uniformly distributed, so that the bending phenomenon of the circuit board (10) can be minimized.

[0075] Meanwhile, as illustrated in FIG. 5, the arrangement of electronic components within the first cavity (112) and the second cavity (132) is not limited, and a portion of the first core layer (110) or the second core layer (130), which is not an electronic component, may be arranged in one or more of the first cavity (112) and the second cavity (132).

[0076] For example, as illustrated in FIG. 5, a cavity coupling portion (116) forming part of the first core layer (110) may be disposed in the first cavity (112). The horizontal width of the cavity coupling portion (116) is formed to be smaller than the horizontal width of the first cavity (112), and the side of the cavity coupling portion (116) may be spaced horizontally apart from the inner wall of the first cavity (112).

[0077] A wiring portion (118) is disposed on the cavity coupling portion (116), and the pattern forming area within the circuit board (10) can be increased by the wiring portion (118), and the strength of the core layer (110) can also be increased.

[0078] Additionally, the cavity coupling portion (116) may be an area protruding from the first insulating layer (101) or the second insulating layer (102). In this case, based on the cavity (112, 132), a coupling structure with a plurality of insulating layers arranged in a vertical direction together with the first protrusion (162) of the third insulating layer (160) and the second protrusion (172) of the fourth insulating layer (170), which will be described later, is formed, thereby increasing the coupling strength between the plurality of insulating layers within the core portion (100). The first protrusion (162) and the second protrusion (172) may be positioned between the inner wall of the cavity (112, 132) and the cavity coupling portion (116).

[0079] An interlayer insulating layer (150) may be placed between the first core layer (110) and the second core layer (130). With respect to the interlayer insulating layer (150), the first core layer (110) and the second core layer (130) may be arranged symmetrically in the vertical direction. The interlayer insulating layer (150) may be placed at the vertical center of the core portion (100). The interlayer insulating layer (150) may have a second thickness that is smaller than the first thickness in the vertical direction. Accordingly, with respect to the interlayer insulating layer (150), the third insulating layer (160) and the fourth insulating layer (170) may be easily laminated between the first core layer (110) and the second core layer (130), respectively. However, this is not limited thereto, and the second thickness, which is the vertical thickness of the interlayer insulating layer (150), may be equal to the first thickness or greater than the first thickness. When the second thickness is greater than the first thickness, the bending phenomenon of the circuit board (10) can be efficiently prevented through the interlayer insulating layer (150) positioned at the vertical center of the core part (100).

[0080] The interlayer insulation layer (150) may be implemented as a single layer, but is not limited thereto and may include two or more insulation layers. When the interlayer insulation layer (150) is formed as a plurality of layers, the vertical thickness of each insulation layer constituting the interlayer insulation layer (150) may be smaller than the vertical thickness of the first core layer (110) or the second core layer (130).

[0081] The interlayer insulation layer (150) may be a prepreg (PPG) containing glass fibers in a resin.

[0082]

[0083] The insulating layer (150) between the 48 layers may be arranged such that at least a portion of it overlaps vertically with the first cavity (112) and the second cavity (132), respectively.

[0084] The first insulating layer (101) may be disposed on one side of the core portion (100). The first insulating layer (101) may be disposed on the lower surface of the core portion (100). The first insulating layer (101) may be disposed on the lower surface of the first core layer (110). The first insulating layer (101) may be disposed facing the lower build-up structure (400) in a vertical direction. The first insulating layer (101) may have a first thickness or a third thickness smaller than the second thickness in the vertical direction. The upper surface of the first insulating layer (101) may be disposed such that at least a portion overlaps the first cavity (112) in a vertical direction. The first electronic element (500) disposed within the first cavity (112) may be disposed on the first insulating layer (101). The first insulating layer (101) may be a prepreg (PPG) containing glass fibers in a resin.

[0085] The second insulating layer (102) may be disposed on the other side of the core portion (100). The second insulating layer (102) may be disposed on the upper surface of the core portion (100). The second insulating layer (102) may be disposed on the upper surface of the second core layer (130). The second insulating layer (102) may be disposed facing the upper build-up structure (300) in a vertical direction. The second insulating layer (102) may have a third thickness in the vertical direction equal to the thickness of the first insulating layer (101). The lower surface of the second insulating layer (102) may be disposed such that at least a portion overlaps the second cavity (132) in a vertical direction. The second electronic element (600) disposed within the second cavity (132) may be disposed on the lower surface of the second insulating layer (102). The second insulating layer (102) may be a prepreg (PPG) containing glass fibers in a resin.

[0086] A third insulating layer (160) may be disposed between the interlayer insulating layer (150) and the first core layer (110). The upper surface of the third insulating layer (160) may face the lower surface of the interlayer insulating layer (150), and the lower surface of the third insulating layer (160) may face the upper surface of the first core layer (110). The vertical thickness of the third insulating layer (160) may be smaller than the vertical thickness of the interlayer insulating layer (150) and / or the vertical thickness of the first core layer (110).

[0087] The third insulating layer (160) may include a first base portion (161) disposed between the lower surface of the interlayer insulating layer (150) and the upper surface of the first core layer (110), and a first protrusion portion (162) that protrudes downward in a vertical direction from the lower surface of the first base portion (161) and is coupled to the first cavity (112). A first electronic element (500) within the first cavity (112) may be embedded through the first protrusion portion (162). Accordingly, the coupling between the third insulating layer (160), the first core layer (110), and the first electronic element (500) within the first cavity (112) can be firmly maintained.

[0088] The fourth insulating layer (170) may be disposed between the interlayer insulating layer (150) and the second core layer (130). The lower surface of the fourth insulating layer (170) may face the upper surface of the interlayer insulating layer (150), and the upper surface of the fourth insulating layer (170) may face the lower surface of the second core layer (130). The vertical thickness of the fourth insulating layer (170) may be smaller than the vertical thickness of the interlayer insulating layer (150) and / or the vertical thickness of the first core layer (110). The vertical thickness of the fourth insulating layer (170) may be the same as the vertical thickness (160) of the third insulating layer (160).

[0089] The fourth insulating layer (170) may include a second base portion (171) disposed between the upper surface of the interlayer insulating layer (150) and the upper surface of the second core layer (130), and a second protrusion portion (172) that protrudes upward in a vertical direction from the upper surface of the second base portion (171) and is coupled to the second cavity (132). A second electronic element (600) within the second cavity (132) may be embedded through the second protrusion portion (172). Accordingly, the coupling between the fourth insulating layer (170), the second core layer (130), and the second electronic element (600) within the second cavity (132) can be firmly maintained.

[0090] The third insulating layer (160) and the fourth insulating layer (170) may each be any insulating material, such as a photocurable and / or thermosetting material. An example of a thermosetting insulating material may be ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation. If the third insulating layer (160) and the fourth insulating layer (170) are photocurable insulating materials, the third insulating layer (160) and the fourth insulating layer (170) may each be a PID (Photo Imageable Dielectric). Additionally, the third insulating layer (160) and the fourth insulating layer (170) may be resin. Accordingly, the vertical thickness of the core portion (100) can be easily adjusted through the third insulating layer (160) and the fourth insulating layer (170), and a vertical coupling structure with a plurality of cavities can be realized through the aforementioned first protrusion (162) and second protrusion (172).

[0091] Referring to FIG. 4, the third insulating layer (160) and the fourth insulating layer (170) may each be a prepreg (PPG) containing glass fibers in the resin. In this case, the first protrusion (162) and the second protrusion (172) in the aforementioned third insulating layer (160) and fourth insulating layer (170) may be omitted. In this case, a molding part may be disposed in the first cavity (112) and the second cavity (132) to embed the first electronic element (500) and the second electronic element (600) in the first cavity (112) and the second cavity (132), respectively. When the third insulating layer (160) and the fourth insulating layer (170) are implemented as prepreg, the bending phenomenon of the circuit board (10) can be further minimized as the rigidity of the core part (100) increases.

[0092] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0093] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0094] A plurality of wiring sections may include a first wiring section (240) disposed on the upper surface of the core section (100) and a second wiring section (230) disposed on the lower surface of the core section (100). The first wiring section (240) may be disposed on the upper surface of the second insulating layer (102). The second wiring section (230) may be disposed on the lower surface of the first insulating layer (101). The first wiring section (240) and the second wiring section (230) may be electrically connected through a core via electrode (210) to be described later.

[0095] A portion of the first wiring portion (240) may be electrically connected to the second electronic element (600). In terms of being connected to the second electronic element (600), the wiring portion of the first wiring portion (240) that is connected to the second electronic element (600) may be named the first connecting wiring portion (192). The first connecting wiring portion (192) may be arranged to overlap horizontally with the first wiring portion (240) connected to the core via electrode (210). The first connecting wiring portion (192) may include a plurality of wiring portions spaced apart in the horizontal direction. The first connecting wiring portion (192) may be arranged to overlap vertically with the second cavity (132). The first connecting wiring portion (192) may be electrically connected to the second electronic element (600) through a first connecting via portion (164) that penetrates at least a portion of the second insulating layer (102).

[0096] A portion of the second wiring portion (230) may be electrically connected to the first electronic element (500). In terms of being connected to the first electronic element (500), the wiring portion of the second wiring portion (230) that is connected to the first electronic element (500) may be named the second connecting wiring portion (182). The second connecting wiring portion (182) may be arranged to overlap horizontally with the second wiring portion (230) connected to the core via electrode (210). The second connecting wiring portion (182) may include a plurality of wiring portions spaced apart in the horizontal direction. The second connecting wiring portion (182) may be arranged to overlap vertically with the first cavity (112). The second connecting wiring portion (182) may be electrically connected to the first electronic element (500) through a second connecting via portion (184) that penetrates at least a portion of the first insulating layer (101).

[0097] A plurality of vias may be a metallic material disposed in via holes formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via may be disposed within the via hole.

[0098] A plurality of vias may include a core via electrode (210), a first connecting via (194), and a second connecting via (184).

[0099] The core via electrode (210) can be positioned to penetrate vertically from the upper surface of the core portion (100) to the lower surface of the core portion (100).

[0100] In detail, the core portion (100) may include a through hole (200). The through hole (200) may have a shape that penetrates from the upper surface to the lower surface of the core portion (100). The through hole (200) is arranged to penetrate the first insulating layer (101), the first core layer (110), the third insulating layer (160), the interlayer insulating layer (150), the fourth insulating layer (170), the second core layer (130), and the second insulating layer (102), and may be arranged to overlap horizontally with the first insulating layer (101), the first core layer (110), the third insulating layer (160), the interlayer insulating layer (150), the fourth insulating layer (170), the second core layer (130), and the second insulating layer (102), respectively. The through hole (200) may have a circular cross-sectional shape, but is not limited thereto.

[0101] The core via electrode (210) may be positioned along the inner wall of the through hole (200). The core via electrode (210) may be positioned to penetrate the core portion (100). The core via electrode (210) penetrates the first insulating layer (101), the first core layer (110), the third insulating layer (160), the interlayer insulating layer (150), the fourth insulating layer (170), the second core layer (130), and the second insulating layer (102) integrally, and may be positioned to overlap horizontally with the first insulating layer (101), the first core layer (110), the third insulating layer (160), the interlayer insulating layer (150), the fourth insulating layer (170), the second core layer (130), and the second insulating layer (102), respectively. The core via electrode (210) can be arranged to overlap horizontally with the first cavity (112) and the second cavity (132), respectively. The core via electrode (210) can be arranged to overlap horizontally with the first electronic element (500) and the second electronic element (600), respectively. The first wiring section (240) and the second wiring section (230) can be electrically connected through the core via electrode (210).

[0102] According to the embodiment, by implementing the core portion (100) of the circuit board (10) through a plurality of insulating layers arranged in a vertical direction, the degree of design freedom regarding the formation of pads and via electrodes is increased, and production efficiency can be improved. In addition, by forming a plurality of cavities (112, 132) that overlap in a vertical direction within the core portion (100), stress is uniformly distributed with respect to the vertical direction, thereby improving the bending characteristics of the circuit board (10). Furthermore, by forming a via portion that penetrates the core portion (100) through the core via electrode (210), there is an advantage of eliminating process inefficiency caused by the formation of individual via portions and simultaneously improving signal transmission efficiency by reducing the signal transmission length.

[0103] The core via electrode (210) may include an electrode portion disposed on the inner wall of the through hole (200) of the core portion (100) and an insulating portion (220) disposed on the inner side of the electrode portion. A hollow is formed on the inner side of the electrode portion, and the insulating portion (220) may be filled into the hollow. Accordingly, the connection of the electrode portion within the through hole (200) can be firmly maintained, and electrical loss of the electrode portion along the vertical direction can be minimized.

[0104] As illustrated in FIGS. 2 and 3, the electrode portion and the insulating portion (220) of the core via electrode (210) may each include a first portion (281) that is horizontally superimposed with the first insulating layer (101), a second portion (282) that is horizontally superimposed with the first core layer (110), a third portion (283) that is horizontally superimposed with the third insulating layer (160), a fourth portion (284) that is horizontally superimposed with the interlayer insulating layer (150), a fifth portion (285) that is horizontally superimposed with the fourth insulating layer (170), a sixth portion (286) that is horizontally superimposed with the second core layer (130), and a seventh portion (287) that is horizontally superimposed with the second insulating layer (102).

[0105] As described above, the core portion (100) may include a plurality of insulating layers arranged in a vertical direction. In this case, as shown in FIG. 2, during the process of forming the through hole (200), a groove (262) may be formed at the bonding interface of the plurality of insulating layers due to a see-through phenomenon depending on the difference in the degree of hardening of two insulating layers adjacent in the vertical direction. The groove (262) may have a concave shape extending outward in the horizontal direction from the inner wall of the through hole (200).

[0106] Due to the shape of the inner wall of the through hole (200) including the groove (262), the core via electrode (210) may include a protrusion (260) that is coupled to the groove (262). The protrusion (260) may have a shape that protrudes outward from the outer surface of the core via electrode (210) more than other regions. Accordingly, the region where the protrusion (260) is formed on the outer surface of the core via electrode (210) may have a wider horizontal width than other regions. Due to the protrusion (260), the core via electrode (210) may have regions with different horizontal widths. The region where the protrusion (260) is formed in the core via electrode (210) may have a wider horizontal width than the region where the protrusion (260) is not formed. Accordingly, as resistance is reduced due to the widened region of the core via electrode (210), power transfer efficiency may be improved. The protrusions (260) may be provided in multiple numbers and arranged along the vertical direction. For example, the protrusions (260) may be arranged between the first insulating layer (101) and the second core layer (110), between the first core layer (110) and the third insulating layer (160), between the third insulating layer (160) and the interlayer insulating layer (150), between the interlayer insulating layer (150) and the fourth insulating layer (170), between the fourth insulating layer (170) and the second core layer (130), and between the second core layer (130) and the second insulating layer (102), respectively.

[0107] As described above, the materials of the plurality of insulating layers constituting the core portion (100) may differ from one another. For example, the materials of the first insulating layer (101), the first core layer (110), the interlayer insulating layer (150), the second core layer (130), and the second insulating layer (102) may be prepreg (PPG) containing glass fibers in the resin. The third insulating layer (160) and the fourth insulating layer (170) may be ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric).

[0108] Accordingly, due to differences in hardness or physical properties of multiple insulating layers arranged in a vertical direction, the core via electrode (210) and the through hole (200) may include an extension with a large horizontal width in the arrangement area of ​​the third insulating layer (160) and the fourth insulating layer (170), which have relatively low strength as shown in FIG. 3. The area where the extension is formed may have a larger horizontal width than other areas. Accordingly, the metal part of the core via electrode (210) may include an extension (270) corresponding to the area where the extension is formed. As the resistance is reduced by the width increase area of ​​the core via electrode (210) through the extension (270), the power transfer efficiency may be improved. The extension (270) may be arranged between the first core layer (110) and the interlayer insulating layer (150), and between the second core layer (130) and the interlayer insulating layer (150), respectively.

[0109] By the extension (270), the horizontal width (D3) of the third part (283) or the fifth part (285) may be larger than the horizontal width (D2) of each of the second part (282), the fourth part (284), and the sixth part (286). By the extension (270), the horizontal width (D3) of the third part (283) or the fifth part (285) may be larger than the horizontal width (D1) of the first part (101) or the seventh part (107).

[0110] In some cases, the horizontal width (D1) of the first part (101) or the seventh part (107), which has a different vertical length, may differ from the horizontal width (D2) of the second part (282), the fourth part (284), and the sixth part (286), respectively. In this case, the horizontal width (D1) of the first part (101) or the seventh part (107) may be larger than the horizontal width (D2) of the second part (282), the fourth part (284), and the sixth part (286), respectively. Accordingly, resistance may be reduced by various vertical thickness increase regions of the metal part of the core via electrode (210).

[0111] Referring to FIG. 1, an upper build-up structure (300) may be disposed on the upper surface of the core portion (100). The upper build-up structure (300) may include a plurality of insulating layers (310) disposed in a vertical direction, a wiring portion (320) disposed on the surface of each of the plurality of insulating layers (310), and a via portion (330) connecting the plurality of wiring portions (320) and penetrating at least a portion of each of the plurality of insulating layers (310).

[0112] A cavity penetrating one or more of the insulating layers may also be disposed in the insulating layer (310) constituting the upper build-up structure (300). An electronic element (360, 370) may be disposed in the cavity of the first build-up structure (300), and the electronic element (360, 370) disposed within the first build-up structure (300) may be arranged in a stepped manner in the vertical direction and may be electrically connected to the electronic element (500, 600) embedded in the core part (100).

[0113] A protective layer (390) may be disposed on the first build-up structure (300). When a semiconductor device is disposed on the surface of the first build-up structure (300) using a material such as solder, the protective layer (390) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent problems where external contaminants penetrate into the build-up structure and reduce reliability. Each of the protective layers (390) may be a solder resist.

[0114] A lower build-up structure (400) may be disposed on the lower surface of the core portion (100). The lower build-up structure (400) may include a plurality of insulating layers (410) disposed in a vertical direction, a wiring portion (420) disposed on the surface of each of the plurality of insulating layers (410), and a via portion (430) connecting the plurality of wiring portions (420) and penetrating at least a portion of each of the plurality of insulating layers (410).

[0115] To minimize bending of the circuit board (10), the number of insulating layers (410) constituting the lower build-up structure (400) may be the same as the number of insulating layers (310) constituting the first build-up structure (300), but may be different.

[0116] Additionally, although not shown, a cavity penetrating one or more of the insulating layers may be disposed in the insulating layer (410) constituting the lower build-up structure (400), and an electronic component may be disposed in the cavity.

[0117] A protective layer (490) may be disposed on the lower surface of the lower build-up structure (400). When a semiconductor device is disposed on the surface of the lower build-up structure (400) using a material such as solder, the protective layer (490) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent external contaminants from penetrating into the build-up structure and reducing reliability. Each of the protective layers (490) may be a solder resist.

[0118] FIG. 6 is a drawing illustrating a modified example of a multiple cavity forming structure according to an embodiment of the present invention.

[0119]

[0120] *84 Referring to FIG. 6, the horizontal widths of the plurality of cavities (112, 132) may differ from one another. For example, the horizontal width (w1) of the first cavity (112) placed in the first core layer (110) may be larger than the horizontal width (w2) of the second cavity (132) placed in the second core layer (130). The first cavity (112) may include a first region that is vertically superimposed with the second cavity (132) and a second region that is placed on both sides of the first region and is not vertically superimposed with the second cavity (132). The horizontal width of the first electronic device (500) placed in the first cavity (112) may also be larger than the width of the second electronic device (600) placed in the second cavity (132). Accordingly, since multiple electronic elements of different sizes can be arranged vertically within the core part (100), there is an advantage in that an arrangement area for various types of electronic elements can be secured.

[0121] In addition, by arranging cavities having different widths in a vertical direction, there is an advantage in that the bending characteristics of the circuit board (10) can be controlled. For example, when an electronic device such as a semiconductor chip is placed in the center on the second build-up structure (300), the horizontal width of the first cavity (112) is formed to be larger than the horizontal width of the second cavity (132), so that the core part (100) can concentrate stress so that the central part protrudes upward, as shown in FIG. 6. As another example, when an electronic device such as a semiconductor chip is placed on the third build-up structure (400), the horizontal width of the second cavity (132) is formed to be larger than the horizontal width of the first cavity (112), so that the core part (100) can concentrate stress so that the central part protrudes downward. With the above structure, the stress within the circuit board (10) can be uniformly distributed in the vertical direction, so there is an advantage in that the bending of the circuit board (10) can be minimized.

[0122] FIG. 7 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, and FIG. 8 is a drawing for explaining the heat dissipation efficiency of a circuit board according to a fourth embodiment of the present invention.

[0123] Referring to FIGS. 7 and 8, a metal part (700) may be disposed in at least one of the plurality of cavities (112, 132). For example, the metal part (700) may be disposed in the first cavity (112). The metal part (700) may be provided in plurality and disposed in each of the plurality of first cavities (112). The metal part (700) may be disposed so as to overlap horizontally with the core via electrode (210). When the metal part (700) is disposed in the first cavity (112), an electronic element (600) is disposed in the second cavity (132), and the electronic element (600) and the metal part (700) may be disposed so as to overlap vertically. When the metal part (700) is placed in the second cavity (132), the electronic element (500) is placed in the first cavity (112), and the electronic element (500) and the metal part (700) can be placed so as to overlap in a vertical direction.

[0124] Accordingly, the heat dissipation efficiency of the circuit board (10) can be improved by the vertical overlapping structure of the electronic element (500, 600) and the metal part (700). Heat generated by the operation of the electronic element (500, 600) is transmitted in the vertical direction, and heat can be dissipated in the horizontal and vertical directions through the metal part (700). The metal part (700) can be embedded within the cavity (112, 132) through the first protrusion (162) of the aforementioned third insulating layer (160) or the second protrusion (172) of the fourth insulating layer (170).

[0125] Referring to FIG. 8 (a), when the metal part (700) is not placed, the temperature of the electronic device (500, 600) is 121.9 degrees, but referring to FIG. 3 (b), it can be seen that heat dissipation of the electronic device (500, 600) is achieved at a temperature of 120 degrees or less depending on the placement of the metal part (700).

[0126] FIG. 9 is a drawing illustrating a modified example of a plurality of cavity structure within a circuit board according to the fourth embodiment of the present invention.

[0127] Referring to FIG. 9, the horizontal widths of the plurality of cavities (112, 132) may differ from one another. For example, the horizontal width (w1) of the first cavity (112) disposed in the first core layer (110) may be larger than the horizontal width (w2) of the second cavity (132) disposed in the second core layer (130). The first cavity (112) may include a first region vertically overlapping with the second cavity (132) and a second region disposed on both sides of the first region that is not vertically overlapping with the second cavity (132).

[0128] For example, the horizontal width of the second cavity (132) in which the electronic element (600) is placed may be smaller than the horizontal width of the first cavity (112) in which the metal part (700) is placed. Accordingly, by forming the horizontal widths of the metal part (700) and the first cavity (112) larger than the horizontal widths of the electronic element (600) and the second cavity (132), respectively, there is an advantage in that the heat dissipation efficiency can be improved due to the increased heat dissipation area resulting from the increased size of the metal part (700).

[0129] In addition, by arranging cavities of different widths in a vertical direction, there is an advantage in that the bending characteristics of the circuit board (10) can be controlled. The explanation for this is to be based on the explanation in FIG. 6 described above.

[0130] FIGS. 10 to 20 are drawings for explaining the manufacturing process of a circuit board according to an embodiment of the present invention. FIGS. 10 to 20 illustrate the arrangement of a plurality of electronic elements (500, 600) within a plurality of cavities (112, 132) as an example, and can also be applied by analogy to cases where a metal part (700) is arranged in a plurality of cavities (112, 132).

[0131] Referring to FIG. 10, the manufacturing process of a circuit board according to an embodiment of the present invention may include a step of preparing a core layer (110, 130). The core layer (110, 130) may be a prepreg in which glass fibers (810) are disposed within a resin as described above. A metal foil (800) for forming a guide (820) may be disposed on the surface of the core layer (110, 130).

[0132] By etching a portion of the metal foil (800), a guide (820) may be formed on the surface of the core layer (110, 130) as shown in FIG. 11. The guide (820) may be an area for marking a processing area including a cavity (112, 132) and a through hole (200) within the core layer (110, 130). Additionally, the guide (820) may be an area for aligning a bond with another insulating layer within the core layer (110, 130).

[0133] As shown in FIG. 12, a cavity (112, 132) can be formed in a set area of ​​the core layer (110, 130) through a guide (820). After the cavity (112, 132) is formed, the surface of the core layer (110, 130), including the inner wall of the cavity (112, 132), can be desmeared.

[0134] As illustrated in FIG. 13, an adhesive layer (830) may be bonded to one side of the core layer (110, 130). The adhesive layer (830) has adhesive force on the surface bonded to the core layer (110, 130) and may be bonded to cover the cavity (112, 132) within the core layer (110, 130). Through the adhesive layer (830), the electronic element (500, 600) within the cavity (112, 132) may be primarily fixed in place. That is, as illustrated in FIG. 14, depending on the bonding of the electronic element (500, 600) within the cavity (112, 132), the electronic element (500, 600) may be fixed within the cavity (112, 132) by the adhesive layer (830).

[0135] Next, as illustrated in FIG. 15, an insulating layer (160, 170) may be laminated on the core layer (110, 130). Here, the insulating layer (160, 170) may be a third insulating layer (160) or a fourth insulating layer (170). The insulating layer for forming the third insulating layer (160) and the fourth insulating layer (170) may be bonded to the core layer (110, 130) through a film (840) attached to the surface of the resin. Depending on the bonding of the insulating layer (160, 170), the cavity (112, 132) may be filled through the protrusion (162, 172) of the insulating layer (160, 170).

[0136] Next, as shown in FIG. 16, the adhesive layer (830) can be separated from the core layer (110, 130). In this case, the adhesive layer (830) of the electronic element (500, 600) can be easily separated by the protrusions (162, 172) of the insulating layer (160, 170). Next, as shown in FIG. 17, the film (840) on the surface of the insulating layer (160, 170) can also be separated.

[0137] Afterwards, as shown in FIG. 18, a plurality of core layers (110, 130) formed by the process of FIG. 10 to 16 can be stacked on one side and the other side of the interlayer insulating layer (150), respectively. Accordingly, as shown in FIG. 19, the first core layer (110), the second core layer (130), the third insulating layer (160), and the fourth insulating layer (170) can be stacked vertically with respect to the interlayer insulating layer (150).

[0138] Meanwhile, if the interlayer insulation layer (150) includes a plurality of insulation layers, a first core layer (110) and a third insulation layer (160) are laminated on one of the plurality of insulation layers, and a second core layer (130) and a fourth insulation layer (170) are laminated on another insulation layer, so that the plurality of insulation layers of the interlayer insulation layer (150) are joined in a vertical direction.

[0139] Next, as illustrated in FIG. 20, the method may include the step of laminating a first insulating layer (101) on the lower surface of the first core layer (110) and the step of laminating a second insulating layer (102) on the upper surface of the second core layer (130). Afterwards, the core portion (100) may include the step of forming a through hole (200) for forming a through core via electrode (210) by integrally integrating the first insulating layer (101), the first core layer (110), the third insulating layer (160), the interlayer insulating layer (150), the fourth insulating layer (170), the second core layer (130), and the second insulating layer (102).

[0140] Hereinafter, a circuit board according to the fifth embodiment of the present invention will be described.

[0141] FIG. 21 is a cross-sectional view of a circuit board according to the fifth embodiment of the present invention, FIG. 22 is an enlarged view of the core portion in FIG. 21, FIG. 23 is an enlarged view of a core via electrode according to the fifth embodiment of the present invention, FIG. 24 is a modified example of a core via electrode according to the fifth embodiment of the present invention, and FIG. 25 is a modified example of a circuit board according to the fifth embodiment of the present invention.

[0142] Referring to FIGS. 21 and 22, a circuit board (20) according to the fifth embodiment of the present invention may include a core part (1100), a first build-up structure (1300), a second build-up structure (1400), and a metal part (1240).

[0143] The circuit board (20) may include a core portion (1100). The core portion (1100) may be a component forming the base of the circuit board (20). Based on the vertical direction of the circuit board (20), the core portion (1100) may be positioned in the center. The material of the core layer (1100) may include at least one selected from the group consisting of glass, resin, plastic, and metal.

[0144] The core portion (1100) may include a plurality of insulating layers stacked in a vertical direction. When the core portion (1100) is implemented with a plurality of insulating layers, the degree of design freedom regarding the formation of pads and via electrodes is increased according to the structure in which the plurality of insulating layers are stacked vertically, and thus there is an advantage that production efficiency can be improved. In addition, the core portion (1100) may have a structure in which a plurality of reinforcing members are stacked along the vertical direction within at least one insulating layer among each insulating layer. In addition, at least two of the reinforcing members may be provided with different materials.

[0145] The core portion (1100) may include a first core layer (1130), a second core layer (1110) disposed on the first core layer (1130), and an inter-layer insulating layer (1150) disposed between the first core layer (1130) and the second core layer (1110).

[0146] The first core layer (1130) can be placed on the second build-up structure (1400).

[0147] The first core layer (1130) may be a thermosetting insulator. The first core layer (1130) may be a prepreg (PPG) containing glass fibers in a resin. The resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenolic resin, etc., and the inorganic and / or organic filler may be provided with materials such as silica, plastic, etc. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers, etc.

[0148] The second core layer (1110) can be placed on the first core layer (1130). The second core layer (1110) can be placed on the interlayer insulating layer (1150).

[0149] The second core layer (1110) may be a thermosetting insulator. The second core layer (1110) may be a prepreg (PPG) containing glass fibers in a resin. The resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenolic resin, etc., and the inorganic and / or organic filler may be provided with materials such as silica, plastic, etc. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers, etc.

[0150] The second core layer (1110) may include cavities (1210, 1230). The cavities (1210, 1230) may have a shape that penetrates from the upper surface to the lower surface of the second insulating layer (1110). The cavities (1210, 1230) may be named through holes.

[0151] Cavities (1210, 1230) may include a first cavity (1210) and a second cavity (1230). The first cavity (1210) and the second cavity (1230) may be arranged alternately along the horizontal direction of the second core layer (1110). An electronic element (1220) may be disposed in the first cavity (1210). The first cavity (1210) may be provided in multiple numbers and arranged along the horizontal direction of the second core layer (1110). A plurality of electronic elements (1220) may be disposed in each of the plurality of first cavities (1210). A second cavity (1230) may be disposed between the plurality of first cavities (1210).

[0152] By arranging the electronic element (1220) in the first cavity (1210), the circuit board (20) can form a semiconductor package together with the electronic element (1220).

[0153] A metal part (1240) may be disposed in the second cavity (1230). The second cavity (1230) may be provided in multiple numbers and arranged along the horizontal direction of the second core layer (1110). A plurality of metal parts (1240) may be disposed in each of the plurality of second cavities (1230). A first cavity (1210) may be disposed between the plurality of second cavities (1230).

[0154] As shown in FIG. 22, the horizontal width (W1) of the first cavity (1210) may be shorter than the horizontal width (W2) of the second cavity (1230). Accordingly, the arrangement space for the metal part (1240) for heat dissipation can be formed wider to increase heat dissipation efficiency.

[0155] However, this is not limited to the horizontal width (W1) of the first cavity (1210) may be longer than the horizontal width (W2) of the second cavity (1230). Accordingly, the placement space for the electronic device (1220) can be secured more widely.

[0156] The horizontal width (W1) of the first cavity (1210) may be larger than the horizontal width of the electronic element (1220). The horizontal width (W2) of the second cavity (1230) may be larger than the horizontal width of the metal part (1240).

[0157] An interlayer insulating layer (1150) can be placed between the first core layer (1130) and the second core layer (1110).

[0158] The interlayer insulating layer (1150) may be any insulating material, such as a photocurable and / or thermosetting material. The interlayer insulating layer (1150) may be an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), as shown in FIG. 23, or may use a prepreg (PPG) containing glass fibers within a resin, as shown in FIG. 25. If the interlayer insulating layer (1150) is a photocurable insulating material, the interlayer insulating layer (1150) may be a PID (Photo Imageable Dielectric).

[0159] As illustrated in FIG. 22, the interlayer insulating layer (1150) may include a base (1151) and protrusions (1152, 1154) protruding from the base (1151) toward the cavity (1210, 1230). The base (1151) may be positioned between the lower surface of the second core layer (1110) and the upper surface of the first core layer (1130). The protrusions (1152, 1154) may include a first protrusion (1152) protruding from the base (1151) and coupled to the first cavity (1210), and a second protrusion (1154) coupled to the second cavity (1230). An electronic component (1220) within the first cavity (1210) can be embedded through the first protrusion (1152). A metal part (1240) within the second cavity (1230) can be embedded through the second protrusion (1154). Accordingly, the electronic component (1220) and the metal part (1240) can be firmly fixed through the first protrusion (1152) and the second protrusion (1154) within the cavity (1210, 1230). The protrusions (1152, 1154) can be positioned between the inner surface of the cavity (1210, 1230) and the outer surface of the electronic component (1220) or the metal part (1240).

[0160] As illustrated in FIG. 25, if the interlayer insulating layer (1150) is prepreg (PPG), the protrusions (1152, 1154) may be omitted. In this case, a molding portion may be disposed in the cavity (1210, 1230) to embed an electronic element (1220) and / or a metal portion (1240) within the cavity (1210, 1230).

[0161] The core portion (1100) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0162] A plurality of wiring sections may each be disposed on the surface of at least one of the plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within the plurality of insulating layers or protective layers and exposed to the outside from the surface. The wiring section may also be referred to as a metal layer. Furthermore, the surfaces of the plurality of insulating layers each include a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of the wiring section being disposed on the surface means that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0163] A plurality of wiring sections of the core section (1100) may include a first wiring section (1254) disposed on the lower surface of the first core layer (1130) and a second wiring section (1252) disposed on the upper surface of the second core layer (1110). The first wiring section (1254) may be disposed on the lower surface of the first core layer (1130). The second wiring section (1252) may be disposed on the upper surface of the second core layer (1110).

[0164] A plurality of wiring sections of the core section (1110) may include connecting wiring sections (1118) connected to electronic elements (1220). The connecting wiring sections (1118) are disposed on the upper surface of the second core layer (1110) and may be disposed to overlap horizontally with the second wiring section (1252). A plurality of connecting wiring sections (1118) may be provided, such that some of them are connected to one of the plurality of electronic elements (1220), and other parts are connected to another of the plurality of electronic elements (1220).

[0165] The via portion of the core portion (1100) may include a core via electrode (1256).

[0166] The core portion (1100) may include a via hole (1250). The via hole (1250) may have a shape that penetrates from the upper surface to the lower surface of the core portion (1100). The via hole (1250) may be arranged to overlap horizontally with the first core layer (1130), the second core layer (1110), and the interlayer insulating layer (1150), respectively. The via hole (1250) may be arranged to overlap horizontally with the electronic element (1220) and the metal portion (1240). The via hole (1250) may have a circular cross-sectional shape, but is not limited thereto.

[0167] The core via electrode (1256) may be positioned along the inner wall of the via hole (1250). The core via electrode (1256) may be positioned to penetrate the core portion (1110). The core via electrode (1256) may be positioned to overlap horizontally with the first core layer (1130), the second core layer (1110), and the interlayer insulating layer (1150), respectively. The core via electrode (1256) may be positioned to overlap horizontally with the electronic element (1220) and the metal portion (1240). The core via electrode (1256) may connect the first wiring portion (1254) and the second wiring portion (1252).

[0168] A hollow is formed on the inner side of the core via electrode (1256), and a filling material (1258) can be filled into the hollow. Accordingly, the connection of the core via electrode (1256) within the via hole (1250) can be firmly maintained, and electrical loss of the core via electrode (1256) along the vertical direction can be minimized.

[0169] As described above, the core portion (1100) may include a plurality of insulating layers arranged in a vertical direction. In this case, as shown in FIG. 23, during the process of forming the via hole (1250), a groove (1180) may be formed at the bonding interface between the plurality of insulating layers due to a seepage phenomenon depending on the difference in the degree of hardening between two insulating layers adjacent in the vertical direction. The groove (1180) may have a shape that is more concave than other areas, extending outward in the horizontal direction from the inner wall of the via hole (1250).

[0170] Due to the shape of the inner wall of the via hole (1250) by the groove (1180), the core via electrode (1256) may include a projection (1257) that is coupled to the groove (1180). The projection (1257) may have a shape that protrudes outward from the outer surface of the core via electrode (1256) more than other regions. Accordingly, the region where the projection (1257) is formed on the outer surface of the core via electrode (1256) may have a wider horizontal width than other regions. Due to the projection (1257), the core via electrode (1256) may have regions with different horizontal widths. The region where the projection (1257) is formed on the core via electrode (1256) may have a wider horizontal width than the region where the projection (1257) is not formed. Accordingly, as resistance is reduced by the increased width area of ​​the core via electrode (1256), power transfer efficiency can be improved. The protrusions (1257) may be provided in multiple numbers and arranged along the vertical direction. For example, the protrusions (1257) may be arranged between the first core layer (1130) and the interlayer insulating layer (1150), and between the interlayer insulating layer (1150) and the second core layer (1110), respectively.

[0171] As illustrated in FIG. 24, the material of the interlayer insulating layer (1150) may be different from the material of the insulating layer constituting the first core layer (1100) or the second core layer (1200). For example, the insulating layer constituting the first core layer (1100) and / or the insulating layer constituting the second core layer (200) may be a prepreg (PPG) containing glass fibers in a resin. The interlayer insulating layer (1150) may be ABF (Ajinomoto Build-up Film) or PID (Photo Imageable Dielectric).

[0172] Accordingly, due to differences in hardness or physical properties of multiple insulating layers arranged in a vertical direction, the via hole (1250) in the arrangement area of ​​the interlayer insulating layer (1150) with relatively low strength, as shown in FIG. 24, may include an extension with a large horizontal width. The area where the extension is formed may have a larger horizontal width than other areas. Accordingly, the core via electrode (1256) may also include an extension (1259) corresponding to the area where the extension (1259) is formed. As resistance is reduced by the increased width area of ​​the core via electrode (1256) through the extension (1259), power transfer efficiency may be improved. The extension (1259) may be arranged between the first core layer (1130) and the second core layer (1110).

[0173] The circuit board (20) may include a metal part (1240). At least a portion of the metal part (1240) may be embedded in the second core layer (1110). The metal part (1240) may be placed between a plurality of electronic elements (1220). The metal part (1240) may be provided in a plurality and may be arranged alternately along the horizontal direction with the electronic elements (1220). The metal part (1240) may be placed between the plurality of electronic elements (1220). The electronic elements (1220) may be placed between the plurality of metal parts (1240). Accordingly, heat generated by the operation of the electronic elements (1220) may be dissipated in the horizontal direction through the metal part (1240). The horizontal width of the metal part (1240) may be greater than the horizontal width of the electronic elements (1220).

[0174] The metal part (1240) can be firmly fixed within the second cavity (1230) through the second protrusion (1154) of the interlayer insulating layer (1150).

[0175] The metal part (1240) may include a protrusion (1244) that penetrates at least a portion of the interlayer insulation layer (1150) and the first core layer (1130). The protrusion (1150) may be positioned to penetrate the interlayer insulation layer (1150) and the first core layer (1130). The protrusion (1150) may be positioned to overlap horizontally with the interlayer insulation layer (1150) and the first core layer (1130). The lower surface of the protrusion (1150) may be positioned to overlap horizontally with the lower surface of the first core layer (1130).

[0176] When the area of ​​the metal part (1240) embedded within the second cavity (1230) is referred to as the metal part body (1242), the protrusion (1244) may have a shape that protrudes downward in a vertical direction from the metal part body (1242). The protrusion (1244) may have a bar or plate shape. The protrusion (1244) may be provided in multiple numbers and arranged along the horizontal direction relative to a single metal part body (1242). A hole through which the protrusion (1244) passes may be formed in the interlayer insulating layer (1150) and the first core layer (1130). The protrusion (1244) may be arranged to overlap in a vertical direction with respect to the core via electrode (1256).

[0177] Heat dissipation efficiency can be improved by increasing the heat dissipation area of ​​the metal part (1240) through the protrusion (1244). Heat from the metal part body (1242) that overlaps the electronic element (1220) in a horizontal direction can be conducted in a vertical direction through the protrusion (1244). In addition, as the protrusion (1244) is provided in multiple numbers, multiple heat discharge paths are also formed, allowing heat dissipation to occur more quickly.

[0178] A first metal layer (1245) may be disposed on the lower surface of the core portion (1100). The first metal layer (1245) may be disposed on the lower surface of the first core layer (1130). The first metal layer (1245) may be disposed so as to overlap vertically with the metal portion body (1242). A protrusion (1244) may connect the metal portion body (1242) and the first metal layer (1245). Based on the protrusion (1244), the metal portion body (1242) may be disposed at the top of the protrusion (1244), and the first metal layer (1245) may be disposed at the bottom. The first metal layer (1245) may be disposed so as to overlap horizontally with the first wiring portion (1254). The first metal layer (1245) may have a plate shape.

[0179] Heat generated from the metal body (1242) can be transferred to the first metal layer (1245) to enable heat dissipation. The horizontal width of the first metal layer (1245) may be equal to or greater than the horizontal width of the metal body (1242). Accordingly, the heat dissipation efficiency through the first metal layer (1245) on the lower surface of the core part (1100) can be increased.

[0180] A second metal layer (1248) may be disposed on the upper surface of the core part (1100). The second metal layer (1248) may be disposed on the upper surface of the second core layer (1110). The second metal layer (1248) may be disposed so as to overlap in a vertical direction with the metal part body (242). The second metal layer (1248) may be disposed so as to overlap in a vertical direction with the first metal layer (1245).

[0181] The second metal layer (1248) may be arranged to overlap the second wiring section (1252) in a horizontal direction. The second metal layer (1248) may have a plate shape.

[0182] Heat generated from the metal body (1242) can be transferred to the second metal layer (1248) to dissipate heat. The horizontal width of the second metal layer (1248) may be equal to or greater than the horizontal width of the metal body (1242). Accordingly, the heat dissipation efficiency through the second metal layer (1248) on the lower surface of the core part (1100) can be increased. That is, heat generated from the electronic element (1220) is conducted to the metal body (1242) along the horizontal direction, and heat from the metal body (1242) is transferred in both the upper and lower directions in the vertical direction, so that heat can be efficiently dissipated through the plurality of metal layers (1245, 1248).

[0183] Referring to FIG. 21, a first build-up structure (1300) may be disposed on the upper surface of the core portion (1100). The first build-up structure (1300) may include a plurality of insulating layers (1310) disposed in a vertical direction, a wiring portion (1320) disposed on the surface of each of the plurality of insulating layers (1310), and a via portion (1330) connecting the plurality of wiring portions (1320) and penetrating at least a portion of each of the plurality of insulating layers (1310).

[0184] A cavity penetrating one or more of the insulating layers may also be disposed in the insulating layer (1310) constituting the first build-up structure (1300). An electronic element (1360, 1370) may be disposed in the cavity of the first build-up structure (1300), and the electronic element (1360, 1370) disposed within the first build-up structure (1300) may be arranged in a stepped manner in the vertical direction and may be electrically connected to the electronic element (1220) embedded in the core part (1100).

[0185] A protective layer (1390) may be disposed on the first build-up structure (1300). When a semiconductor device is disposed on the surface of the first build-up structure (1300) using a material such as solder, the protective layer (1390) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent problems where external contaminants penetrate into the build-up structure and reduce reliability. Each protective layer (1390) may be a solder resist.

[0186] A second build-up structure (1400) may be disposed on the lower surface of the core portion (1100). The second build-up structure (1400) may include a plurality of insulating layers (1410) disposed in a vertical direction, a wiring portion (1420) disposed on the surface of each of the plurality of insulating layers (1410), and a via portion (1430) connecting the plurality of wiring portions (1420) and penetrating at least a portion of each of the plurality of insulating layers (1410).

[0187] In order to minimize bending of the circuit board (20), the number of insulating layers (1410) constituting the second build-up structure (1400) may be the same as the number of insulating layers (1310) constituting the first build-up structure (1300), but may be different.

[0188] Additionally, although not shown, a cavity penetrating one or more of the insulating layers may be disposed in the insulating layer (1410) constituting the second build-up structure (1400), and an electronic element may be disposed in the cavity.

[0189] A protective layer (1490) may be disposed on the lower surface of the second build-up structure (1400). When a semiconductor device is disposed on the surface of the second build-up structure (1400) using a material such as solder, the protective layer (1490) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent problems where external contaminants penetrate into the build-up structure and reduce reliability. Each protective layer (1490) may be a solder resist.

[0190] Hereinafter, a circuit board according to the 6th embodiment of the present invention will be described.

[0191] In this embodiment, other parts are identical to the fifth embodiment, except for a difference in the number of insulating layers constituting the first core layer and the second core layer. Therefore, below, only the characteristic parts of this embodiment will be described, and for the remaining parts, the description according to the fifth embodiment will be used.

[0192] FIG. 26 is a cross-sectional view of a circuit board according to the 6th embodiment of the present invention, FIG. 27 is an enlarged view of the core portion in FIG. 26, FIG. 28 is an enlarged view of a core via electrode according to the 6th embodiment of the present invention, FIG. 29 is a modified example of a core via electrode according to the 6th embodiment of the present invention, and FIG. 30 is a modified example of a circuit board according to the 6th embodiment of the present invention.

[0193] Referring to FIGS. 26 to 30, the circuit board according to the present embodiment may include a core part (1100), a first build-up structure (1300), a second build-up structure (1400), and a metal part (1240).

[0194] The core portion (1100) may include a first core layer (1130), a second core layer (1110) disposed on the first core layer (1130), and an inter-layer insulating layer (1150) disposed between the first core layer (1130) and the second core layer (1110).

[0195] The first core layer (1130) may include a first insulating layer (1131), a second insulating layer (1132) disposed on the first insulating layer (1131), and a third insulating layer (1133) disposed on the second insulating layer (1132). The first to third insulating layers (1131, 1132, 1133) may be arranged in a vertical direction.

[0196] The first to third insulating layers (1131, 1132, 1133) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used as an example, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to third insulating layers (1131, 1132, 1133) are photocurable insulators, the first to third insulating layers (1131, 1132, 1133) may each be a PID (Photo Imageable Dielectric).

[0197] The vertical thickness of the first insulating layer (1131) may be thicker than the vertical thickness of the second insulating layer (1132) and / or the third insulating layer (1133). Accordingly, warpage of the circuit board (20) can be minimized through the first insulating layer (1131) forming the lower surface of the core portion (1100). The vertical thickness of the second insulating layer (1132) and the vertical thickness of the third insulating layer (1133) may be the same.

[0198] The second core layer (1110) may be disposed on the first core layer (1130). The second core layer (1110) may be disposed on the interlayer insulating layer (1150). The second core layer (1110) may include a fourth insulating layer (1111) and a fifth insulating layer (1112) disposed on the fourth insulating layer (1111).

[0199] The fourth insulating layer (1111) and the fifth insulating layer (1112) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used as an example, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resins mentioned above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the fourth insulating layer (1111) and the fifth insulating layer (1112) are photocurable insulators, the fourth insulating layer (1111) and the fifth insulating layer (1112) may each be a PID (Photo Imageable Dielectric).

[0200] The vertical thickness of the fourth insulating layer (1111) may be thicker than the vertical thickness of the fifth insulating layer (1112). Accordingly, warpage of the circuit board (20) can be minimized through the fourth insulating layer (1111) which is positioned relatively close to the vertical center of the core portion (1100). In addition, by forming the vertical thickness of the fifth insulating layer (1112) positioned on the upper surface of the core portion (1100) relatively small, it is easy to implement a fine pattern and increase the wiring density. In addition, as a cavity (1210, 1230) is formed within the fourth insulating layer (1111) in which an electronic element (1220) and a metal part (1240), which will be described later, are disposed, the vertical thickness of the fourth insulating layer (1111) is formed relatively thickly, thereby securing a large space for disposing of the electronic element (1220) and the metal part (1240).

[0201] Cavities (1210, 1230) may be disposed in the fourth insulating layer (1111). Cavities (1210, 1230) may have a shape that penetrates from the upper surface to the lower surface of the fourth insulating layer (1111). Cavities (1210, 1230) may be named through holes.

[0202] A plurality of first cavities (1210) may be provided and arranged along the horizontal direction of the fourth insulating layer (1111). A plurality of electronic elements (1220) may be arranged in each of the plurality of first cavities (1210). A second cavity (1230) may be arranged between the plurality of first cavities (1210).

[0203] A metal part (1240) may be disposed in the second cavity (1230). The second cavity (1230) may be provided in multiple numbers and arranged along the horizontal direction of the fourth insulating layer (1111). A plurality of metal parts (1240) may be disposed in each of the plurality of second cavities (1230). A first cavity (1210) may be disposed between the plurality of second cavities (1230).

[0204] The interlayer insulation layer (1150) can be placed between the fourth insulation layer (1111) and the third insulation layer (1133).

[0205] The interlayer insulating layer (1150) may include a base (1151) and protrusions (1152, 1154) protruding from the base (1151) toward the cavity (1210, 1230). The base (1151) may be positioned between the lower surface of the fourth insulating layer (1111) and the upper surface of the third insulating layer (1133). The protrusions (1152, 1154) may include a first protrusion (1152) protruding from the base (1151) and coupled to the first cavity (1210), and a second protrusion (1154) coupled to the second cavity (1230). An electronic element (1220) within the first cavity (1210) may be embedded through the first protrusion (1152). A metal part (1240) inside a second cavity (1230) can be embedded through the second protrusion (1154). Accordingly, an electronic element (1220) and a metal part (1240) can be firmly fixed through the first protrusion (1152) and the second protrusion (1154) inside the cavity (1210, 1230). The protrusion (1152, 1154) can be positioned between the inner surface of the cavity (1210, 1230) and the outer surface of the electronic element (1220) or the metal part (1240).

[0206] A plurality of wiring sections of the core section (1100) may include a first wiring section (1254) disposed on the lower surface of the first core layer (1130) and a second wiring section (1252) disposed on the upper surface of the second core layer (1110). The first wiring section (1254) may be disposed on the lower surface of the first insulating layer (1131). The second wiring section (1252) may be disposed on the upper surface of the fifth insulating layer (1112).

[0207] A plurality of wiring sections of the core section (1110) may include connecting wiring sections (1118) connected to electronic elements (1220). The connecting wiring sections (1118) are disposed on the upper surface of the fifth insulating layer (1112) and may be disposed to overlap horizontally with the second wiring section (1252). A plurality of connecting wiring sections (1118) may be provided, such that some of them are connected to one of the plurality of electronic elements (1220), and other parts are connected to another of the plurality of electronic elements (1220).

[0208] The core portion (1100) may include a core via electrode (1256).

[0209] As illustrated in FIG. 28, during the formation process of the via hole (1250), a groove (1180) may be formed at the bonding interface between multiple insulating layers due to a seepage phenomenon, depending on the difference in the degree of curing between two insulating layers adjacent in the vertical direction. The groove (1180) may have a shape that is more concave than other areas, extending outward from the inner wall of the via hole (1250) in the horizontal direction.

[0210] Due to the shape of the inner wall of the via hole (1250) by the groove (1180), the core via electrode (1256) may include a projection (1257) that is coupled to the groove (1180). The projection (1257) may be disposed between the first insulating layer (1131) and the second insulating layer (1132), between the second insulating layer (1132) and the third insulating layer (1133), between the third insulating layer (1133) and the interlayer insulating layer (1150), between the interlayer insulating layer (1150) and the fourth insulating layer (1111), and between the fourth insulating layer (1111) and the fifth insulating layer (1112), respectively.

[0211] Due to differences in hardness or physical properties of multiple insulating layers arranged in a vertical direction, as illustrated in FIG. 29, the via hole (1250) in the arrangement area of ​​the interlayer insulating layer (1150) with relatively low strength may include an extension with a large horizontal width. The area where the extension is formed may have a larger horizontal width than other areas. Accordingly, the core via electrode (1256) may also include an extension (1259) corresponding to the area where the extension (1259) is formed. As resistance is reduced by the increased width area of ​​the core via electrode (1256) through the extension (1259), power transfer efficiency may be improved. The extension (1259) may be arranged between the third insulating layer (1133) and the fourth insulating layer (1111).

[0212] As illustrated in FIG. 27, a plurality of vias of the core portion (1100) may include a connecting via portion (1117). The connecting via portion (1117) may be positioned to penetrate at least a portion of the fifth insulating layer (1112). The lower end of the connecting via portion (1117) may be connected to the first cavity (1210). The connecting via portion (1117) may electrically connect the connecting wiring portion (1118) and the pad of the electronic element (1220) placed in the first cavity (1210). The connecting via portion (1246) may be positioned to overlap horizontally with the core via electrode (1256).

[0213] The metal part (1240) may include a protrusion (1244) that penetrates at least a portion of the interlayer insulation layer (1150) and the first core layer (1130). The protrusion (1150) may be positioned to penetrate the interlayer insulation layer (1150) and the first to third insulation layers (1131, 1132, 1133) of the first core layer (1130). The protrusion (1150) may be positioned to overlap horizontally with the interlayer insulation layer (1150) and the first to third insulation layers (1131, 1132, 1133). The lower surface of the protrusion (1150) may be positioned to overlap horizontally with the lower surface of the first insulation layer (1131).

[0214] A first metal layer (1245) may be disposed on the lower surface of the core portion (1100). The first metal layer (1245) may be disposed on the lower surface of the first insulating layer (1131). The first metal layer (1245) may be disposed so as to overlap vertically with the metal body (242). A protrusion (1244) may connect the metal body (1242) and the first metal layer (1245). Based on the protrusion (1244), the metal body (1242) may be disposed at the top of the protrusion (1244), and the first metal layer (1245) may be disposed at the bottom. The first metal layer (1245) may be disposed so as to overlap horizontally with the first wiring portion (1254). The first metal layer (1245) may have a plate shape.

[0215] A second metal layer (1248) may be disposed on the upper surface of the core portion (1100). The second metal layer (1248) may be disposed on the upper surface of the fifth insulating layer (1112). The second metal layer (1248) may be disposed so as to overlap in a vertical direction with the metal portion body (1242). The second metal layer (1248) may be disposed so as to overlap in a vertical direction with the first metal layer (1245).

[0216] The circuit board (20) may include a heat dissipation via (1246) connecting the second metal layer (1248) and the metal body (1242). The heat dissipation via (1246) may be arranged to penetrate the fourth insulating layer (1111). The heat dissipation via (1246) may be provided in multiple numbers and arranged along the horizontal direction. The heat dissipation via (1246) may have a shape in which the horizontal width gradually decreases as it faces the fourth insulating layer (1111).

[0217] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0218] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0219] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0220] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A core portion comprising a first core layer, a second core layer disposed on the first core layer, and an interlayer insulating layer disposed between the first core layer and the second core layer; An upper build-up structure disposed on the upper surface of the above-mentioned core portion and comprising a plurality of stacked insulating layers; A lower build-up structure disposed on the lower surface of the core portion and comprising a plurality of stacked insulating layers; and It includes a core via electrode penetrating the upper and lower surfaces of the core portion, and The first core layer and the second core layer each include at least one cavity, and The above core via electrode is a circuit board superimposed along the horizontal direction with the cavity of the first core layer and the cavity of the second core layer.

2. In Paragraph 1, The above core portion comprises a first insulating layer disposed between the first core layer and the lower build-up structure, a second insulating layer disposed between the second core layer and the upper build-up structure, a third insulating layer disposed between the interlayer insulating layer and the first core layer, and a fourth insulating layer disposed between the interlayer insulating layer and the second core layer.

3. In Paragraph 2, The third insulating layer includes a first protrusion protruding toward the lower build-up structure, and The first protrusion is a circuit board disposed within the cavity of the first core layer.

4. In Paragraph 2, The above-mentioned fourth insulating layer includes a second protrusion protruding toward the upper build-up structure, and The above second protrusion is a circuit board disposed within the cavity of the above second core layer.

5. In Paragraph 1, The cavity of the first core layer and the cavity of the second core layer are vertically superimposed circuit boards.

6. In Paragraph 1, The cavities of the first core layer are provided in plurality and arranged to overlap in the horizontal direction, and A circuit board having a plurality of cavities in the second core layer and arranged to overlap in a horizontal direction.

7. In Paragraph 6, The plurality of first core layer cavities and the plurality of second core layer cavities are each vertically superimposed circuit boards.

8. In Paragraph 1, A circuit board in which the horizontal width of the cavity of the first core layer is the same as the horizontal width of the cavity of the second core layer.

9. In Paragraph 1, A circuit board in which the horizontal width of the cavity of the first core layer is different from the horizontal width of the cavity of the second core layer.

10. In Paragraph 1, The core via electrode is a circuit board that integrally penetrates the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the interlayer insulating layer, the first core layer, and the second core layer.

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