Plasma chamber with direct coupling of capacitively controlled power to edge ring for voltage equalization at interface between substrate and edge ring

Abstract

A system including a plasma chamber configured for generating plasma with a lower electrode located within an electrostatic chuck (ESC), and an upper electrode disposed above the lower electrode. The system includes an edge ring surrounding the lower electrode. A main power generator is electrically coupled to the lower electrode and the edge ring via a common node, and is configured to supply a pulsed direct current (DC) power signal to the common node. A variable capacitor is electrically coupled between the common node and the edge ring, wherein the variable capacitor splits the pulsed DC power signal into a bias power signal delivered to the lower electrode and a tunable edge sheath (TES) power signal delivered to the edge ring. A high frequency power source is electrically coupled to the upper electrode and configured to supply a high frequency radio frequency (RE) power signal to the upper electrode.

Description

PLASMA CHAMBER WITH DIRECT COUPLING OF CAPACITIVELY CONTROLLED POWER TO EDGE RING FOR VOLTAGE EQUALIZATION AT INTERFACE BETWEEN SUBSTRATE AND EDGE RINGTECHNICAL FIELD

[0001] The present embodiments relate to semiconductor fabrication, and more specifically to systems and methods for controlling plasma density (i.e., achieving plasma uniformity) at the edge of a substrate using a capacitively coupled plasma chamber providing capacitively controlled power to an edge ring to achieve desired system capacitances at an edge of a substrate to achieve voltage equalization at the interface between the substrate and edge ring.BACKGROUND OF THE DISCLOSURE

[0002] Many modern semiconductor chip fabrication processes such as plasma etching processes are performed within a plasma processing chamber in which a substrate, e.g., wafer, is supported on an electrostatic chuck (ESC). In plasma etching processes, the wafer is exposed to a plasma generated within a plasma processing volume. Plasma contains various types of radicals, electrons, as well as positive and negative ions. The chemical reactions of the various radicals, electrons, positive ions, and negative ions are used to etch features, surfaces and materials of a wafer.

[0003] For example, when a process gas is supplied into the plasma processing chamber, one or more radio frequency (RF) signals provide power that are applied to one or more electrodes and coils of the plasma processing chamber to form an electric field. The process gas is turned into plasma by the RF signals, thereby performing plasma etching on a predetermined layer disposed on the wafer. Unfortunately, during wafer processing, the plasma non-uniformity arising from plasma generation zones may result in ions striking the wafer with a non-vertical direction (e.g., ion tilt angles) occurring all across the wafer and along the extreme edge of the wafer which may cause tilted etch features in the wafer.

[0004] It is in this context that embodiments of the disclosure arise.SUMMARY

[0005] The present embodiments relate to plasma processing systems for controlling plasma density and / or plasma uniformity at an edge of a substrate plasma uniformity using a capacitively coupled plasma chamber providing capacitively controlled power to an edge ring to achieve desired system capacitances at an edge of a substrate to achieve voltage equalization at the interface between the substrate and edge ring. Several inventive embodiments of the present disclosure are described below.

[0006] Embodiments of the present disclosure provide for a system. The system including a plasma chamber configured for generating plasma, wherein the plasma chamber includes a lowerelectrode located within an electrostatic chuck (ESC. The system including an upper electrode disposed above the lower electrode. The system including an edge ring surrounding the lower electrode. The system including a main power generator electrically coupled to the lower electrode and the edge ring via a common node, wherein the main power generator is configured to supply a pulsed direct current (DC) power signal to the common node. The system including a variable capacitor electrically coupled between the common node and the edge ring, wherein the variable capacitor splits the pulsed DC power signal into a bias power signal delivered to the lower electrode and a tunable edge sheath (TES) power signal delivered to the edge ring. The system including a high frequency power source electrically coupled to the upper electrode and configured to supply a high frequency radio frequency (RF) power signal to the upper electrode.

[0007] Other embodiments of the present disclosure provide for another system. The system including a plasma chamber configured for generating plasma, wherein the plasma chamber includes a lower electrode located within an electrostatic chuck (ESC). The system including an upper electrode disposed above the lower electrode. The system including an edge ring surrounding the lower electrode. The system including a main power generator electrically coupled to the lower electrode and the edge ring via a common node, wherein the main power generator is configured to supply a pulsed direct current (DC) power signal to the common node. The system including a variable capacitor electrically coupled between the common node and the edge ring, wherein the variable capacitor splits the pulsed DC power signal into a bias power signal delivered to the lower electrode and a tunable edge sheath (TES) power signal delivered to the edge ring. The system including a high frequency power source electrically coupled to the lower electrode and configured to supply a high frequency radio frequency (RF) power signal to the lower electrode.

[0008] These and other advantages will be appreciated by those skilled in the art upon reading the entire specification and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments may best be understood by reference to the following description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 A illustrates an embodiment of a capacitively coupled plasma processing system configured for splitting main power to a lower electrode and an edge ring, wherein the power to the edge ring is capacitively controlled using a variable capacitor, wherein a high frequency radio frequency power signal is delivered to the lower electrode, in accordance with one embodiment of the present disclosure.

[0011] FIG. IB illustrates an embodiment of a capacitively coupled plasma processing system configured for splitting main power to a lower electrode and an edge ring, wherein the power to the edge ring is capacitively controlled using a variable capacitor, wherein a high frequency radio frequency power signal is delivered to an upper electrode, in accordance with one embodiment of the present disclosure.

[0012] FIG. 2 illustrates capacitance measurement locations in the CCP processing system of FIG. 1 used for providing capacitively controlled power to an edge ring to achieve desired system capacitances at the edge of a substrate in order to achieve voltage equalization at the interface between the substrate and edge ring, in accordance with one embodiment of the present disclosure.

[0013] FIG. 3 A illustrates direct coupling of capacitively controlled power to an edge ring to achieve desired system capacitances at an interface between a substrate and edge ring, in accordance with one embodiment of the present disclosure.

[0014] FIG. 3B illustrates direct coupling of capacitively controlled power to an edge ring including an interfacing between a threaded socket and threaded hole in the edge ring, in accordance with one embodiment of the disclosure.

[0015] FIG. 4 illustrates an opportunity for tuning voltages at a substrate and / or edge ring to achieve voltage equalization at an interface between the substrate and edge ring, in accordance with one embodiment of the present disclosure.

[0016] FIGS. 5a-5b illustrate measured voltage waveforms on a substrate and edge ring that are tunable to achieve matching waveforms, in accordance with one embodiment of the present disclosure.

[0017] FIG. 6 illustrates tilt of patterned features at the edge of a substrate when tuning a split power capacitor providing power to an edge ring, in accordance with one embodiment of the present disclosure.DETAILED DESCRIPTION

[0018] Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the present disclosure.Accordingly, the aspects of the present disclosure described below are set forth without any loss of generality to, and without imposing limitations upon, the claims that follow this description.

[0019] Generally speaking, the various embodiments of the present disclosure describe plasma processing systems for controlling voltages at the edge of a substrate, which leads to increased plasma uniformity across an interface between a substrate and edge ring. In particular, in a capacitively coupled plasma processing system, power controlled using a variable capacitoris provided to an edge ring. In that manner, desired system capacitances at the interface between the ESC and the edge ring can be achieved in order to obtain voltage equalization at the interface between the substrate and edge ring. Voltage equalization at the interface between the substrate and edge ring increases plasma uniformity across the interface. In one embodiment, the power to the edge ring and power to the lower electrode may be split from power generated by a main power generator, wherein the variable capacitor splits the power at the output of the main power generator to deliver the power to the edge ring.

[0020] Advantages of the various embodiments, disclosing plasma processing systems, including a capacitively coupled plasma chamber delivering capacitively controlled power to an edge ring, include improved increased plasma uniformity across an interface between a substrate and edge ring. In particular, the capacitance at the edge ring adjacent to where power is delivered to the edge ring can be controlled to achieve desired system capacitances across the ESC, at the interface between an outer shoulder of the ESC and inner region of the edge ring, and at the outer region of the edge ring adjacent to a support or coupling ring. The capacitance at the edge ring can be directly controlled because a power pin assembly delivering capacitively controlled power is directly coupled with the edge ring, wherein the capacitance is controlled using a variable capacitor. As such, voltage equalization can be achieved at the interface between the substrate and edge ring resulting in increased plasma uniformity at the interface. Further, by controlling the plasma uniformity at the interface, plasma uniformity across the substrate is also increased.

[0021] With the above general understanding of the various embodiments, example details of the embodiments will now be described with reference to the various drawings. Similarly numbered elements and / or components in one or more figures are intended to generally have the same configuration and / or functionality. Further, figures may not be drawn to scale but are intended to illustrate and emphasize novel concepts. It will be apparent, that the present embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0022] Throughout the specification the terms substrate and wafer may be used interchangeably. Generally, plasma processing may be performed on a substrate and / or wafer to etch features on a surface, or to deposit layers on the surface of the substrate and / or wafer.

[0023] FIG. 1 A illustrates an embodiment of a capacitively coupled plasma (CCP) processing system 100 A configured for splitting main power to a lower electrode and an edge ring, wherein the power to the edge ring is capacitively controlled using a variable capacitor, in accordance with one embodiment of the present disclosure. Generally, exemplary CCPprocessing system 100A can be utilized for operations including etching and / or depositing films, such as for operations used to perform plasma processing of a substrate 120.

[0024] In particular, FIG. 1 A illustrates an exemplary embodiment of the plasma processing system 100A utilized for etching operations that is configured as a CCP processing system, and includes a CCP plasma process chamber 102 that is configured for generating plasma 130. The plasma process chamber 102 includes a substrate support or pedestal, such as an electrostatic chuck (ESC) 118. In embodiments, the ESC may have several circular rings with different material types to achieve a certain capacitive coupling between the ESC and / or a powered edge ring 126. A lower electrode 122 may be embedded within the ESC 118. One or more power sources may be coupled to components of the plasma processing system 100A. A substrate 120 may be placed on the pedestal for processing, wherein the substrate or wafer 120 is processed to make one or more semiconductor chips.

[0025] Facing the pedestal is an upper electrode 124 that is disposed over the lower electrode 122. The upper electrode 124 may be configured with an extension 123 that may be shaped as a ring. Between the upper electrode 124 and the lower electrode 122 is a gap forming a processing volume within which a plasma 130 may be formed. In one embodiment, the upper electrode 124 is grounded. In some embodiments, a dielectric (not shown) may be configured to separate the upper electrode 124 and the extension 123, wherein each of the upper electrode 124 and the extension 123 is grounded and / or floating.

[0026] In one embodiment, the upper electrode 124 is of a similar diameter as the substrate 120. In another embodiment, the upper electrode 124 has an outer diameter that is greater than the outer diameter of the substrate 120. Furthermore, the upper electrode 124 may be bigger than the ESC 118, in one embodiment.

[0027] The plasma process chamber 102 also includes the edge ring 126, which surrounds the ESC 118 and / or the lower electrode 122. As an example, the edge ring 126 is fabricated from a conductive material, such as silicon, boron doped single crystalline silicon, silicon carbide, an alloy of silicon, or a combination thereof. It should be noted that the edge ring 126 has an annular body, such as a circular body, or ring-shaped body, or dish-shaped body. As an illustration, the edge ring 126 has an inner radius and an outer radius, and the inner radius is greater than a radius of the ESC 118. The edge ring 126 performs many functions including positioning the substrate 120 on the ESC 118, confining plasma to an area above the substrate 120, protecting the ESC 118 from erosion by ions of the plasma, and shielding underlying components of the plasma chamber 102 from being damaged by ions of the plasma. Further, the edge ring is configured to improve performance at the edge of the substrate. For example, by varying an amount of the power coupled to the edge ring, plasma density of the plasma at theedge region, sheath uniformity of the plasma at the edge region; etch rate uniformity of the plasma at the edge region, and ion tilt at which the substrate is etched in the edge region may be controlled.

[0028] One or more power sources may be coupled to components of the plasma processing system 100A, in embodiments. For instance, power is delivered to at least one of the lower electrode 122 and / or edge ring 126, such as RF power, DC power, mixed RF and DC power, continuous, pulsed, etc. A substrate 120 may be placed on the pedestal for processing, wherein the substrate or wafer 120 is processed to make one or more semiconductor chips.

[0029] A single power source delivers power to the lower electrode 122 and the edge ring 126. In particular, a main power generator / source 112 is configured to provide a main power signal as an output. The output of the main power generator / source is electrically coupled to common node 171. That is, instead of coupling a power source to the edge ring 126, a variable capacitor 140 is coupled to the edge ring in order to control plasma uniformity at the interface between the substrate 120 and the edge ring 126. In one embodiment, the main power signal is a pulsed direct current (DC) power signal. For example, the waveform of the pulsed DC power signal is non-sinusoidal. For example, the main power generator 112 is configured to provide a pulsed DC signal that is pulsed at frequencies ranging between 100 to 1200 kilohertz (kHz).That is, the frequency of the pulsed DC power signal operates in the range of 100 to 1200 kilohertz (kHz). For example, the pulsed DC power signal may operate at 400 kHz. Also, the pulse width of the pulsed DC power signal may be in the nanosecond range. As such, in some embodiments, the main power generator 112 delivers nanosecond pulsed DC power. Further, the pulse shape of the pulsed DC power signal is a square wave. Pulsed DC power may provide certain advantages over RF power, such as using less power and not requiring an impedance match network.

[0030] In one embodiment, the main power generator 112 (e.g., output at common node 171) is electrically coupled to the lower electrode 122 to deliver a bias voltage, for example. Because the main power signal is split, the power delivered to the lower electrode 122 is a pulsed DC power signal. As previously described, the main power generator 112 is configured for supplying a pulsed DC power signal to the lower electrode to generate plasma. Pulsing may be performed at selected frequencies. For example, the main power generator 112 may provide nanosecond pulsed DC power.

[0031] In one embodiment, the main power generator / source 112 provides a pulsed DC power signal to the lower electrode 122 via a filter circuit 106, which is configured to reduce and / or remove any frequency (e.g., high, etc.) harmonics (e.g., through attenuation) and controlany oscillation of the signal all of which are caused by the pulsing. In one embodiment, the filter circuit 106 removes frequencies from an RF signal.

[0032] The main power generator 112 also is configured to provide power (i.e., in the form of a TES power signal) to the edge ring 126. In particular, a variable capacitor 140, electrically coupled to the edge ring 126 and the common node 171, splits the power of the main power signal. For example, the output of the main power generator 112 is presented at the common node 171, and power of the output power signal at common node 171 is split between the lower electrode 122 and the edge ring 126. In particular, the variable capacitor 140 splits the main power signal into a bias power signal delivered to the lower electrode 122, and a TES power signal delivered to the edge ring. As such, the capacitively controlled TES power signal is delivered directly to the edge ring. For example, a power pin coupled on one end to the variable capacitor 140, is also directly coupled to and / or conductively interfaced with the edge ring 126. Further, the variable capacitor 140 may be coupled to the edge ring 126 via a support ring 127, that is adjacent to the edge ring (e.g., under).

[0033] Because the TES power signal is split from the main power signal delivered (e.g., at the output) by the main power generator 112, pulsed DC power is delivered to the edge ring 126. For example, the TES power signal may deliver pulsed DC power to the edge ring 126 for purposes of generating plasma, in embodiments. Pulsing may be performed at selected frequencies. For example, the TES power signal may provide nanosecond pulsed DC power.

[0034] In addition, a high frequency (HF) radio frequency (RF) generator 170a provides a an RF power signal via an HF RF impedance match network 175a to provide RF power to the lower electrode 122 in order to generate plasma. The RF power signal may be continuous or pulsed, in embodiments. In particular, the HF RF power signal from generator 170a is combined with the split pulsed DC power signal (i.e., bias signal) delivered to the lower electrode 122 from the common node 171. For example, the HF RF generator 160 may be configured to produce high frequencies ranging from and including 10 to 130 megahertz (MHz), including operating at baseline frequencies between 54 to 63 megahertz (MHz). The match network 175a enables dynamic tuning of power provided to the lower electrode 122 by matching impedance between the load (e.g., plasma chamber and any connecting cabling) and a source (e.g., HF RF generator 170a and any connecting cabling).

[0035] Because a single power source (i.e., the main power generator 112) is utilized, the power delivered to the edge ring 126 is substantially aligned with the power delivered to the ESC 118. That is, the frequency and phase and pulse shape of the power signals to the ESC and the edge ring are substantially aligned. For example, when the main power generator 112 provides nanosecond pulsed DC power, the frequency and phase and pulse shape of the lowfrequency pulsed DC power signal delivered to the edge ring 126 is substantially aligned to the frequency and phase and pulse shape of the low frequency pulsed DC power signal delivered to the ESC 118 (e.g., via lower electrode 122.

[0036] The variable capacitor 140 is configured to provide capacitively controlled power to the edge ring 126. As will be described more fully below with respect to FIG. 2, a capacitance at the edge ring is controllable using variable capacitor 140. In that manner, system capacitances at the edge of a substrate can be controlled in order to achieve voltage equalization at the interface of the substrate and edge ring, such as when measuring surface voltage. For example, a dotted box “A” illustrates the interface of the substrate and edge ring and is described in more detail in FIG. 2.

[0037] In addition, plasma processing chamber 102 of FIG. 1A may optionally include a C- shroud 150 that extends from the upper electrode 124 and / or extension 123 to the ESC 118 including the lower electrode 122 to provide additional plasma containment. The C-shroud may have a plurality of apertures to allow gas and byproducts to flow out of the C-shroud. The C- shroud may be grounded. In other embodiments, the plasma processing chamber may be configured differently to include confinement rings (not shown) for confining plasma 130 during etching operations.

[0038] In another embodiment, gas source(s) 114 are connected to the plasma process chamber 102 and are configured to inject the desired process gas(es) into the plasma process chamber 102. As an example of plasma formation, after providing one or more bias signals (e.g., RF and / or DC and / or continuous and / or pulsed) to the ESC 118 and injecting process gas(es) into the plasma process chamber 102, plasma 130 is then formed between the upper electrode 124 (and optionally the extension 123) and the ESC 118. The plasma 130 can be used to etch the surface of the substrate 120. Although not shown, pumps are connected to the plasma chamber 102 to enable pressure control and removal of gaseous byproducts from the plasma chamber during operational plasma processing.

[0039] In some embodiments, the system may include a controller 116 that is used for controlling various components of the plasma processing system 100 A. In one example, the controller 116 can be connected to the plasma generators (e.g., main power generator 112 and HF RF generator 170a), to the gas source(s) 114 that are coupled to the plasma process chamber 102, TES filter 107, HF RF match 175a, and to other components. The controller 116 includes a processor, memory, software logic, hardware logic and input and output subsystems from communicating with, monitoring and controlling the plasma processing system 100 A. In some embodiments, the controller 116 includes one or more recipes 117 including multiple set points and various operating parameters (e.g., voltage, current, frequency, pressure, flow rate, powerlevels, temperature, timing parameters, process gases, mechanical movement of the substrate 120, etc.) for operating the plasma processing system 100A. For example, depending on the processing being performed, the controller 116 manages the delivery of process gases delivered from the gas source(s) 114 to achieve a designed processing condition, such as to etch features and / or deposit or form films over the substrate 120. The chosen gases are then distributed in a space volume defined between the top electrode 101 A and the substrate 120 resting over the ESC 118.

[0040] Further, the controller 116 may include a capacitance controller 160 that is configured to determine system capacitances at the edge of the substrate. The capacitance controller 160 is further configured to adjust the capacitance of the variable capacitor 140 in order to satisfy desired relationships between the system capacitance at the edge of the substrate. In that manner, voltage equalization at the interface of the substrate and edge ring can be achieved, such as when measuring surface voltage of the substrate and the edge ring at the interface. Voltage equalization at the interface promotes uniform plasma density (e.g., positive ions) over the edge of the substrate and the edge ring, such as exhibiting uniform ion tilt between the plasma sheaths over the substrate (e.g., at the edge) and over the edge ring, and especially at the interface between the substrate and the edge ring. In that manner, the ion tilt and correspondingly plasma uniformity and pattern tilt (i.e., of features) may be uniform globally across the entirety of the substrate (e.g., interior and at the edge of the substrate). In some embodiments, the capacitance controller 160 is separate and acts independently from the controller 116.

[0041] FIG. IB illustrates an embodiment of a capacitively coupled plasma processing system 100B configured for splitting main power to a lower electrode and an edge ring, wherein the power to the edge ring is capacitively controlled using a variable capacitor, in accordance with one embodiment of the present disclosure. Generally, exemplary CCP processing system 100B can be utilized for operations including etching and / or depositing films, such as for operations used to perform plasma processing of a substrate 120. The CCP processing system 100B is similar in operation as the CCP processing system 100A, and are similarly configured, wherein like numbered elements in the CCP processing systems have similar functionality as described in relation to FIG. 1 A, except that CCP processing system 100B provides high frequency RF power to the upper electrode 124, instead of the lower electrode 122, as previously described.

[0042] In particular, FIG. IB illustrates an exemplary embodiment of the plasma processing system 100B utilized for etching operations that is configured as a CCP processing system, and includes a CCP plasma process chamber 102 that is configured for generating plasma 130. Theplasma process chamber 102 includes a substrate support or pedestal, such as an electrostatic chuck (ESC) 118. In embodiments, the ESC may have several circular rings with different material types to achieve a certain capacitive coupling between the ESC and / or a powered edge ring 126. A lower electrode 122 may be embedded within the ESC 118. An upper electrode is disposed above the lower electrode, wherein the upper electrode may be configured with an extension. The plasma process chamber 102 also includes the edge ring 126, which surrounds the ESC 118 and / or the lower electrode 122.

[0043] One or more power sources may be coupled to components of the plasma processing system 100B, in embodiments. For instance, power is delivered to at least one of the upper electrode 124, extension 123, lower electrode 122, and / or edge ring 126, such as RF power, DC power, mixed RF and DC power, continuous, pulsed, etc. A substrate 120 may be placed on the pedestal for processing, wherein the substrate or wafer 120 is processed to make one or more semiconductor chips. In some embodiments, nanosecond pulsed DC power is delivered to the ESC 118 (e.g., via the lower electrode 122) and / or the edge ring 126, as previously described.

[0044] As previously introduced, a single power source delivers power to the lower electrode 122 and the edge ring 126. In particular, a main power generator / source 112 is configured to provide a main power signal as an output. The output of the main power generator / source is electrically coupled to common node 171. That is, instead of coupling a power source, a variable capacitor 140 is coupled to the edge ring in order to control plasma uniformity at the interface between the substrate 120 and the edge ring 126. In some embodiments, the main power generator 112 may supply a main power signal that is a pulsed DC power signal, as previously described. In some embodiments, the main power generator delivers nanosecond pulsed DC power. The main power generator 112 (e.g., output at common node 171) is electrically coupled to the lower electrode 122 to deliver a bias voltage, for example. Because the main power signal is split, the bias power delivered to the lower electrode 122 is a pulsed DC power signal. Also, the main power generator 112 also is configured to provide power (i.e., in the form of a TES power signal) to the edge ring 126. In particular, a variable capacitor 140, electrically coupled to the edge ring 126 and the common node 171, splits the power of the main power signal, as previously described. As such, pulsed DC power is delivered to the edge ring 126.

[0045] In addition, a high frequency (HF) radio frequency (RF) generator 170b provides a an RF power signal via an HF RF impedance match network 175b to provide RF power to the upper electrode 124 in order to generate plasma. The RF power signal may be continuous or pulsed, in embodiments. The match network 175b enables dynamic tuning of power provided tothe upper electrode 124 by matching impedance between the load (e.g., plasma chamber and any connecting cabling) and a source (e.g., HF RF generator 170b and any connecting cabling).

[0046] Because a single power source (i.e., the main power generator 112) is utilized, the power delivered to the edge ring 126 is substantially aligned with the power delivered to the ESC 118. That is, the frequency and phase and pulse shape of the power signals to the ESC and the edge ring are substantially aligned. For example, when the main power generator 112b provides nanosecond pulsed DC power, the frequency and phase and pulse shape of the low frequency pulsed DC power signal delivered to the edge ring 126 is substantially aligned to the frequency and phase and pulse shape of the low frequency pulsed DC power signal delivered to the ESC 118 (e.g., via lower electrode 122).

[0047] Additionally, variable capacitor 140b is configured to provide capacitively controlled power to the edge ring 126. As will be described more fully below with respect to FIG. 2, a capacitance at the edge ring is controllable using variable capacitor 140b. In that manner, system capacitances at the edge of a substrate can be controlled in order to achieve voltage equalization at the interface of the substrate and edge ring, such as when measuring surface voltage. For example, a dotted box “A” illustrates the interface of the substrate and edge ring and is described in more detail in FIG. 2.

[0048] FIG. 2 illustrates a control system 200 that is utilized to determine system capacitances at the interface between the outer edge of a substrate and an edge ring, and correspondingly to achieve desired relationships between the system capacitances in order to achieve voltage equalization at the interface and / or plasma uniformity globally across the substrate and at the interface, in accordance with one embodiment of the present disclosure. For example, control of the capacitance measured at the edge ring 126 may be implemented through control of the variable capacitor 140 in FIGS. 1A-1B. In particular, control system 200 illustrates capacitance measurement locations in the CCP plasma processing system 100 A or 100B of FIGS. 1 A-1B used for providing capacitively controlled power to an edge ring to achieve desired system capacitances at the edge of a substrate in order to achieve voltage equalization at the interface between the substrate and edge ring. For purposes of illustration, control system 200 may be adapted for implementation within the exemplary plasma processing systems 100A and / or 100B of FIGS. 1A-1B.

[0049] For purposes of brevity and clarity the control system 200 may be implemented in a plasma processing system that is described in FIG. 1 A and / or IB. For example, the CCP plasma processing system 100A and / or 100B includes, in part, an ESC 118 that is configured to support a substrate 120, an edge ring 126, and a support ring 127, as previously described. In addition, a pulsed DC power source (not shown) is coupled to the ESC 118 and the edge ring 126. In oneembodiment, the pulsed DC power source provides nanosecond pulsed DC power. Also, a high frequency RF power generator may provide RF power to either the lower electrode 122 or the upper electrode 124, in various configurations.

[0050] The ESC 118 includes a baseplate that is separated into a main portion 118a, configured within a central region of the ESC, and a shoulder portion 118b, configured as an outer portion of the ESC. The shoulder portion 118b may include a step (i.e., a step down from an upper surface of the main portion 118a of the ESC) that is configured to support an inner region of the edge ring 126. Further, a support ring 127 is adjacent to and disposed under the edge ring 126. For example, the support ring may be configured to support the edge ring in a vertical direction. The support ring 127 may include a through-via 360 permitting a power pin assembly 301 to travel through the support ring in order to electrically couple with the edge ring 126.

[0051] The power pin assembly 301 is electrically coupled to a variable capacitor 140 at one end, and to the edge ring 126 at the opposing end, wherein the power pin assembly is configured to provide a TES power signal to the edge ring. In particular, the power pin assembly includes a vertical shaft 210 and an electrode 215 that is configured for delivering power to the edge ring. For example, the hole 361 (e.g., hole of a certain depth) in the edge ring 126 allows entry of the power pin assembly 210, such that an electrode 215 of the power pin assembly 301 electrically contacts the edge ring 126. Further, the power pin assembly may include a conductive coupling interface 217 that is coupled to the electrode 215 at the top of the vertical shaft 210, wherein the conductive coupling interface (e.g., banana plug, etc.) is electrically coupled to the edge ring 126. For instance, the conductive coupling interface is inserted within a socket 320 that is disposed within the hole 361 of the edge ring 126. Because the socket is conductive, the conductive coupling interface 217 is electrically coupled to the edge ring 126 so that power from the electrode 215 is directly delivered to the edge ring via the conductive coupling interface and socket (i.e., rather than through a coupling ring situated adjacent to the edge ring). In another embodiment, the power pin assembly comprises an electrode, which directly contacts the edge ring (e.g., interior of the edge ring). FIGS. 3A-3B provide additional description for providing TES power signal to the edge ring using the power pin assembly 301.

[0052] In particular, control system 200 implements a control scheme for controlling relative values of system capacitances at an interface between the outer edge of a substrate and an edge ring 126. Proper balancing of capacitance values at the interface leads to voltage equalization at the interface, such as voltages seen at the top of the substrate 120 and the top of the edge ring 126. Because the voltages are equalized at the interface (e.g., top of the substrate and top of the edge ring), plasma density at the edge of the substrate and over the edge ring are uniform. Forexample, there may be a plasma sheath formed over the ESC and separate plasma sheath formed over the edge ring, wherein because of the plasma uniformity across the interface, the plasma sheaths may be coplanar at the interface.

[0053] To achieve proper balancing of the capacitances, capacitance values are measured at one or more in-situ locations within the CCP plasma processing system. In particular, a first measuring system 250 is configured to measure a first capacitance (referred to as “C_esc”) at a top surface 118a of the ESC 118, and more particularly at an interface located between the top surface of the ESC 118 and a substrate 120 supported by the ESC. For example, the first measuring system measures the capacitive coupling at the interface. A second measuring system 255 is configured to measure a second capacitance (referred to as “C edge”) at a surface of the baseplate shoulder 118b, and more particularly at an interface located between the surface of the baseplate shoulder of the ESC 118 and a bottom surface of the edge ring 126. The interface is located adjacent to an outer diameter of the ESC 118 and an inner diameter of the edge ring 126. For example, the second measuring system measures the capacitive coupling at the interface. A third capacitance (referred to as “C_tes”) is presented to the edge ring 126 by the variable capacitor 140. That is, the capacitance value of C tes is the capacitance of the variable capacitor 140, and can be controlled via controller 116 and / or 160 for purposes of achieving voltage equalization at the interface between the substrate 120 and edge ring 126. In one implementation, the capacitance of the variable capacitor 140 is measured to determine C tes.

[0054] The measurements of one or more of the measurement sensors 250 and 255, as well as the value of C tes, may be delivered to controller 116 and / or capacitance controller 160 for purposes of achieving voltage equalization at the interface between the substrate 120 and edge ring 126. Without being bound by theory or mechanism of action, and for purposes of clarity, balancing the capacitances seen at the substrate 120 and the edge ring 126 achieves voltage equalization at the interface between the substrate and edge ring. That is, voltages above the substrate and voltages above the edge ring at the interface between the outer diameter of the substrate and the inner diameter of the edge ring are approximately equal. Voltage equalization at the interface of the substrate and edge ring promotes uniform plasma density globally across the entirety of the substrate, and especially at the interface between the substrate and the edge ring. In one embodiment, voltage equalization is achieved when the capacitance C tes is larger than the difference between the capacitance C esc and C edge ([C esc - C edge] < C tes). As such, desired system capacitances can be achieved by measuring the capacitance values C esc and C edge using the previously described measurement systems, and by appropriately setting the value of C tes to satisfy the above relationship between the system capacitances, all of which can be controlled using the controller 116 and / or capacitive controller 160. Forexample, the controller 116 and / or capacitive controller 160 are configured to adjust the variable capacitor (i.e., capacitance value C tes) such that C tes is at least greater than a difference between C esc and C edge. In one example, a value of C esc may range between 3 to 8 nanofarads (nF), and C edge may range between 1 to 4 nanofarads (nF), so that the value of C tes can be determined to satisfy the above relationship between system capacitances (e.g., larger than 500 picofarads, as an example). Increased accuracy and better control of system capacitances may be achieved by further measuring the value of C tes. In one embodiment, when the above relationship between the system capacitances is achieved, a maximum operating voltage range of the pulsed DC TES power signal may be achieved.

[0055] FIG. 3 A illustrates direct coupling of capacitively controlled power to an edge ring to achieve desired system capacitances at an interface between a substrate and edge ring, in accordance with one embodiment of the present disclosure. For example, the direct coupling of power to the edge ring may be implemented by the control system 200 shown in FIG. 2 and may be adapted for implementation within the exemplary plasma processing systems 100A and / or 100B of FIGS. 1A-1B.

[0056] As shown, support ring 127 is adjacent to and disposed under the edge ring 126. A through-via 360 in the support ring is configured to allow entry of the power pin assembly 301. In one embodiment, power pin assembly includes a vertical shaft 210 having a vertical travel space 370 for passage and / or introduction of electrode 215, wherein the electrode is located within the vertical travel space. The shaft includes an outer surface 211, wherein the outer surface may be conductive or non-conductive. The vertical travel space may be filled with some material to support and / or isolate the electrode 215, wherein the material may be conductive or non-conductive. Power pin assembly includes an optional conductive coupling interface 217 configured to electrically couple the power pin assembly to the edge ring, such that power is delivered to an interior of the edge ring. More specifically, the electrode 215 is electrically coupled to the conductive coupling interface 217. Further, the conductive coupling interface 217 is inserted into a socket 320, wherein the socket 320 is disposed within a hole 323 of the edge ring 126. The socket 320 includes a hollow receiver configured to receive the power pin assembly, and / or the conductive coupling interface 217. Because the socket 320 is conductive and contacts the edge ring at a side surface SS of the hole, the conductive coupling interface is also electrically coupled to the edge ring 126, and more specifically to the interior of the edge ring. In that manner, power is delivered directly to the edge ring, and more specifically to the interior of the edge ring.

[0057] O-ring 310b is confined within a cavity 306 that is formed in the bottom surface of the support ring. In particular, cavity 306 is located at an interface between the cavity and theouter surface 211 of the power pin assembly 301 and / or other components (not shown). As such, the O-ring 310b is configured to seal an inner cavity (not shown) of the plasma chamber at the interface between the cavity 306 and, for example, the outer surface of the power pin assembly 301. That is, the inner cavity is sealed and isolated from the exterior of the plasma processing chamber using the O-ring 310b.

[0058] In addition, O-ring 310a is confined within a cavity 305 formed in the bottom surface 330 of the edge ring 126. In particular, cavity 305 is located at an interface between the cavity and the outer surface 326 of the socket 320. The interface is defined as being between the bottom surface 330 of the edge ring 126 and an upper surface 340 of the support ring 127 and the outer surface 326 of the socket 320. As such, O-ring 310a is configured to seal the inner cavity (not shown) of the plasma chamber at the interface between the cavity 305 and the outer surface 326 of the socket 320. That is, the inner cavity is sealed and isolated from the exterior of the plasma processing chamber using the O-ring 310a.

[0059] FIG. 3B illustrates direct coupling of capacitively controlled power to an edge ring 126 including an interfacing between a threaded hole 323 of an edge ring 126 and threaded socket 320, and the interfacing and / or insertion of the conducive coupling interface 217a into the socket 320, in accordance with one embodiment of the disclosure. For example, the direct coupling of power to the edge ring may be implemented by the control system 200 shown in FIG. 2 and may be adapted for implementation within the exemplary plasma processing systems 100A and / or 100B of FIGS. 1A-1B.

[0060] As shown, edge ring 126 may include a socket 320 disposed within a hole 323 formed in the bottom surface 330 in the edge ring. The socket 320 extends beyond the bottom surface 330 of the edge ring 126, in one embodiment. An example of a hole within an edge ring is a screw hole. The hole 323 may be formed by drilling into the bottom surface 330 of the edge ring 126. The hole 323 is of a certain depth such that a top surface of the hole is within the interior of the edge ring. The hole 323 has a side surface SS that may be threaded, such that SS may include spiral threads 328 for receiving a matching threaded component. For example, socket 320 is threaded, and may include spiral threads 329 that match with the threads on the hole 323. As such, socket 320 may be screwed into hole 323. That is, the threaded conductive coupling interface 217a is configured to interface with the threaded side surface SS of the hole, such that the socket 320 is electrically coupled to the power pin assembly 301 so that power may be delivered to the edge ring 126.

[0061] The socket 320 may include a hollow receiver 321 that is configured to receive the power pin assembly 301 and / or the conductive coupling interface 217a so that power may bedelivered to the edge ring. In particular, the socket includes an opening 325, wherein the opening is configured to provide access to the hollow receiver 321 of the socket 320.

[0062] As shown, the hollow receiver 321 of the socket 320 is configured to receive the power pin assembly 301, wherein the socket is configured to receive the power pin assembly through the opening 325. In one implementation, the socket interfaces directly with the power pin assembly for delivery of power to the edge ring. For example, direct contact is made between the power pin assembly and an inner surface 324 of the socket 320, such that the inner surface 324 and the power pin assembly are designed to interface with each other so that power may be delivered to the edge ring. That is, the inner surface 321 of the hollow receiver 323 is fitted to and / or configured to receive the power pin assembly 301, such that the inner surface of the hollow receiver is electrically coupled to the power pin assembly 301 so that power may be delivered to the edge ring. For example, the power pin assembly 301 may include a conductive coupling interface 217a connected to the shaft 210, wherein the conductive coupling interface is configured as a banana plug. The banana plug may include leaves that flexibly bulge outward, such that when the banana plug is inserted into the hollow receiver 323 the leaves provide a secure fit and good electrical connectivity between the conductive coupling interface and the socket 320.

[0063] FIG. 4 illustrates an opportunity for tuning voltages at a substrate and / or edge ring to achieve voltage equalization at an interface between the substrate and edge ring, in accordance with one embodiment of the present disclosure. For example, capacitively controlled power to the edge ring provides for described system capacitances at the interface between the outer edge of a substrate and an edge ring that lead to voltage equalization at the interface. Voltage equalization and / or control of system capacitances may be implemented in plasma processing systems lOOA and 100B of FIGS. 1A-1B.

[0064] As shown, graph 400 compares voltages at one or more locations of the plasma processing system to capacitance. For example, the x-axis 401 provides split capacitance values of capacitor 140 that correspond with C tes, and the y-axis 402 provides voltages, measured at a substrate and at an edge ring, for various capacitance values. For example, legend 450 shows the voltage measured (e.g., by a high voltage probe or measurement sensor) at a substrate or wafer (e.g., surface) indicated by dotted line 410 including filled circles (i.e., darkened circles). Also, legend 450 shows the voltage measured (e.g., by a high voltage probe or measurement sensor) at an edge ring (e.g., surface) indicated by dotted line 420 including clear boxes.

[0065] As shown, the voltage on the substrate / wafer is relatively constant for one or more split capacitance values (i.e., C tes). More importantly, the voltage on the edge ring varies with different split capacitance values (i.e., C tes). As such, the voltage on the edge ring is tunableby tuning the capacitor 140 (i.e., C tes). In particular, the capacitance value of capacitor 140 is tuned until voltage equalization at the interface between the substrate and edge ring is achieved, such as when both the voltages converge at the far right.

[0066] FIGS. 5a-5b illustrate measured voltage waveforms on a substrate and edge ring that are tunable to achieve matching waveforms, in accordance with one embodiment of the present disclosure. In both FIGS. 5a-5b, voltage waveforms are provided as measured over a period of time, and show pulses for corresponding pulse cycles. The voltage waveforms correspond to voltages measured over a substrate / wafer (as shown by a solid line), and voltages measured over the edge ring (as shown by a dotted line). In particular, FIG. 5a shows voltage waveforms for a split capacitance value of 109 picofarads (pF) for the capacitor 140 (i.e., C tes), and FIG. 5b shows voltage waveforms for a split capacitance value of 2118 picofarads (pF) for the capacitor 140.

[0067] As shown, between FIGS. 5a and 5b, the voltage waveform measured over the substrate / wafer is relatively stable. However, the voltage waveforms measured over the edge ring between graph 500a of FIGS. 5a and graph 500b of FIG. 5b show a variation, which indicates that the voltage waveform is tunable by selecting the desired split capacitance value of the capacitor 140. In particular, in graph 500a, when the split capacitance value is 109 pF, there is a large delta in voltage between the two voltage waveforms at any point in time. On the other hand, in graph 500b, when the split capacitance value is 2118 pF, the two voltage waveforms begin to merge. That is, the voltage waveforms over the substrate / wafer and over the edge ring are similarly shaped, such that they have similar maximum and minimum voltage values. As such, by varying the split capacitance value in capacitor 140 (i.e., C tes), capacitively controlled power that is tuned can be delivered to the edge ring to achieve voltage equalization of the measured voltages and / or voltage waveforms. This voltage equalization is achieved by ensuring a desired relationship, previously described, between system capacitances at the edge of the substrate. For example, voltage equalization may be implemented through control of the variable capacitor 140 in FIGS. 1 A-1B. As previously introduced, voltage equalization at the interface promotes uniform plasma density (e.g., positive ions) over the edge of the substrate and the edge ring. As such, the plasma sheath is uniform over the substrate and at the edge of the substrate, and even over the edge ring. In that manner, plasma uniformity is uniform globally across the entirety of the substrate.

[0068] FIG. 6 illustrates tilt of patterned features at the edge of a substrate when tuning a split power capacitor providing power to an edge ring, in accordance with one embodiment of the present disclosure. In particular, graph 600 includes y-axis 602 providing angular tilt of patterned features measured from a vertical line that is perpendicular to the top surface of thesubstrate. Tilt can be measured for various regions of the substrate, as indicated by the x-axis 601 which marks the radius of the substrate, and focuses on a region extending beyond 80 millimeters (mm) to the edge.

[0069] As shown, patterned features were created on three different substrates, each patterned with the same process but with variation in the split capacitance value of the split power capacitor (e.g., capacitor 140 or C-tes). The clear boxes indicate tilt of patterned features at various radii over the substrate, wherein the process included a split capacitance value of 787 picofarads (pF), corresponding to 3.9 kV measured at the edge ring. The clear triangles indicate tilt of patterned features at various radii over the substrate, wherein the process included a split capacitance value of 448 picofarads (pF), corresponding to 3.4 kV measured at the edge ring. The clear circles indicate tilt of patterned features at various radii over the substrate, wherein the process included a split capacitance value of 109 picofarads (pF), corresponding to 3.2 kV measured at the edge ring.

[0070] In particular, the clear boxes, corresponding with a split capacitance value of 787 picofarads (pF), indicate that the patterned features at the edge of the substrate are tilted outwards (e.g., away from the center of the substrate). Also, the clear circles, corresponding with a split capacitance value of 109 picofarads (pF), indicate that the patterned features at the edge of the substrate are tilted inwards (e.g., towards the center of the substrate). However, the clear triangles, corresponding with a split capacitance value of 448 picofarads (pF), indicate that the patterned features at the edge of the substrate are minimally titled away from vertical. A desired tilt at the edge of the substrate can be achieved by selecting the appropriate split capacitance value of the split power capacitor (e.g., capacitor 140 or C-tes). As such, by selecting the appropriate capacitance value of the split power capacitor, voltage equalization of measured voltages over the substrate and the edge ring may be achieved. As previously introduced, voltage equalization at the interface promotes uniform plasma density (e.g., positive ions) over the edge of the substrate and the edge ring. As such, the plasma sheath is uniform over the substrate and at the edge of the substrate, and even over the edge ring. In that manner, plasma uniformity is uniform globally across the entirety of the substrate, leading to minimal tilt of patterned features, especially at the edge of the substrate.

[0071] In embodiments, a substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and / or target, which may be implemented by control system or controller 160 of FIGS. 1 A-1B. In some implementations, a controller is part of a system, which may be part of the abovedescribed examples. Such systems can comprise semiconductor processing equipment,including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a substrate pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, and process implemented for operating a plasma chamber. Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor substrate or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0072] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” of all or a part of a fab host computer system, which can allow for remote access of the substrate processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to a system over a network, which may include a local network or the Internet.

[0073] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, a plasma enhanced chemical vapor deposition (PECVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0074] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selectedembodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

[0075] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within their scope and equivalents of the claims.

Claims

CLAIMS1. A system, comprising: a plasma chamber configured for generating plasma, wherein the plasma chamber includes a lower electrode located within an electrostatic chuck (ESC); an upper electrode disposed above the lower electrode; an edge ring surrounding the lower electrode; a main power generator electrically coupled to the lower electrode and the edge ring via a common node, wherein the main power generator is configured to supply a pulsed direct current (DC) power signal to the common node; a variable capacitor electrically coupled between the common node and the edge ring, wherein the variable capacitor splits the pulsed DC power signal into a bias power signal delivered to the lower electrode and a tunable edge sheath (TES) power signal delivered to the edge ring; and a high frequency radio frequency (RF) power source electrically coupled to the upper electrode and configured to supply a high frequency RF power signal to the upper electrode.

2. The system of claim 1, further comprising: a power pin assembly electrically coupled to the variable capacitor and to the edge ring, wherein the power pin assembly is configured to supply the TES power signal to the edge ring.

3. The system of claim 2, further comprising: a support ring adjacent to and disposed under the edge ring, wherein the power pin assembly travels through a via in the support ring to electrically couple with the edge ring.

4. The system of claim 3, further comprising: an O-ring confined within a cavity formed in the bottom surface of the support ring, wherein the cavity is located at an interface between the cavity and an outer surface of the power pin assembly, wherein the O-ring is configured to seal an inner cavity of the plasma chamber at the interface.

5. The system of claim 3, wherein the power pin assembly delivers the TES power signal to an interior of the edge ring.

6. The system of claim 3, further comprising: an O-ring confined within a cavity formed in the bottom surface of the edge ring,wherein the cavity is located at an interface between the cavity and an outer surface of the power pin assembly, wherein the O-ring is configured to seal an inner cavity of the plasma chamber at the interface.

7. The system of claim 6, wherein the interface is further defined as being between the bottom surface of the edge ring and an upper surface of the support ring and the outer surface of a socket configured to receive the power pin assembly.

8. The system of claim 3, wherein the support ring is configured to support the edge ring in a vertical direction.

9. The system of claim 2, further comprising: a socket including a hollow receiver and disposed within a hole in the edge ring, wherein the socket extends beyond a bottom surface of the edge ring, wherein the socket includes an opening located at a bottom end, wherein the opening is configured to provide access to the hollow receiver, wherein the socket is configured to receive the power pin assembly through the opening.

10. The system of claim 9, wherein an inner surface of the hole is threaded and configured to receive the socket that is threaded on an outer surface, wherein the inner surface of the hollow receiver is electrically coupled to the power pin assembly.

11. The system of claim 9, wherein the inner surface of the hollow receiver is fitted to receive the power pin assembly, wherein an inner surface of the hollow receiver is electrically coupled to the power pin assembly.

12. The system of claim 2, wherein the power pin assembly includes: a vertical shaft including an outer surface and including a vertical travel space; an electrode located within the vertical travel space of the vertical shaft; and a conductive coupling interface at a top of the vertical shaft and configured to contact the electrode, wherein the conductive coupling interface is electrically coupled to the edge ring through the hollow receiver.

13. The system of claim 12, wherein the conductive coupling interface includes a banana plug.

14. The system of claim 1, wherein the pulsed DC power signal operates in the frequency range of 100 to 1200 kilohertz (kHz).

15. The system of claim 1, wherein the high frequency RF power signal operates in the frequency range of 10 to 130 megahertz (MHz)16. The system of claim 1, a first measuring system configured to measure a first capacitance between the ESC and a substrate located above the ESC; a second measuring system configured to measure a second capacitance in an interface between the ESC and the edge ring, wherein the interface is located adjacent to an outer diameter of the ESC and an inner diameter of the edge ring; and a controller configured to adjust the variable capacitor such that a capacitance of the variable capacitor is at least greater than a difference between the first capacitance and the second capacitance.

17. The system of claim 1, further comprising: a match circuit electrically coupled between the high frequency RF power source and the lower electrode.

18. The system of claim 1, further comprising: a TES filter electrically coupled between the common node and the variable capacitor; and an RF filter electrically coupled between the common node and the lower electrode.

19. A system, comprising: a plasma chamber configured for generating plasma, wherein the plasma chamber includes a lower electrode located within an electrostatic chuck (ESC); an upper electrode disposed above the lower electrode; an edge ring surrounding the lower electrode; a main power generator electrically coupled to the lower electrode and the edge ring via a common node, wherein the main power generator is configured to supply a pulsed direct current (DC) power signal to the common node; a variable capacitor electrically coupled between the common node and the edge ring, wherein the variable capacitor splits the pulsed DC power signal into a bias power signal delivered to the lower electrode and a tunable edge sheath (TES) power signal delivered to the edge ring; and a high frequency power source electrically coupled to the lower electrode and configured to supply a high frequency radio frequency (RF) power signal to the lower electrode.

20. The system of claim 19, further comprising: a power pin assembly electrically coupled to the variable capacitor and to the edge ring, wherein the power pin assembly is configured to supply the TES power signal to the edge ring.

21. The system of claim 20, further comprising: a support ring adjacent to and disposed under the edge ring, wherein the support ring is configured to support the edge ring in a vertical direction, wherein the power pin assembly travels through a via in the support ring to electrically couple with the edge ring.

22. The system of claim 21, wherein the power pin assembly delivers the TES power signal to an interior of the edge ring.

23. The system of claim 20, further comprising: a socket including a hollow receiver and disposed within a hole in the edge ring, wherein the socket extends beyond a bottom surface of the edge ring; wherein the socket includes an opening located at a bottom end, wherein the opening is configured to provide access to the hollow receiver, wherein the socket is configured to receive the power pin assembly through the opening.

24. The system of claim 20, wherein an inner surface of the hole is threaded and configured to receive the socket that is threaded on an outer surface, wherein the inner surface of the hollow receiver is electrically coupled to the power pin assembly.

25. The system of claim 20, wherein the inner surface of the hollow receiver is fitted to receive the power pin assembly, wherein an inner surface of the hollow receiver is electrically coupled to the power pin assembly.

26. The system of claim 20, wherein the power pin assembly includes: a vertical shaft including an outer surface and including a vertical travel space; an electrode located within the vertical travel space of the vertical shaft; and a conductive coupling interface at a top of the vertical shaft and configured to contact the electrode,wherein the conductive coupling interface is electrically coupled to the edge ring through the hollow receiver.

27. The system of claim 26, wherein the conductive coupling interface includes a banana plug.

28. The system of claim 19, wherein the pulsed DC power signal operates in the frequency range of 100 to 1200 kilohertz (kHz).

29. The system of claim 19, wherein the high frequency RF power signal operates in the frequency range of 10 to 130 megahertz (MHz).

30. The system of claim 19, a first measuring system configured to measure a first capacitance between the ESC and a substrate located above the ESC; a second measuring system configured to measure a second capacitance in an interface between the ESC and the edge ring, wherein the interface is located adjacent to an outer diameter of the ESC and an inner diameter of the edge ring; and a controller configured to adjust the variable capacitor such that a capacitance of the variable capacitor is at least greater than a difference between the first capacitance and the second capacitance.

31. The system of claim 19, further comprising: a match circuit electrically coupled between the high frequency RF power source and the lower electrode.

32. The system of claim 19, further comprising: a TES filter electrically coupled between the common node and the variable capacitor; and an RF filter electrically coupled between the common node and the lower electrode.

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