Control method, control apparatus, memory circuit, computing-in-memory system and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a control method, a control apparatus, a memory circuit, a computing-in-memory system and an electronic device. The memory circuit comprises a computing-in-memory cell, wherein the computing-in-memory cell comprises m memory cell blocks. The control method comprises: controlling the writing of valid data into a computing-in-memory cell, wherein the valid data is stored in m1 memory cell blocks among m memory cell blocks, m2 memory cell blocks among the m memory cell blocks are used for storing null data or invalid data, m=m1+m2, and m2<m1; controlling a first refresh of the valid data of the computing-in-memory cell, wherein at least one of the m2 memory cell blocks is used for storing first valid data, the first valid data is stored in at least one of the m1 memory cell blocks prior to the first refresh, and at least one of the m1 memory cell blocks is used for storing null data or invalid data. The solution can improve the performance of a computing-in-memory architecture.

Description

Control methods, control devices, storage circuits, memory computing systems, and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411923892.2, filed on December 24, 2024, entitled "Control Method, Control Device, In-Memory System and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a control method, control device, storage circuit, memory computing system, and electronic device. Background Technology

[0003] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0004] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their performance still needs improvement. Summary of the Invention

[0005] This application provides a control method, control device, storage circuit, in-memory computing system, and electronic device, which can improve the performance of in-memory computing architecture.

[0006] A first aspect provides a control method for controlling a storage circuit, the storage circuit including a storage and computing unit, the storage and computing unit including m storage cell blocks, the control method including: controlling the writing of valid data to the storage and computing unit, wherein the valid data is stored in m1 storage cell blocks among the m storage cell blocks, and m2 storage cell blocks among the m storage cell blocks are used to store empty data or invalid data, m = m1 + m2, m2 < m1, and m, m1 and m2 are positive integers; controlling a first refresh of the valid data in the storage and computing unit, wherein at least one storage cell block among the m2 storage cell blocks is used to store first valid data, the valid data including the first valid data, and the first valid data is stored in at least one storage cell block among the m1 storage cell blocks before the first refresh, and at least one storage cell block among the m1 storage cell blocks is used to store empty data or invalid data.

[0007] According to the technical solution of this application embodiment, the storage circuit's in-memory processing unit includes a storage unit block for storing empty or invalid data. This storage unit block can be called a redundant storage unit block or a backup storage unit block, and can be used to store refreshed data. The redundant storage unit block can support the continued storage of refreshed data in the current in-memory processing unit, which helps reduce the waiting latency caused by refreshing in in-memory processing applications, thereby improving the storage accuracy of the storage circuit while also considering the performance improvement of in-memory processing applications. Furthermore, the structure of this storage circuit simplifies the refresh control logic of the storage circuit.

[0008] In some implementations of the first aspect, the first refresh of the valid data of the memory computing unit includes: controlling the first refresh of the valid data of the memory computing unit according to a set rule. For example, the set rule may indicate the order in which storage cell blocks in the memory computing unit are used as redundant storage cell blocks; or the set rule may indicate the target storage cell block of the storage cell blocks in the memory computing unit, etc.; thereby, when the refresh is controlled according to the set rule, the wear degree among the storage cell blocks of the memory computing unit is balanced, which can reduce the difference in the lifespan between the storage cell blocks in the memory computing unit, reduce the probability of bad blocks, and extend the overall lifespan of the memory computing unit.

[0009] In some implementations of the first aspect, a set rule is used to indicate the set order in which m storage unit blocks are used to store empty or invalid data. The storage unit block currently storing empty or invalid data includes a first storage unit block, and the storage unit block to be stored with empty or invalid data includes a second storage unit block. The first refresh of the valid data of the storage unit is controlled according to the set rule, which includes: controlling the writing of data in the second storage unit block to the first storage unit block according to the set order.

[0010] In this implementation, the set order can be used to characterize the refresh order of storage unit blocks. Thus, according to the set order, the data of the first storage unit block can be refreshed in one refresh of the storage unit, reducing the refresh time and minimizing business or work interruptions caused by refreshing the entire storage unit.

[0011] In some implementations of the first aspect, a set rule is used to indicate the target storage cell block for each of the m storage cell blocks. The first refresh of the valid data in the in-memory computing unit, according to the set rule, includes: controlling the data stored in the storage cell block currently storing some valid data to be written to the target storage cell block indicated by the set rule; and controlling the state of the target storage cell block of the storage cell block currently storing empty or invalid data to be empty or invalid. Thus, according to the set rule, the valid data of the in-memory computing unit can be refreshed in one refresh of the in-memory computing unit, reducing the overall number of refreshes and improving the accuracy and consistency of the valid data throughout the entire in-memory computing unit.

[0012] Through the technical solutions described in the above embodiments, during a single refresh of the in-memory computing unit, some or all of the valid data in the in-memory computing unit can be refreshed according to set rules. This not only facilitates wear leveling among multiple storage unit blocks within the in-memory computing unit, but also simplifies refresh control, improves refresh fairness, prevents some storage unit blocks from missing refresh resources, and provides predictability for the refreshed in-memory computing units, thus facilitating the control of computing operations.

[0013] In some implementations of the first aspect, the control method further includes: when a bad block appears in the storage unit, controlling the writing of the bad block's data to a non-bad block in the storage unit. The non-bad block includes a storage unit block currently storing empty or invalid data, or a target storage unit block of a bad block indicated by a set rule. The storage unit includes m³ bad blocks, where m³ ≤ m², and m³ is a positive integer. Thus, the number of storage unit blocks in the storage unit is m² more than the number of valid storage unit blocks. Therefore, when the number of bad blocks in a storage unit is no greater than m², the storage unit can still store complete and valid data, thereby preventing bad blocks from affecting the storage function and further extending the lifespan of the storage circuit.

[0014] In some implementations of the first aspect, the storage circuit further includes an external storage cell block, which is not part of the storage and computing unit. When m3 = m2, the control method further includes: controlling the second refresh of the valid data of the storage and computing unit, wherein the external storage cell block and the non-bad block of the storage and computing unit are used to store the valid data.

[0015] This technical solution utilizes external storage blocks to refresh the data within the in-memory computing unit, ensuring that valid data circulates within the unit. This reduces latency caused by refreshes in in-memory computing applications, improving storage accuracy while simultaneously enhancing performance. Furthermore, the structure of this storage circuit simplifies refresh control logic.

[0016] In some implementations of the first aspect, when m3 < m2, the control method further includes: controlling the third refresh of the valid data of the storage unit in m-m3 non-bad blocks according to a set rule.

[0017] In some implementations of the first aspect, the control method further includes: in response to a first refresh, updating the mapping relationship, which indicates the correspondence between the physical addresses and logical addresses of the m1 storage cell blocks currently storing valid data.

[0018] This implementation method enables the recording and maintenance of logical and physical addresses related to valid data, improving the accuracy and reliability of data operations, thereby further enhancing the storage and computing performance of the storage circuit.

[0019] In some implementations of the first aspect, the mapping relationship is also used to indicate the correspondence between the physical addresses and logical addresses of the m2 storage cell blocks currently storing empty or invalid data.

[0020] In this implementation, the mapping relationship can record the address information of each storage unit block in the computing process more comprehensively. Based on this mapping relationship, the control method of the control device on the storage circuit can be simplified, and the accuracy and reliability of data operation in the control storage circuit can be further improved.

[0021] In some implementations of the first aspect, m1 = 8 and m2 = 1. In this implementation, the in-memory computing unit includes a single redundant storage cell block, resulting in less waste of storage resources in the storage circuit, less occupation of area and hardware resources, and minimal impact on the original functionality of the storage circuit. Furthermore, the single redundant storage cell block can be used to refresh the valid data of the in-memory computing unit within the in-memory computing unit, which is beneficial for the in-memory computing application of the in-memory computing unit and improves the in-memory computing performance of the storage circuit.

[0022] In some implementations of the first aspect, the m storage unit blocks in the in-memory unit have the same capacity to simplify the control logic of the in-memory unit.

[0023] In a second aspect, a storage circuit is provided, comprising: a storage and computing unit, the storage and computing unit comprising m storage unit blocks, wherein at a first time, m1 of the m storage unit blocks are used to store valid data, and m2 of the m storage unit blocks are used to store empty data or invalid data, m = m1 + m2, m2 < m1, and m, m1 and m2 are positive integers.

[0024] In some implementations of the second aspect, at a second time after the first refresh of the valid data of the storage unit, at least one of the m2 storage unit blocks is used to store the first valid data, the valid data including the first valid data, and the first valid data is stored in at least one of the m1 storage unit blocks at the first time, and at the second time, at least one of the m1 storage unit blocks is used to store empty data or invalid data.

[0025] In some implementations of the second aspect, the refresh of valid data in the storage unit is based on a set rule.

[0026] In some implementations of the second aspect, a setting rule is used to indicate the setting order of m storage cell blocks for storing empty or invalid data, or the setting rule is used to indicate the target storage cell block for each of the m storage cell blocks.

[0027] In some implementations of the second aspect, the storage circuit also includes an external storage cell block, which is not part of the storage unit. In the event of a bad block in the storage unit, during the second refresh process of the valid data in the storage unit, the external storage cell block and the non-bad block of the storage unit are used to store the valid data.

[0028] In some implementations of the second aspect, m1 = 8 and m2 = 1.

[0029] In some implementations of the second aspect, the m storage cell blocks have the same capacity.

[0030] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0031] Thirdly, a control device is provided, comprising: an interface circuit for communicating with a storage circuit; and at least one processing circuit for executing any of the control methods of the first aspect.

[0032] Fourthly, a storage computing system is provided, comprising: a storage circuit according to any of the second aspects; and a control device for executing a control method according to any of the first aspects to control the storage circuit.

[0033] Fifthly, an electronic device is provided, including the storage and computing system of the fourth aspect. Attached Figure Description

[0034] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0035] Figure 2 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0036] Figure 3 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0037] Figure 4 shows a schematic diagram of a three-dimensional memory array in a memory circuit according to an exemplary embodiment of this application.

[0038] Figure 5 shows a schematic diagram of a control method according to an exemplary embodiment of this application.

[0039] Figure 6 shows a schematic diagram of the storage state of a memory computing unit according to an exemplary embodiment of this application.

[0040] Figure 7 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application.

[0041] Figure 8 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of the present application.

[0042] Figure 9 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of the present application.

[0043] Figure 10 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of the present application.

[0044] Figure 11 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of the present application.

[0045] Figure 12 shows a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of the present application.

[0046] Figure 13 shows a schematic diagram of the memory operation of a memory computing unit according to an exemplary embodiment of the present application.

[0047] Figure 14 shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0048] Figure 15 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0049] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0050] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0051] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0052] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0053] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0054] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0055] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0056] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0057] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0058] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0059] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0060] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0061] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,r], j∈[1,t], r is the number of rows in the storage cell array, and t is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S rj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0062] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0063] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in the example of Figure 2, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0064] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly along columns, and the output terminals can be connected collinearly along rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0065] During use, storage circuits may experience precision loss, affecting the accuracy of stored data. Therefore, the data stored in the storage circuit can be refreshed periodically. When the storage circuit is applied to an in-memory computing system, precision loss can lead to a decrease in the accuracy of weight data, which may result in a decrease in the accuracy of calculation results and affect the reliability of the in-memory computing system. Therefore, the need for refreshing the storage circuit in an in-memory computing system still exists to improve the reliability of the system, but the refresh process may affect the computational efficiency of the storage circuit. In view of this, this application proposes a control method that can balance the requirements of reliability and computational efficiency in an in-memory computing system. By controlling the refresh of the storage circuit, the impact of the refresh on the computational efficiency is mitigated, so that the storage circuit has good storage precision when used for storage and good reliability and computational efficiency when used for in-memory computing, reducing the impact of refresh on the computational task.

[0066] As an example, Figure 3 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application.

[0067] As shown in Figure 3, the storage circuit 300 includes one or more storage units, which can be used as units for computation, i.e., storage areas that are opened or introduced in a single computation. This storage unit can also be called a storage unit 310, which includes m storage unit blocks, of which m1 storage unit blocks (shown as storage unit blocks B1 to B1 in Figure 3) are... m1 ) is used to store valid data (shown in the diagram as data D1 to D). m1 ), m2 of the m storage blocks (shown as storage block B in the diagram). m1+1 To B m1+m2 ) is used to store empty or invalid data (shown as data D' in the diagram). m1+1 To D' m1+m2 In other words, the state of m2 storage units is empty or invalid, where m = m1 + m2, m2 < m1, and m, m1, and m2 are positive integers.

[0068] The m² storage unit blocks shown in Figure 3 can be used as backup storage unit blocks within the in-memory computing unit 310. Thus, when data needs to be refreshed from a storage unit block containing valid data within the in-memory computing unit 310, the backup storage unit block can be used to handle the refreshed data. Since the backup storage unit block is still within the in-memory computing unit, the data from the refreshed storage unit block is updated in the backup storage unit block. The data stored in the in-memory computing unit is used for multiplication and accumulation calculations; therefore, refreshing the storage unit block does not affect the weight data of the in-memory computing unit, and the calculation of the same model can continue. This reduces the impact of refreshing on the calculation of the in-memory computing unit, improving the overall computational efficiency of the in-memory computing system. Furthermore, data refreshing can improve the accuracy of the weight data stored in the in-memory computing unit, thereby improving computational efficiency while maintaining computational reliability.

[0069] As can be seen, through the technical solution of this application embodiment, the storage circuit's storage unit includes a storage unit block for storing empty or invalid data. This storage unit block can be called a redundant storage unit block or a backup storage unit block, and can be used to store refreshed data. The redundant storage unit block can support the refreshed data still being stored in the current storage unit, which helps reduce the waiting latency caused by refreshing in storage circuits during storage applications, thereby improving the storage accuracy of the storage circuit while also considering the performance improvement of storage applications. Furthermore, the structure of this storage circuit simplifies the refresh control logic of the storage circuit.

[0070] In this embodiment, during the current refresh, the refreshed storage cell block can serve as a backup storage cell block after the refresh, thereby improving the wear leveling of storage cell blocks within the computing unit. For example, Figure 3 only shows one state of the computing unit 310. In other states, the backup storage cell block can vary; for instance, in another state, the backup storage cell block can be storage cell blocks B1 to B2. m1 One or more of them.

[0071] In the embodiments of this application, the above calculations may include in-memory calculations and near-memory calculations. For example, in in-memory calculations, the in-memory unit may perform analog domain multiplication and accumulation calculations within the in-memory unit based on the stored weight data and the input data received by the in-memory unit; as another example, in near-memory calculations, the weight data stored in the in-memory unit may also be read out, and the processing circuit outside the storage circuit is used to perform digital domain multiplication and accumulation calculations. The processing circuit may be packaged together with the storage circuit to realize near-memory calculations. The processing circuit may include a control circuit, or may be integrated with the control circuit, for example, implemented in the form of a system on chip (SOC).

[0072] In the following description of the embodiments, valid data can be used to distinguish invalid data or empty data, but it does not limit whether the specific data they point to is the same; it only indicates that the data is valid data. For example, the content pointed to by valid data may be different in different contexts. For instance, the valid data stored in the in-memory computing unit refers to the entire valid data stored in the in-memory computing unit. The valid data stored in the storage unit block may be a portion of the entire valid data.

[0073] In some embodiments, the storage cell blocks in the in-memory unit have the same capacity to simplify the control logic of the in-memory unit.

[0074] In some embodiments, the storage circuit may include a three-dimensional storage array, which may have a greater storage density or storage capacity, enabling the in-memory computing system to support larger model deployments. As an example, Figure 4 shows a schematic diagram of a three-dimensional storage array in a storage circuit according to an exemplary embodiment of this application.

[0075] As shown in Figure 4, the storage circuit 400 includes multiple storage units P1-P1 arranged along the X direction. x Where x is a positive integer greater than 1. A storage unit P u Includes multiple memory cell blocks B arranged along the Y direction u1 -B uy Where u∈[1,x], and y is a positive integer greater than 1. A storage unit block B uv Includes multiple memory cell arrays A arranged along the Z direction uv1 -Auvz Where v∈[1,y], and z is a positive integer greater than 1. Storage cell array A uvw The storage cell array A has a two-dimensional structure. uvw This includes storage cells arranged along the X and Y directions, where w∈[1,z]. For example, the storage cell array 210 shown in FIG2 may include one or more storage cell arrays, and when multiple storage cell arrays are included, these multiple storage cell arrays may be located in the same computing unit P. u In different storage cell blocks. In some embodiments, the plurality of storage cell arrays may be located in the same storage unit P. u In the same layer along the Z direction, multiple arrays of memory cells in that same layer can be referred to as a single memory cell (e.g., A shown in the figure). xw A storage operator unit can include multiple groups of storage units. A group of storage units can include storage units from multiple storage blocks arranged along the Y direction with the same X-coordinate position. The outputs of these storage units are collinearly connected and can be used to perform multiply-accumulate calculations. For example, storage block B... u1 -B uy The output terminals of storage cells with the same X coordinate located on the same layer in the Z direction can be connected collinearly.

[0076] For ease of distinction, in some embodiments of this application, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction. The X, Y, and Z directions can be any three distinct directions in three-dimensional space. In some examples, any two of the X, Y, and Z directions are perpendicular to each other.

[0077] In some examples, the storage circuitry includes, but is not limited to, NAND flash memory; the storage unit is referred to as a plane or bank; and the storage unit block is referred to as a block. This application is not limited thereto, and storage circuitry with different three-dimensional structures may have different names.

[0078] In some embodiments of this application, the memory computing unit may include multiple memory cell blocks, which can serve as erase units in the memory circuit.

[0079] In some embodiments of this application, the multiple storage cell blocks can be used to flexibly refresh data within the in-memory computing unit. Optionally, the multiple storage cell blocks in the in-memory computing unit can have the same capacity, which simplifies the control of the multiple storage cell blocks and reduces the possibility of insufficient capacity or redundant waste of storage capacity in the storage cell blocks to be written during refresh control. In other possible embodiments, the capacities of the multiple storage cell blocks can also be different. The capacity of the storage cell block can be used to characterize the storage capability of the storage cell block, and can be replaced by parameters such as storage space, storage size, storage upper limit, storage scale, storage range, or storage quota.

[0080] Invalid data refers to data stored in a storage unit that is unavailable or invalid. Empty data can include the storage state or stored data after the storage unit has been erased. This empty data can include, but is not limited to, "1" or "0". In storage unit block B... m1+1 To B m1+m2 In the case of storing invalid or empty data, this storage unit block B m1+1 To B m1+m2 It can be labeled, for example, storage cell block B. m1+1 If it is marked as "invalid", then during subsequent data writing, storage unit block B can be cleared first. m1+1 Invalid data is erased from the memory, and valid data is then written into it. For example, in memory cell block B... m1+1 After the data is erased, it can be marked as "empty," and valid data can be directly written into it during subsequent data writing processes. For ease of description, a storage cell block containing valid data can be called a valid storage cell block.

[0081] In some embodiments of this application, redundant storage unit blocks and effective storage unit blocks can be dynamically changed to improve wear leveling of storage unit blocks within the in-memory computing unit. In some embodiments of this application, the number of redundant storage unit blocks m2 can be less than the number of effective storage unit blocks m1. This results in a smaller proportion of redundant storage unit blocks within the in-memory computing unit, allowing more resources to be used for data storage or computation. This facilitates data refresh within the in-memory computing unit while reducing waste of storage or computing resources. As an example and not a limitation, m1 can be any positive integer between 4 and 8, and m2 can be less than or equal to... The values ​​of m1 and m2 are any positive integers. For example, m1 = 8, m2 = 1; or m1 = 8, m2 = 2; or m1 = 6, m2 = 3; m1 = 7, m2 = 2, etc. This application does not limit the specific values ​​of m1 and m2 in its embodiments.

[0082] This application also provides a control method. This control method can be executed by a control device (e.g., the control circuit in the above embodiments). As an example, FIG5 shows a schematic diagram of a control method according to an exemplary embodiment of this application.

[0083] As shown in Figure 5, the control method 500 may include the following steps.

[0084] S510, control the writing of valid data to the storage unit, wherein the valid data is stored in the m1 storage unit block of the m storage unit blocks, and the m2 storage unit block of the m storage unit blocks is used to store empty data or invalid data, m = m1 + m2, m2 < m1, and m, m1 and m2 are positive integers.

[0085] S520, control the first refresh of the valid data of the storage unit, wherein at least one of the m2 storage unit blocks is used to store the first valid data, the valid data includes the first valid data, and the first valid data is stored in at least one of the m1 storage unit blocks before the first refresh, and at least one of the m1 storage unit blocks is used to store empty data or invalid data.

[0086] The above control method utilizes redundant storage unit blocks to store the refreshed data when controlling the refresh of valid data in the in-memory computing unit. This ensures that the valid data remains stored in the current in-memory computing unit after the refresh, which helps reduce the waiting latency caused by the refresh of the storage circuit in in-memory computing applications. Thus, while maintaining storage accuracy, it can also improve the performance of in-memory computing applications.

[0087] For ease of understanding and illustration, Figure 6 shows a schematic diagram of the storage state of a memory computing unit according to an exemplary embodiment of this application. Figure 6 illustrates an example where the memory computing unit includes nine memory cell blocks (illustrated as memory cell blocks B1 to B9 in the figure), and the nine memory cell blocks include one redundant memory cell block (illustrated as memory cell block B' in the figure). The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of memory cell blocks and the number of redundant memory cell blocks in the memory computing unit can be other values.

[0088] After the control device executes S510 and controls the writing of valid data to the storage unit of the storage circuit, the storage state of the storage unit can be as shown in part (a) of Figure 6, wherein storage unit blocks B1 to B8 store valid data D1 to D8, storage unit block B9 stores invalid data or empty data, and storage unit block B9 is a redundant storage unit block B'.

[0089] The control device executes S520, controlling the first refresh of the valid data in the in-memory computing unit. This first refresh may include refreshing the valid data stored in at least one storage cell block in the in-memory computing unit. For example, the control device may control the refresh of the valid data D1 in storage cell block B1, writing the valid data D1 to storage cell block B9. After the refresh, the storage state of the in-memory computing unit can be as shown in part (b) of Figure 6, where storage cell block B9 is used to store the valid data D1, and storage cell block B1 is a new redundant storage cell block B'. ​​Storage cell block B1, which is the redundant storage cell block B', can be erased, making its state "empty", or the state of storage cell block B1 can be set to "invalid".

[0090] In the embodiments of this application, the storage unit may have different storage states at different times. The states in Figure 6 above are only examples of some of these states.

[0091] When the in-memory computing unit includes a redundant storage unit block B', the effective data refresh process of the in-memory computing unit can be similar to that shown in Figure 6. The redundant storage unit block B' is used to refresh the effective data stored in multiple storage unit blocks within the in-memory computing unit. The redundant storage unit block B' can be dynamically rotated among the multiple storage unit blocks of the in-memory computing unit. Alternatively, the multiple storage unit blocks of the in-memory computing unit can serve as redundant storage unit block B' at different times to refresh multiple effective data within the in-memory computing unit. In this implementation, the in-memory computing unit includes a single redundant storage unit block, resulting in less waste of storage resources in the storage circuit, less occupation of area and hardware resources, and minimal impact on the original functionality of the storage circuit. Furthermore, the single redundant storage unit block can be used to refresh the effective data within the in-memory computing unit, which is beneficial for the in-memory computing application and improves the in-memory computing performance of the storage circuit.

[0092] When the in-memory computing unit includes multiple redundant storage cell blocks B', during a single refresh of the valid data in the in-memory computing unit, the refreshed data can be stored using a single redundant storage cell block B' or multiple redundant storage cell blocks B'. For example, when the in-memory computing unit includes two redundant storage cell blocks B', one of the redundant storage cell blocks B' can be used to store the refreshed valid data in a single storage cell block, or the two redundant storage cell blocks B' can be used in parallel to store the refreshed valid data in two storage cell blocks. In this implementation, more space is reserved in the in-memory computing unit for storing refreshed data, thereby improving the refresh speed and flexibility of the valid data in the in-memory computing unit and further improving the in-memory computing performance of the storage circuit.

[0093] In some embodiments, the control device can control the refresh of valid data in the in-memory computing unit according to a set rule. For example, the set rule can indicate the order in which storage cell blocks in the in-memory computing unit are used as redundant storage cell blocks; or, for example, the set rule can indicate the target storage cell block in the in-memory computing unit; thereby, when the refresh is controlled according to the set rule, the wear degree among the storage cell blocks in the in-memory computing unit is balanced, which can reduce the difference in the lifespan between the storage cell blocks in the in-memory computing unit, reduce the probability of bad blocks, and extend the overall lifespan of the in-memory computing unit.

[0094] Optionally, a single refresh of a storage unit can refresh either a portion of the valid data in the storage unit or all the valid data in the storage unit.

[0095] Refreshing only some valid data takes less time than refreshing all valid data in a single refresh, allowing for timely response to business data processing after a single refresh. For example, in some embodiments, a set rule can be used to indicate the set order in which m storage unit blocks are used to store empty or invalid data; wherein, the storage unit block currently storing empty or invalid data is called the first storage unit block, and the storage unit block to be storing empty or invalid data is called the second storage unit block. In a single refresh (e.g., the first refresh), the control device can control the writing of data from the second storage unit block to the first storage unit block according to the set order. This set order can be used to characterize the refresh order of the storage unit blocks.

[0096] Refresh triggering methods can include periodic triggering or event triggering. For example, a refresh cycle can be set for the storage blocks within a memory unit. The refresh cycles of the storage blocks within the memory unit are the same, but the refresh start times are different, thus forming a rotating periodic refresh. This simplifies the control logic and ensures a balanced wear level among the storage blocks. Alternatively, event triggering conditions can include the storage block's precision being less than or equal to a precision threshold, or the number of reads or calculations reaching a threshold. This allows for timely refresh of the storage block when its precision decreases to the point where it might affect the computation result. Furthermore, periodic triggering and event triggering can be combined to jointly control the refresh of the memory unit. This application does not restrict the preset order, as long as the refresh frequency among the storage blocks is as balanced as possible.

[0097] According to some embodiments, as shown in part (a) of Figure 6, in the current state of the in-memory computing unit, storage block B9 is a storage block currently storing empty or invalid data (which can be referred to as the first storage block). According to a set rule or set order, storage block B1 is a storage block to store empty or invalid data (which can be referred to as the second storage block). According to the set rule, controlling the first refresh of valid data in the in-memory computing unit includes controlling the writing of data from storage block B1 to storage block B9. After the first refresh is completed, the storage state of the in-memory computing unit can be as shown in part (b) of Figure 6.

[0098] Setting rules or setting order determines the refresh order between storage unit blocks within a storage unit; in other words, it sets the order in which storage unit blocks store empty or invalid data in turn. The setting order can, for example, include: B1 to B... m The storage cell block currently storing empty or invalid data (referred to as the first storage cell block) is storage cell block B. k At that time, storage unit block B k+1 The storage unit block to be stored for empty or invalid data (referred to as the second storage unit block) is defined as follows: k ∈ [1, m], where m is the number of storage unit blocks within the storage unit. When k+1 is greater than the number of storage unit blocks m in the storage unit, for example, when k+1 is greater than 9, the starting storage unit block in this set order is used as the storage unit block to be stored for empty or invalid data, i.e., the second storage unit block. For example, when B9 is the first storage unit block, B1 is the second storage unit block.

[0099] Figure 7 illustrates a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application. Figure 7 illustrates an example in which the in-memory computing unit includes nine storage cell blocks (shown as storage cell blocks B1 to B9 in the figure), and the nine storage cell blocks include two redundant storage cell blocks (shown as storage cell block B' in the figure). The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of storage cell blocks and redundant storage cell blocks in the in-memory computing unit can be other values.

[0100] As shown in part (a) of Figure 7, in the current state, storage unit blocks B1 to B7 store valid data D1 to D7, while storage unit blocks B8 and B9 store invalid or empty data. During the first refresh in the current state, storage unit block B8 becomes the first storage unit block, and storage unit block B1 becomes the second storage unit block. The first refresh of valid data in the storage unit is controlled according to set rules, including controlling the writing of data from storage unit block B1 to storage unit block B8. After the first refresh is completed, the storage state of the storage unit can be as shown in part (b) of Figure 7.

[0101] As shown in part (b) of Figure 7, in the current state, storage blocks B2 to B8 store valid data D2 to D7 and D1, while storage blocks B9 and B1 store invalid or empty data. During a refresh in the current state, storage block B9 becomes the first storage block, and storage block B2 becomes the second storage block. The refresh of valid data in the in-memory unit is controlled according to set rules, including controlling the writing of data from storage block B2 to storage block B9. After the refresh is complete, the storage state of the in-memory unit can be as shown in part (c) of Figure 7.

[0102] Optionally, the refresh of sections 7(b) and (c) can be completed in one refresh.

[0103] For example, setting rules or setting order may include: storage cell block group 1; storage cell block group 2; storage cell block group m0, where m0 can be half of m. A storage cell block group includes a number of redundant storage cell blocks. Taking two as an example, the storage cell block currently storing empty or invalid data is storage cell block B. k and B g At that time, storage unit block B k and storage unit block B g For the first storage unit block, storage unit block B k+1 and storage unit block B g+1 Let B be the second storage unit block, where k∈[1,m0], g∈[1,m0], and k≠g. When k+1 or g+1 is greater than the number m of storage unit blocks in the storage unit, for example, when k+1 or g+1 is greater than 9, the initial storage unit block group in this set order is used as the storage unit block to store empty or invalid data, that is, the second storage unit block. For example, when storage unit block B8 is the first storage unit block, storage unit block B1 is the second storage unit block; when storage unit block B9 is the first storage unit block, B2 is the second storage unit block.

[0104] Refreshing all valid data is more advantageous for refresh control than refreshing only some valid data, and the overall accuracy of the storage and computing units is more consistent. For example, in some embodiments, a set rule can be used to indicate the target storage block for each of m storage block blocks; in a single refresh (e.g., the first refresh), based on the set rule, the data stored in the storage block currently storing some valid data is written to the target storage block indicated by the set rule, and the target storage block of the storage block currently storing empty or invalid data is controlled to be empty or invalid. Thus, according to the set rule, the valid data of the storage and computing unit can be refreshed in a single refresh of the storage and computing unit, reducing the overall number of refreshes and improving the accuracy consistency of the valid data of the entire storage and computing unit.

[0105] Figure 8 illustrates a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application. Figure 8 uses an example where the in-memory computing unit includes nine storage cell blocks (shown as storage cell blocks B1 to B9 in Figure 8), and these nine storage cell blocks include one redundant storage cell block (shown as storage cell block B' in the figure). The following description is for illustrative purposes only and is not limiting. In other alternative examples, the number of storage cell blocks and the number of redundant storage cell blocks in the in-memory computing unit can be other values. In this example, the setting rules may include: storage cell block B... k The target storage unit block is storage unit block B. g k∈[1,m], g∈[1,m], and k≠g. For example, g=k+1, and k<m, when k=m, g=1. For example, the target storage unit block of storage unit block B9 is storage unit block B1.

[0106] As shown in part (a) of Figure 8, in the current state of the in-memory computing unit, storage blocks B1 to B8 store partially valid data, while storage block B9 is currently storing empty or invalid data. During the first refresh, based on set rules, the data D1 to D8 stored in storage blocks B1 to B8 are written to target storage blocks B2 to B9 as indicated by the set rules, and the state of target storage block B1 in storage block B9 is controlled to be empty or invalid. After the first refresh is completed, the storage state of the in-memory computing unit can be as shown in part (b) of Figure 8.

[0107] According to some embodiments, the setting rules for the target storage unit block can correspond to the write order of the storage unit blocks. First, data whose target storage unit block is currently storing empty or invalid data is written to that storage unit block. Then, writes are sequentially executed to target storage unit blocks whose data source was from the last write. For example, according to the setting rules, the target storage unit block for storage unit block B8 is storage unit block B9, and storage unit block B8 is the target storage unit block for storage unit block B7. Thus, it is possible to control the writing of data stored in storage unit block B8 to target storage unit block B9 first, and then write the data stored in storage unit block B7 to target storage unit block B8. And so on, thus, a refresh can be completed using the storage unit blocks within the computing unit.

[0108] As shown in part (b) of Figure 8, in the current state, storage unit blocks B2 to B9 store partially valid data, while storage unit block B1 stores either empty or invalid data. During a refresh in the current state, based on set rules, the data D1 to D8 stored in storage units B2 to B9 are written to target storage units B3 to B9 and B1 as indicated by the set rules. The state of target storage unit B2 in storage unit B1 is controlled to be empty or invalid. After the refresh is complete, the storage state of the in-memory unit can be as shown in part (c) of Figure 8.

[0109] Through the technical solutions described in the above embodiments, during a single refresh of the in-memory computing unit, some or all of the valid data in the in-memory computing unit can be refreshed according to set rules. This not only facilitates wear leveling among multiple storage unit blocks within the in-memory computing unit, but also simplifies refresh control, improves refresh fairness, prevents some storage unit blocks from missing refresh resources, and provides predictability for the refreshed in-memory computing units, thus facilitating the control of computing operations.

[0110] According to some embodiments, a refresh can be performed using storage blocks other than the compute unit. For example, data stored in storage block B8 can be controlled to be written to storage blocks other than storage blocks B1 to B9 first. Then, data stored in storage block B7 can be controlled to be written to the target storage block B8. Subsequently, data stored in storage block B8 can be written to storage block B9 from storage blocks other than storage blocks B1 to B9 at any stage of the first refresh. This improves the flexibility of the refresh.

[0111] Controlling refresh using set rules can help reduce the probability of bad blocks occurring. Furthermore, this application also considers technical solutions for situations where bad blocks occur.

[0112] In some embodiments of this application, when a bad block appears in the memory computing unit, the control device can control the writing of the data stored in the bad block to a non-bad block in the memory computing unit. The non-bad block includes a memory cell block currently storing empty or invalid data, or a target memory cell block of the bad block indicated by a set rule. Assume that the memory computing unit has m3 bad blocks, where m3 ≤ m2, and m3 is a positive integer. Thus, when the number of bad blocks in the memory unit is no greater than the number of redundant memory cell blocks m2, the memory computing unit can still store complete and valid data. Therefore, even when bad blocks appear, calculations can still be performed, reducing the impact on the memory computing function and further extending the lifespan of the storage circuit.

[0113] In some examples, bad blocks may include memory cell blocks that are unusable due to physical damage or exhaustion of their lifespan. Bad blocks cannot be read, written, or erased normally. When performing read / write control operations on the memory unit, the control device can determine if the data can be read / written normally. For example, the control device can determine a memory cell block is bad if an uncorrectable error is read from it, or if the memory cell block cannot be erased correctly. When the control device detects a bad block in the memory unit, it can write the valid data corresponding to the bad block to a non-bad block in the memory unit. This non-bad block includes redundant memory cell blocks storing empty or invalid data, or valid memory cell blocks storing valid data. In some examples, the control device can write the valid data of the bad block to the current redundant memory cell block. Alternatively, in other examples, the control device can first write the data in a valid memory cell block to another memory cell block, erase the data in that valid memory cell block, and then write the valid data of the bad block to that valid memory cell block. In some implementations, the control device can obtain valid data of the bad block from other data sources for writing to non-bad blocks in the memory unit. For example, the control device can obtain valid data of the bad block from other data sources based on the logical address corresponding to the bad block for writing to non-bad blocks in the memory unit.

[0114] As examples, Figures 9 and 10 respectively illustrate schematic diagrams of different storage states of a memory computing unit according to an exemplary embodiment of this application. Figures 9 and 10 illustrate an example where the memory computing unit includes nine memory cell blocks (illustrated as memory cell blocks B1 to B9 in the figures), and the nine memory cell blocks include one redundant memory cell block (illustrated as memory cell block B' in the figures). The following description is for illustrative purposes only and is not limiting. In other alternative examples, the number of memory cell blocks and the number of redundant memory cell blocks in the memory computing unit can be other values.

[0115] As shown in parts (a) and (b) of Figure 9, in a storage unit, a certain storage cell block becomes a bad block, for example, storage cell block B5 is shown as a bad block in the figure. The control device can write the valid data D5 of storage cell block B5 into the current redundant storage cell block B9.

[0116] As shown in parts (a) and (b) of Figure 10, in the storage unit, a certain storage cell block becomes a bad block, for example, storage cell block B5 is shown as a bad block in the figure. Partially valid data is refreshed according to any of the above-mentioned setting rules, thereby ensuring that the valid data corresponding to the bad block is refreshed into the storage cell block indicated by the setting rule. For example, the control device can write valid data from storage cell blocks B5, B6, B7, and B8 to storage cell blocks B6, B7, B8, and B9.

[0117] In this implementation, the setting rules can be updated after writing valid data from a bad block to a non-bad block, thus removing the bad block from the setting rules. For example, in the updated setting rules, the target storage block for storage block B4 is changed from storage block B5 to storage block B6. This simplifies the updating of the setting rules.

[0118] Figures 9 and 10 illustrate only the case where the in-memory computing unit includes a single redundant storage block. In some alternative embodiments, the in-memory computing unit may include multiple redundant storage blocks. Even if the number of bad blocks in the in-memory computing unit is less than the number of redundant storage blocks, after writing valid data from the bad blocks to the non-bad blocks, the number of non-bad blocks will still be greater than the number of valid storage blocks. Thus, after updating the setting rules to remove bad blocks from the setting rules, the control device can control the refreshing of valid data within the in-memory computing unit based on the updated setting rules. The process of refreshing valid data can be found in the relevant descriptions of the embodiments above, and will not be repeated here.

[0119] In some implementations, when the number of bad blocks within a memory cell equals the number of redundant memory cell blocks within that memory cell, the valid data in the memory cell can be refreshed using external memory cell blocks, which are not part of that memory cell. During the refresh process, the external memory cell blocks and the non-bad blocks within the memory cell are used to store valid data.

[0120] Figure 11 illustrates a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application. Figure 11 is illustrated using an example where the in-memory computing unit includes nine storage cell blocks (shown as storage cell blocks B1 to B9 in the figure), and the nine storage cell blocks include one bad block. The following description is for illustrative purposes only and is not limiting. In other alternative examples, the number of storage cell blocks and the number of bad blocks in the in-memory computing unit can be other values.

[0121] As shown in part (a) of Figure 11, the in-memory computing unit includes storage cell blocks B1 to B9. Storage cell block B0 does not belong to this in-memory computing unit and can be referred to as an external storage cell block. Storage cell block B0 can be a storage cell block in other in-memory computing units, or it can be a storage cell block independently set in the storage circuit. Storage cell block B0 is currently in an empty or invalid state.

[0122] When bad blocks appear in a memory cell, and the number of bad blocks equals the number of redundant memory cell blocks in the memory cell, when refreshing the valid data of the memory cell, the data of any memory cell block (non-bad block) to be refreshed can be written to memory cell block B0. For example, as shown in part (b) of Figure 11, the valid data D8 in memory cell block B9 to be refreshed can be written to memory cell block B0, and memory cell block B9 can be erased. Then, as shown in part (c) of Figure 11, the valid data D8 in memory cell block B0 can be written back to memory cell block B9 to refresh the valid data of the memory cell. After refreshing, the data in memory cell block B0 can be erased. Memory cell block B0 can be written with valid data from other memory cell blocks in the memory cell for refreshing the valid data of the memory cell.

[0123] Figure 12 illustrates a schematic diagram of the storage state of another in-memory computing unit according to an exemplary embodiment of this application. Figure 12 illustrates an example where the in-memory computing unit includes nine storage cell blocks (shown as storage cell blocks B1 to B9 in the figure), and the nine storage cell blocks include one bad block. The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of storage cell blocks and the number of bad blocks in the in-memory computing unit can be other values.

[0124] The scheme shown in part (a) of Figure 12 can be found in the description of the scheme shown in part (a) of Figure 11 above. When bad blocks appear in the in-memory unit, and the number of bad blocks equals the number of redundant storage blocks in the in-memory unit, storage block B0 can be used to refresh all valid data in the in-memory unit. For example, as shown in part (b) of Figure 12, valid data D8 in storage block B9 can be written to storage block B0. After erasing storage block B9, valid data D7 in storage block B8 can be written to storage block B9, and so on. Valid data from storage blocks B7 to B6 and B4 to B1 can be written to storage blocks B8 to B6 and B4 to B2. Then, as shown in part (c) of Figure 12, valid data D8 in storage block B0 can be written to storage block B1. This refreshes the valid data in the in-memory unit.

[0125] In the examples shown in Figures 11 and 12 above, the refresh of valid data in the in-memory unit can be performed using a single storage block outside the in-memory unit. In other examples, multiple storage blocks outside the in-memory unit can be used to refresh the valid data in the in-memory unit. If bad blocks appear within the in-memory unit, the refresh of valid data in the in-memory unit will avoid the bad blocks. The refresh methods shown in Figures 11 and 12 are for illustrative purposes only and are not limiting. For refresh methods of non-bad blocks in the in-memory unit and at least one storage block outside the in-memory unit, please refer to the relevant descriptions in other embodiments.

[0126] The technical solution of this application embodiment allows for data refresh of the in-memory computing unit using storage unit blocks outside the computing unit. This ensures that valid data continues to circulate within the computing unit, reducing the latency caused by refreshes in in-memory computing applications. This improves the storage accuracy of the storage circuit while simultaneously enhancing the performance of the in-memory computing application. Furthermore, the structure of the above storage circuit simplifies the refresh control logic for the storage circuit.

[0127] In some embodiments of this application, the control device may update the mapping relationship in response to the refresh of the storage unit or the writing of bad block data to non-bad blocks in the storage unit. The mapping relationship is used to indicate the correspondence between the physical addresses and logical addresses of the m1 storage unit blocks that currently store valid data.

[0128] In some embodiments of this application, the control device may update the mapping relationship in response to writing bad block data to non-bad blocks in the memory unit.

[0129] In some embodiments of this application, the storage circuit can store mapping relationships.

[0130] In some embodiments, the control device can obtain an initial mapping relationship between logical addresses and physical addresses. Based on this initial mapping relationship, the control device can control the writing of valid data to storage cell blocks in the storage unit. After the valid data is refreshed or data from a bad block is written to a non-bad block, the correspondence between the physical address and logical address of the storage cell block currently storing valid data can be updated. Through the above technical solution, the logical and physical addresses related to valid data can be recorded and maintained, improving the accuracy and reliability of data operations, thereby further enhancing the storage and computing performance of the storage circuit.

[0131] Optionally, the above mapping relationship is also used to indicate the correspondence between the physical addresses and logical addresses of the m2 storage cell blocks currently storing empty or invalid data. In this implementation, the mapping relationship can record the address information of each storage cell block in the computation more comprehensively. Based on this mapping relationship, the control method of the control device on the storage circuit can be simplified, and the accuracy and reliability of data operations in the control storage circuit can be further improved.

[0132] Optionally, the above mapping relationship is also used to indicate the correspondence between the physical address and logical address of a bad block.

[0133] Figure 13 illustrates a schematic diagram of a memory operation of a memory computing unit according to an exemplary embodiment of this application. Figure 13 is illustrated using an example where the memory computing unit includes nine memory cell blocks (shown as memory cell blocks B1 to B9 in the figure), and the nine memory cell blocks include one redundant memory cell block (shown as memory cell block B' in the figure). The following description is for illustrative purposes only and is not a limitation. In other alternative examples, the number of memory cell blocks and the number of redundant memory cell blocks in the memory computing unit can be other values.

[0134] As shown in part (a) of Figure 13, in the storage unit, any storage unit block can be a redundant storage unit block, and other storage unit blocks can be used to store valid data. For example, as shown in the figure, storage unit blocks B1, B3 to B9 store valid data D1 to D8, and storage unit block B2 is a redundant storage unit block B', which stores invalid data or empty data.

[0135] As shown in part (b) of Figure 13, the control device can determine the input data sequence based on the input data to be calculated. The control device can convert the input data into an input data sequence based on the location of redundant storage cell blocks. This input data sequence includes valid data sequences In1 to In8 and supplementary data, which, for example, can be all "0"s. The control device can perform supplementary data operations on the original input data sequence. This supplementary data does not affect the calculation result; for example, the supplementary data may include, but is not limited to, all "0"s. The control device can obtain the physical address of redundant storage cell block B' in the in-memory computing unit. Based on this physical address, the location of the supplementary data in the input data sequence can be determined so that the supplementary data corresponds to redundant storage cell block B'. ​​Additionally, the control device can obtain the physical addresses of multiple valid storage cell blocks (e.g., storage cell blocks B1, B3 to B9 shown in the figure). Based on these physical addresses, the location of multiple valid input data in the input data sequence can be determined so that multiple valid input data correspond to multiple valid storage cell blocks, and the valid input data and the weight data stored in the corresponding valid storage cell block can correspond to the same logical address. In some examples, the control device can obtain the mapping relationship in the above embodiments and determine the physical address of the valid storage unit block corresponding to the input data based on the logical address of the input data and the mapping relationship. As shown in part (b) of Figure 13, the control device can input the supplemented input data sequence into the in-memory computing unit of the storage circuit. The storage unit block in the in-memory computing unit can perform calculations based on the stored weight data and the received input data. In the embodiment shown in Figure 13, the in-memory computing unit can perform dynamic supplementation operations on the input data sequence for in-memory calculations when no bad blocks appear, without affecting its in-memory computing performance due to the update of the valid data of one storage unit block; in addition, when bad blocks appear in the in-memory computing unit, redundant storage unit blocks can be used to replace the bad blocks to continue the calculations, without affecting its in-memory computing performance due to the appearance of bad blocks.

[0136] Through the technical solutions of the above embodiments, the control device can input multiple adapted input data into the in-memory computing unit according to the stored data of multiple storage unit blocks in the in-memory computing unit. Among the multiple input data, the valid input data can be input into the valid storage unit block and calculated with the stored data therein, thereby improving the calculation accuracy of the in-memory computing unit. In addition, the invalid data (e.g., "0" data) among the multiple input data can be input into the redundant storage unit block and / or bad block. The calculation of the redundant storage unit block and / or bad block will not affect the overall calculation result of the in-memory computing unit, which is conducive to further improving the calculation accuracy of the in-memory computing unit.

[0137] This application also provides a control device, which may be located within or include the above-described control circuit. The control device may be located within the control circuit 120 / 220 shown in FIG. 1 or FIG. 2, or may be independent of the control circuit 120 / 220. This control device can be used to execute any of the above-described control methods.

[0138] This application also provides a control device, as shown in FIG14. FIG14 illustrates a schematic diagram of a control device according to an exemplary embodiment of this application. As shown in FIG14, the control device 1400 includes: at least one processing circuit 1410 and an interface circuit 1420, the interface circuit 1420 being signal-connected to a storage circuit, and the at least one processing circuit 1410 being used to execute any of the control methods provided in the above embodiments. The control device 1400 may further include a storage device for storing setting rules. The storage device may include volatile memory or non-volatile memory.

[0139] For example, in some embodiments, the processing circuit may include an application-specific integrated circuit (ASIC), which implements some or all of the functions of the control device by designing the logical relationships between the devices within the circuit; as another example, in some embodiments, the processing circuit may be implemented by a programmable logic device (PLD) circuit, which may include a large number of logic devices, and the logical relationships between the logic devices are configured through a configuration file, thereby implementing some or all of the functions of the control device.

[0140] Optionally, the control device provided in the embodiments of this application can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0141] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented by an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, including, for example, a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor (DSP). Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0142] This application also provides a memory computing system, which includes: a memory circuit as described in any of the above embodiments; and a control device for executing any of the control methods described in the embodiments of this application to control the memory circuit.

[0143] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0144] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0145] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0146] This application also provides an electronic device, as shown in FIG15. FIG15 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG15, the electronic device 1500 may include any of the above-described in-memory computing systems 1510 for processing data of the electronic device. The electronic device may also include an input / output device 1520 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1530, which may process data provided to the in-memory computing system 1510 or process output data of the in-memory computing system 1510. The output of the input / output device 1520 may be based on the output of the processor 1530 or the output of the in-memory computing system 1510.

[0147] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0148] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method, characterized in that, For controlling a storage circuit, the storage circuit including a storage computing unit, the storage computing unit including m storage unit blocks, the control method including: The control writes valid data to the storage unit, wherein the valid data is stored in m1 storage unit blocks out of the m storage unit blocks, and m2 storage unit blocks out of the m storage unit blocks are used to store empty data or invalid data, m = m1 + m2, m2 < m1, and m, m1 and m2 are positive integers; The first refresh of the valid data of the storage unit is controlled, wherein at least one of the m2 storage unit blocks is used to store the first valid data, the valid data includes the first valid data, and the first valid data is stored in at least one of the m1 storage unit blocks before the first refresh, and the at least one of the m1 storage unit blocks is used to store empty data or invalid data.

2. The control method according to claim 1, characterized in that, The first refresh of the valid data of the storage unit includes: According to the set rules, the first refresh of the valid data in the storage unit is controlled.

3. The control method according to claim 2, characterized in that, The setting rule is used to indicate the setting order of the m storage unit blocks for storing empty or invalid data; wherein, the storage unit block currently storing empty or invalid data includes the first storage unit block, and the storage unit block to be stored with empty or invalid data includes the second storage unit block. The step of controlling the first refresh of the valid data of the storage unit according to the set rules includes: According to the set sequence, the data in the second storage cell block is written into the first storage cell block.

4. The control method according to claim 2, characterized in that, The setting rule is used to indicate the target storage unit block for each of the m storage unit blocks; The step of controlling the first refresh of the valid data of the storage unit according to the set rules includes: According to the set rules, control the data stored in the storage unit block that currently stores some valid data to be written into the target storage unit block indicated by the set rules; Controls the state of the target storage cell block that currently stores empty or invalid data to be empty or invalid.

5. The control method according to any one of claims 1 to 4, characterized in that, Also includes: When a bad block appears in the storage unit, the data of the bad block is written to a non-bad block in the storage unit. The non-bad block includes a storage unit block that currently stores empty or invalid data or a target storage unit block of the bad block indicated by a set rule. The storage unit includes m3 bad blocks, where m3 ≤ m2 and m3 is a positive integer.

6. The control method according to claim 5, characterized in that, The storage circuit further includes an external storage unit block, which is not part of the storage unit. When m3 = m2, the control method further includes: The second refresh of the valid data of the storage unit is controlled, wherein the external storage unit block and the non-bad block of the storage unit are used to store the valid data.

7. The control method according to claim 5, characterized in that, When m3 < m2, the control method further includes: According to the set rules, the effective data of the storage unit is refreshed in the third time among m-m3 non-bad blocks.

8. The control method according to any one of claims 1 to 7, characterized in that, Also includes: In response to the first refresh, the mapping relationship is updated, which is used to indicate the correspondence between the physical addresses and logical addresses of the m1 storage unit blocks that currently store valid data.

9. The control method according to claim 8, characterized by, The mapping relationship is also used to indicate the correspondence between the physical addresses and logical addresses of the m2 storage cell blocks that currently store empty or invalid data.

10. The control method according to any one of claims 1 to 9, characterized by, m1 = 8, m2 = 1.

11. The control method according to any one of claims 1 to 10, characterized in that, The m storage unit blocks have the same capacity.

12. A storage circuit, characterized in that, include: The storage and computing unit includes m storage unit blocks. At the first time, m1 of the m storage unit blocks are used to store valid data, and m2 of the m storage unit blocks are used to store empty data or invalid data. m = m1 + m2, m2 < m1, and m, m1 and m2 are positive integers.

13. The storage circuit according to claim 12, characterized in that, At a second time after the first refresh of the valid data in the storage unit, at least one of the m2 storage unit blocks is used to store the first valid data, the valid data including the first valid data, and the first valid data is stored in at least one of the m1 storage unit blocks at the first time. Furthermore, during the second time, at least one of the m1 storage cell blocks is used to store empty or invalid data.

14. The storage circuit according to claim 13, characterized in that, The refresh of valid data in the storage unit is based on a set rule.

15. The storage circuit of claim 14, wherein, The setting rule is used to indicate the setting order of the m storage unit blocks for storing empty or invalid data; or, the setting rule is used to indicate the target storage unit block of each of the m storage unit blocks.

16. The storage circuit according to any one of claims 12 to 15, characterized in that, The storage circuit also includes an external storage unit block, which does not belong to the storage and computing unit. In the event of a bad block in the storage and computing unit, during the second refresh process of the valid data in the storage and computing unit, the external storage unit block and the non-bad block of the storage and computing unit are used to store the valid data.

17. The storage circuit according to any one of claims 12 to 16, characterized in that, m1 = 8, m2 = 1.

18. The storage circuit according to any one of claims 12 to 17, characterized in that, The m storage unit blocks have the same capacity.

19. A control device, characterized in that, include: Interface circuitry used to communicate with storage circuitry; At least one processing circuit is used to perform the control method as described in any one of claims 1 to 11.

20. An in-memory computing system, characterized in that, include: The storage circuit as described in any one of claims 12 to 18; A control device for performing the control method as described in any one of claims 1 to 11 to control the storage circuit.

21. An electronic device, characterized in that, Including the in-memory computing system as described in claim 20.

Images