LED dimming system and control circuit thereof

Abstract

The present application discloses an LED dimming system and a control circuit thereof. On the basis of a feedback signal of an output voltage of a power conversion circuit and a dimming control signal, the control circuit controls, by means of an oscillator control circuit, the turn-on and turn-off of a clock signal, so that the turn-on of the power conversion circuit can be synchronized with a rising edge of the dimming control signal, and a minimum turn-on time is ensured for the power conversion circuit each time. In addition, when the turn-on time of a dimming switch is short, some dimming cycles can be adaptively skipped, thereby not only preventing the problem of output voltage drop when the dimming switch is turned on, but also reducing the output ripple of the circuit and improving a dimming ratio.

Description

LED dimming system and its control circuit

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411959461.1, filed on December 27, 2024, entitled "LED Dimming System and Control Circuit Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of LED driving technology, and more specifically, to an LED dimming system and its control circuit. Background Technology

[0004] A light-emitting diode (LED) is a solid-state semiconductor device that converts electrical energy into visible light. LEDs have advantages such as high luminous intensity, easy control, low-voltage DC drive, and long lifespan, and therefore have been widely used in many applications such as lighting and display backlighting.

[0005] Currently, the main dimming methods for LED systems are TRIAC (Silicon Controlled Rectifier) ​​dimming and Pulse Width Modulation (PWM) dimming. PWM dimming adjusts the brightness of the LED string by using a PWM signal with a specific duty cycle to open and close the current flowing through it. Compared to TRIAC dimming, a significant advantage of PWM dimming is that it avoids visible flicker. The higher the dimming frequency, the less noticeable the flicker becomes to the human eye. When the dimming frequency is greater than 3kHz, flicker is virtually imperceptible to the human eye. Therefore, PWM dimming is increasingly favored by the industry.

[0006] Figures 1 and 2 show the circuit diagram and waveform diagram of a prior art LED dimming system, respectively. Figure 1 shows an LED dimming system 100 based on peak current mode, including a power conversion circuit 101, a controller 102, a dimming controller 103, and dimming switches S2 and S3. The power conversion circuit 101 provides an output voltage Vout to the LED strip 104 based on the input voltage Vin. The controller 102 controls the switching on and off of the power switch T1 in the power conversion circuit 101 to achieve stable output. The dimming controller 103 generates a dimming control signal PWM_dim based on an external dimming signal to control the switching of the dimming switches S2 and S3 connected in series with the LED strip 104, thereby controlling the brightness of the LED strip 104. The controller 102 controls the power switch T1 to turn on when the pulse of the clock signal CLK provided by the oscillator 122 arrives, thereby causing the inductor current in the power conversion circuit 101 to start rising; when the peak value of the inductor current reaches the output value of the error amplifier 121, the controller 102 turns off the power switch T1, thereby causing the inductor current to start falling, and finally stabilizing the output voltage Vout of the power conversion circuit 101 at a suitable value.

[0007] In the LED dimming system 100 shown in Figure 1, the dimming control signal PWM_dim not only controls the on and off states of the dimming switch, but also simultaneously controls the output of the error amplifier 121 and the on and off states of the power switch T1. As shown in Figure 2, the drive control signal PWM_CTL is the control signal for the power switch T1 in the power conversion circuit. When the dimming control signal PWM_dim is low, the dimming switch is off, and the current ILED in the LED strip 104, which is the load of the power conversion circuit 101, is also low. Therefore, the power switch T1 in the power conversion circuit 101 needs to be turned off simultaneously to avoid excess energy accumulating on the output capacitor Cout. At the same time, the peak information of the inductor current is stored on the capacitor C1. In this way, when the dimming control signal PWM_dim is high again, the controller 102 can respond quickly so that the power conversion circuit 101 can quickly establish the inductor current under steady-state operation.

[0008] However, a problem exists in the existing LED dimming system 100: when the dimming control signal PWM_dim flips to a high level, the clock signal CLK may not flip to a high level at the same time. This results in a delay time t1, as shown in Figure 2, between the effective pulse of the clock signal CLK and the rising edge of the dimming control signal PWM_dim. This delay time t1 prevents the power conversion circuit 101 from quickly establishing a stable inductor current when the dimming control signal PWM_dim flips to a high level, leading to a drop in the output voltage Vout. This not only causes significant output voltage ripple but may also introduce noise in severe cases. Furthermore, in applications with high LED dimming ratios, the duty cycle of the dimming control signal PWM_dim becomes very small, resulting in an even shorter inductor current build-up time, thus exacerbating the aforementioned problem. Therefore, it is difficult to achieve a very short on-time in existing LED dimming systems, severely limiting further improvements in LED dimming ratio. Summary of the Invention

[0009] In view of the above problems, the purpose of the present invention is to provide an LED dimming system and its control circuit. By synchronizing the power conversion circuit's activation with the rising edge of the dimming control signal, and by ensuring that the minimum activation time of the power conversion circuit each time adaptively spans some dimming cycles when the dimming switch's on-time is short, the problem of output voltage drop when the dimming switch is turned on can be avoided, and the output ripple of the circuit can be reduced and the dimming ratio improved.

[0010] According to one aspect of the present invention, a control circuit for an LED dimming system is provided, wherein the LED dimming system includes a power switch and a dimming switch, the switching of the dimming switch on and off being controlled by a dimming control signal, wherein the control circuit includes: a feedback circuit for generating a feedback signal based on the current flowing through an LED load; an oscillator for generating a clock signal, the clock signal including a plurality of continuous pulses; a logic circuit for controlling the power switch to be turned on according to the clock signal, wherein the effective edges of adjacent pulses define a switching period; and an oscillator control circuit for receiving the feedback signal and the dimming control signal, and, when the feedback signal is less than a second reference voltage, providing a synchronization control signal to the oscillator based on the effective edges of the dimming control signal, the oscillator generating pulses of the clock signal according to the synchronization control signal to achieve synchronous turning on of the load switch and the dimming switch.

[0011] Optionally, when the feedback signal is less than the second reference voltage, the effective edge of the synchronization control signal is synchronized with the effective edge of the dimming control signal, and the invalid edge of the synchronization control signal is delayed by a first time relative to the invalid edge of the dimming control signal.

[0012] Optionally, the first time is equal to one of the switching cycles.

[0013] Optionally, the effective level time of the synchronization control signal is greater than or equal to the minimum turn-on time, wherein the minimum turn-on time is equal to M switching cycles, and M is an integer greater than 1.

[0014] Optionally, the control circuit further includes: a peak current detection module, configured to compare the feedback signal with a first reference voltage to generate an error amplification signal, and generate a peak current detection signal when the current detection signal representing the inductor current of the LED dimming system reaches the error amplification signal, wherein the logic circuit is configured to control the power switch to turn off in each switching cycle according to the peak current detection signal.

[0015] Optionally, the second reference voltage is greater than the first reference voltage.

[0016] Optionally, the oscillator control circuit includes: a first RS latch, with a set terminal for receiving the dimming control signal, a reset terminal for receiving the clock signal, and an output terminal for generating a first trigger signal; a first comparator, with a non-inverting input terminal for receiving the second reference voltage, an inverting input terminal for receiving the feedback signal, and an output terminal for generating a first comparison signal; a single-sided delay unit, used to delay the invalid edge of the first comparison signal for a second time to obtain a delayed signal, wherein the second time is greater than the first time; a first AND gate, used to perform an AND logic operation on the first trigger signal and the delayed signal to generate a second trigger signal; a minimum on-time module, used to count the period of the clock signal at the start time of the synchronization control signal, and generate the minimum on-time signal after a preset time, wherein the period count value of the clock signal within the preset time period represents the minimum on-time; and a second RS latch, with a set terminal for receiving the second trigger signal, a reset terminal for receiving the minimum on-time signal, and an output terminal for providing the synchronization control signal.

[0017] Optionally, the minimum turn-on time module includes: an OR gate, with a first input terminal for receiving the clock signal and a second input terminal for receiving the minimum turn-on time signal; and M cascaded D flip-flops, wherein the data terminal and negative output terminal of each D flip-flop are shorted, the reset terminal of each D flip-flop is used to receive the synchronization control signal, the clock terminal of the first D flip-flop among the M D flip-flops is connected to the output terminal of the OR gate, the clock terminals of the second to Mth D flip-flops among the M D flip-flops are connected to the negative output terminal of the preceding D flip-flop, and the positive output terminal of the Mth D flip-flop among the plurality of D flip-flops is used to provide the minimum turn-on time signal.

[0018] Optionally, the oscillator includes: a ramp generation module for generating a ramp signal; a second comparator for comparing the ramp signal with a reference voltage to generate a second comparison signal; a third RS latch, with a set terminal for receiving the second comparison signal, a reset terminal for receiving the inverted signal of the clock signal, and an output terminal for providing a third trigger signal; a second AND gate for performing an AND logic operation between the third trigger signal and the synchronization control signal; and a single pulse module for generating the clock signal based on the output of the second AND gate.

[0019] Optionally, the ramp generation module includes: a first current source and a first capacitor connected in series between the power supply voltage and ground; and a first transistor, with a first terminal connected to the intermediate node of the first current source and the first capacitor, a second terminal connected to ground, and a control terminal connected to the output of the second AND gate, wherein the first transistor generates the ramp signal at the intermediate node of the first capacitor by controlling the charging and discharging process of the first current source on the first capacitor.

[0020] Optionally, the peak current detection module includes: an error amplifier, with an inverting input for receiving the feedback signal, a non-inverting input for receiving a first reference voltage, and an output for generating an error amplification signal; and a third comparator, with an inverting input for receiving the error amplification signal, a non-inverting input for receiving a current detection signal, and an output for generating the peak current detection signal, wherein the current detection signal is obtained through a sampling resistor connected to the power switch.

[0021] Optionally, the peak current detection module further includes: a first switch connected between the output terminal of the error amplifier and the inverting input terminal of the first comparator, wherein the dimming control signal is used to control the switching of the first switch on and off; and a second capacitor connected between the inverting input terminal of the third comparator and ground.

[0022] Optionally, the logic circuit includes: a fourth RS latch, a set terminal for receiving the clock signal, a reset terminal for receiving the peak current detection signal, and an output terminal for generating a drive control signal, wherein the drive control signal is used to control the on and off switching of the power switch.

[0023] According to another aspect of the present invention, an LED dimming system is provided, comprising: a power conversion circuit including at least one power switch, the power conversion circuit being configured to provide an output voltage to an LED load according to an input voltage; a dimming switch being configured to be connected in series with the LED load; a dimming controller being configured to generate a dimming control signal according to an external dimming signal, the dimming control signal being configured to control the switching on and off of the dimming switch; and a control circuit being configured to generate a drive control signal being configured to control the switching on and off of the at least one power switch.

[0024] This invention provides an LED dimming system and its control circuit based on a peak current mode control architecture. The control circuit uses an oscillator control circuit to control the clock signal to turn on and off according to the feedback signal of the output voltage of the power conversion circuit and the dimming control signal. This allows the power conversion circuit to turn on synchronously with the rising edge of the dimming control signal, thereby avoiding the problem of output voltage drop when the dimming switch is turned on and reducing the output ripple of the circuit. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a circuit diagram of a prior art LED dimming system.

[0027] Figure 2 shows a waveform diagram of a prior art LED dimming system.

[0028] Figure 3 shows a schematic diagram of the LED dimming system according to an embodiment of the present invention.

[0029] Figure 4 shows a schematic diagram of the peak current detection circuit according to an embodiment of the present invention.

[0030] Figure 5 shows a circuit diagram of the oscillator control circuit according to an embodiment of the present invention.

[0031] Figure 6 shows a circuit diagram of the oscillator according to an embodiment of the present invention.

[0032] Figure 7 shows a waveform diagram of the LED dimming system according to an embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time.

[0033] Figure 8 shows a simulation waveform of the LED dimming system according to an embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time. Detailed Implementation

[0034] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0035] Throughout this specification, references to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases “in one embodiment” or “in an embodiment” appearing throughout this specification do not necessarily refer to the same embodiment. The verbs “comprising” and “having” are used herein as open-ended limitations, neither excluding nor requiring the presence of any unrecited features. Unless expressly stated otherwise, the features recited in the dependent claims may be freely combined with each other. The use of “a” or “an” (i.e., the singular form) to define an element throughout the document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term “connected” is used to specify a direct electrical connection between circuit elements, while the term “coupled” is used to specify an electrical connection between circuit elements that may be direct or may be via one or more other elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, no intermediate element is present. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is assumed to be the voltage between the node and a reference potential (usually ground). Similarly, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is assumed to refer to a reference potential. The voltage and potential of a given node or terminal will be further specified using the same reference numerals. A signal that alternates between a first logic state (e.g., logic low) and a second logic state (e.g., logic high) is called a "logic signal". The high and low states of different logic signals in the same electronic circuit may differ. In particular, the high and low states of a logic signal may correspond to voltages or currents that may not be completely constant in either the high or low state.

[0036] In this application, the power switch is a transistor that operates in switching mode to provide a current path, including one selected from metal-oxide-semiconductor field-effect transistors, insulated-gate bipolar transistors, and bipolar transistors. The first terminal and the second terminal of the power switch are respectively the high potential terminal and the low potential terminal on the current path, and the control terminal is used to receive a drive signal to control the switching on and off of the switch.

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] Figure 3 shows a circuit diagram of an LED dimming system 200 according to an embodiment of the present invention. In the embodiment shown in Figure 3, the LED dimming system 200 includes a power conversion circuit 201, a control circuit 202, a dimming controller 203, an LED load 204, a dimming switch 205, and a current biasing circuit 206.

[0039] The power conversion circuit 201 has an input terminal for receiving an input voltage Vin, and an output terminal connected to an LED load 204. The power conversion circuit 201 includes at least one power switch, and by controlling the on / off switching of the at least one power switch, an output voltage is provided at the output terminal of the power conversion circuit 201 to drive the LED load 204.

[0040] In the embodiment shown in Figure 3, the power conversion circuit 201 is schematically a power conversion circuit with a BOOST topology. Specifically, the power conversion circuit 201 includes an inductor L1, a power switch T1, a freewheeling diode D1, an output capacitor Cout, and a sampling resistor Rs. The inductor L1, power switch T1, and sampling resistor Rs are connected in series between the input voltage Vin and the reference ground. The common node of the inductor L1 and the power switch T1 is labeled as the switching node SW. The freewheeling diode D1 is connected between the switching node SW and the output terminal of the power conversion circuit 201. The output capacitor Cout is connected between the output terminal of the power conversion circuit 201 and the reference ground. It should be understood that in other embodiments, the power conversion circuit 201 can also be selected from other suitable isolated or non-isolated topologies, such as BUCK topology, FLYBACK, resonant half-bridge topology, etc.

[0041] Furthermore, in the embodiment shown in Figure 3, the power switch T1 is schematically represented as an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the freewheeling diode D1 is schematically represented as an uncontrolled diode. Those skilled in the art will understand that in other embodiments, the power switch T1 may also include other suitable semiconductor power switching device types, such as junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), and double-diffusion metal-oxide-semiconductor (DMOS). The freewheeling diode D1 may also be replaced by a power switching device, such as a synchronous rectifier. The switching of the power switch T1 on and off is controlled by the drive control signal PWM_CTL generated by the control circuit 202. In embodiments where the freewheeling diode D1 is replaced by a power switching device, the control circuit 202 also generates an inverted signal of the drive control signal PWM_CTL to control the switching of the synchronous rectifier. Those skilled in the art will understand that the inverted signal of the drive control signal PWM_CTL refers to a signal that is logically complementary to the drive control signal PWM_CTL.

[0042] Furthermore, in this embodiment, the LED load 204 is, for example, an LED string formed by connecting multiple LEDs in series.

[0043] In one embodiment, the dimming switch 205 is a group of dimming switches, the number of which is determined by the number of LED strings. Schematically, in the embodiment shown in Figure 3, the dimming switch 205 includes two dimming switches S2 and S3. Dimming switches S2 and S3 are respectively connected between the two parallel LED strings of the LED load 204 and the current bias circuit 206. Specifically, dimming switch S2 is connected between the first LED string and the first current terminal of the current bias circuit 206, and dimming switch S3 is connected between the second LED string and the second current terminal of the current bias circuit 206. Those skilled in the art will understand that in a dimming system, the number and arrangement of LED strings can vary depending on the application, and are not limited to the two parallel LED strings shown here. The dimming switch 205 is controlled by a dimming control signal PWM_dim generated by the dimming controller 203. The dimming control signal PWM_dim controls the conduction or cutoff of the dimming switch 205, thereby closing or opening the current flowing through the LED strings, thus achieving the purpose of LED dimming.

[0044] Furthermore, the dimming controller 203 generates the dimming control signal PWM_dim based on the LED dimming setpoint provided by the external dimming signal. In one embodiment, the dimming controller 203 may include a microcontroller unit (MCU), and the dimming control signal PWM_dim is a digital pulse width modulation signal with logic high and low levels.

[0045] Furthermore, the current biasing circuit 206 is used to provide current to multiple LED strings in the LED load 204. In one embodiment, the current biasing circuit 206 includes a bias current source Ib and a current mirror composed of transistors M1 to M3. Transistors M1 to M3 are, for example, N-type MOSFETs. The sources of transistors M1 to M3 are connected to a reference ground. One end of the bias current source Ib is connected to the power supply voltage, and the other end is connected to the drain and gate of transistor M1. The drain of transistor M2 serves as the first current terminal of the current biasing circuit 206 and is connected to the first LED string. The gate of transistor M2 is connected to the gate and drain of transistor M1. The drain of transistor M3 serves as the second current terminal of the current biasing circuit 206 and is connected to the second LED string. The gate of transistor M3 is connected to the gate and drain of transistor M1. Furthermore, the size ratio of transistors M1, M2, and M3 is 1:N:N, where N is an integer greater than 1. Therefore, the current biasing circuit 206 can provide a set current of N*Ib to the LED strings in the LED load 204.

[0046] In the embodiment shown in Figure 3, the control circuit 202 uses peak current mode to control the power conversion circuit 201, which includes a feedback circuit 210, an oscillator 211, a peak current detection circuit 212, a logic circuit 213, a driver 214, and an oscillator control circuit 215.

[0047] The feedback circuit 211 is used to sample the current flowing through the LED load 204 and generate a feedback signal Vfb. For example, the feedback circuit 211 compares and generates the minimum voltage of VDS of the current sink under each channel LED string, and uses this minimum voltage as the feedback signal Vfb.

[0048] Oscillator 211 is used to generate a clock signal CLK, which has multiple consecutive pulses, each pulse determining the on-time of the power switch T1 in each switching cycle. In this embodiment, the effective edges of adjacent pulses of the clock signal CLK define one switching cycle.

[0049] The peak current detection circuit 212 is used to detect the peak inductor current of the power conversion circuit 201 based on the feedback signal Vfb, the reference voltage Vref1, and the current detection signal Vs, to generate a peak current detection signal IPEAK. This peak current detection circuit IPEAK is used to determine the turn-off time of the power switch T1 in each switching cycle. In this embodiment, the peak current detection module 212 compares the feedback signal Vfb with the reference voltage Vref1 to generate an error amplification signal, and generates the peak current detection signal IPEAK when the current detection signal Vs reaches the error amplification signal. For example, the current detection signal Vs can be obtained through a sampling resistor Rs connected to the power switch T1.

[0050] Logic circuit 213 is used to implement the logic control function of the circuit. It receives the clock signal CLK, the peak current detection signal IPEAK, and the dimming control signal PWM_dim, and generates the drive control signal PWM_CTL to control the power switch T1 to turn on and off. In this embodiment, logic circuit 213 is implemented through an RS latch. Its set terminal receives the clock signal CLK, and its reset terminal receives the peak current detection signal IPEAK. When the pulse of the clock signal CLK arrives, the power switch T1 turns on, and the inductor current begins to rise. When the peak value of the inductor current reaches the error amplification signal, the power switch T1 turns off, and the inductor current begins to decrease.

[0051] The driver 214 is connected between the gate of the power switch T1 and the output of the logic circuit 213, and is used to drive the power switch T1 to turn on or off according to the drive control signal PWM_CTL generated by the logic circuit 213.

[0052] Oscillator control circuit 215 is used to receive feedback signal Vfb and dimming control signal PWM_dim, and control the oscillator 211 to be enabled or disabled according to feedback signal Vfb and dimming control signal PWM_dim. For example, oscillator control circuit 215 is used to compare feedback signal Vfb with reference voltage Vref2, and if feedback signal Vfb is less than reference voltage Vref2, provides synchronization control signal OSC_CTL to oscillator 211 according to the effective edge (e.g., rising edge) of dimming control signal PWM_dim. Oscillator 211 generates pulses of clock signal CLK according to synchronization control signal OSC_CTL, so that clock signal CLK is synchronized with the effective edge of dimming control signal PWM_dim, ultimately enabling power switch T1 and dimming switch 205 to be turned on synchronously, reducing circuit output ripple.

[0053] Figure 4 shows a circuit diagram of the peak current detection circuit according to an embodiment of the present invention. As shown in Figure 4, the peak current detection circuit 212 of this embodiment includes an error amplifier 2101, a switch S1, a capacitor C1, and a comparator 2102. The error amplifier 2101 has a non-inverting input terminal, an inverting input terminal, and an output terminal. Its non-inverting input terminal is used to receive the reference voltage Vref1, its inverting input terminal is used to receive the feedback signal Vfb, and its output terminal is used to output the error amplification signal Vea. The comparator 2102 has a non-inverting input terminal, an inverting input terminal, and an output terminal. Its non-inverting input terminal is used to receive the current detection signal Vs, its inverting input terminal is connected to the output terminal of the error amplifier 2101 via the switch S1, and its output terminal is used to provide the peak current detection signal IPEAK. The capacitor C1 is connected between the inverting input terminal of the comparator 2102 and the reference ground.

[0054] In this embodiment, error amplifier 2101 is used to adjust the peak current threshold of the inductor current. For example, error amplifier 2101 can compare the actual current of the LED load 204 (which can be represented by the feedback signal Vfb) with the desired LED current (which can be represented by the reference voltage Vref1). This desired LED current can be established by a fixed or adjustable reference voltage source (not shown). The output of error amplifier 2101 can be used to set the peak current threshold of the inductor current. Capacitor C1 can be used to maintain a voltage representing the peak current threshold level, and when the dimming control signal PWM_dim transitions to an inactive state (e.g., low level), switch S1 is turned off to disconnect capacitor C1 from the output of error amplifier 2101. Comparator 2102, acting as a peak current comparator, is used to compare the current detection signal Vs, representing the actual inductor current, with the error amplification signal Vea, representing the peak current threshold. When the effective level (e.g., high level) of the dimming control signal PWM_dim is long, the inductor current can increase to the peak current threshold, and then the power switch T1 is turned off by logic circuit 213, causing the inductor current to begin to decrease. If the effective level of the dimming control signal PWM_dim is still present at this time, the logic circuit 210 can turn on the power switch T1 again when it receives another clock pulse, and the inductor current will start to rise again, so that the switching cycle of inductor L1 can continue to repeat until the invalid edge (e.g., falling edge) of the dimming control signal PWM_dim arrives, at which point the power switch T1 is turned off simultaneously, thus avoiding the accumulation of excess energy on the output capacitor Cout. At the same time, since the voltage of the peak current threshold level is stored on capacitor C1, when the dimming control signal PWM_dim becomes effective again (e.g., high level), the power conversion circuit 201 can quickly establish the inductor current under steady-state operation.

[0055] Figure 5 shows a circuit diagram of the oscillator control circuit 215 according to an embodiment of the present invention. As shown in Figure 5, the oscillator control circuit 215 includes a comparator 2103, a single-sided delay unit 2104, an AND gate 2106, RS latches 2105 and 2107, and a minimum turn-on time module 2108.

[0056] The comparator 2103 has a non-inverting input, an inverting input, and an output. Its non-inverting input receives the reference voltage Vref2, its inverting input receives the feedback signal Vfb, and its output outputs the comparison signal V1. In this embodiment, the reference voltage Vref2 is greater than the reference voltage Vref1. In this embodiment, the comparator 2103 is a hysteresis comparator.

[0057] The single-sided delay unit 2104 is used to delay the invalid edge (e.g., falling edge) of the comparison signal V1 for a first time to obtain the delayed signal V2.

[0058] The set terminal of RS latch 2105 is connected to the dimming control signal PWM_dim, the reset terminal is connected to the clock signal CLK, and the output terminal is used to provide the trigger signal Ka.

[0059] One input of AND gate 2106 is connected to the delayed signal V2, and the other input is connected to the output of RS latch 2105. It is used to perform an AND logic operation on the trigger signal Ka and the delayed signal V2 to generate the trigger signal Kb.

[0060] The minimum on-time module 2108 receives the clock signal CLK and starts at the beginning of each cycle of the synchronization control signal OSC_CTL, generating a minimum on-time signal Tmin such that the effective level time of the synchronization control signal OSC_CTL is greater than or equal to the minimum on-time. In one embodiment, the start time of the synchronization control signal OSC_CTL is the rising edge of the synchronization control signal OSC_CTL. In other embodiments, if the synchronization control signal OSC_CTL is active low, the start time is the falling edge of the synchronization control signal OSC_CTL.

[0061] In this embodiment, the minimum turn-on time module 2108 is used to count the periods of the clock signal CLK at the start of the synchronization control signal OSC_CTL, and generate the minimum turn-on time signal Tmin after a preset time period. Therefore, the minimum turn-on time can be represented by the period count value of the clock signal CLK (i.e., the count value of the switching cycles) within the preset time period. In the embodiment shown in Figure 5, when the period count value of the clock signal CLK reaches a preset value M, the minimum turn-on time signal Tmin changes from logic low level to logic high level. Therefore, the minimum turn-on time in this embodiment is equal to M switching cycles, where M is an integer greater than 1.

[0062] Specifically, the minimum turn-on time module 2108 includes an OR gate 2109 and multiple M cascaded D flip-flops (DFFs). The data terminal and negative output terminal of each D flip-flop are shorted together. The reset terminal of each D flip-flop is used to receive the synchronization control signal OSC_CTL. The clock terminal of the first D flip-flop among the M D flip-flops is connected to the output terminal of the OR gate 2109. The clock terminals of the second to Mth D flip-flops among the M D flip-flops are connected to the negative output terminal of the preceding D flip-flop. The positive output terminal of the Mth D flip-flop among the multiple D flip-flops is used to provide the minimum turn-on time signal Tmin.

[0063] Taking M=2 as an example, one input of the OR gate 2109 is used to receive the clock signal CLK, and the other input is used to receive the minimum turn-on time signal. The data terminals and negative output terminals of D flip-flops DFF1 and DFF2 are shorted. The reset terminals of D flip-flops DFF1 and DFF2 are used to receive the synchronization control signal OSC_CTL. The clock terminal of D flip-flop DFF1 is connected to the output of the OR gate 2109, the clock terminal of D flip-flop DFF2 is connected to the negative output terminal of D flip-flop DFF1, and the positive output terminal of D flip-flop DFF2 is used to provide the minimum turn-on time signal Tmin.

[0064] RS latch 2107 is used to generate the synchronization control signal OSC_CTL based on the trigger signal Kb and the minimum on-time signal Tmin. In this embodiment, the set terminal of RS latch 2107 is connected to the trigger signal Kb, the reset terminal of RS latch 2107 is connected to the minimum on-time Tmin, and the output terminal is used to provide the synchronization control signal OSC_CTL.

[0065] In this embodiment, when the dimming switch is on for a long time, the feedback signal Vfb decreases due to the switch being on, resulting in a high output signal V1 from comparator 2103. Therefore, when the rising edge of the dimming control signal PWM_dim arrives, the output signal Kb of AND gate 2106 becomes high, causing the synchronization control signal OSC_CTL to change from low to high. When the dimming switch is on for a short time, the time for the LED load 204 to draw current from the output capacitor Cout in each dimming cycle becomes very short. Therefore, if the power conversion circuit 201 is turned on in each dimming cycle, the output voltage Vout will be significantly increased, resulting in increased output ripple. Therefore, in order to reduce output ripple, when the dimming switch is on for a short time, if the feedback signal Vfb is greater than the reference voltage Vref2, the output signal V1 of the comparator 2103 will remain at a low level. In this case, when the rising edge of the dimming control signal PWM_dim arrives, the output of the RS latch 2107 will still not become high, so that the power conversion circuit 201 will not be turned on in some dimming cycles until the feedback signal Vfb is less than the reference voltage Vref2. Only then will the RS latch 2107 turn the synchronization control signal OSC_CTL high when the rising edge of the dimming control signal PWM_dim arrives.

[0066] Figure 6 shows a circuit diagram of the oscillator 211 according to an embodiment of the present invention. As shown in Figure 6, the oscillator 211 of this embodiment includes a ramp generation module 2112, a comparator 2113, an RS latch 2114, an AND gate 2115, a single pulse module 2116, and an inverter 2117.

[0067] The ramp generation module 2112 is used to generate a ramp signal RAMP. In one embodiment, the ramp signal RAMP is a triangular wave signal. Specifically, the ramp generation module 2112 includes a current source Is, a capacitor Cs, and a transistor Ms. The current source Is and the capacitor Cs are connected in series between the power supply voltage VDD and a reference ground. The first terminal of the transistor Ms is connected to the intermediate node between the current source Is and the capacitor Cs, and the second terminal of the transistor Ms is connected to the reference ground. The transistor Ms generates the ramp signal RAMP at the intermediate node between the two by controlling the charging and discharging process of the capacitor Cs by the current source Is. For example, the transistor Ms can be an N-type MOSFET.

[0068] Comparator 2113 compares the ramp signal RAMP with the reference voltage Vbg to generate a comparison signal V3. In one embodiment, comparator 2113 is a hysteresis comparator. The set terminal of RS latch 2114 is connected to the comparison signal V3, and the reset terminal is connected to the clock signal CLK via inverter 2117 to receive the inverted signal of the clock signal CLK. The output terminal is used to provide a trigger signal Kd. AND gate 2115 performs an AND logic operation between the trigger signal Kd and the synchronization control signal OSC_CTL. The single-pulse module 2116 is connected to the output terminal of AND gate 2115 and is used to generate the clock signal CLK based on the output of AND gate 2115.

[0069] In this embodiment, when the synchronization control signal OSC_CTL is low, the output of AND gate 2115 is low, so transistor Ms is turned off, current source Is charges capacitor Cs, and ramp signal RAMP gradually rises. When ramp signal RAMP is greater than reference voltage Vbg, comparison signal V3 flips to high, so the output signal Kd of RS latch 2114 flips to high. Therefore, when the synchronization control signal OSC_CTL flips to high, the output of AND gate 2115 immediately becomes high, and then the pulse of clock signal CLK is generated by single pulse module 2116 to control the inductor current of power conversion circuit 201 to rise.

[0070] Figure 7 shows a waveform diagram of the LED dimming system according to an embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time. The waveform shown in Figure 7 illustrates a conceptual example of the dimming control signal PWM_dim, the synchronization control signal OSC_CTL, the clock signal, and the inductor current. The principle of the LED dimming system according to an embodiment of the present invention will be explained below with reference to Figures 3 to 7.

[0071] For a longer dimming switch on-time (e.g., time period t0-t1 in Figure 7), in one embodiment, the dimming switch on-time is greater than the minimum on-time set by the minimum on-time module 2108 (e.g., 2 switching cycles). When the rising edge of the dimming control signal PWM_dim arrives, the output Ka of RS latch 2105 goes high. Simultaneously, due to the dimming switch being on, the feedback signal Vfb decreases, thus the output signal V1 of comparator 2103 also goes high (at this time, the comparator output toggles on the rising edge without delay). Therefore, the output signal Kb of AND gate 2106 goes high, causing the synchronization control signal OSC_CTL to change from low to high. Thus, the rising edge of the synchronization control signal OSC_CTL is synchronized with the rising edge of the dimming control signal PWM_dim. After the synchronization control signal OSC_CTL goes high, the control oscillator 211 generates a pulse of the clock signal CLK, causing the inductor current to gradually increase, preventing a drop in the output voltage Vout. Since the reference voltage Vref2 is greater than the reference voltage Vref1, when the dimming control signal PWM_dim is high, the feedback signal Vfb is adjusted by the error amplifier 2101 to be equal to the reference voltage Vref1. Therefore, the output V1 of the comparator 2103 is always high, which allows the synchronization control signal OSC_CTL to also remain high, and the oscillator 211 continuously outputs continuous pulses.

[0072] Furthermore, since the high-level time of the dimming control signal PWM_dim is longer than the minimum on time, when the falling edge of the dimming control signal PWM_dim arrives, the minimum on signal Tmin has already become high. Simultaneously, the opening of the dimming switch causes the feedback signal Vfb to go high. However, due to the presence of the single-sided delay unit 2104, the falling edge of signal V2 is delayed relative to signal V1 for a certain period. Therefore, the synchronization control signal OSC_CTL remains high at this time. Only when the next pulse of the clock signal CLK arrives and pulls the trigger signal Ka low will the output Kb of the AND gate 2106 become low. At this time, the set input of the RS latch 2107 is low ("0") and the reset input is high ("1"), thus the synchronization control signal OSC_CTL becomes low. Therefore, in this embodiment, the invalid edge (e.g., falling edge) of the synchronization control signal OSC_CTL is delayed by a first time relative to the invalid edge of the dimming control signal PWM_dim. In one embodiment, the first time is equal to one switching cycle, so that after the dimming control signal PWM_dim flips to a low level, the synchronization control signal OSC_CTL will not immediately flip to a low level, but will only flip to a low level after the clock signal CLK pulses for at least one more cycle. This allows the power conversion circuit 201 to replenish the output capacitor Cout with additional charge, ensuring that the voltage on the output capacitor Cout is sufficient when the dimming control signal PWM_dim flips high again.

[0073] For shorter dimming switch on-times (e.g., time period t2-t3 in Figure 7), in one embodiment, the dimming switch on-time is less than the minimum on-time set by the minimum on-time module 2108, for example, the dimming switch on-time is less than one switching cycle. The rising edge process of the dimming control signal PWM_dim is the same as described above and will not be repeated here. The only difference is that when the falling edge of the dimming control signal PWM_dim arrives, since the count value of the minimum on-time module 2108 has not reached the cycle count value corresponding to the minimum on-time, the minimum on-time signal Tmin is low. Consequently, the set and reset terminals of the RS latch 2107 are both low ("0"), and the output of the RS latch 2107 remains high ("1"). Only when the count value of the minimum on-time module 2108 reaches the set value, and the minimum on-time signal Tmin becomes high, will the synchronization control signal OSC_CTL become low. This setting ensures that the effective level of the synchronization control signal OSC_CTL is always greater than the minimum turn-on time, guaranteeing that the power conversion circuit 201 can operate for at least two switching cycles each time it is turned on. This ensures that the power conversion circuit 201 can provide enough charge to the output capacitor Cout to meet the charge required by the LED load during the dimming cycle.

[0074] Figure 8 shows the simulated waveforms of the LED dimming system according to an embodiment of the present invention when the dimming switch changes from a longer on-time to a shorter on-time. Figure 8 shows the simulated waveforms of the dimming control signal PWM_dim, inductor current IL, LED current ILED, and output voltage Vout. As shown in Figure 8, when the dimming switch suddenly switches from a longer on-time to a shorter on-time, the time for the LED load to draw current from the output capacitor Cout in each dimming cycle becomes very short. Therefore, if the power conversion circuit 201 is turned on in every dimming cycle, the output voltage Vout will be significantly increased. Therefore, in order to reduce output ripple, the LED dimming system of this embodiment of the present invention does not turn on the power conversion circuit 201 in every dimming cycle, but adaptively skips some dimming cycles, thereby achieving a balance between the charge drawn by the LED load on the output capacitor and the charge replenished by the power conversion circuit. This not only reduces the output voltage ripple but also achieves a higher dimming ratio. Furthermore, when the oscillator control circuit detects that it needs to replenish the output capacitor with charge, the LED dimming system of this embodiment can control the power conversion circuit to turn on without delay when the rising edge of the dimming control signal PWM_dim arrives, so as to start building up the inductor current and replenishing the output capacitor with charge.

[0075] Furthermore, as the LED dimming system transitions from a longer dimming switch on-time to a shorter dimming switch on-time, it undergoes a longer adjustment period. During this process, the output of the error amplifier in the control circuit 202 gradually decreases, thereby gradually reducing the peak value of the inductor current. Ultimately, this stabilizes the output of the error amplifier at a suitable value, ensuring that the charge provided to the output capacitor by the power conversion circuit each time it is turned on is equal to the charge consumed by the LED load during the dimming cycle. This allows the circuit's output voltage to be maintained within a reasonable range, achieving a smaller output voltage ripple.

[0076] This invention provides an LED dimming system and its control circuit based on a peak current mode control architecture. The control circuit uses an oscillator control circuit to control the clock signal to turn on and off according to the feedback signal of the output voltage of the power conversion circuit and the dimming control signal. This allows the power conversion circuit to turn on synchronously with the rising edge of the dimming control signal, thereby avoiding the problem of output voltage drop when the dimming switch is turned on and reducing the output ripple of the circuit.

[0077] The oscillator control circuit of the present invention also includes a minimum turn-on time module, which ensures the minimum turn-on time of the power conversion circuit each time. This allows the power conversion circuit to provide sufficient charge to the output capacitor when the dimming switch is on for a short time, so that the turn-on time of the dimming switch is no longer limited by the switching cycle of the power conversion circuit, which can significantly improve the dimming ratio of the circuit.

[0078] Furthermore, the LED dimming system of this embodiment can adaptively skip some dimming cycles when the dimming switch is on for a short time, so that the power conversion circuit will not be turned on in every dimming cycle. This avoids the problem of the output voltage being raised due to the dimming cycle being too short, thereby achieving a balance between the charge drawn from the LED load on the output capacitor and the charge replenished by the power conversion circuit, which can effectively reduce the output ripple of the circuit under high dimming ratio.

[0079] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A control circuit for an LED dimming system, wherein, The LED dimming system includes a power switch and a dimming switch. The switching of the dimming switch on and off is controlled by a dimming control signal. The control circuit includes: Feedback circuit, used to generate a feedback signal based on the current flowing through the LED load; An oscillator for generating a clock signal, the clock signal comprising a plurality of continuous pulses; Logic circuitry for controlling the conduction of the power switch according to the clock signal, wherein the effective edges of adjacent pulses define a switching cycle; and An oscillator control circuit is used to receive the feedback signal and the dimming control signal, and when the feedback signal is less than the second reference voltage, to provide a synchronization control signal to the oscillator according to the effective edge of the dimming control signal. The oscillator generates a pulse of the clock signal according to the synchronization control signal to realize the synchronous opening of the load switch and the dimming switch.

2. The control circuit according to claim 1, wherein, When the feedback signal is less than the second reference voltage, the effective edge of the synchronization control signal is synchronized with the effective edge of the dimming control signal, and the invalid edge of the synchronization control signal is delayed by a first time relative to the invalid edge of the dimming control signal.

3. The control circuit according to claim 2, wherein, The first time is equal to one switching cycle.

4. The control circuit according to claim 2, wherein, The effective level time of the synchronization control signal is greater than or equal to the minimum turn-on time, wherein the minimum turn-on time is equal to M switching cycles, and M is an integer greater than 1.

5. The control circuit according to claim 1, wherein, Also includes: A peak current detection module is used to compare the feedback signal with a first reference voltage to generate an error amplification signal, and to generate a peak current detection signal when the current detection signal representing the inductor current of the LED dimming system reaches the error amplification signal. The logic circuit is used to control the power switch to turn off in each switching cycle based on the peak current detection signal.

6. The control circuit according to claim 5, wherein, The second reference voltage is greater than the first reference voltage.

7. The control circuit according to claim 4, wherein, The oscillator control circuit includes: The first RS latch has a set terminal for receiving the dimming control signal, a reset terminal for receiving the clock signal, and an output terminal for generating a first trigger signal. The first comparator has a non-inverting input terminal for receiving the second reference voltage, an inverting input terminal for receiving the feedback signal, and an output terminal for generating a first comparison signal. A single-sided delay unit is used to delay the invalid edge of the first comparison signal by a second time to obtain a delayed signal, wherein the second time is greater than the first time; The first AND gate is used to perform an AND logic operation on the first trigger signal and the delayed signal to generate the second trigger signal; A minimum start time module is used to count the period of the clock signal at the start time of the synchronization control signal and generate the minimum start time signal after a preset time period, wherein the period count value of the clock signal within the preset time period represents the minimum start time; and The second RS latch has a set terminal for receiving the second trigger signal, a reset terminal for receiving the minimum turn-on time signal, and an output terminal for providing the synchronization control signal.

8. The control circuit according to claim 7, wherein, The minimum start time module includes: An OR gate, with its first input terminal for receiving the clock signal and its second input terminal for receiving the minimum on-time signal; and M cascaded D flip-flops, with the data terminal and negative output terminal of each D flip-flop shorted together, and the reset terminal of each D flip-flop used to receive the synchronization control signal. The clock terminal of the first D flip-flop among the M D flip-flops is connected to the output terminal of the OR gate, and the clock terminals of the second to Mth D flip-flops among the M D flip-flops are connected to the negative output terminal of the preceding D flip-flop. The positive output terminal of the Mth D flip-flop among the plurality of D flip-flops is used to provide the minimum turn-on time signal.

9. The control circuit according to claim 1, wherein, The oscillator includes: The ramp generation module is used to generate ramp signals; A second comparator is used to compare the ramp signal with a reference voltage to generate a second comparison signal; The third RS latch has a set terminal for receiving the second comparison signal, a reset terminal for receiving the inverted signal of the clock signal, and an output terminal for providing the third trigger signal. A second AND gate is used to perform an AND logic operation between the third trigger signal and the synchronization control signal; and A single-pulse module is used to generate the clock signal based on the output of the second AND gate.

10. The control circuit according to claim 9, wherein, The ramp generation module includes: A first current source and a first capacitor connected in series between the power supply voltage and ground; and The first transistor has a first terminal connected to the midpoint between the first current source and the first capacitor, a second terminal connected to ground, and a control terminal connected to the output of the second AND gate. The first transistor generates the ramp signal at the intermediate node between the first capacitor and the first current source by controlling the charging and discharging process of the first capacitor.

11. The control circuit according to claim 5, wherein, The peak current detection module includes: An error amplifier has an inverting input for receiving the feedback signal, a non-inverting input for receiving a first reference voltage, and an output for generating an amplified error signal; and The third comparator has an inverting input for receiving the error amplification signal, a non-inverting input for receiving the current detection signal, and an output for generating the peak current detection signal, wherein the current detection signal is obtained through a sampling resistor connected to the power switch.

12. The control circuit according to claim 11, wherein, The peak current detection module also includes: A first switch connected between the output of the error amplifier and the inverting input of the first comparator, wherein the dimming control signal is used to control the on and off switching of the first switch; and The second capacitor is connected between the inverting input of the third comparator and ground.

13. The control circuit according to claim 5, wherein, The logic circuit includes: The fourth RS latch has a set terminal for receiving the clock signal, a reset terminal for receiving the peak current detection signal, and an output terminal for generating a drive control signal, wherein the drive control signal is used to control the on and off switching of the power switch.

14. An LED dimming system, comprising: A power conversion circuit includes at least one power switch, the power conversion circuit being used to provide an output voltage to an LED load according to an input voltage; A dimming switch is used to connect in series with the LED load; A dimming controller is used to generate a dimming control signal based on an external dimming signal, the dimming control signal being used to control the dimming switch to be turned on and off; as well as The control circuit according to any one of claims 1-13, wherein the control circuit is used to generate a drive control signal, the drive control signal being used to control the on and off of the at least one power switch.

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