Display panel and display device

Abstract

A display panel and a display device. The display panel comprises: a substrate (110); a driving transistor (Tdr) and a first capacitor (C1); an active layer (120), arranged on the substrate (110), wherein the active layer (120) comprises a first active region (121), and a channel region of the driving transistor (Tdr) is located in the first active region (121); a first conductive layer (M1), arranged on the side of the active layer (120) away from the substrate (110), wherein the first conductive layer (M1) comprises a first electrode plate (C11) of the first capacitor (C1) and a first scanning signal line (S1) extending in a first direction X, the first scanning signal line (S1) is located on one side of the first electrode plate (C11) of the first capacitor (C1), and the orthographic projection of the first electrode plate (C11) of the first capacitor (C1) on the substrate (110) at least partially covers the orthographic projection of the channel region of the driving transistor (Tdr) on the substrate (110); and a second conductive layer (M2), arranged on the side of the first conductive layer (M1) away from the substrate (110), wherein the second conductive layer (M2) comprises a first conductive portion (M21), the first conductive portion (M21) is connected to the first electrode plate (C11) of the first capacitor (C1), and the orthographic projection of the first conductive portion (M21) on the substrate (110) overlaps with the orthographic projection of the first scanning signal line (S1) on the substrate (110).

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411910059.4, filed with the Chinese Patent Office on December 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel and a display device. Background Technology

[0003] The display panel can use low-temperature polycrystalline silicon and oxide (LTPO) circuits to drive the light-emitting devices, which can improve the flickering phenomenon caused by leakage current at low refresh rates. Summary of the Invention

[0004] This application provides a display panel and a display device, which enable the display panel to balance manufacturing cost and display effect at low refresh rates.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] Substrate;

[0007] Drive transistor and first capacitor;

[0008] An active layer is disposed on one side of the substrate, the active layer includes a first active region, and the channel region of the driving transistor is located in the first active region;

[0009] A first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes a first electrode of the first capacitor and a first scan signal line extending along a first direction. The first scan signal line is located on a first side of the first electrode of the first capacitor. The orthographic projection of the first electrode of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

[0010] A second conductive layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer includes a first conductive portion, which is connected to the first plate of the first capacitor. The orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate.

[0011] Secondly, embodiments of this application also provide a display device, including the display panel described in the first aspect. Attached Figure Description

[0012] Figure 1 is a partial structural schematic diagram of a display panel provided in an embodiment of this application;

[0013] Figure 2 is a schematic diagram of an active layer structure provided in an embodiment of this application;

[0014] Figure 3 is a schematic diagram of the structure of a first conductive layer provided in an embodiment of this application;

[0015] Figure 4 is a schematic diagram of the structure of a second conductive layer provided in an embodiment of this application;

[0016] Figure 5 is a schematic diagram of the structure of a third conductive layer provided in an embodiment of this application;

[0017] Figure 6 is a schematic diagram of a combination of an active layer and a first conductive layer provided in an embodiment of this application;

[0018] Figure 7 is a schematic diagram of a combination of an active layer, a first conductive layer and a third conductive layer provided in an embodiment of this application;

[0019] Figure 8 is a schematic diagram of a combination of an active layer, a first conductive layer, a second conductive layer and a third conductive layer provided in an embodiment of this application;

[0020] Figure 9 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0021] Figure 10 is a schematic diagram of the cross-sectional structure of the display panel provided in the embodiment of this application, obtained by taking a section along the first direction at the first via.

[0022] Figure 11 is a schematic diagram of the cross-sectional structure of a display panel obtained by taking a section along the first direction at the third via hole according to an embodiment of this application.

[0023] Figure 12 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0024] Figure 13 is a schematic diagram of the cross-sectional structure of a display panel provided in this application, obtained by cross-sectioning the fourth and fifth vias along the first direction.

[0025] Figure 14 is a schematic cross-sectional view of a display panel obtained by taking a cross-section of the third conductive part along the extension direction according to an embodiment of this application.

[0026] Figure 15 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0027] Figure 16 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0028] Figure 17 is a schematic diagram of a fourth conductive layer and an anode structure provided in an embodiment of this application;

[0029] Figure 18 is a schematic diagram of the cross-sectional structure of a display panel provided in this application, obtained by cross-sectioning the eighth and ninth vias along the first direction.

[0030] Figure 19 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0031] Figure 20 is a schematic diagram of the cross-sectional structure of a display panel obtained by taking a section along the second direction at the tenth through hole according to an embodiment of this application.

[0032] Figure 21 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0033] Figure 22 is a schematic cross-sectional view of a display panel provided in an embodiment of this application, showing the cross-section of the fourth conductive part along the extension direction.

[0034] Figure 23 is a schematic cross-sectional view of a display panel provided in an embodiment of this application, showing the cross-section of the fifth conductive part along the extension direction.

[0035] Figure 24 is a schematic diagram of the cross-sectional structure of a display panel obtained by cutting along AA' according to an embodiment of this application;

[0036] Figure 25 is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0037] Figure 26 is a timing waveform diagram of a scanning signal provided in an embodiment of this application;

[0038] Figure 27 is a schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of this application, obtained by cross-sectioning along the first direction at the nineteenth via.

[0039] Figure 28 is a schematic cross-sectional view of a display panel provided in an embodiment of this application, obtained by taking a cross-section along the second direction at the 20th and 21st vias.

[0040] Figure 29 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0041] The present application will now be described in detail with reference to the accompanying drawings and embodiments. The specific embodiments described herein are merely illustrative of the present application. For ease of description, only the parts relevant to the present application are shown in the drawings, not the entire structure.

[0042] Figure 1 is a partial structural schematic diagram of a display panel provided in an embodiment of this application; Figure 2 is a structural schematic diagram of an active layer provided in an embodiment of this application; Figure 3 is a structural schematic diagram of a first conductive layer provided in an embodiment of this application; Figure 4 is a structural schematic diagram of a second conductive layer provided in an embodiment of this application; Figure 5 is a structural schematic diagram of a third conductive layer provided in an embodiment of this application; Figure 6 is a structural schematic diagram of a combination of an active layer and a first conductive layer provided in an embodiment of this application; Figure 7 is a structural schematic diagram of a combination of an active layer, a first conductive layer, and a third conductive layer provided in an embodiment of this application; Figure 8 is a structural schematic diagram of a combination of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer provided in an embodiment of this application; and Figure 9 is a structural schematic diagram of a pixel circuit provided in an embodiment of this application. As shown in Figures 1 to 9, the display panel includes:

[0043] Substrate 110;

[0044] Drive transistor Tdr and first capacitor C1;

[0045] An active layer 120 is disposed on one side of the substrate 110. The active layer 120 includes a first active region 121, and the channel region of the driving transistor Tdr is located in the first active region 121.

[0046] A first conductive layer M1 is disposed on the side of the active layer 120 away from the substrate 110. The first conductive layer M1 includes a first electrode C11 of a first capacitor C1 and a first scan signal line S1 extending along a first direction X. The first scan signal line S1 is located on a first side of the first electrode C11 of the first capacitor C1. The orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110 at least partially covers the orthographic projection of the channel region of the driving transistor Tdr on the substrate 110.

[0047] The second conductive layer M2 is disposed on the side of the first conductive layer M1 away from the substrate 110. The second conductive layer M2 includes a first conductive part M21, which is connected to the first electrode C11 of the first capacitor C1. The orthographic projection of the first conductive part M21 on the substrate 110 overlaps with the orthographic projection of the first scan signal line S1 on the substrate 110.

[0048] In some embodiments, the display panel includes a pixel circuit for driving a light-emitting device to emit light. As shown in FIG9, the pixel circuit may include a driving transistor Tdr, a first capacitor C1, and ten switching transistors, namely the first transistor T1 to the tenth transistor T10. Both the driving transistor Tdr and the switching transistors can be P-type transistors. The first conductive layer M1 and the second conductive layer M2 can be metal layers for forming the devices in the pixel circuit and the interconnections between the devices. In the manufacturing process of the display panel, the need for additional photomasks can be avoided, reducing the manufacturing cost of the display panel. Exemplarily, both the driving transistor Tdr and the switching transistors can be low-temperature polysilicon (LTPS) transistors. The switching transistors are used to write a data voltage into the gate of the driving transistor Tdr and, during the light-emitting stage, write a positive power supply signal provided by the first power supply line VDD1 into the first terminal of the driving transistor Tdr, so that the driving transistor Tdr forms a driving current according to the positive power supply signal and the data voltage, and transmits it to the anode of the light-emitting device through the switching transistors. The cathode of the light-emitting device is connected to another power supply line VSS, driving the light-emitting device to emit light.

[0049] The first scan signal provided by the first scan signal line S1 can be a light emission inverse control signal, meaning the first scan signal and the light emission control signal have opposite levels but the same timing. The orthographic projection of the first conductive part M21 on the substrate 110 overlaps with the orthographic projection of the first scan signal line S1 on the substrate 110, resulting in a parasitic capacitance between the first conductive part M21 and the first scan signal line S1. One plate of this parasitic capacitance is equivalent to being connected to the first scan signal line S1. During the light emission stage of the pixel circuit, the light emission control signal transitions from a high level to a low level, controlling the switching transistor to conduct and form a current path. At this time, the first scan signal transitions from a low level to a high level. The parasitic capacitance between the first conductive part M21 and the first scan signal line S1 can increase the potential of the first conductive part M21 through coupling, i.e., increase the gate potential of the driving transistor Tdr. This reduces the degree of gate potential increase of the driving transistor Tdr due to leakage during the light emission stage, improves the brightness reduction phenomenon caused by the gate potential change of the driving transistor Tdr during the light emission process, reduces the flicker phenomenon of the display panel, and improves the display effect of the display panel. For example, the capacitance value of the parasitic capacitance between the first conductive part M21 and the first scan signal line S1 can be in the range of 2.2f-3.0f. Optionally, the capacitance value of the parasitic capacitance between the first conductive part M21 and the first scan signal line S1 can be 2.6f.

[0050] In this embodiment, the orthographic projection of the first conductive part on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate, creating a parasitic capacitance between the first conductive part and the first scan signal line. During the light-emitting phase, when the light-emitting reverse control signal transitions from a low level to a high level, the parasitic capacitance between the first conductive part and the first scan signal line can increase the gate potential of the driving transistor through coupling. This reduces the degree of gate potential increase in the driving transistor due to leakage during the light-emitting phase, improves the brightness reduction caused by changes in the gate potential of the driving transistor during light emission, reduces flickering in the display panel, and enhances the display effect.

[0051] Referring again to Figures 1 to 8, the first scan signal line S1 is located on one side of the first plate C11 of the first capacitor C1 along the second direction Y, where the first direction X intersects the second direction Y.

[0052] In some embodiments, the first scan signal line S1 is located on one side of the first plate C11 of the first capacitor C1 along the second direction Y, so as to avoid the first scan signal line S1 overlapping with the first plate C11 of the first capacitor C1 when it extends in the first direction X, thus avoiding a short circuit.

[0053] Referring again to Figures 1 to 8, the channel region of the driving transistor Tdr is located at the orthogonal projection position Tr of the first plate C11 of the first capacitor C1 in the first active region 121, and the first plate C11 of the first capacitor C1 is multiplexed as the gate of the driving transistor Tdr.

[0054] In some embodiments, as shown in FIG1, the first plate C11 of the first capacitor C1 overlaps with the first active region 121 to form a driving transistor Tdr, so that the first plate C11 of the first capacitor C1 reuses the gate of the driving transistor Tdr, which can improve the space utilization of the display panel and is beneficial to improving the pixel density of the display panel.

[0055] Referring again to Figures 1 to 8, the display panel also includes a third conductive layer M3, which is located between the first conductive layer M1 and the second conductive layer M2. The third conductive layer M3 includes a first power supply trace VDD1 and a second electrode C12 of the first capacitor C1. The first power supply trace VDD1 and the second electrode C12 of the first capacitor C1 are connected and integrally formed.

[0056] In some embodiments, as shown in FIG1, the third conductive layer M3 can be a metal layer. An insulating layer is provided between the first conductive layer M1 and the third conductive layer M3 to prevent short circuit between the first conductive layer M1 and the third conductive layer M3. The orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate 110 overlaps with the orthographic projection of the first plate C11 onto the substrate 110, such that the first plate C11, the second plate C12, and the insulating layer between them form the first capacitor C1. The first power supply line VDD1 is used to provide a fixed potential signal, and the second plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, so that the potential of the second plate C12 of the first capacitor C1 is fixed. At the same time, the first plate C11 of the first capacitor C1 serves as the gate of the driving transistor Tdr, so that the first capacitor C1 can store the gate potential of the driving transistor Tdr, ensuring the light emission stability of the display panel during the light emission stage of the pixel circuit. Exemplarily, the capacitance value of the first capacitor C1 can be in the range of 50f-54f, and optionally, the capacitance value of the first capacitor C1 is 52f. The fixed potential signal provided by the first power supply trace VDD1 can be the positive power supply signal for the pixel circuit, ensuring the potential stability of the second plate C12 of the first capacitor C1. For example, the positive power supply signal can be +7V. The first power supply trace VDD1 and the second plate C12 of the first capacitor C1 are connected and integrally formed, which simplifies the manufacturing process of the display panel while meeting the connection requirements of the pixel circuit.

[0057] Referring again to Figures 1 and 8, the first power supply trace VDD1 extends along the first direction X.

[0058] In some embodiments, the first power trace VDD1 extends along the first direction X, which can connect the second plates C12 of the first capacitor C1 in different pixel circuits, so that the second plates C12 of the first capacitor C1 in different pixel circuits are part of the first power trace VDD1. A continuous first power trace VDD1 is formed on the third conductive layer M3 along the first direction X, which is used to provide a first power signal to different pixel circuits. This is beneficial to achieve the consistency of the first power signal, thereby improving the brightness consistency of the display panel.

[0059] Figure 10 is a cross-sectional view of the display panel provided in the embodiment of this application, obtained by taking a section along a first direction at the first via. As shown in Figures 1, 4 and 10, the second electrode plate C12 of the first capacitor C1 is provided with a first via DL1, and the first conductive part M21 passes through the first via DL1 and is connected to the first electrode plate C11 of the first capacitor C1.

[0060] In some embodiments, the first conductive part M21 is disposed on the side of the second electrode plate C12 away from the first electrode plate C11. By providing a first via DL1 on the second electrode plate C12 of the first capacitor C1, the first conductive part M21 can be connected to the first electrode plate C11 of the first capacitor C1 through the first via DL1, avoiding short circuit between the first conductive part M21 and the second electrode plate C12 of the first capacitor C1, and ensuring the reliability of the pixel circuit.

[0061] Referring again to Figures 1 and 10, a first insulating layer P1 is disposed between the first conductive layer M1 and the second conductive layer M2. A second via DL2 is disposed on the first insulating layer P1. The orthographic projection of the second via DL2 on the substrate 110 is located within the orthographic projection of the first via DL1 on the substrate 110. The orthographic projection of the second via DL2 on the substrate 110 overlaps with the orthographic projection of the first conductive part M21 on the substrate 110 and the orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110. The first conductive part M21 is connected to the first electrode C11 of the first capacitor C1 through the second via DL2.

[0062] In some embodiments, the first insulating layer P1 may include two insulating layers: a first interlayer insulating layer P11 and a second interlayer insulating layer P12. The first interlayer insulating layer P11 is disposed between the first conductive layer M1 and the third conductive layer M3, and the second interlayer insulating layer P12 is disposed between the third conductive layer M3 and the second conductive layer M2. The second via DL2 penetrates the first insulating layer P1, and its orthographic projection on the substrate 110 overlaps with the orthographic projections of the first conductive portion M21 and the first electrode C11 of the first capacitor C1 on the substrate 110, respectively, so that the first conductive portion M21 can be connected to the first electrode C11 of the first capacitor C1 through the second via DL2. Exemplarily, during the fabrication of the display panel, when forming the first conductive portion M21, the first conductive portion M21 can extend to the first electrode C11 of the first capacitor C1 through the second via DL2, so that the first conductive portion M21 and the first electrode C11 of the first capacitor C1 are in contact and connected. Meanwhile, the orthogonal projection of the second via DL2 on the substrate 110 is located within the orthogonal projection of the first via DL1 on the substrate 110. When the first conductive part M21 passes through the second via DL2, it avoids short circuit between the first conductive part M21 and the second plate C12 of the first capacitor C1, thus ensuring the reliability of the pixel circuit.

[0063] Referring again to Figure 1, the orthographic projection of the first plate C11 of the first capacitor C1 onto the substrate 110 lies within the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate 110.

[0064] In some embodiments, the area of ​​the second plate C12 of the first capacitor C1 is larger than the area of ​​the first plate C11 of the first capacitor C1, and the second plate C12 of the first capacitor C1 completely covers the first plate C11 of the first capacitor C1. This allows the capacitance value of the first capacitor C1 to be increased as much as possible when the area of ​​the first plate C11 of the first capacitor C1 is preset and fixed, thereby further improving the flickering phenomenon of the display panel and enhancing the display effect of the display panel.

[0065] Referring again to Figure 1, the orthographic projection of the first via DL1 on the substrate 110 is located within the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 110.

[0066] In some embodiments, the orthographic projection of the first via DL1 on the substrate 110 is located within the orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110. This ensures that the first conductive part M21 contacts the first electrode C11 of the first capacitor C1 when it passes through the first via DL1, thereby connecting the first conductive part M21 to the first electrode C11 of the first capacitor C1. This avoids the need for additional connection lines and simplifies the wiring layout of the display panel.

[0067] Referring again to Figures 1 to 8, the display panel also includes a first transistor T1, the channel region of which is located at the first orthographic projection position 1211 of the first scan signal line S1 in the first active region 121.

[0068] In some embodiments, the channel region of the first transistor T1 is located at the first orthographic projection position 1211 of the first scan signal line S1 in the first active region 121, such that the gate of the first transistor T1 is connected to the first scan signal line S1. During the light-emitting phase of the pixel circuit, the first scan signal line S1 transitions from a low level to a high level, and the first transistor T1 is turned off. The first terminal of the first transistor T1 is connected to the gate of the driving transistor Tdr, thereby preventing leakage of the gate potential of the driving transistor Tdr through the first transistor T1 during the light-emitting phase, improving the stability of the gate potential of the driving transistor Tdr, and thus improving the flicker phenomenon of the display panel.

[0069] Referring again to Figure 1, the first end of the first conductive part M21 is connected to the first plate C11 of the first capacitor C1, and the second end of the first conductive part M21 is connected to the first electrode of the first transistor T1 through the first active region 121.

[0070] In some embodiments, as shown in FIG1, the first end of the first conductive part M21 is connected to the first electrode C11 of the first capacitor C1 through the first via DL1 and the second via DL2, and the second end of the first conductive part M21 is connected to the first electrode of the first transistor T1 through the first active region 121. Thus, the first conductive part M21 can be provided on the second conductive layer M2, realizing the connection between the first electrode C11 of the first capacitor C1 and the first electrode of the first transistor T1, reducing the circuit layout of the first conductive layer M1 and the third conductive layer M3, and simplifying the manufacturing process of the display panel.

[0071] Figure 11 is a schematic cross-sectional view of a display panel provided in this application, obtained by cross-sectioning along a first direction at the third via. As shown in Figures 1 and 11, a second insulating layer P2 is provided between the first conductive layer M1 and the active layer 120. A third via DL3 is provided on the first insulating layer P1 and the second insulating layer P2. The third via DL3 penetrates the first insulating layer P1 and the second insulating layer P2. The orthographic projection of the third via DL3 on the substrate 110 overlaps with the orthographic projection of the first conductive part M21 on the substrate 110 and the orthographic projection of the first active region 121 on the substrate 110, respectively. The first conductive part M21 is connected to the first active region 121 through the third via DL3.

[0072] In some embodiments, as shown in FIG1, the third via DL3 penetrates the first insulating layer P1 and the second insulating layer P2, so that there is a through hole between the second conductive layer M2 and the active layer 120 at the location of the third via DL3. Simultaneously, the orthographic projection of the third via DL3 on the substrate 110 overlaps with the orthographic projections of the first conductive portion M21 and the first active region 121 on the substrate 110, respectively. During the fabrication of the display panel, the first conductive portion M21 extends to the surface of the first active region 121 through the third via DL3, realizing the connection between the first conductive portion M21 and the first active region 121. Furthermore, the active layer 120 between the overlapping position of the third via DL3 and the first active region 121 and the channel region of the first transistor T1 can be a heavily doped semiconductor material, which can serve as a wire connecting the first conductive portion M21 at the third via DL3 to the first electrode of the first transistor T1, realizing the connection between the second end of the first conductive portion M21 and the first electrode of the first transistor T1.

[0073] Referring again to Figures 1 to 8, the display panel also includes a second transistor T2, the channel region of which is located at the second orthographic projection position 1212 of the first scan signal line S1 in the first active region 121.

[0074] In some embodiments, the channel region of the second transistor T2 is located at the second orthographic projection position 1212 of the first scan signal line S1 in the first active region 121, such that the gate of the second transistor T2 is connected to the first scan signal line S1. During the light-emitting phase of the pixel circuit, the first scan signal line S1 transitions from a low level to a high level, and the second transistor T2 is turned off. The first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor Tdr through the fifth transistor T5. This avoids leakage of the gate potential of the driving transistor Tdr through the first transistor T1, the second transistor T2, and the fifth transistor T5 during the light-emitting phase, which helps to improve the stability of the gate potential of the driving transistor Tdr.

[0075] Referring again to Figures 1 to 8, the display panel also includes a third transistor T3, the channel region of which is located at the third orthographic projection position 1213 of the first scan signal line S1 in the first active region 121.

[0076] In some embodiments, the channel region of the third transistor T3 is located at the third orthographic projection position 1213 of the first scan signal line S1 in the first active region 121, such that the gate of the third transistor T3 is connected to the first scan signal line S1. During the light-emitting phase of the pixel circuit, the first scan signal line S1 transitions from a low level to a high level, and the third transistor T3 is turned off. The first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, thereby further reducing the probability of leakage of the gate potential of the driving transistor Tdr through the first transistor T1 and the third transistor T3 during the light-emitting phase, and further improving the stability of the gate potential of the driving transistor Tdr.

[0077] Referring again to Figures 1 to 8, the second terminal of the first transistor T1, the first terminal of the second transistor T2, and the first terminal of the third transistor T3 are connected through the first active region 121.

[0078] In some embodiments, the first scan signal line S1 extends along the first direction X, such that the first transistor T1, the second transistor T2, and the third transistor T3 are all arranged along the first direction X. The second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 are all located in the active layer 120, thereby allowing the first active region 121 to extend along the first direction X, and the active layer 120 between the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 to be a heavily doped semiconductor material, such that the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 are connected through the first active region 121.

[0079] Figure 12 is a partial structural schematic diagram of another display panel provided in an embodiment of this application. As shown in Figure 12, the display panel also includes a second capacitor C2. The first electrode C21 of the second capacitor C2 is located in the first conductive layer M1. The first electrode C21 of the second capacitor C2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 through the second conductive part M22.

[0080] In some embodiments, the second capacitor C2 has a first plate C21 and a second plate C22. The first plate C21 of the second capacitor C2 is connected to the connection path of the second terminal of the first transistor T1, the first terminal of the second transistor T2, and the first terminal of the third transistor T3. This allows the first plate C21 of the second capacitor C2 to be connected to the second terminals of the first transistor T1, the second transistor T2, and the third transistor T3, i.e., the first plate C21 of the second capacitor C2 is connected to the first node N1 of the pixel circuit. The second plate C22 of the second capacitor C2 can be used to receive a fixed potential signal, thereby stabilizing the potential of the first node N1 through the second capacitor C2. During the light-emitting stage of the pixel circuit, the potential change of the first node N1 can be prevented from affecting the gate potential change of the driving transistor Tdr, further improving the gate potential stability of the driving transistor Tdr and reducing the flicker phenomenon of the display panel. Exemplarily, the display panel includes a first power supply line VDD1, which is used to provide a positive power supply signal for the pixel circuit. The second plate C22 of the second capacitor C2 can be connected to the first power supply line VDD1, so that the second plate C22 of the second capacitor C2 has a fixed potential signal. The capacitance value of the second capacitor C2 can be in the range of 60F-64F, and optionally, the capacitance value of the second capacitor C2 is 62F.

[0081] Referring again to Figures 4 and 12, the irregular shapes of the first plate C21 and the second plate C22 of the second capacitor C2 are beneficial to improving the compactness of different structures in the pixel circuit, increasing the capacitance value of the second capacitor C2, saving space occupied by the pixel circuit, and improving the pixel density of the display panel.

[0082] Referring again to Figures 4 and 12, the second conductive part M22 is located in the second conductive layer M2. The first end of the second conductive part M22 is connected to the first electrode C21 of the second capacitor C2. The second end of the second conductive part M22 is connected to the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3.

[0083] For example, FIG13 is a schematic diagram of the cross-sectional structure of a display panel obtained by cross-sectioning the fourth and fifth vias along the first direction according to an embodiment of the present application. As shown in Figures 4, 12, and 13, a fourth via DL4 is provided on the first insulating layer P1, and a fifth via DL5 is provided on the first insulating layer P1 and the second insulating layer P2. The fifth via DL5 penetrates the first insulating layer P1 and the second insulating layer P2. The orthographic projection of the fourth via DL4 on the substrate 110 overlaps with the orthographic projection of the second conductive part M22 on the substrate 110 and the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate 110. The second conductive part M22 is connected to the first electrode C21 of the second capacitor C2 through the fourth via DL4. The orthographic projection of the fifth via DL5 on the substrate 110 overlaps with the orthographic projection of the second conductive part M22 on the substrate 110 and the orthographic projection of the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 on the substrate 110. The second conductive part M22 is connected to the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 through the fifth via DL5.

[0084] In some embodiments, the fifth via DL5 penetrates the first insulating layer P1 and the second insulating layer P2, creating a through-hole between the second conductive layer M2 and the active layer 120 at the fifth via DL5. Simultaneously, the orthographic projection of the fifth via DL5 onto the substrate 110 overlaps with the orthographic projection of the second conductive portion M22 onto the substrate 110 and the orthographic projection of the connection paths of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 onto the substrate 110. During the fabrication of the display panel, the second conductive portion M22 extends through the fifth via DL5 to the connection paths of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3, making contact between the second end of the second conductive portion M22 and the connection paths of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3. Simultaneously, the orthographic projection of the fourth via DL4 on the substrate 110 overlaps with the orthographic projection of the second conductive part M22 on the substrate 110 and the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate 110, resulting in a through-hole between the second conductive layer M2 and the first conductive layer M1 at the fourth via DL4. During the manufacturing process of the display panel, the second conductive part M22 can extend through the fourth via DL4 to the first electrode C21 of the second capacitor C2, thereby making contact between the second conductive part M22 and the first electrode C21 of the second capacitor C2.

[0085] In some embodiments, the second electrode C22 of the second capacitor C2 is located on the third conductive layer M3, and the orthogonal projection of the second electrode C22 of the second capacitor C2 on the substrate 110 at least partially covers the orthogonal projection of the first electrode C21 of the second capacitor C2 on the substrate 110.

[0086] In some embodiments, a first interlayer insulating layer P11 is provided between the first conductive layer M1 and the third conductive layer M3, and when the orthogonal projection of the second electrode C22 of the second capacitor C2 on the substrate 110 at least partially covers the orthogonal projection of the first electrode C21 of the second capacitor C2 on the substrate 110, the second electrode C22 of the second capacitor C2, the first electrode C21 of the second capacitor C2, and the first interlayer insulating layer P11 between them form the second capacitor C2.

[0087] In some embodiments, the orthogonal projection of the second plate C22 of the second capacitor C2 onto the substrate 110 at least partially covers the orthogonal projection of the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 onto the substrate 110.

[0088] In some embodiments, continuing to refer to FIG12, the second plate C22 of the second capacitor C2 has a fixed potential signal. By setting the orthogonal projection of the second plate C22 of the second capacitor C2 on the substrate 110 to at least partially cover the orthogonal projection of the connection path of the second terminal of the first transistor T1, the first terminal of the second transistor T2, and the first terminal of the third transistor T3 on the substrate 110, the second plate C22 of the second capacitor C2 can extend between the first scan signal line S1 and the first node N1, thereby reducing the parasitic capacitance between the first scan signal line S1 and the first node N1. During the light-emitting stage of the pixel circuit, when the first scan signal line S1 jumps from a low level to a high level, the potential rise of the first node N1 can be reduced, thereby reducing the potential difference between the gate of the driving transistor Tdr and the first node N1, and further reducing the leakage current of the gate of the driving transistor Tdr through the first transistor T1, improving the gate potential stability of the driving transistor Tdr, and improving the flicker phenomenon of the display panel. For example, the capacitance value of the parasitic capacitance between the first scan signal line S1 and the first node N1 can be in the range of 0.6f-1.0f, and optionally, the capacitance value of the parasitic capacitance between the first scan signal line S1 and the first node N1 is 0.8f.

[0089] Referring again to Figures 12 and 4, the second plate C22 of the second capacitor C2 is connected to the second plate C12 of the first capacitor C1 through the third conductive part M23.

[0090] In some embodiments, when the second plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, and the second plate C22 of the second capacitor C2 is connected to the second plate C12 of the first capacitor C1 through the third conductive part M23, the second plate C22 of the second capacitor C2 can be connected to the first power supply line VDD1 through the second plate C12 of the first capacitor C1, thereby providing a fixed potential signal to the second plate C22 of the second capacitor C2 through the first power supply line VDD1.

[0091] Referring again to Figures 12 and 4, the third conductive part M23 is located on the second conductive layer M2. The first end of the third conductive part M23 is connected to the second plate C22 of the second capacitor C2, and the second end of the third conductive part M23 is connected to the second plate C12 of the first capacitor C1.

[0092] In some embodiments, the third conductive part M23 is located on the second conductive layer M2, such that the connection line between the second electrode C22 of the second capacitor C2 and the second electrode C12 of the first capacitor C1 is located on the second conductive layer M2, which can simplify the wiring of the first conductive layer M1 and the second conductive layer M2.

[0093] For example, FIG14 is a schematic cross-sectional view of a display panel obtained by cross-sectioning the third conductive part along the extension direction according to an embodiment of the present application. As shown in FIG4, FIG12 and FIG14, the first insulating layer P1 includes a second interlayer insulating layer P12 disposed between the third conductive layer M3 and the second conductive layer M2. The second interlayer insulating layer P12 is provided with a sixth via DL6 and a seventh via DL7. The orthographic projection of the sixth via DL6 on the substrate 110 overlaps with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode C12 of the first capacitor C1 on the substrate 110, respectively. The third conductive part M23 is connected to the second electrode C12 of the first capacitor C1 through the sixth via DL6. The orthographic projection of the seventh via DL7 on the substrate 110 overlaps with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate 110, respectively. The third conductive part M23 is connected to the second electrode C22 of the second capacitor C2 through the seventh via DL7.

[0094] In some embodiments, the sixth via DL6 and the seventh via DL7 penetrate the second interlayer insulating layer P12, so that the third conductive layer M3 and the second conductive layer M2 have through holes at the sixth via DL6 and the seventh via DL7. During the fabrication of the display panel, by setting the orthographic projection of the sixth via DL6 on the substrate 110 to overlap with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode C12 of the first capacitor C1 on the substrate 110, the second end of the third conductive part M23 can extend through the sixth via DL6 to the surface of the second electrode C12 of the first capacitor C1, thus achieving contact connection between the second end of the third conductive part M23 and the second electrode C12 of the first capacitor C1. By setting the orthographic projection of the seventh via DL7 on the substrate 110 to overlap with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate 110, the first end of the third conductive part M23 can extend through the seventh via DL7 to the surface of the second electrode plate C22 of the second capacitor C2, thereby achieving contact connection between the first end of the third conductive part M23 and the second electrode plate C22 of the second capacitor C2.

[0095] Figure 15 is a partial structural schematic diagram of another display panel provided in the embodiment of this application. As shown in Figures 3 and 15, the first conductive layer M1 further includes a second scanning signal line S2. The second scanning signal line S2 extends along the first direction X and is located between the first scanning signal line S1 and the first plate C11 of the first capacitor C1.

[0096] In some embodiments, as shown in Figures 3 and 15, the second scan signal line S2 is used to provide a second scan signal to the pixel circuit to control the state of the switching transistor connected to the second scan signal line S2 in the pixel circuit. The second scan signal line S2 extends along the first direction X, which avoids short circuits between the second scan signal line S2 and the first scan signal line S1, ensuring the reliability of the pixel circuit. Simultaneously, the second scan signal line S2 is located between the first scan signal line S1 and the first plate C11 of the first capacitor C1, allowing the switching transistor connected to the second scan signal line S2 to be closer to the driving transistor Tdr, simplifying the connection lines with the driving transistor Tdr and simplifying the wiring of the pixel circuit.

[0097] Referring again to Figures 3, 9 and 15, the display panel also includes a fourth transistor T4 and a fifth transistor T5. The channel region of the fourth transistor T4 is located at the first orthographic projection position 1214 of the second scan signal line S2 in the first active region 121, and the channel region of the fifth transistor T5 is located at the second orthographic projection position 1215 of the second scan signal line S2 in the first active region 121.

[0098] In some embodiments, the channel region of the fourth transistor T4 is located at the first orthographic projection position 1214 of the second scan signal line S2 in the first active region 121, such that the gate of the fourth transistor T4 is connected to the second scan signal line S2. When the second scan signal provided by the second scan signal line S2 is high, the fourth transistor T4 is off; when the second scan signal is low, the fourth transistor T4 is on. The channel region of the fifth transistor T5 is located at the second orthographic projection position 1215 of the second scan signal line S2 in the first active region 121, such that the gate of the fifth transistor T5 is connected to the second scan signal line S2. When the second scan signal provided by the second scan signal line S2 is high, the fifth transistor T5 is off; when the second scan signal is low, the fifth transistor T5 is on. Thus, the states of the fourth transistor T4 and the fifth transistor T5 can be controlled by the second scan signal.

[0099] Referring again to Figures 3 and 15, the first terminal of the driving transistor Tdr and the first terminal of the fourth transistor T4 are connected through the first active region 121, and the second terminal of the driving transistor Tdr and the first terminal of the fifth transistor T5 are connected through the first active region 121.

[0100] In some embodiments, as shown in FIG3, the first active region 121 can extend from the first terminal of the driving transistor Tdr to the first terminal of the fourth transistor T4, and the active layer 120 between the first terminal of the driving transistor Tdr and the first terminal of the fourth transistor T4 can be a heavily doped semiconductor material. This allows the first terminal of the driving transistor Tdr and the first terminal of the fourth transistor T4 to be directly connected through the first active region 121, simplifying the wiring of the display panel. Similarly, the first active region 121 can extend from the second terminal of the driving transistor Tdr to the first terminal of the fifth transistor T5, and the active layer 120 between the second terminal of the driving transistor Tdr and the first terminal of the fifth transistor T5 can be a heavily doped semiconductor material. This allows the second terminal of the driving transistor Tdr and the first terminal of the fifth transistor T5 to be directly connected through the first active region 121, simplifying the wiring of the display panel.

[0101] Referring again to Figures 3 and 15, the second terminal of the fifth transistor T5 and the second terminal of the second transistor T2 are connected through the first active region 121.

[0102] In some embodiments, the first active region 121 may extend from the second electrode of the fifth transistor T5 to the second electrode of the second transistor T2, and the active layer 120 between the second electrode of the fifth transistor T5 and the second electrode of the second transistor T2 may be a heavily doped semiconductor material, thereby connecting the second electrode of the fifth transistor T5 and the second electrode of the second transistor T2 through the first active region 121, simplifying the wiring of the display panel.

[0103] Figure 16 is a partial structural schematic diagram of another display panel provided in an embodiment of this application, and Figure 17 is a structural schematic diagram of a fourth conductive layer and an anode structure provided in an embodiment of this application. As shown in Figures 16 and 17, the display panel further includes a fourth conductive layer M4, which is located on the side of the second conductive layer M2 away from the first conductive layer M1. The fourth conductive layer M4 includes a data signal line DATA, which is connected to the second electrode of the fourth transistor T4.

[0104] In some embodiments, when the second scan signal controls the fourth transistor T4 to be turned on, the data voltage provided by the data signal line DATA can be transmitted to the first terminal of the driving transistor Tdr through the fourth transistor T4. When the driving transistor Tdr is turned on, the data voltage can be transmitted to the gate of the driving transistor Tdr through the driving transistor Tdr, the fifth transistor T5, the second transistor T2 and the first transistor T1, thereby realizing the writing of the data voltage.

[0105] Referring again to Figure 17, the data signal line DATA extends along the second direction Y.

[0106] In some embodiments, the data signal line DATA extends along the second direction Y, providing data voltage to a column of pixel circuits. Simultaneously, the data signal line DATA is disposed on the fourth conductive layer M4 to prevent short circuits caused by intersections between the data signal line DATA and signal lines extending along the first conductive layer in the first direction X, thus ensuring the reliability of the pixel circuits.

[0107] Referring again to Figures 2, 4, 16 and 17, the data signal line DATA is connected to the second terminal of the fourth transistor T4 through the first active region 121.

[0108] In some embodiments, the first active region 121 can be heavily doped to form a wire for connecting the data signal line DATA to the second pole of the fourth transistor T4, simplifying the wiring of the pixel circuit.

[0109] Figure 18 is a schematic cross-sectional view of a display panel provided in this application, obtained by cross-sectioning along a first direction at the eighth and ninth vias. As shown in Figures 2, 4, 16, 17, and 18, a third insulating layer P3 is disposed between the second conductive layer M2 and the fourth conductive layer M4. An eighth via DL8 is disposed on the third insulating layer P3, and a ninth via DL9 is disposed on the first insulating layer P1 and the second insulating layer P2. The orthographic projection of the eighth via DL8 on the substrate 110 overlaps with the orthographic projection of the data signal line DATA on the substrate 110. The orthographic projection of the eighth via DL8 on the substrate 110 overlaps with the orthographic projection of the ninth via DL9 on the substrate 110. The orthographic projection of the ninth via DL9 on the substrate 110 overlaps with the orthographic projection of the first active region 121 on the substrate 110. The data signal line DATA is connected to the first active region 121 through the eighth via DL8 and the ninth via DL9.

[0110] In some embodiments, the eighth via DL8 can penetrate the third insulating layer P3. During the manufacturing process of the display panel, the data signal line DATA can extend to the first active region 121 through the eighth via DL8 and the ninth via DL9, allowing the data signal line DATA to be connected to the first active region 121. Then, the first active region 121 extends to the second terminal of the fourth transistor T4, thereby enabling the data signal line DATA to be connected to the second terminal of the fourth transistor T4 to provide data voltage to the fourth transistor T4.

[0111] Figure 19 is a partial structural schematic diagram of another display panel provided in the embodiment of this application. As shown in Figures 19 and 3, the first conductive layer M1 further includes a third scanning signal line S3. The third scanning signal line S3 extends along the first direction X and is located on the side of the first plate C11 away from the first capacitor C1 of the first scanning signal line S1.

[0112] In some embodiments, as shown in Figures 3 and 19, the third scan signal line S3 is used to provide a third scan signal to the pixel circuit to control the state of the switching transistor connected to the third scan signal line S3 in the pixel circuit. The third scan signal line S3 extends along the first direction X, which avoids short circuits between the third scan signal line S3 and the first scan signal line S1, ensuring the reliability of the pixel circuit. Simultaneously, the third scan signal line S3 is located on the side of the first plate C11 of the first scan signal line S1 away from the first capacitor C1, allowing the switching transistor connected to the third scan signal line S3 to be located on the side of the third transistor T3, simplifying its connection wiring with the third transistor T3.

[0113] Referring again to Figures 2 to 4 and Figure 19, the display panel also includes a sixth transistor T6, the channel region of which is located at the orthographic projection position 1216 of the third scan signal line S3 in the first active region 121.

[0114] In some embodiments, the channel region of the sixth transistor T6 is located at the orthogonal projection position 1216 of the third scan signal line S3 onto the first active region 121, such that the gate of the sixth transistor T6 is connected to the third scan signal line S3. When the third scan signal provided by the third scan signal line S3 is high, the sixth transistor T6 is turned off; when the third scan signal is low, the sixth transistor T6 is turned on.

[0115] Referring again to Figures 2 to 4 and Figure 19, the first terminal of the sixth transistor T6 is connected to the second terminal of the third transistor T3 through the first active region 121.

[0116] In some embodiments, as shown in FIG19, the first active region 121 extends from the second electrode of the third transistor T3 to the first electrode of the sixth transistor T6, and the active layer 120 between the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 is a heavily doped semiconductor material, so that the first electrode of the sixth transistor T6 is directly connected to the second electrode of the third transistor T3 through the first active region 121, which can simplify the wiring of the display panel.

[0117] Referring again to Figures 2 to 4 and Figure 19, the second terminal of the sixth transistor T6 is connected to the first initialization signal line VREF1 through the first active region 121.

[0118] In some embodiments, the second terminal of the sixth transistor T6 is connected to the first initialization signal line VREF1. During the gate initialization phase of the pixel circuit, when the third scan signal controls the sixth transistor T6 to turn on, the first initialization signal provided by the first initialization signal line VREF1 can be transmitted to the gate of the driving transistor Tdr through the sixth transistor T6, the third transistor T3, and the first transistor T1 to initialize the gate of the driving transistor Tdr, making the driving transistor Tdr turn on. The start time of the third scan signal is one scan time earlier than the start time of the second scan signal, so that the pixel circuit initializes the gate of the driving transistor Tdr first during the gate initialization phase, and then controls the fourth transistor T4 and the fifth transistor T5 to turn on through the second scan signal during the data writing phase of the pixel circuit, writing the data voltage to the gate of the driving transistor Tdr, thereby realizing the writing of the data voltage.

[0119] Figure 20 is a schematic cross-sectional view of a display panel obtained by cross-sectioning along the second direction at the tenth via according to an embodiment of this application. As shown in Figures 2, 4, 19 and 20, the first initialization signal line VREF1 is located in the second conductive layer M2. The tenth via DL10 is provided on the first insulating layer P1 and the second insulating layer P2. The tenth via DL10 penetrates the first insulating layer P1 and the second insulating layer P2. The first initialization signal line VREF1 is connected to the second electrode of the sixth transistor T6 through the tenth via DL10 and the first active region 121.

[0120] In some embodiments, the tenth via DL10 penetrates the first insulating layer P1 and the second insulating layer P2, creating a through-hole between the second conductive layer M2 and the active layer 120 at the tenth via DL10. During the fabrication of the display panel, the orthographic projection of the first initialization signal line VREF1 on the substrate 110 overlaps with the orthographic projection of the tenth via DL10 on the substrate 110, and the orthographic projection of the tenth via DL10 on the substrate 110 overlaps with the orthographic projection of the first active region 121 on the substrate 110, so that the first initialization signal line VREF1 extends to the first active region 121 through the tenth via DL10, i.e., the first initialization signal line VREF1 is connected to the first active region 121. Then, the first active region 121 extends to the second electrode of the sixth transistor T6 at the tenth via DL10, and the active layer 120 between the tenth via DL10 and the second electrode of the sixth transistor T6 can be a heavily doped semiconductor material, thereby enabling the first initialization signal line VREF1 to be connected to the second electrode of the sixth transistor T6 through the first active region 121.

[0121] In some embodiments, the first initialization signal line VREF1 is disposed between the third scan signal line S3 and the first scan signal line S1. The first initialization signal line VREF1 extends along the first direction X, which can prevent the first initialization signal line VREF1 from intersecting and short-circuiting with other structures, thus ensuring the reliability of the display panel.

[0122] Figure 21 is a partial structural schematic diagram of another display panel provided in an embodiment of this application. As shown in Figures 21 and 3, the first conductive layer M1 further includes a light-emitting control signal line EM, which extends along the first direction X and is located on the second side of the first electrode plate C11 of the first capacitor C1.

[0123] In some embodiments, as shown in Figures 3 and 21, the light emission control signal line EM is used to provide a light emission control signal to the pixel circuit. The light emission control signal line EM extends along the first direction X, which avoids short circuits between the light emission control signal line EM and other signal lines, ensuring the reliability of the display panel. Simultaneously, the light emission control signal line EM is located on the second side of the first plate C11 of the first capacitor C1, allowing the switching transistor connected to the light emission control signal line EM to be located on one side of the driving transistor Tdr, simplifying its connection wiring with the driving transistor Tdr.

[0124] Referring again to Figures 2 to 4 and Figure 21, the display panel also includes a seventh transistor T7, the channel region of which is located at the orthographic projection position 1217 of the light emission control signal line EM in the first active region 121.

[0125] In some embodiments, the channel region of the seventh transistor T7 is located at the orthogonal projection position 1217 of the light emission control signal line EM in the first active region 121, such that the gate of the seventh transistor T7 is connected to the light emission control signal line EM. When the light emission control signal provided by the light emission control signal line EM is high, the seventh transistor T7 is turned off; when the light emission control signal is low, the seventh transistor T7 is turned on.

[0126] Referring again to Figures 2 to 4 and Figure 21, the first terminal of the seventh transistor T7 is connected to the second terminal of the driving transistor Tdr through the first active region 121.

[0127] In some embodiments, the first active region 121 may extend from the first electrode of the seventh transistor T7 to the second electrode of the driving transistor Tdr, and the active layer 120 between the first electrode of the seventh transistor T7 and the second electrode of the driving transistor Tdr is a heavily doped semiconductor material, so that the first electrode of the seventh transistor T7 is directly connected to the second electrode of the driving transistor Tdr through the first active region 121, which can simplify the wiring of the display panel.

[0128] Referring again to Figures 2 to 4 and Figure 21, the display panel also includes an eighth transistor T8, and the active layer 120 also includes a second active region 122. The second active region 122 is on the same layer as the first active region 121 and is not connected. The channel region of the eighth transistor T8 is located at the orthographic projection position 1221 of the light emission control signal line EM in the second active region 122.

[0129] In some embodiments, the second active region 122 is on the same layer as the first active region 121 but not connected. The first active region 121 and the second active region 122 can be formed simultaneously through patterning during the formation of the active layer 120. The channel region of the eighth transistor T8 is located at the orthogonal projection position 1221 of the light-emitting control signal line EM on the second active region 122, such that the gate of the eighth transistor T8 is connected to the light-emitting control signal line EM. When the light-emitting control signal provided by the light-emitting control signal line EM is high, the eighth transistor T8 is turned off; when the light-emitting control signal is low, the eighth transistor T8 is turned on.

[0130] Referring again to Figures 2 to 4 and Figure 21, the first terminal of the eighth transistor T8 is connected to the first terminal of the driving transistor Tdr through the fourth conductive part M24.

[0131] In some embodiments, a light-emitting control signal line EM is provided between the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 along the second direction Y. At this time, the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 are connected by the fourth conductive part M24 to prevent the second active region 122 from overlapping with the light-emitting control signal line EM to form another transistor.

[0132] Referring again to Figures 2 to 4 and Figure 21, the fourth conductive part M24 is located in the second conductive layer M2. The first end of the fourth conductive part M24 is connected to the first electrode of the eighth transistor T8 through the second active region 122, and the second end of the fourth conductive part M24 is connected to the first electrode of the driving transistor Tdr through the second active region 122.

[0133] In some embodiments, as shown in Figures 2 to 4 and Figure 21, a light-emitting control signal line EM is provided between the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 along the second direction Y. In this case, the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 are connected by the fourth conductive portion M24, preventing the second active region 122 from overlapping with the light-emitting control signal line EM to form another transistor.

[0134] Figure 22 is a schematic cross-sectional view of a display panel according to an embodiment of this application, showing the fourth conductive part along its extension direction. As shown in Figures 2 to 4, and Figures 21 and 22, an eleventh via DL11 and a twelfth via DL12 are provided on the first insulating layer P1 and the second insulating layer P2, respectively. The eleventh via DL11 and the twelfth via DL12 penetrate the first insulating layer P1 and the second insulating layer P2. The first end of the fourth conductive part M24 is connected to the first electrode of the eighth transistor T8 through the eleventh via DL11 and the second active region 122, and the second end of the fourth conductive part M24 is connected to the first electrode of the driving transistor Tdr through the twelfth via DL12 and the second active region 122.

[0135] Referring again to Figures 2 to 4 and Figure 21, the second electrode of the eighth transistor T8 is connected to the second plate C12 of the first capacitor C1 through the fifth conductive part M25.

[0136] In some embodiments, the second plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, and the second terminal of the eighth transistor T8 is connected to the second plate C12 of the first capacitor C1 through the fifth conductive part M25. This allows the second terminal of the eighth transistor T8 to be connected to the first power supply line VDD1 through the second plate C12 of the first capacitor C1, thereby providing a positive power supply signal for the pixel circuit to the second terminal of the eighth transistor T8 through the first power supply line VDD1. During the light-emitting stage of the pixel circuit, the light-emitting control signal controls the seventh transistor T7 and the eighth transistor T8 to conduct, allowing the positive power supply signal to be transmitted through the eighth transistor T8 to the first terminal of the driving transistor Tdr. The driving transistor Tdr then forms a driving current based on the positive power supply signal and the gate data voltage, and transmits it to the light-emitting device through the seventh transistor T7, thus realizing the display of the display panel.

[0137] Referring again to Figures 2 to 4 and Figure 21, the fifth conductive part M25 is located in the second conductive layer M2. The first end of the fifth conductive part M25 is connected to the second electrode of the eighth transistor T8, and the second end of the fifth conductive part M25 is connected to the second electrode C12 of the first capacitor C1.

[0138] In some embodiments, along the second direction Y, there is a light-emitting control signal line EM between the second plate C12 of the first capacitor C1 and the second electrode of the eighth transistor T8. At this time, the second plate C12 of the first capacitor C1 and the second electrode of the eighth transistor T8 are connected by the fifth conductive part M25 to prevent the second active region 122 from overlapping with the light-emitting control signal line EM to form another transistor.

[0139] Figure 23 is a schematic cross-sectional view of a display panel according to an embodiment of this application, showing the fifth conductive part along its extension direction. Referring again to Figures 2 to 4, and Figures 21 and 23, a thirteenth via DL13 is provided on the first insulating layer P1 and the second insulating layer P2, and a fourteenth via DL14 is provided on the second interlayer insulating layer P12. The first end of the fifth conductive part M25 is connected to the second electrode of the eighth transistor T8 through the thirteenth via DL13, and the second end of the fifth conductive part M25 is connected to the second electrode C12 of the first capacitor C1 through the fourteenth via DL14.

[0140] In some embodiments, the thirteenth via DL13 penetrates the first insulating layer P1 and the second insulating layer P2, creating a through-hole between the second conductive layer M2 and the active layer 120 at the thirteenth via DL13. Simultaneously, the orthographic projection of the thirteenth via DL13 onto the substrate 110 overlaps with the orthographic projections of the second electrode of the eighth transistor T8 and the fifth conductive portion M25 onto the substrate 110. Therefore, during the fabrication of the display panel, the fifth conductive portion M25 extends through the thirteenth via DL13 to the second electrode of the eighth transistor T8, connecting the first end of the fifth conductive portion M25 to the second electrode of the eighth transistor T8. The sixth via DL6 can be reused as the fourteenth via DL14. The orthographic projection of the fourteenth via DL14 on the substrate 110 overlaps with the orthographic projections of the fifth conductive part M25 and the second electrode C12 of the first capacitor C1 on the substrate 110. Therefore, during the manufacturing process of the display panel, the fifth conductive part M25 extends through the fourteenth via DL14 to the second electrode C12 of the first capacitor C1, connecting the second end of the fifth conductive part M25 to the second electrode C12 of the first capacitor C1. Simultaneously, the second electrode C12 of the first capacitor C1 is connected to the first power supply line VDD1, allowing the second electrode of the eighth transistor T8 to be connected to the first power supply line VDD1 through the second electrode C12 of the first capacitor C1, providing a positive power supply signal for the pixel circuit to the second electrode of the eighth transistor T8.

[0141] Referring again to Figures 17 and 21, the fourth conductive layer M4 also includes a second power supply trace VDD2, which is connected to the second plate C12 of the first capacitor C1.

[0142] In some embodiments, the second power supply line VDD2 is connected to the second plate C12 of the first capacitor C1, that is, the second power supply line VDD2 is connected to the first power supply line VDD1, so that a positive power signal can be provided to the first power supply line VDD1 through the second power supply line VDD2.

[0143] Referring again to Figures 17 and 21, the second power supply trace VDD2 is located on one side of the data signal line DATA. The second power supply trace VDD2 extends along the second direction Y to avoid short circuits with the data signal line DATA. At the same time, it can form a crisscross distribution of power signal lines with the first power supply trace VDD1, which can reduce the line impedance of the power signal lines and improve the uniformity of the positive power signal, thereby improving the brightness uniformity of the display panel.

[0144] Referring again to Figures 17, 18 and 23, a fifteenth via DL15 is provided on the third insulating layer P3. The orthographic projection of the fifteenth via DL15 on the substrate 110 overlaps with the orthographic projection of the fourteenth via DL14 on the substrate 110. The second power supply line VDD2 is connected to the second plate C12 of the first capacitor C1 through the fifteenth via DL15 and the fourteenth via DL14.

[0145] In some embodiments, the fifteenth via DL15 penetrates the third insulating layer P3. The orthographic projection of the fifteenth via DL15 on the substrate 110 overlaps with the orthographic projection of the fourteenth via DL14 on the substrate 110, and the orthographic projection of the fourteenth via DL14 on the substrate 110 overlaps with the orthographic projection of the fifth conductive portion M25 on the substrate 110, so that the second power supply trace VDD2 can be connected to the fifth conductive portion M25 in the fourteenth via DL14 through the fifteenth via DL15, and the fifth conductive portion M25 is connected to the second electrode C12 of the first capacitor C1 through the fourteenth via DL14, so that the second power supply trace VDD2 is connected to the second electrode C12 of the first capacitor C1 through the fifteenth via DL15 and the fourteenth via DL14.

[0146] Referring again to Figures 17 and 21, the display panel also includes an anode structure, which is disposed on the side of the fourth conductive layer M4 away from the substrate 110; the second electrode of the seventh transistor T7 is connected to the anode structure through the first active region 121.

[0147] In some embodiments, the anode structure serves as the anode of the light-emitting device in the pixel circuit. The second terminal of the seventh transistor T7 is connected to the anode structure, so that during the light-emitting phase of the pixel circuit, when the seventh transistor T7 is turned on, the driving current provided by the driving transistor Tdr is transmitted through the seventh transistor T7 to the anode of the light-emitting device, driving the light-emitting device to emit light.

[0148] Figure 24 is a schematic cross-sectional view of a display panel obtained by cross-sectioning along AA' according to an embodiment of this application. As shown in Figures 17, 21 and 24, a fourth insulating layer P4 is disposed between the anode structure Anode and the fourth conductive layer M4. A sixteenth via DL16 is provided on the fourth insulating layer P4. A seventeenth via DL17 is provided on the first insulating layer P1 and the second insulating layer P2. The seventeenth via DL17 penetrates the first insulating layer P1 and the second insulating layer P2. An eighteenth via DL18 is provided on the third insulating layer P3. The orthographic projection of the sixteenth via DL16 on the substrate 110 is respectively aligned with the anode structure Anode. The orthographic projection on substrate 110 overlaps with the orthographic projection of the eighteenth via DL18 on substrate 110. The orthographic projection of the eighteenth via DL18 on substrate 110 overlaps with the orthographic projection of the seventeenth via DL17 on substrate 110. The orthographic projection of the seventeenth via DL17 on substrate 110 overlaps with the orthographic projection of the first active region 121 on substrate 110. The anode structure Anode is connected to the first active region 121 through the sixteenth via DL16, the eighteenth via DL18 and the seventeenth via DL17.

[0149] In some embodiments, the sixteenth via DL16 penetrates the fourth insulating layer P4. During the fabrication of the display panel, the anode structure can extend through the sixteenth via DL16 to the fourth conductive layer M4, then through the eighteenth via DL18 on the third insulating layer P3 to the second conductive layer M2, and then through the seventeenth via DL17 to the first active region 121, connecting with the first active region 121. The first active region 121 extends to the second electrode of the seventh transistor T7, thereby enabling the second electrode of the seventh transistor T7 to be connected to the anode structure.

[0150] Figure 25 is a partial structural schematic diagram of another display panel provided in the embodiment of this application. As shown in Figures 25 and 3, the first conductive layer M1 further includes a fourth scanning signal line S4. The fourth scanning signal line S4 extends along the first direction X and is located on the side of the light emission control signal line EM away from the first electrode plate C11 of the first capacitor C1.

[0151] In some embodiments, the fourth scan signal line S4 is used to provide a fourth scan signal to the pixel circuit to control the state of the switching transistors connected to the fourth scan signal line S4 in the pixel circuit. The fourth scan signal line S4 extends along the first direction X, which avoids short circuits caused by intersections with other signal lines, ensuring the reliability of the pixel circuit. Simultaneously, the fourth scan signal line S4 is located on the side of the light-emitting control signal line EM away from the first plate C11 of the first capacitor C1, which facilitates simultaneous connection of the fourth scan signal line S4 to transistors in both the upper and lower rows of pixel circuits, thus improving the pixel density of the display panel.

[0152] In some embodiments, FIG26 is a timing waveform diagram of a scanning signal provided in an embodiment of this application. Wherein, s2 is the timing of the second scanning signal provided by the second scanning signal line S2, s3 is the timing of the third scanning signal provided by the third scanning signal line S3, and s4 is the timing of the fourth scanning signal provided by the fourth scanning signal line S4. As shown in FIG26, the signal waveform in the fourth scanning signal line S4 is the same as the signal waveform in the third scanning signal line S3, and the start time of the signal in the fourth scanning signal line S4 is one scan time later than the start time of the signal in the third scanning signal line S3.

[0153] In some embodiments, the signal waveform in the fourth scan signal line S4 is the same as the signal waveform in the third scan signal line S3, so that the fourth scan signal provided by the fourth scan signal line S4 can initialize the anode of the light-emitting device and the first terminal of the driving transistor Tdr during the anode initialization stage of the pixel circuit, ensuring the reliability of the initialization. Simultaneously, the start time of the signal in the fourth scan signal line S4 is one scan time later than the start time of the signal in the third scan signal line S3, enabling row-by-row driving of pixel circuits in different rows.

[0154] In some embodiments, the signal in the fourth scan signal line S4 of the previous row is multiplexed into the signal in the third scan signal line S3 of the current row.

[0155] In some embodiments, the fourth scan signal line S4 of the previous row can be reused as the third scan signal line S3 of the current row, which can simplify the structure of the display panel and help improve the pixel density of the display panel.

[0156] Referring again to Figures 2 to 4 and Figure 25, the display panel also includes a ninth transistor T9 and a tenth transistor T10. The channel region of the ninth transistor T9 is located at the orthogonal projection position 1222 of the fourth scan signal line S4 in the second active region 122, and the channel region of the tenth transistor T10 is located at the orthogonal projection position 1218 of the fourth scan signal line S4 in the first active region 121.

[0157] In some embodiments, the channel region of the ninth transistor T9 is located at the orthogonal projection position 1222 of the fourth scan signal line S4 in the second active region 122, such that the gate of the ninth transistor T9 is connected to the fourth scan signal line S4. The channel region of the tenth transistor T10 is located at the orthogonal projection position 1218 of the fourth scan signal line S4 in the first active region 121, such that the gate of the tenth transistor T10 is connected to the fourth scan signal line S4. When the fourth scan signal provided by the fourth scan signal line S4 is high, the ninth transistor T9 and the tenth transistor T10 are turned off; when the fourth scan signal is low, the ninth transistor T9 and the tenth transistor T10 are turned on.

[0158] Referring again to Figures 2 to 4 and Figure 25, the first terminal of the ninth transistor T9 is connected to the first terminal of the eighth transistor T8 through the second active region 122, and the first terminal of the tenth transistor T10 is connected to the second terminal of the seventh transistor T7 through the first active region 121.

[0159] In some embodiments, when the first terminal of the eighth transistor T8 is connected to the first terminal of the driving transistor Tdr, and the first terminal of the ninth transistor T9 is connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9 can be connected to the first terminal of the driving transistor Tdr. When the ninth transistor T9 outputs a second initialization signal, the first terminal of the driving transistor Tdr can be initialized.

[0160] Referring again to Figures 2 to 4 and Figure 25, the second conductive layer M2 also includes a second initialization signal line VREF2, and the second terminal of the ninth transistor T9 is connected to the second initialization signal line VREF2 through the second active region 122.

[0161] In some embodiments, the second initialization signal line VREF2 is used to provide a second initialization signal. During the anode initialization phase of the pixel circuit, the fourth scan signal line S4 is provided at a low level, and the ninth transistor T9 and the tenth transistor T10 are turned on to provide the second initialization signal to the first terminal of the driving transistor Tdr.

[0162] Figure 27 is a schematic cross-sectional view of a display panel provided in an embodiment of this application, obtained by cross-sectioning along a first direction at the nineteenth via. As shown in Figures 2 to 4, and Figures 25 and 27, the nineteenth via DL19 is provided on the first insulating layer P1 and the second insulating layer P2. The nineteenth via DL19 penetrates the first insulating layer P1 and the second insulating layer P2. The second initialization signal line VREF2 passes through the nineteenth via DL19 and is connected to the second terminal of the ninth transistor T9 through the second active region 122.

[0163] In some embodiments, the nineteenth via DL19 penetrates the first insulating layer P1 and the second insulating layer P2, creating a through-hole between the second conductive layer M2 and the active layer 120 at the nineteenth via DL19. During the fabrication of the display panel, the orthographic projection of the nineteenth via DL19 on the substrate 110 overlaps with the orthographic projection of the second active region 122 on the substrate 110, and the orthographic projection of the second initialization signal line VREF2 on the substrate 110 overlaps with the orthographic projection of the nineteenth via DL19 on the substrate 110. The second initialization signal line VREF2 extends through the nineteenth via DL19 to the second active region 122, connecting the second initialization signal line VREF2 to the second active region 122. Simultaneously, the second active region 122 extends to the second terminal of the ninth transistor T9, allowing the second initialization signal line VREF2 to connect to the second terminal of the ninth transistor T9. During the anode initialization phase of the pixel circuit, the ninth transistor T9 provides a second initialization signal to the first terminal of the driving transistor Tdr.

[0164] Referring again to Figures 4 and 25, the second initialization signal line VREF2 is located on the side of the fourth scan signal line S4 away from the driving transistor Tdr. The second initialization signal line VREF2 extends along the first direction X to avoid contact and connection between the second initialization signal line VREF2 and other conductive structures on the second conductive layer M2, thereby ensuring the reliability of the display panel.

[0165] Referring again to Figures 2 to 5, Figure 17 and Figure 25, the fourth conductive layer M4 also includes a third initialization signal line VREF3, which is connected to the second pole of the tenth transistor T10 through the first active region 121.

[0166] In some embodiments, the third initialization signal line VREF3 is used to provide a third initialization signal. During the anode initialization phase of the pixel circuit, the fourth scan signal line S4 is provided at a low level, and the tenth transistor T10 is turned on to provide a third initialization signal for the anode of the light-emitting device.

[0167] Referring again to Figures 2 to 5, Figure 17 and Figure 25, the third initialization signal line VREF3 is located on the side of the second power supply trace VDD2 away from the data signal line DATA. The third initialization signal line VREF3 extends along the second direction Y to avoid short circuits between the third initialization signal line VREF3 and the data signal line DATA or the second power supply trace VDD2.

[0168] Figure 28 is a schematic cross-sectional view of a display panel provided in an embodiment of this application, obtained by cross-sectioning along a second direction at the 20th and 21st vias. As shown in Figures 2 to 5, 17, 25 and 28, a 20th via DL20 is provided on the first insulating layer P1 and the second insulating layer P2, penetrating the first insulating layer P1 and the second insulating layer P2. A 21st via DL21 is provided on the third insulating layer P3. The orthographic projection of the 21st via DL21 on the substrate 110 overlaps with the orthographic projection of the third initialization signal line VREF3 on the substrate 110 and the orthographic projection of the 20th via DL20 on the substrate 110. The orthographic projection of the 20th via DL20 on the substrate 110 overlaps with the orthographic projection of the first active region 121 on the substrate 110. The third initialization signal line VREF3 is connected to the first active region 121 through the 21st via DL21 and the 20th via DL20.

[0169] In some embodiments, the twentieth via DL20 penetrates the first insulating layer P1 and the second insulating layer P2, creating a through-hole between the second conductive layer M2 and the active layer 120 at the twentieth via DL20. The twentieth via DL21 penetrates the third insulating layer P3 and overlaps with the twentieth via DL20, allowing the third initialization signal line VREF3 to extend through the twentieth via DL21 to the second conductive layer M2, and then through the twentieth via DL20 to the first active region 121. The first active region 121 extends from the twentieth via DL20 to the second terminal of the tenth transistor T10, thereby enabling the third initialization signal line VREF3 to be connected to the second terminal of the tenth transistor T10.

[0170] In some embodiments, the first scan signal line S1 extends in a zigzag pattern along the first direction X. This can save the area occupied by the pixel circuit layout according to the spatial layout of the display panel, thereby improving the pixel density of the display panel. For example, as shown in FIG25, between the first capacitor C1 and the second capacitor C2, the first scan signal line S1 extends in a zigzag pattern along the first direction X, so that the extended shape of the first scan signal line S1 matches the edge of the second capacitor C2. This allows full utilization of the space between the first capacitor C1 and the second capacitor C2 to form the first transistor T1, the second transistor T2, and the third transistor T3. While satisfying the pixel circuit layout, this helps to reduce the distance between the first capacitor C1 and the second capacitor C2 along the second direction Y, thereby saving the area occupied by the pixel circuit layout and improving the pixel density of the display panel.

[0171] This application also provides a display device. Figure 29 is a schematic diagram of the structure of a display device provided in an embodiment of this application. As shown in Figure 29, the display device 100 includes the display panel 10 provided in any embodiment of this application. Since the display device 100 includes the display panel 10 provided in any embodiment of this application, it has the same beneficial effects as the display panel 10 provided in any embodiment of this application, and will not be described again here. The display device 100 can be, for example, any product or component with display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart wearable device, or information kiosks in public lobbies.

Claims

1. A display panel, comprising: Substrate; Drive transistor and first capacitor; An active layer is disposed on one side of the substrate, the active layer includes a first active region, and the channel region of the driving transistor is located in the first active region; A first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes a first electrode of the first capacitor and a first scan signal line extending along a first direction. The first scan signal line is located on the first side of the first electrode of the first capacitor. The orthographic projection of the first plate of the first capacitor onto the substrate at least partially covers the orthographic projection of the channel region of the driving transistor onto the substrate; A second conductive layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer includes a first conductive portion, which is connected to the first plate of the first capacitor. The orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate.

2. The display panel according to claim 1, wherein, The first scan signal line is located on one side of the first plate of the first capacitor along the second direction, and the first direction intersects the second direction; The channel region of the driving transistor is located at the position of the first plate of the first capacitor projected onto the first active region, and the first plate of the first capacitor is multiplexed as the gate of the driving transistor.

3. The display panel according to claim 1 further includes a third conductive layer, the third conductive layer being located between the first conductive layer and the second conductive layer, the third conductive layer including a first power line and a second electrode of a first capacitor, the first power line and the second electrode of the first capacitor being connected and integrally formed; The first power supply trace extends along the first direction; The second plate of the first capacitor is provided with a first through hole, and the first conductive part passes through the first through hole and connects to the first plate of the first capacitor. A first insulating layer is provided between the first conductive layer and the second conductive layer. A second via is provided on the first insulating layer. The orthographic projection of the second via on the substrate is located within the orthographic projection of the first via on the substrate. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first electrode plate of the first capacitor on the substrate, respectively. The first conductive part is connected to the first electrode plate of the first capacitor through the second via. The orthographic projection of the first plate of the first capacitor onto the substrate is located within the orthographic projection of the second plate of the first capacitor onto the substrate; The orthographic projection of the first via on the substrate is located within the orthographic projection of the first electrode of the first capacitor on the substrate.

4. The display panel according to claim 3 further includes a first transistor, wherein the channel region of the first transistor is located at the first orthographic projection position of the first scan signal line in the first active region; The first end of the first conductive part is connected to the first plate of the first capacitor, and the second end of the first conductive part is connected to the first electrode of the first transistor through the first active region. A second insulating layer is disposed between the first conductive layer and the active layer. A third via is provided on the first insulating layer and the second insulating layer. The third via penetrates the first insulating layer and the second insulating layer. The orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first active region on the substrate, respectively. The first conductive part is connected to the first active region through the third via.

5. The display panel according to claim 4, wherein the display panel further comprises a second transistor, the channel region of the second transistor being located at the second orthographic projection position of the first scan signal line in the first active region; The display panel further includes a third transistor, the channel region of which is located at the third orthographic projection position of the first scan signal line in the first active region; The second terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the third transistor are connected through the first active region.

6. The display panel according to claim 5 further includes a second capacitor, wherein the first electrode of the second capacitor is located on the first conductive layer, and the first electrode of the second capacitor is connected to the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor through the second conductive part. The second conductive part is located in the second conductive layer. The first end of the second conductive part is connected to the first plate of the second capacitor. The second end of the second conductive part is connected to the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor. A fourth via is provided on the first insulating layer, and a fifth via is provided on the first insulating layer and the second insulating layer, the fifth via penetrating the first insulating layer and the second insulating layer; The orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second conductive part on the substrate and the orthographic projection of the first electrode of the second capacitor on the substrate, respectively. The second conductive part is connected to the first electrode of the second capacitor through the fourth via. The orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the second conductive part on the substrate and the orthographic projection of the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor on the substrate, respectively. The second conductive part is connected to the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor through the fifth via. The second plate of the second capacitor is located on the third conductive layer, and the orthographic projection of the second plate of the second capacitor on the substrate at least partially covers the orthographic projection of the first plate of the second capacitor on the substrate. The orthogonal projection of the second plate of the second capacitor onto the substrate at least partially covers the orthogonal projection of the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor onto the substrate. The second plate of the second capacitor is connected to the second plate of the first capacitor through a third conductive part; The third conductive part is located in the second conductive layer. The first end of the third conductive part is connected to the second plate of the second capacitor, and the second end of the third conductive part is connected to the second plate of the first capacitor. The first insulating layer includes an interlayer insulating layer disposed between the third conductive layer and the second conductive layer. The interlayer insulating layer has a sixth via and a seventh via. The orthographic projection of the sixth via on the substrate overlaps with the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second electrode of the first capacitor on the substrate, respectively. The third conductive part is connected to the second electrode of the first capacitor through the sixth via. The orthographic projection of the seventh via on the substrate overlaps with the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second electrode of the second capacitor on the substrate, respectively. The third conductive part is connected to the second electrode of the second capacitor through the seventh via.

7. The display panel according to claim 5, wherein, The first conductive layer further includes a second scan signal line, which extends along the first direction and is located between the first scan signal line and the first plate of the first capacitor.

8. The display panel according to claim 7 further includes a fourth transistor and a fifth transistor, wherein the channel region of the fourth transistor is located at the first orthographic projection position of the second scan signal line in the first active region, and the channel region of the fifth transistor is located at the second orthographic projection position of the second scan signal line in the first active region; The first terminal of the driving transistor and the first terminal of the fourth transistor are connected through the first active region, and the second terminal of the driving transistor and the first terminal of the fifth transistor are connected through the first active region. The second terminal of the fifth transistor and the second terminal of the second transistor are connected through the first active region.

9. The display panel according to claim 8, further comprising a fourth conductive layer, the fourth conductive layer being located on the side of the second conductive layer away from the first conductive layer, the fourth conductive layer including a data signal line, the data signal line being connected to the second electrode of the fourth transistor; The data signal line extends along the second direction; The data signal line is connected to the second electrode of the fourth transistor through the first active region; A third insulating layer is disposed between the second conductive layer and the fourth conductive layer. An eighth via is disposed on the third insulating layer. A ninth via is disposed on the first insulating layer and the second insulating layer. The ninth via penetrates the first insulating layer and the second insulating layer. The orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the data signal line on the substrate. The orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the ninth via on the substrate. The orthographic projection of the ninth via on the substrate overlaps with the orthographic projection of the first active region on the substrate. The data signal line is connected to the first active region through the eighth via and the ninth via.

10. The display panel according to claim 9, wherein, The first conductive layer further includes a third scan signal line, which extends along the first direction and is located on the side of the first scan signal line away from the first plate of the first capacitor.

11. The display panel according to claim 10, further comprising a sixth transistor, wherein the channel region of the sixth transistor is located at the orthogonal projection position of the third scan signal line onto the first active region; The first terminal of the sixth transistor is connected to the second terminal of the third transistor through the first active region; The second terminal of the sixth transistor is connected to the first initialization signal line through the first active region; The first initialization signal line is located in the second conductive layer. A tenth via is provided on the first insulating layer and the second insulating layer. The tenth via penetrates the first insulating layer and the second insulating layer. The first initialization signal line is connected to the second electrode of the sixth transistor through the tenth via and the first active region. The orthographic projection of the tenth via on the substrate overlaps with the orthographic projection of the first active region on the substrate, and the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the tenth via on the substrate; The first initialization signal line is disposed between the third scan signal line and the first scan signal line, and the first initialization signal line extends along the first direction.

12. The display panel according to claim 11, wherein, The first conductive layer further includes a light-emitting control signal line, which extends along the first direction and is located on the second side of the first plate of the first capacitor. The display panel further includes a seventh transistor, the channel region of which is located at the orthogonal projection position of the light emission control signal line onto the first active region; The first terminal of the seventh transistor is connected to the second terminal of the driving transistor through the first active region; The display panel further includes an eighth transistor, and the active layer further includes a second active region, which is on the same layer as the first active region but not connected. The channel region of the eighth transistor is located at the orthogonal projection position of the light emission control signal line in the second active region. The first electrode of the eighth transistor is connected to the first electrode of the driving transistor through the fourth conductive part; The fourth conductive portion is located in the second conductive layer. The first end of the fourth conductive portion is connected to the first electrode of the eighth transistor through the second active region, and the second end of the fourth conductive portion is connected to the first electrode of the driving transistor through the second active region. The first insulating layer and the second insulating layer are provided with an eleventh via and a twelfth via, the eleventh via and the twelfth via penetrating the first insulating layer and the second insulating layer; the first end of the fourth conductive part is connected to the first electrode of the eighth transistor through the eleventh via and the second active region, and the second end of the fourth conductive part is connected to the first electrode of the driving transistor through the twelfth via and the second active region; The second electrode of the eighth transistor is connected to the second plate of the first capacitor through the fifth conductive part; The fifth conductive part is located in the second conductive layer, the first end of the fifth conductive part is connected to the second electrode of the eighth transistor, and the second end of the fifth conductive part is connected to the second plate of the first capacitor; The first insulating layer and the second insulating layer are provided with a thirteenth via, and the second interlayer insulating layer is provided with a fourteenth via. The first end of the fifth conductive part is connected to the second electrode of the eighth transistor through the thirteenth via, and the second end of the fifth conductive part is connected to the second electrode of the first capacitor through the fourteenth via.

13. The display panel according to claim 12, wherein, The fourth conductive layer also includes a second power trace, which is connected to the second plate of the first capacitor. The second power supply trace is disposed on one side of the data signal line, and the second power supply trace extends along the second direction; The third insulating layer has a fifteenth via, the orthographic projection of the fifteenth via on the substrate overlaps with the orthographic projection of the fourteenth via on the substrate, and the second power supply trace is connected to the second plate of the first capacitor through the fifteenth via and the fourteenth via.

14. The display panel according to claim 12, further comprising an anode structure disposed on the side of the fourth conductive layer away from the substrate; the second electrode of the seventh transistor is connected to the anode structure through the first active region; A fourth insulating layer is disposed between the anode structure and the fourth conductive layer. A sixteenth via is provided on the fourth insulating layer. A seventeenth via is provided on the first insulating layer and the second insulating layer. The seventeenth via penetrates the first insulating layer and the second insulating layer. An eighteenth via is provided on the third insulating layer. The orthographic projection of the sixteenth via on the substrate overlaps with the orthographic projection of the anode structure on the substrate and the orthographic projection of the eighteenth via on the substrate, respectively. The orthographic projection of the eighteenth via on the substrate overlaps with the orthographic projection of the seventeenth via on the substrate. The orthographic projection of the seventeenth via on the substrate overlaps with the orthographic projection of the first active region on the substrate. The anode structure is connected to the first active region through the sixteenth via, the eighteenth via, and the seventeenth via.

15. The display panel according to claim 12, wherein, The first conductive layer further includes a fourth scan signal line, which extends along the first direction and is located on the side of the light emission control signal line away from the first plate of the first capacitor. The signal waveform in the fourth scan signal line is the same as the signal waveform in the third scan signal line, and the start time of the signal in the fourth scan signal line is one scan time later than the start time of the signal in the third scan signal line. The signal in the fourth scan signal line of the previous row is multiplexed into the signal in the third scan signal line of the current row.

16. The display panel according to claim 15, further comprising a ninth transistor and a tenth transistor, wherein the channel region of the ninth transistor is located at the orthogonal projection position of the fourth scan signal line in the second active region, and the channel region of the tenth transistor is located at the orthogonal projection position of the fourth scan signal line in the first active region; The first terminal of the ninth transistor is connected to the first terminal of the eighth transistor through the second active region, and the first terminal of the tenth transistor is connected to the second terminal of the seventh transistor through the first active region.

17. The display panel according to claim 16, wherein, The second conductive layer further includes a second initialization signal line, and the second terminal of the ninth transistor is connected to the second initialization signal line through the second active region; The second initialization signal line is disposed on the side of the fourth scan signal line away from the driving transistor, and the second initialization signal line extends along the first direction; A nineteenth via is provided on the first insulating layer and the second insulating layer. The nineteenth via penetrates the first insulating layer and the second insulating layer. The second initialization signal line passes through the nineteenth via and is connected to the second electrode of the ninth transistor through the second active region. The orthographic projection of the nineteenth via on the substrate overlaps with the orthographic projection of the second active region on the substrate, and the orthographic projection of the second initialization signal line on the substrate overlaps with the orthographic projection of the nineteenth via on the substrate.

18. The display panel according to claim 16, wherein, The fourth conductive layer further includes a third initialization signal line, which is connected to the second electrode of the tenth transistor through the first active region; The third initialization signal line is disposed on the side of the second power supply trace away from the data signal line, and the third initialization signal line extends along the second direction; The first insulating layer and the second insulating layer are provided with a twentieth via, which penetrates the first insulating layer and the second insulating layer. The third insulating layer is provided with a twentieth via. The orthographic projection of the twentieth via on the substrate overlaps with the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the twentieth via on the substrate, respectively. The orthographic projection of the twentieth via on the substrate overlaps with the orthographic projection of the first active region on the substrate. The third initialization signal line is connected to the first active region through the twentieth via and the twentieth via.

19. The display panel according to claim 1, wherein, Along the first direction, the first scan signal line extends in a tortuous manner.

20. A display device comprising the display panel according to any one of claims 1-19.

Images