CPU power supply circuit and method, and main control chip

Abstract

The present application relates to the technical field of design of power supply circuits, and discloses a CPU power supply circuit and method, and a main control chip. The CPU power supply circuit comprises a main control chip, a CPU, and a power conversion circuit. The main control chip is integrated with codes of at least two power communication protocols. The main control chip is configured to determine a currently available communication protocol from among the at least two power communication protocols on the basis of the type of the CPU, and communicate with the CPU on the basis of the currently available communication protocol. The main control chip is further configured to receive a voltage regulation instruction from the CPU, generate a modulation signal on the basis of the voltage regulation instruction, and send the modulation signal to the power conversion circuit. The power conversion circuit is configured to receive the modulation signal, adjust an external input voltage on the basis of the modulation signal, and output same to the CPU to supply power to the CPU. In the present solution, by adjusting the software and hardware design of the chip, a single power chip can be made compatible with processors across multiple platforms, thereby solving the problems of low design flexibility and high complexity.

Description

A CPU power supply circuit, power supply method and main control chip

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411958041.1, filed on December 27, 2024, entitled "A CPU power supply circuit, power supply method and main control chip", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of power supply circuit design technology, and in particular to a CPU power supply circuit, power supply method and main control chip. Background Technology

[0004] The current server CPU (Central Processing Unit) power supply needs to use VRM (Voltage Regulator Module), as shown in Figure 1. Compared with the traditional analog power supply solution, the digital multiphase power supply solution has a faster response speed, and the power parameters of the digital multiphase power supply can be adjusted through the digital interface. Therefore, the digital multiphase power supply has greater flexibility and can adapt to more application scenarios.

[0005] Currently, different CPU platforms have different requirements for the main control chip, mainly in two aspects: software requirements and hardware requirements. Software requirements primarily concern the power communication protocol. Although CPUs communicate with the main control chip via clock signals (CLK) and data (DATA), different platforms define different specifications for CLK and DATA. Therefore, even the same CLK and DATA waveforms convey different information. For Intel platforms, the main control chip needs to support SVID (SVID Power Management Protocol), while AMD platforms require support for the SVI3 protocol, and the Ampere platform requires support for the AVSBUS protocol. Currently, different platforms require different main control chips for design, making multi-platform compatibility impossible. This means that if a platform only supports one power communication protocol, it cannot meet the needs of multi-protocol, multi-platform operation. Furthermore, current software and hardware designs for single-platform main control chips result in high design complexity and low flexibility. Summary of the Invention

[0006] In view of this, this application provides a CPU power supply circuit, power supply method and main control chip to solve the problems of low design flexibility and poor procurement caused by the need to use different power supply chips due to different CPU power protocols.

[0007] In a first aspect, this application provides a CPU power supply circuit, which includes: a main control chip, a CPU, and a power conversion circuit, wherein the main control chip integrates the code of at least two power communication protocols and is configured to provide the CPU with communication functions of multiple power communication protocols.

[0008] The main control chip is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and communicate with the CPU according to the currently available communication protocol;

[0009] The main control chip is also configured to receive voltage regulation instructions from the CPU during communication, generate modulation signals according to the voltage regulation instructions, and send the modulation signals to the power conversion circuit.

[0010] The power conversion circuit is configured to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to power the CPU.

[0011] The CPU power supply circuit provided in this paper features a main control chip with an internally adjustable code chip. It integrates code for at least two power communication protocols, supporting multiple power communication protocols. Based on the CPU type, it determines the currently available communication protocol from among these protocols and communicates with the CPU according to the available protocol. This design improves design flexibility and the reusability of schematics across different platforms. By adjusting the chip's software and hardware design, a single power chip becomes compatible with multiple platform processors, thus solving the problems of low design flexibility and high design complexity caused by requiring different power chips for different processors.

[0012] In conjunction with the first aspect, in one possible implementation, the main control chip is further configured to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is configured to indicate the currently used power communication protocol.

[0013] In conjunction with the first aspect, in another possible implementation, the main control chip is connected to the CPU via multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin;

[0014] The main control chip is also configured to control the switching switch to turn on the communication link between the first pin and the CPU, and to turn off the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is configured to transmit data or signals of the currently available communication protocol.

[0015] In conjunction with the first aspect, in yet another possible implementation, the main control chip is also configured to transmit clock signals and digital signals on the communication link between the first pin and the CPU, according to currently available communication protocols.

[0016] In conjunction with the first aspect, in another possible implementation, the CPU power supply circuit further includes a baseboard management controller, which is connected to both the main control chip and the CPU.

[0017] The baseboard management controller is configured to communicate with the CPU, obtain the CPU type, and transmit indication information including the CPU type to the main control chip.

[0018] The main control chip is also configured to receive instruction information from the baseboard management controller, determine the CPU type based on the instruction information, and, after determining the currently available communication protocol based on the CPU type, return a message of selecting the power communication protocol to the baseboard management controller.

[0019] The baseboard management controller is also configured to receive selected messages and forward them to the CPU.

[0020] In conjunction with the first aspect, in another possible implementation, the power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal, and a pulse width modulation terminal; wherein the voltage input terminal is connected to the power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip.

[0021] The main control chip is also configured to send an enable signal to the enable terminal of the power conversion circuit and a modulation signal to the pulse width modulation terminal.

[0022] The power conversion circuit is also configured to adjust the voltage according to the enable signal and the modulation signal, and output the adjusted voltage to the CPU.

[0023] In conjunction with the first aspect, in another possible implementation, the power conversion circuit further includes a third pin and a fourth pin, both of which are connected to the main control chip;

[0024] The power conversion circuit is also configured to transmit the collected CPU current information to the main control chip via the third pin, and to transmit the collected CPU temperature information to the main control chip via the fourth pin.

[0025] The main control chip is also configured to receive and detect whether one or more of the current and temperature information are within a preset value range, and if they are within the preset value range, to send a command to the CPU indicating that the voltage regulation is complete.

[0026] Optionally, at least two power communication protocols may be included, including at least two of SVID, SVI3, and AVSBUS.

[0027] Secondly, this application provides a CPU power supply method, which is applied to the CPU power supply circuit of the first aspect or any embodiment of the first aspect, and the method includes:

[0028] Get CPU type;

[0029] Based on the CPU type, determine the currently available communication protocol from at least two power communication protocols, and communicate with the CPU according to the currently available communication protocol;

[0030] During communication, the system receives voltage regulation instructions from the CPU, generates a modulation signal based on the voltage regulation instructions, and sends the modulation signal to the power conversion circuit. The power conversion circuit is configured to adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

[0031] In conjunction with the second aspect, in one possible implementation, the method further includes: after determining the currently available communication protocol, updating the bit identifier corresponding to the currently available communication protocol, wherein the bit identifier has a unique correspondence with the currently available communication protocol and is configured to indicate the currently used power communication protocol.

[0032] In conjunction with the second aspect, in another possible implementation, the main control chip is connected to the CPU via multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin, and the method further includes:

[0033] The control switch connects the communication link between the first pin and the CPU, and disconnects the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is configured to transmit data or signals of the currently available communication protocol.

[0034] In conjunction with the second aspect, in another possible implementation, communication with the CPU is performed according to currently available communication protocols, including: transmitting clock signals and digital signals on the communication link between the first pin and the CPU according to currently available communication protocols.

[0035] Thirdly, this application also provides a main control chip, which includes: a communication module, a computing module, and a driver module; wherein the computing module is connected to the communication module and the driver module respectively, the communication module is connected to an external baseboard management controller and a CPU respectively, and the driver module is also connected to the CPU.

[0036] The communication module integrates code for at least two power communication protocols and is configured to provide the CPU with communication functions for multiple power communication protocols.

[0037] The communication module is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol.

[0038] The computing module is configured to receive voltage regulation instructions from the CPU during communication, generate drive instructions based on the voltage regulation instructions, and send the drive instructions to the drive module.

[0039] The driver module is configured to receive drive commands, generate modulation signals, and send the modulation signals to the power conversion circuit so that the power conversion circuit adjusts the external input voltage according to the modulation signals and outputs it to the CPU to power the CPU.

[0040] In conjunction with the third aspect, in one possible implementation, the communication module further includes a register configured to store at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0041] In conjunction with the third aspect, in another possible implementation, the communication module further includes multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin;

[0042] The first pin establishes a communication link with the CPU and is configured to communicate with the main control chip according to the currently available communication protocol.

[0043] The second pin establishes a communication link with the CPU and is configured to communicate with the main control chip according to other communication protocols. The other communication protocols are at least two power communication protocols other than the currently available communication protocols.

[0044] The toggle switch is configured to disconnect or connect the communication link.

[0045] Fourthly, this application also provides a communication module, which includes a receiving unit, a determining unit, and a sending unit. Optionally, the receiving unit is configured to receive indication information containing the CPU type sent by the board management controller; the determining unit is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type; and the sending unit is configured to send a selected message determining the currently available communication protocol through the board management controller to inform the CPU, so that the CPU can communicate with the communication module according to the currently available communication protocol.

[0046] This application provides a CPU power supply circuit, power supply method, and main control chip. By adjusting the chip software and hardware design, a single power supply chip can be made compatible with multiple platform processors, thereby solving the problem of low design flexibility and high design complexity caused by different processors requiring different power supply chips. Optionally, it includes the following beneficial effects:

[0047] The main control chip in this application adopts a flexible code chip architecture and pre-integrates code for at least two power communication protocols. This design enables the main control chip to intelligently select the optimal power communication protocol from multiple options based on the CPU type, and then communicate efficiently with the CPU according to the selected protocol. This not only improves communication flexibility but also significantly enhances the circuit's compatibility with different types of CPUs, realizing communication transmission using multiple power communication protocols on the main control chip.

[0048] The main control chip in this application achieves a rapid response to voltage regulation commands from the CPU. It can accurately parse the voltage regulation commands and generate precise modulation signals accordingly, which are then sent to the power conversion circuit to adjust the input voltage and provide a suitable output voltage for the CPU. This optimized process makes voltage regulation faster and more precise, effectively meeting the CPU's fine-grained requirements for power supply voltage under different workloads, and improving the CPU's performance stability and energy efficiency.

[0049] Furthermore, this method can adjust the output voltage in real time, providing a stable and reliable power supply to the CPU. Since the main control chip can intelligently select the optimal communication protocol based on the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, support for multiple power supply communication protocols increases the circuit's adaptability to complex environments and improves the overall system reliability.

[0050] In addition, power chips for SVID, SVI3 and AVSBUS protocols usually require three different models. This application uses a power control chip that is compatible with multiple protocols, reducing the number of material models from three to one, which is beneficial for procurement and preparation and reduces the risk of material stagnation or shortage. Attached Figure Description

[0051] To more clearly illustrate the optional embodiments of this application or the technical solutions in the prior art, the drawings used in the description of the optional embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0052] Figure 1 is a schematic diagram of a digital multiphase power supply scheme according to this application;

[0053] Figure 2a is a schematic diagram of communication between the INTEL platform CPU and the main control chip according to an embodiment of this application;

[0054] Figure 2b is a schematic diagram of communication between the AMD platform CPU and the main control chip according to an embodiment of this application;

[0055] Figure 3 is a schematic diagram of a multi-protocol integrated power control chip provided according to an embodiment of this application;

[0056] Figure 4 is a schematic diagram of a CPU power supply circuit according to an embodiment of this application;

[0057] Figure 5 is a schematic diagram of software-level compatibility according to an embodiment of this application;

[0058] Figure 6 is a schematic diagram of hardware functional compatibility according to an embodiment of this application;

[0059] Figure 7 is a schematic flowchart of a CPU power supply method according to an embodiment of this application;

[0060] Figure 8 is a structural block diagram of a communication module provided according to an embodiment of this application. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0064] The technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0065] The technical solutions provided in this application can be applied to CPU (Central Processing Unit) power supply scenarios. CPU power supply scenarios generally adopt digital multiphase power supply schemes, as shown in Figure 1, which is a schematic diagram of a digital multiphase power supply scheme.

[0066] The solution includes a CPU, a main control chip, and a power conversion module or power conversion chip. Since the CPU has high-performance and low-power modes, different operating voltages Vout need to be selected in different working scenarios. The voltage requirement is determined by the CPU and transmitted to the main control chip through clock signals and data signals to achieve real-time voltage adjustment.

[0067] Currently, different CPU platforms have different requirements for the main control chip, mainly in two aspects: software requirements and hardware requirements. The software requirements primarily concern the power communication protocol, which is incompatible with the power communication protocols of different platforms. For example, as shown in Figure 2a, on the Intel CPU platform, the XDPE1***4 chip is generally recommended as the main control chip. This chip supports Intel CPU's SVID (SVID Power Management Protocol) communication.

[0068] The SVID power management protocol is a communication protocol for power management. It defines the specifications for transmitting and interpreting power management-related information within a system, aiming to achieve power management across vendors. By providing rich functionality, high flexibility, and strong scalability, the SVID protocol helps improve energy efficiency, reduce power consumption, and simplify system integration and development processes. This protocol has wide applications in the field of power management, especially in systems requiring efficient and reliable power management.

[0069] The AMD (Advanced Micro Devices) CPU platform uses the XDPE1***3 chip as the main controller chip, as shown in Figure 2b. It supports the AMD SVI3 power protocol. In addition to the difference in power protocol, the two main controller chips also differ in the pin definitions.

[0070] Specifically, SV13 is an improved or upgraded version based on the SVID interface. AMD Serial VID Interface (SVID) is a communication interface between the AMD processor and the power management system, configured to implement voltage identification (VID) and power management functions. The SVID interface allows the processor to send its required voltage and current requirements to the power management system, enabling the system to adjust power supply parameters accordingly, thereby ensuring stable processor operation and efficient power consumption.

[0071] In AMD Ryzen 6000 series processors, SVI3 (System Voltage Interface 3) is an advanced technology configured to enable faster, more precise, and finer-grained platform-level power or power consumption control. SVI3 technology achieves more granular power management through improved system voltage interface design. It allows the processor to more accurately monitor and control voltage and current changes, thereby optimizing the balance between power consumption and performance. In high-performance computing, SVI3 technology enables AMD Ryzen 6000 series processors to achieve better energy efficiency in these scenarios, as well as higher energy efficiency and lower operating costs in data center environments, resulting in longer battery life.

[0072] Currently, due to the different PIN definitions for the two types of main control chips, different platforms require different main control chips for design, making multi-platform compatibility impossible. This not only leads to high design complexity and low flexibility but also results in a large variety of materials to choose from, which is detrimental to material procurement.

[0073] To address the aforementioned issues, this application provides a CPU power supply design scheme that is compatible with multiple power protocols simultaneously. This involves integrating three power communication protocols—SVID, SVI3, and AVSBUS—into a single main control chip and adjusting the chip packaging design to allow one main power control chip to functionally replace three other main power control chips.

[0074] The technical solutions provided in the embodiments of the application will be described in detail below.

[0075] To meet the design requirements, two aspects of the communication module need to be addressed: one at the software level and the other at the hardware level. To ensure that a single main control chip can be compatible with multiple power communication protocols, improvements are necessary at both the software and hardware levels.

[0076] The software improvements include the need for compatibility design with three power protocols: SVID, SVI3, and AVSBUS. As shown in Figure 3, the communication module's hardware design involves changing from an ASIC architecture chip to an ARM architecture chip, which is a more flexible code-adjustable chip. Compared to ASIC architecture chips, ARM architecture chips allow for repeated programming and flexible code adjustments to achieve repeated switching between different protocols. Previously, ASIC architecture generally refers to chips with an application-specific integrated circuit (ASIC) hardware structure and organization that internally stores a certain power protocol and cannot be changed, thus only supporting a single platform.

[0077] Among them, ARM architecture, short for Advanced RISC Machine, is a processor design scheme. ARM architecture chips are widely used in mobile devices, IoT devices, servers, and data centers due to their low power consumption, high performance, flexibility, and scalability.

[0078] Then, the three power communication protocols, OTP (One-Time Programmable), are compressed to reduce the code space occupied by each protocol. The compressed code is then embedded into the memory space of the ARM architecture chip for later use, and a two-bit protocol setting register is defined in the memory space. The protocol selection register is placed in the memory space along with the communication protocol code and is specifically used to set which power communication protocol the current power controller chip will use.

[0079] It should be noted that the registers and the compressed protocol code can exist side by side. Regarding the storage method, the compressed protocol code can be stored in a portion of the communication module's storage resources, while the communication module's registers are used to store the two-bit protocol relationship, as shown in Table 1 below.

[0080] Referring to Figure 4, it is a schematic diagram of a CPU power supply circuit provided in an embodiment of this application. The CPU power supply circuit includes: a main control chip, a CPU, and a power conversion circuit. In addition, the power supply circuit may also include other modules or circuits, such as a BMC (Baseboard Management Controller). The main control chip is a flexibly adjustable code chip and integrates code for at least two power communication protocols, configured to provide the CPU with communication functions for multiple power communication protocols.

[0081] The main control chip is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol.

[0082] Optionally, at least two power communication protocols are included: SVID, SVI3, and AVSBUS. Among them, AVSBUS (Adaptive Voltage Scaling Bus) is a high-speed, point-to-point bus primarily configured to connect the CPU and the power supply to achieve efficient voltage regulation and power management, and is mainly used in scenarios requiring high performance, low power consumption, and precise power management.

[0083] Furthermore, AVSBUS aims to provide a mechanism that allows ASICs (Application-Specific Integrated Circuits), FPGAs (Field-Programmable Gate Arrays), or processors to change the voltage of their power supply by sending commands to the POL (Point-of-Load Converter). Additionally, AVSBUS supports reading back the voltage and current of the POL, enabling precise monitoring and management of the power supply subsystem. Through AVSBUS, digital multiphase controllers can be directly connected to the load to dynamically adjust voltage levels for efficiency savings.

[0084] Optionally, the main control chip is also configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and inform the CPU via the BMC, as well as communicate with the CPU according to the currently available communication protocol. For example, the current communication protocol could be one of SVID, SVI3, or AVSBUS. Furthermore, the communication module communicates with the CPU via CLK and DATA signals.

[0085] In addition, the main control chip is also configured to receive voltage regulation instructions from the CPU during communication, generate modulation signals according to the voltage regulation instructions, and send the modulation signals to the power conversion circuit.

[0086] The power conversion circuit is configured to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to power the CPU.

[0087] In addition, the aforementioned BMC is connected to the main control chip and the CPU respectively; it is configured to communicate with the CPU, obtain the CPU type, and transmit indication information containing the CPU type to the main control chip.

[0088] The main control chip is also configured to receive indication information from the BMC, determine the CPU type based on the indication information, and, after determining the currently available communication protocol based on the CPU type, return a message to the BMC to select the power communication protocol.

[0089] The BMC is also configured to receive selected messages and forward them to the CPU.

[0090] Optionally, the main control chip mentioned above includes: a communication module, a computing module, and a driver module. As shown in Figure 4, the connection relationships are as follows: the communication module is connected to both the BMC and the CPU, and the BMC and the CPU are connected via an I2C channel; the computing module is connected to both the communication module and the driver module, and the driver module is also connected to the CPU.

[0091] Furthermore, the calculation module is configured to receive voltage regulation instructions from the CPU during communication, generate drive instructions based on the voltage regulation instructions, and send them to the drive module. Additionally, the calculation module is responsible for collecting current, voltage, and temperature information from the power conversion chip for instruction calculation.

[0092] The driver module is configured to receive drive commands and generate and output modulated signals to the power conversion circuit according to the drive commands.

[0093] In one optional implementation of this embodiment, the communication module of the main control chip includes a register, as shown in Figure 5. The register stores at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0094] The protocol setting register sets different numbers to select different communication protocols. The selection method is shown in Table 1 below. Among them, 00 / 01 / 10 correspond to SVID / SVI3 / AVSBUS protocols respectively, and 11 represents that no communication protocol is selected.

[0095] Table 1

[0096] After the main control chip is designed, the protocol setting register is set to "11" by default. In the initial state, the power communication protocol recorded in the register is empty, indicating that the chip does not support any power protocol at this time. After the main control chip is soldered onto the PCB board, the BMC on the board will work first and detect which platform CPU solution is being used by the CPU on the current board.

[0097] Initialization process: The BMC communicates with the CPU via the I2C channel to detect the CPU type. The CPU reports its current platform to the BMC. If the BMC detects an Intel platform CPU, it informs the communication module via the PMBUS channel that the current CPU platform is Intel.

[0098] PMBUS, short for Power Management Bus, is an open standard digital power management protocol. The PMBUS protocol aims to facilitate communication with power converters or other devices by defining the transmission and physical interfaces as well as the command language.

[0099] The main control chip is also configured to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. This bit identifier has a unique correspondence with the currently available communication protocol and is configured to indicate the currently used power communication protocol.

[0100] One optional implementation is that the communication module determines, based on the currently acquired platform (e.g., Intel), that the power communication protocol supported by the current Intel CPU platform is the SVID communication protocol, i.e., the currently available communication protocol. After determining the currently available communication protocol, the register bit identifier is updated from empty to the target bit identifier, and the target bit identifier has a unique correspondence with the currently available communication protocol. For example, according to Table 1 above, "11" is updated to "00", where, in the SVID communication protocol scenario, the corresponding target bit identifier is "00".

[0101] As shown in Figure 4, once the communication protocol is selected, the main control chip informs the BMC, and the BMC notifies the CPU. After receiving the completion instruction, the CPU starts communicating with the power supply main control chip.

[0102] Optionally, the BMC communicates with the CPU via an I2C channel to obtain the CPU type and transmits the indication information containing the CPU type to the communication module of the main control chip via PMBUS. The communication module receives the indication information transmitted from the BMC, determines the currently available communication protocol based on the CPU type contained in the indication information, and returns the selected message to the BMC. The BMC receives the selected message sent by the communication module and forwards it to the CPU.

[0103] In an optional embodiment of this example, the process of communication between the power supply main control chip and the CPU includes:

[0104] The main control chip first retrieves the compressed code from the storage space, and then decompresses the code to obtain the source code of the SVID protocol, i.e., the decompressed file. Optionally, when the CPU is detected to be an Intel platform, the protocol setting register is changed to 00. At this time, the SVID code pre-stored in the storage space will be decompressed and the functional adaptation will be completed to achieve normal communication with the CPU.

[0105] The main control chip uses the decompressed source code to generate the corresponding DATA or CLK signal to confirm that the SVID protocol path is in the conducting state. Then, it uses the communication module to communicate with the CPU using CLK and digital signals according to the current SVID protocol.

[0106] If the protocol setting fails during programming, the software will display an error message to ensure that the correct communication protocol has been selected before the chip is installed on the board, preventing CPU malfunctions due to different communication protocols. In this embodiment, the main control chip supports multiple programming cycles, allowing for flexible switching between different protocols.

[0107] After resolving the software-level issues of the aforementioned communication module, hardware issues also need to be addressed. Currently, there are many differences in the pin functions of power controllers on different platforms. In order to achieve compatibility of a single chip with multiple platforms, hardware design compatibility must also be achieved.

[0108] To achieve this goal, this embodiment uses a multi-functional multiplexed pin design to ensure compatibility for different pins. That is, one channel can simultaneously support multiple pin functions. For example, all three power communication protocols require communication with the CPU via the CLK and DATA pins. However, designing separate CLK and DATA pins for each power protocol would result in a larger chip package. Furthermore, since only one power communication protocol is active during operation, the extra pins would be wasted. Therefore, the internal hardware circuitry is designed to be compatible with the requirements of different platform CPUs. As shown in Figure 6, the main control chip connects to the CPU through multiple pins and a switching switch. These multiple pins include at least a first pin and a second pin.

[0109] Furthermore, the main control chip is also configured to control the switching switch to connect the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is configured to transmit data or signals using currently available communication protocols (such as SVID). The communication link between the second pin and the CPU can be configured to transmit data or signals using SVI3 and AVSBUS protocols. Since the transmission of SVI3 and AVSBUS protocol signals is not currently required, these links are disconnected by the switching switch, and only the communication link for the data or signals currently required to be transmitted is connected.

[0110] In this embodiment, the main control chip can connect two communication links of the SVID protocol through the control unit, one for transmitting CLK1 and the other for transmitting DATA1, while disconnecting the communication links between the SVI3 and AVSBUS protocols and the CPU.

[0111] In this embodiment, when different power communication protocols are selected, the control unit closes the hardware switches of the corresponding CLK and DATA channels, and opens the switches of the other communication protocols, so that only two multi-function pins can replace the functions of six pins, thereby saving costs and simplifying the circuit.

[0112] The following explains the CPU power supply and voltage regulation process.

[0113] As shown in Figure 4, the CPU power supply circuit also includes a power conversion circuit, which includes a voltage input terminal Vout, a voltage output terminal Vin, an enable terminal (EN), and a PWM (Pulse Width Modulation) terminal. Furthermore, this power conversion circuit may include more or fewer pins, such as a third pin and a fourth pin, both of which are connected to the main control chip.

[0114] The voltage input terminal Vin is connected to an external power supply, the voltage output terminal Vout is connected to the CPU, and the enable terminal EN and the PWM terminal are connected to the drive module respectively.

[0115] Optionally, the third pin is the Imon pin and the fourth pin is the Tmon pin, and the third and fourth pins are respectively connected to the computing module.

[0116] The third pin is configured to acquire current information and transmit the current information to the computing module; similarly, the fourth pin can be configured to acquire CPU temperature information and report the acquired temperature information to the computing module.

[0117] The workflow is as follows: The CPU sends voltage regulation commands to the communication module via CLK and DATA, and the communication module sends the received voltage regulation commands to the computing module.

[0118] After receiving the voltage regulation command, the calculation module sets the PWM drive command to be executed and sends the drive command to the drive module.

[0119] After receiving the drive command, the drive module sends an enable signal (ENABLE) and a PWM signal to the power conversion circuit. The EN and PWM terminals of the power conversion circuit receive the enable and PWM signals respectively, adjust the output voltage Vout, and output Vout externally. A portion of Vout is configured to power the CPU, while the other portion is sampled and fed back to the calculation module to check if the voltage reaches the expected set value. If the calculation module detects that the output voltage Vout has reached the set value, it sends a voltage adjustment command to the communication module to complete the voltage adjustment process.

[0120] Optionally, the drive module is also configured to send an enable signal EN to the enable terminal of the power conversion circuit and a PWM drive signal to the PWM terminal. The power conversion circuit is configured to adjust the output voltage according to the enable signal ENABLE and the PWM drive signal, and transmit the adjusted output voltage to the CPU. The PWM drive signal is a modulation signal.

[0121] In addition, the power conversion circuit includes a third pin and a fourth pin, both of which are connected to the computing module. The power conversion circuit is also configured to transmit the acquired CPU current information to the main control chip via the third pin, and to transmit the acquired CPU temperature information to the main control chip via the fourth pin.

[0122] The main control chip is also configured to receive and detect whether one or more of the current and temperature information are within a preset range, and if they are within the preset range, to send a command to the CPU indicating that the voltage regulation is complete.

[0123] In this embodiment, hardware improvements to the main control chip enable multi-channel switching in the communication module. It should be understood that, besides the communication module, the PINs for the computing module and driver module, which differ across platforms, can be redesigned using multi-functional hardware PINs. Figure 6 shows the PIN definitions for the multi-protocol power control chip. PINs 1-17 are universal across the three platforms and have consistent definitions. PINs 18-24 are reused through multi-functional design as shown in Table 2 to achieve hardware compatibility across the three platforms. The feasibility of this solution has been verified through actual testing after tape-out. See Table 2 for details.

[0124] Table 2

[0125] The difference between APWM and BPWM is that a master control chip can support outputting a maximum of two different voltages, voltage A and voltage B, or it can output only one voltage. If all 12 channels are used to output voltage A, the PWM voltages can be represented as APWM1 to APWM12. If 6 of the 12 channels are used to output voltage A and the other 6 channels are used to output voltage B, then the voltages transmitted by the 6 channels are represented as APWM1 to APWM6, and the voltages transmitted by the other 6 channels are represented as BPWM1 to BPWM6.

[0126] Table 2 shows the hardware definition of the chip and the connection relationship of PIN multiplexing when selecting three power communication protocols under three platforms. This is used to implement the multi-functional multiplexing design in hardware. Combined with the above-mentioned software improvements, the goal is to achieve the beneficial effect of a single power chip being compatible with processors on multiple platforms.

[0127] The main control chip provided in this embodiment adopts a flexible code chip architecture in its software design and pre-integrates code for at least two power communication protocols, which are selected through a protocol setting register. At the hardware level, hardware compatibility of the three protocols is achieved through the design of a multi-functional multiplexed PIN. The chip design is based on the theoretical design at both the software and hardware levels, and the feasibility of the scheme is verified through on-chip testing. This not only improves communication flexibility but also significantly enhances the circuit's compatibility with different types of CPUs, realizing communication transmission of multiple power communication protocols on the main control chip.

[0128] This application achieves a rapid response to voltage regulation commands from the CPU, accurately parsing the commands and generating precise modulation signals, which are then sent to the power conversion circuit to adjust the input voltage and provide the CPU with a suitable output voltage. This optimized process makes voltage regulation faster and more precise, effectively meeting the CPU's fine-grained power supply voltage requirements under different workloads, and improving the CPU's performance stability and energy efficiency.

[0129] Furthermore, this method can adjust the output voltage in real time, providing a stable and reliable power supply to the CPU. Since the main control chip can intelligently select the optimal communication protocol based on the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, support for multiple power supply communication protocols increases the circuit's adaptability to complex environments and improves the overall system reliability.

[0130] In addition, normally three different models of power chips are required for SVID, SVI3 and AVSBUS protocols. This application uses a power control chip that is compatible with multiple protocols, reducing the number of material models from three to one, which is beneficial for procurement and preparation and reduces the risk of material stagnation or shortage.

[0131] This application provides an embodiment of a CPU power supply method. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0132] This embodiment provides a CPU power supply method, which can be used in the main control chip of the above embodiments. Figure 7 is a flowchart of the CPU power supply method according to an embodiment of this application. The method includes:

[0133] Step S101: Obtain CPU type.

[0134] The CPU type can be obtained by the main control chip based on the indication information containing the CPU type sent by the BMC.

[0135] Step S102: Determine the currently available communication protocol from at least two power communication protocols based on the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0136] Step S103: During the communication process, receive the voltage regulation command from the CPU, generate the modulation signal according to the voltage regulation command, and send the modulation signal to the power conversion circuit.

[0137] The power conversion circuit is configured to adjust the external input voltage according to the modulation signal and output it to the CPU to power the CPU.

[0138] In addition, the method in this embodiment also includes: after the CPU receives the selected message, the CPU communicates with the communication module according to the currently available communication protocol.

[0139] In step S102 above, after the main control chip determines the currently available communication protocol, it updates the bit identifier corresponding to the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is configured to indicate the power communication protocol currently being used.

[0140] The aforementioned correspondence can be stored in the register of the communication module. Initially, the power communication protocol recorded in the register is empty; after determining the currently available communication protocol, the register's identifier is updated from empty to the target bit identifier, and the target bit identifier has a unique correspondence with the currently available communication protocol.

[0141] In another possible implementation, the main control chip is connected to the CPU via multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin. The method of this embodiment further includes:

[0142] The main control chip controls the switching switch to turn on the communication link between the first pin and the CPU, and to turn off the communication link between the second pin and the CPU. The communication link between the first pin and the CPU is configured to transmit data or signals of the currently available communication protocol, and the second pin or other pins are configured to establish a communication link with the CPU using the SVI3 and / or AVSBUS protocols.

[0143] The CPU communicates with the communication module according to the currently available communication protocol, including transmitting clock signals and digital signals on the communication link between the first pin and the CPU according to the currently available communication protocol.

[0144] Optionally, the detailed process of the above method can be found in the foregoing embodiments, and will not be repeated here.

[0145] This embodiment also provides a communication module configured to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0146] This embodiment provides a communication module, as shown in FIG8. The communication module includes a receiving unit 810, a determining unit 820, and a sending unit 830. In addition, the communication module may include other more or fewer modules, such as a storage module, etc. This embodiment does not limit this.

[0147] The receiving unit 810 is configured to receive indication information containing the CPU type sent by the baseboard management controller, and to obtain the CPU type based on the indication information.

[0148] The determination unit 820 is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol.

[0149] Optionally, the sending unit 830 is configured to send a selected message of the currently available communication protocol to the CPU via the BMC, so that the CPU can communicate with the communication module according to the currently available communication protocol, and to power the CPU using the computing module and the driver module.

[0150] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0151] In this embodiment, the communication module is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0152] This application embodiment also provides a main control chip having the communication modules shown in Figures 4, 5, 6 and 8 above.

[0153] Optionally, as shown in Figure 4, the main control chip includes: a communication module, a computing module, and a driver module; wherein the computing module is connected to the communication module and the driver module respectively, the communication module is connected to the external BMC and the CPU respectively, and the driver module is also connected to the CPU.

[0154] The communication module is a flexibly adjustable code chip, such as an ARM architecture chip circuit. The communication module has pre-embedded code for at least two power communication protocols and is configured to provide multi-power communication functionality for the computing module. The communication module is configured to execute the CPU power supply method shown in Figure 7.

[0155] Optionally, the communication module is configured to determine the currently available communication protocol among at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol.

[0156] The computing module is configured to receive voltage regulation instructions from the CPU during communication, generate drive instructions based on the voltage regulation instructions, and send the drive instructions to the drive module.

[0157] The driver module is configured to receive drive commands, generate modulation signals, and send the modulation signals to the power conversion circuit so that the power conversion circuit adjusts the external input voltage according to the modulation signals and outputs it to the CPU to power the CPU.

[0158] Furthermore, the communication module also includes a register configured to store at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0159] Furthermore, the communication module provided in this embodiment also includes: multiple pins and a switching switch. The multiple pins include at least a first pin and a second pin. The first pin establishes a communication link with the CPU and is configured to communicate with the main control chip according to the currently available communication protocol. The second pin establishes a communication link with the CPU, and this link is configured to communicate with the main control chip according to another communication protocol, which is a protocol other than the currently available communication protocol among at least two power communication protocols. The switching switch is configured to disconnect or connect at least one communication link.

[0160] The functions of each module are described in the foregoing embodiments and will not be repeated here.

[0161] Furthermore, in this embodiment, the CPU can be a central processing unit. The CPU may further include a hardware chip. This hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device can be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPRS), or any combination thereof.

[0162] In the communication module, the computing module can also be a processing circuit or processing module, and can be a programmable logic device or a complex programmable logic device.

[0163] In addition, the communication module also includes a storage module or storage unit, which may include a stored program area and a stored data area. The stored program area may store the operating system and applications required for at least one function; the stored data area may store data created based on the use of the computer device, etc. Furthermore, the storage module or storage unit may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device.

[0164] In addition, the registers in the communication module may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive.

[0165] In addition, the aforementioned main control chip also includes multiple pins or terminals, and at least one communication interface configured to communicate with other devices or modules.

[0166] This application also provides a computer non-volatile readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and to be stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a special-purpose processor, or programmable or special-purpose hardware.

[0167] The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; furthermore, the storage medium can also include combinations of the above types of memory. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0168] Embodiments of this application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the methods described above. The computer program product may be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code may execute entirely on a user's computing device, partially on a user's device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0169] The above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A power supply circuit for a central processing unit (CPU), characterized in that, The CPU power supply circuit includes a main control chip, a CPU, and a power conversion circuit, wherein; The main control chip integrates code for at least two power communication protocols and is configured to provide the CPU with communication functions for multiple power communication protocols. The main control chip is configured to determine the currently available communication protocol from at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol. The main control chip is also configured to receive voltage regulation instructions from the CPU during communication, generate a modulation signal according to the voltage regulation instructions, and send the modulation signal to the power conversion circuit. The power conversion circuit is configured to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to power the CPU.

2. The CPU power supply circuit according to claim 1, characterized in that, The main control chip is further configured to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique correspondence with the currently available communication protocol and is used to indicate the power communication protocol currently being used.

3. The CPU power supply circuit according to claim 1, characterized in that, The main control chip is connected to the CPU through multiple pins and a switching switch, and the multiple pins include at least a first pin and a second pin. The main control chip is also configured to control the switching switch to turn on the communication link between the first pin and the CPU, and to turn off the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is configured to transmit data or signals of the currently available communication protocol.

4. The CPU power supply circuit according to claim 3, characterized in that, The main control chip is also configured to transmit clock signals and digital signals on the communication link between the first pin and the CPU in accordance with the currently available communication protocol.

5. The CPU supply circuit according to any one of claims 1 to 4, characterized by The CPU power supply circuit also includes a baseboard management controller, which is connected to the main control chip and the CPU respectively; The baseboard management controller is configured to communicate with the CPU, obtain the CPU type, and transmit indication information containing the CPU type to the main control chip. The main control chip is also configured to receive the indication information from the baseboard management controller, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of selecting the power communication protocol to the baseboard management controller. The baseboard management controller is also configured to receive the selected message and forward it to the CPU.

6. The CPU supply circuit of claim 1, wherein The power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal, and a pulse width modulation terminal; wherein the voltage input terminal is connected to the power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip. The main control chip is also configured to send an enable signal to the enable terminal of the power conversion circuit and to send the modulation signal to the pulse width modulation terminal. The power conversion circuit is further configured to adjust the voltage according to the enable signal and the modulation signal, and output the adjusted voltage to the CPU.

7. The CPU supply circuit according to claim 6, wherein The power conversion circuit also includes a third pin and a fourth pin, both of which are connected to the main control chip; The power conversion circuit is also configured to transmit the collected CPU current information to the main control chip via the third pin, and to transmit the collected CPU temperature information to the main control chip via the fourth pin. The main control chip is also configured to receive and detect whether one or more of the current information and temperature information are within a preset value range, and if the preset value range is met, to send a voltage regulation completion instruction to the CPU.

8. The CPU power supply circuit according to claim 6, characterized in that, The at least two power communication protocols include at least two of the following: System Voltage Identifier Power Management Protocol (SVID), System Voltage Interface (SVI3), and AVSBUS.

9. A CPU power supply method characterized by comprising: The method is applied to a main control chip as described in any one of claims 1 to 8, wherein the main control chip integrates code for at least two power communication protocols to provide the CPU with communication functions for multiple power communication protocols, and the method includes: Get CPU type; Based on the CPU type, determine the currently available communication protocol from at least two power communication protocols, and communicate with the CPU according to the currently available communication protocol; During communication, the system receives a voltage adjustment command from the CPU, generates a modulation signal based on the voltage adjustment command, and sends the modulation signal to the power conversion circuit. The power conversion circuit is used to adjust the external input voltage according to the modulation signal and output it to the CPU to supply power to the CPU.

10. The method according to claim 9, characterized in that, The method further includes: After determining the currently available communication protocol, the bit identifier corresponding to the currently available communication protocol is updated. The bit identifier has a unique correspondence with the currently available communication protocol and is configured to indicate the currently used power communication protocol.

11. The method of claim 9, wherein, The main control chip is connected to the CPU via multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin, and the method further includes: The switch controls the connection between the first pin and the CPU to be turned on, and the connection between the second pin and the CPU to be turned off, wherein the connection between the first pin and the CPU is configured to transmit data or signals of the currently available communication protocol.

12. The method of claim 11, wherein, The communication with the CPU according to the currently available communication protocol includes: According to the currently available communication protocol, clock signals and digital signals are transmitted on the communication link between the first pin and the CPU.

13. A master chip, comprising: The main control chip includes: a communication module, a computing module, and a driver module; wherein the computing module is connected to the communication module and the driver module respectively, the communication module is connected to an external baseboard management controller and a CPU respectively, and the driver module is also connected to the CPU; The communication module integrates code for at least two power communication protocols and is configured to provide the CPU with communication functions for multiple power communication protocols. The communication module is configured to determine the currently available communication protocol from at least two power communication protocols based on the CPU type, and to communicate with the CPU according to the currently available communication protocol. The computing module is configured to receive a voltage adjustment instruction from the CPU during communication, generate a driving instruction based on the voltage adjustment instruction, and send the driving instruction to the driving module. The driving module is configured to receive the driving instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit so that the power conversion circuit adjusts the external input voltage according to the modulation signal and outputs it to the CPU to power the CPU.

14. The main control chip according to claim 13, characterized in that, The communication module also includes a register configured to store at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

15. The main control chip according to claim 13 or 14, characterized in that, The communication module also includes multiple pins and a switching switch, wherein the multiple pins include at least a first pin and a second pin; The first pin establishes a communication link with the CPU and is configured to communicate with the main control chip according to the currently available communication protocol. The second pin establishes a communication link with the CPU and is configured to communicate with the main control chip according to other communication protocols, wherein the other communication protocols are protocols other than the currently available communication protocols among at least two power communication protocols. The switch is configured to disconnect or connect the communication link.

16. The main control chip according to claim 15, characterized in that, The communication module includes a storage unit, which includes a program storage area and a data storage area. The program storage area is configured to store applications required by the operating system.

17. The main control chip according to claim 16, characterized in that, The storage unit includes high-speed random access memory or non-transient memory.

18. The master chip of claim 16, wherein, The main control chip also includes a communication interface, through which the main control chip communicates with other devices or modules.

19. The main control chip according to claim 14, wherein the communication module is configured to update the bit identifier of the register from empty to the target bit identifier after determining the currently available communication protocol, wherein, The target bit identifier has a unique correspondence with the currently available communication protocol.

20. The main control chip according to claim 13, characterized in that, The communication module receives indication information transmitted from the baseboard management controller and determines the currently available communication protocol based on the CPU type contained in the indication information.

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