Self-test method, integrated circuit, chip, sensor, and device

Abstract

The present application relates to the technical field of digital chips, and discloses a self-test method, an integrated circuit, a chip, a sensor, and a device. The self-test method of the present application comprises: after a power-on phase and before a startup phase of an integrated circuit, performing a first logic built-in self-test; and before a first operation phase of the integrated circuit, performing a second logic built-in self-test, the first operation phase being after the startup phase. In embodiments of the present application, before each of a startup stage and an operation stage, a corresponding logic built-in self-test is performed, so that it is ensured that a corresponding logic built-in self-test of an automotive grade chip is completed before each stage, thereby improving the operating efficiency of the automotive grade chip, and saving the startup time of the automotive grade chip; additionally, a logic built-in self-test is performed by means of a self-test function inside the automotive grade chip, so that it is unnecessary to change the circuit structure inside the chip or an algorithm, and the costs and the accuracy of the self-test of the automotive grade chip are also considered.

Description

Self-testing methods, integrated circuits, chips, sensors and devices Cross-reference to related applications

[0001] This application is based on and claims priority to Chinese Patent Application No. 2024119453492, filed on December 26, 2024, entitled "Self-Detection Method, Integrated Circuit, Chip, Sensor and Device", the entire contents of which are hereby incorporated herein by reference. Technical Field

[0002] This application relates to the field of digital chip technology, and in particular to a self-testing method, integrated circuit, chip, sensor and device. Background Technology

[0003] Currently, in order to meet functional safety requirements, automotive-grade chips require each functional module to be designed with a power-on self-test after startup. With the increase in chip size and design complexity, the amount of power-on self-test data has increased dramatically, which has led to a sharp increase in power-on self-test time. The power-on self-test time is included in the chip startup time, resulting in a longer startup time for automotive-grade chips.

[0004] In related technologies, the following two methods are commonly used to reduce the startup time of automotive-grade chips. One is to use more complex compression circuits to reduce test time by increasing test parallelism. However, this method will have greater circuit overhead, leading to an increase in the area of ​​automotive-grade chips and higher production costs. The other is to use test algorithms with reduced complexity to reduce test time by generating less test data. However, this method has lower accuracy. Neither of the above two methods can balance the cost of automotive-grade chips with the accuracy of self-testing. Summary of the Invention

[0005] The purpose of this application is to provide a self-testing method, integrated circuit, chip, sensor, and device, thereby balancing the cost of automotive-grade chips with the accuracy of self-testing.

[0006] To address the aforementioned technical problems, embodiments of this application provide a self-testing method applied to an integrated circuit. The method includes: performing a first logic built-in self-test after the power-on phase and before the startup phase of the integrated circuit; and performing a second logic built-in self-test before the first operating phase of the integrated circuit, wherein the first operating phase is after the startup phase.

[0007] Embodiments of this application also provide an integrated circuit, including: a first circuit, a second circuit, a first self-test circuit, and a second self-test circuit; the first circuit is configured to operate during a startup phase; the second circuit is configured to operate during a first operating phase; the first operating phase occurs after the startup phase; the first self-test circuit is configured to perform a first logic built-in self-test on the first circuit after a power-on phase and before the startup phase; the second self-test circuit is configured to perform a second logic built-in self-test on the second circuit before the first operating phase.

[0008] An embodiment of this application also provides a radar chip, including the aforementioned integrated circuit.

[0009] Embodiments of this application also provide a radar sensor, including: a carrier; an integrated circuit as described above, disposed on the carrier; an antenna, disposed on the carrier, or the antenna and the integrated circuit are integrated into a single device disposed on the carrier; wherein the integrated circuit is connected to the antenna and is used to transmit radio frequency transmission signals and / or receive radio frequency reception signals.

[0010] An embodiment of this application also provides an electronic device, including: a device body; and the aforementioned radar sensor disposed on the device body; wherein the radar sensor is used to provide measurement information.

[0011] The technical solution provided in this application has at least the following advantages: This application's embodiments complete the built-in logic self-test for each stage (including the startup stage and the running stage) before the start of each stage. This ensures that the automotive-grade chip has completed the corresponding built-in logic self-test before each stage without affecting the normal operating sequence of the automotive-grade chip, thus improving the efficiency of the automotive-grade chip's operation and saving startup time. Simultaneously, this application's embodiments perform built-in logic self-tests through the self-test function within the automotive-grade chip, without changing the chip's internal circuit structure or algorithm. This ensures low cost for automotive-grade chip self-testing and guarantees the accuracy of the built-in logic self-testing. By balancing the cost of automotive-grade chips with the accuracy of self-testing, the startup time of automotive-grade chips is reduced. Attached Figure Description

[0012] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0013] Figure 1 is a detailed flowchart of a self-testing method according to an embodiment of the present application; Figure 2 is a timeline diagram of a self-testing method according to an embodiment of the present application; Figure 3 is a structural block diagram of a self-testing system according to an embodiment of the present application; Figure 4 is a detailed flowchart of a self-testing method according to another embodiment of the present application; Figure 5 is a timeline diagram of a self-testing method according to another embodiment of the present application; Figure 6 is a circuit structure diagram of an integrated circuit according to an embodiment of the present application. Detailed Implementation

[0014] As can be seen from the background technology, the relevant technologies cannot reduce the startup time of automotive-grade chips while taking into account both the cost of automotive-grade chips and the accuracy of self-testing.

[0015] To address the aforementioned technical issues, embodiments of this application perform a first built-in self-test (BIST) after the power-on phase and before the boot phase of the integrated circuit; and a second built-in self-test (BIST) before the first operating phase of the integrated circuit, thereby reducing the boot time of automotive-grade chips while considering both the cost of automotive-grade chips and the accuracy of self-tests.

[0016] The time period of the second built-in logic self-test (BIST) in this embodiment overlaps with the time period of the boot phase, which may be partially or completely overlapped. By running the boot phase of the automotive-grade chip and the second built-in logic self-test in parallel, the boot time of the automotive-grade chip is further reduced. This embodiment also performs the (N+1)th built-in logic self-test (BIST) before the Nth operating phase of the integrated circuit, where N is a natural number greater than 1. The Nth operating phase follows the (N-1)th operating phase. By performing the corresponding built-in logic self-test (BIST) before the corresponding operating phase, the BIST is performed without affecting the normal operating sequence of the automotive-grade chip. This ensures that the automotive-grade chip has completed the corresponding built-in logic self-test (BIST) before each operating phase, improving the operating efficiency of the automotive-grade chip.

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0018] Some embodiments of this application relate to a self-detection method, the specific flowchart of which is shown in Figure 1. The self-detection method includes the following steps:

[0019] Step 101: Perform the first logic built-in self-test after the power-on phase of the integrated circuit and before the startup phase.

[0020] Step 102: Before the first operating phase of the integrated circuit, perform a second logic built-in self-test. The first operating phase is after the startup phase.

[0021] Specifically, the embodiments of this application are applied to integrated circuits. The integrated circuit can be housed in automotive-grade chips and is used to run during the startup of the automotive-grade chip. The operation process of the integrated circuit can be divided into a power-on phase, a startup phase, and a first running phase. The embodiments of this application may also include multiple running phases, such as a second running phase, a third running phase, etc., mainly set according to actual needs, and the embodiments of this application do not impose specific limitations. Each running phase is a function running (Fuc Running), representing the process of the integrated circuit running after the startup phase is completed.

[0022] The integrated circuit in this application embodiment also performs multiple built-in logic self-tests (BISTs), such as a first built-in logic self-test BIST and a second built-in logic self-test BIST. Built-in logic self-tests are a technique that embeds relevant functional circuits into the circuit during the design phase to provide self-test functionality, thereby reducing the reliance of device testing on automatic test equipment (ATE). It should be noted that the first built-in logic self-test BIST in this application embodiment performs a self-test on the circuit running in the startup phase, and the second built-in logic self-test BIST performs a self-test on the circuit running in the first operating phase. It is sufficient to ensure that the self-test process of the corresponding built-in logic self-test BIST is completed before each phase.

[0023] In some embodiments, the time period of the second logic built-in self-test (BIST) overlaps with the time period of the startup phase (BOOT), and the overlap can be complete or partial.

[0024] Figure 2 shows a timeline diagram of the self-test method corresponding to an embodiment of this application. The power-on stage is marked as Power-on, the startup stage is marked as BOOT, the first running stage is Fuc Running1, the first logic built-in self-test is marked as BIST1, and the second logic built-in self-test is marked as BIST2. BIST1 is located between Power-on and BOOT, and BIST2 overlaps with BOOT. The figure shows BIST2 and BOOT completely overlapping. In other implementations, BIST2 and BOOT may only partially overlap, or BIST2 may also be located between Power-on and BOOT.

[0025] Figure 3 shows a structural block diagram of the self-test system according to an embodiment of this application. The self-test system includes an IO (Input / Output) interface, an AUX (Auxiliary Multiplexer Logic), an FSM (Finite State Machine), a Bist Controller (built-in self-test controller), a BOOT module, and a BIST module. The four transmission channels between the FSM and the Bist Controller are used to transmit enable, reset, clk, and fail-flag signals, respectively. The BOOT module connected to the FSM can perform both BOOT and BIST functions, and the Bist Controller can connect to at least one BIST module.

[0026] During the built-in self-test, the FSM transitions from the IDLE state to the INIT state. The BIST Controller receives the enable signal, and the AUX multiplexing logic selects the test port, switching the memory's I / O interface from the functional path to the BIST test path. At this point, the memory's address / data input is taken over by the BIST Controller. Subsequently, the BIST Controller drives the FSM state machine to precisely flow according to the test algorithm and coordinates the synchronous operation of each submodule.

[0027] Referring again to Figure 2, in this embodiment of the application, after the power-on phase is completed, the Bist Controller first controls one BIST module to execute BIST1; then, the Bist Controller controls the BOOT module to execute the BOOT function, and at the same time, the Bist Controller controls another BIST module to execute BIST2.

[0028] In some embodiments, the integrated circuit has N operating stages, where N is a natural number greater than 1, such as a first operating stage, a second operating stage, a third operating stage, and so on. Each operating stage corresponds to a built-in logic self-test BIST, namely the second built-in logic self-test BIST, the third built-in logic self-test BIST, the fourth built-in logic self-test BIST, and so on. Before the Nth operating stage of the integrated circuit, the (N+1)th built-in logic self-test BIST is performed, where N is a natural number greater than 1. The Nth operating stage is after the (N-1)th operating stage. That is, before each operating stage, the self-test process of the built-in logic self-test BIST corresponding to each operating stage is completed. For ease of description, this application embodiment uses an integrated circuit with 3 operating stages as an example for illustration. In this case, the specific flowchart of the self-test method is shown in Figure 4. The self-test method includes the following steps:

[0029] Step 201: Perform the first logic built-in self-test after the power-on phase of the integrated circuit and before the startup phase.

[0030] Step 202: Before the first operating phase of the integrated circuit, perform a second logic built-in self-test. The first operating phase is after the startup phase.

[0031] Steps 201 and 202 are largely the same as steps 101 and 102 above, and will not be repeated here to avoid repetition.

[0032] Step 203: Before the second operating phase of the integrated circuit, a third logic built-in self-test is performed. The second operating phase is after the first operating phase.

[0033] In some embodiments, the time period of the third logic built-in self-test BIST overlaps with the time period of the first running phase, which may be a complete overlap or a partial overlap; in other embodiments, the third logic built-in self-test BIST is performed during the time interval between the BOOT phase and the first running phase, or the time period of the third logic built-in self-test BIST overlaps with the time period of the BOOT phase, which may be a complete overlap or a partial overlap.

[0034] Step 204: Before the third operating phase of the integrated circuit, perform the fourth logic built-in self-test. The third operating phase is after the second operating phase.

[0035] In some embodiments, after the second running phase, a fourth logical built-in self-test (BIST) is performed, i.e., the fourth logical built-in self-test BIST runs during the time interval between the second and third running phases. In other embodiments, the time period of the fourth logical built-in self-test BIST may overlap with the time period of the BOOT phase (including full or partial overlap), or the fourth logical built-in self-test BIST may be performed during the time interval between the BOOT phase and the first running phase, or the time period of the fourth logical built-in self-test BIST may overlap with the time period of the first running phase (including full or partial overlap), or the fourth logical built-in self-test BIST may be performed during the time interval between the first and second running phases, or the time period of the fourth logical built-in self-test BIST may overlap with the time period of the second running phase (including full or partial overlap).

[0036] Figure 5 shows a timeline diagram of a self-testing method according to an embodiment of this application. The power-on stage is marked as Power-on, the startup stage is marked as BOOT, the first running stage is Fuc Running1, the second running stage is Fuc Running2, the third running stage is Fuc Running3, the first logic built-in self-test is marked as BIST1, the second logic built-in self-test is marked as BIST2, the third logic built-in self-test is marked as BIST3, and the fourth logic built-in self-test is marked as BIST4. Among them, BIST1 is located between Power-on and BOOT, BIST2 overlaps with BOOT, BIST3 overlaps with Fuc Running1, and BIST4 is located in the time interval between Fuc Running2 and Fuc Running3. The figure illustrates that all overlaps are shown in the figure. It can be understood that BIST2 and BOOT may also partially overlap, and BIST3 and Fuc Running1 may also partially overlap.

[0037] Referring again to Figure 3, in this embodiment, after the power-on phase is completed, the Bist Controller first controls one BIST module to execute BIST1; then, the Bist Controller controls the BOOT module to execute the BOOT function, and at the same time, the Bist Controller controls another BIST module to execute BIST2; then, during the first running phase Fuc Running1, the Bist Controller controls another BIST module to execute BIST3; after the second running phase Fuc Running2 ends, the Bist Controller controls yet another BIST module to execute BIST4.

[0038] In other embodiments, BIST4 may overlap with BOOT (including full or partial overlap), or BIST4 may be performed during the time interval between BOOT and Fuc Running1, or BIST4 may overlap with Fuc Running1 (including full or partial overlap), or BIST4 may be performed during the time interval between Fuc Running1 and Fuc Running2, or BIST4 may overlap with Fuc Running2 (including full or partial overlap).

[0039] This application embodiment completes the built-in logic self-test (BIST) for each stage (including the BOOT and running stages) before the start of each stage. This BIST is performed without affecting the normal operating sequence of the automotive-grade chip, ensuring that the corresponding built-in logic BIST is completed before each stage. This improves the efficiency of the automotive-grade chip's operation and saves startup time. Furthermore, this application embodiment utilizes the chip's internal self-test function for the built-in logic BIST, without altering the chip's internal circuit structure or algorithm. This ensures low cost for self-testing and guarantees the accuracy of the built-in logic BIST. By balancing the cost and accuracy of self-testing, the startup time of the automotive-grade chip is reduced.

[0040] Another aspect of this application embodiment also provides an integrated circuit, as shown in FIG6, which is a schematic diagram of the structure of the integrated circuit of this application embodiment. The integrated circuit 30 includes: a first circuit 311, a second circuit 321, a first self-test circuit 312, and a second self-test circuit 322.

[0041] The first circuit 311 of this application embodiment is used to operate in the startup phase; the second circuit 321 is used to operate in the first running phase; the first running phase is after the startup phase; the first self-test circuit 312 is used to perform a first logic built-in self-test (BIST) on the first circuit 311 after the power-on phase and before the startup phase; the second self-test circuit 322 is used to perform a second logic built-in self-test (BIST) on the second circuit 321 before the first running phase.

[0042] Specifically, after the integrated circuit 30 is powered on and before the boot phase, the first self-test circuit 312 performs a first logic built-in self-test (BIST). The first self-test circuit 312 corresponds to the first circuit 311 used by the integrated circuit 30 during the boot phase. The first logic built-in self-test (BIST) is a self-test function embedded in the design of the first self-test circuit 312.

[0043] During the startup phase of integrated circuit 30, the second self-test circuit 322 performs a second logic built-in self-test (BIST) on the second circuit 321. That is, the time period of the second logic built-in self-test overlaps with the time period of the startup phase, specifically, it can overlap completely or partially. In other embodiments, the second logic built-in self-test (BIST) can be performed on the second circuit 321 between the power-on phase and the startup phase of integrated circuit 30. That is, the second logic built-in self-test (BIST) is located between the power-on phase and the startup phase.

[0044] In this embodiment of the application, before the BOOT phase, the first self-test circuit 312 performs a first logic built-in self-test (BIST) on the first circuit 311 used in the BOOT phase. Before the first running phase, the second self-test circuit 322 performs a second logic built-in self-test (BIST) on the second circuit 321 used in the first running phase. This ensures that the automotive-grade chip has completed the corresponding logic built-in self-test before each phase, thereby improving the efficiency of the automotive-grade chip and saving the startup time of the automotive-grade chip.

[0045] The integrated circuit 30 in this embodiment further includes: a third circuit 331 and a third self-test circuit 332; the third circuit 331 is used to operate in a second operating phase, which is after the first operating phase; the third self-test circuit 332 is used to perform a third logic built-in self-test (BIST) on the third circuit 331 before the second operating phase.

[0046] Specifically, the first operating phase is followed by the second operating phase; the first operating phase is after the startup phase (BOOT), and the second operating phase is after the first operating phase.

[0047] During the boot phase of integrated circuit 30, only the second self-test circuit 322 may perform the second logic built-in self-test (BIST), or the second self-test circuit 322 may perform the second logic built-in self-test (BIST) and the third self-test circuit 332 may also perform the third logic built-in self-test (BIST). The second logic built-in self-test (BIST) is a self-test function embedded in the design of the second self-test circuit 322, and the third logic built-in self-test (BIST) is a self-test function embedded in the design of the third self-test circuit 332.

[0048] It should be noted that during the startup phase of integrated circuit 30, only the third self-test circuit 332 can perform the third logic built-in self-test BIST. In this case, the second logic built-in self-test BIST runs between the power-on phase and the startup phase.

[0049] It is understandable that the second logic built-in self-test BIST is performed during the boot phase. The boot phase time period can completely overlap with the second logic built-in self-test BIST time period, or the boot phase time period can partially overlap with the second logic built-in self-test time period. Similarly, the third logic built-in self-test BIST is performed during the boot phase. The boot phase time period can completely overlap with the third logic built-in self-test BIST time period, or the boot phase time period can partially overlap with the third logic built-in self-test BIST time period.

[0050] When only the second self-test circuit 322 performs the second logic built-in self-test BIST during the startup phase (BOOT) of integrated circuit 30, the third self-test circuit 332 performs the third logic built-in self-test BIST during the first operating phase. In this case, the time period of the third logic built-in self-test BIST overlaps with the time period of the first operating phase, which can be a complete overlap or a partial overlap. Alternatively, when only the second self-test circuit 322 performs the second logic built-in self-test BIST during the startup phase (BOOT) of integrated circuit 30, the third self-test circuit 332 performs the third logic built-in self-test BIST during the time gap between the startup phase (BOOT) and the first operating phase.

[0051] The integrated circuit 30 in this embodiment further includes: a fourth circuit 341 and a fourth self-test circuit 342; the fourth circuit 341 is used to operate in a third operating phase, which is after the second operating phase; the fourth self-test circuit 342 is used to perform a fourth logic built-in self-test (BIST) on the fourth circuit 341 before the third operating phase.

[0052] Specifically, the second operating phase is followed by a third operating phase, which occurs after the second operating phase. The fourth logic built-in self-test (BIST) is a self-test function embedded in the design of the fourth self-test circuit 342.

[0053] Specifically, when the third self-test circuit 332 performs the third logic built-in self-test BIST during the startup phase (BOOT), the fourth self-test circuit 342 can also perform the fourth logic built-in self-test BIST during the startup phase (BOOT), or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST during the time gap between the startup phase (BOOT) and the first operating phase, or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST during the first operating phase, or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST during the time gap between the first operating phase and the second operating phase, or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST during the second operating phase, or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST during the time gap between the second operating phase and the third operating phase.

[0054] Specifically, when the third self-test circuit 332 performs the third logic built-in self-test BIST in the first operating phase, the fourth self-test circuit 342 can also perform the fourth logic built-in self-test BIST in the first operating phase, or the fourth self-test circuit 342 performs the fourth logic built-in self-test BIST during the time gap between the first operating phase and the second operating phase; or the fourth self-test circuit 342 can perform the fourth logic built-in self-test BIST in the second operating phase, or the fourth self-test circuit 342 performs the fourth logic built-in self-test BIST during the time gap between the second operating phase and the third operating phase.

[0055] Specifically, when the third self-test circuit 332 performs the third logic built-in self-test BIST during the time gap between the first operation phase and the second operation phase, the fourth self-test circuit 342 can also perform the fourth logic built-in self-test BIST during the time gap between the first operation phase and the second operation phase, or the fourth self-test circuit 342 performs the fourth logic built-in self-test BIST during the second operation phase, or the fourth self-test circuit 342 performs the fourth logic built-in self-test BIST during the time gap between the second operation phase and the third operation phase.

[0056] It is understandable that the fourth logic built-in self-test (BIST) is performed during the startup phase (BOOT). The startup phase time period and the fourth logic built-in self-test BIST time period can completely overlap, or they can partially overlap. The fourth logic built-in self-test BIST is performed during the first running phase. The first running phase and its time period can completely overlap, or they can partially overlap. The fourth logic built-in self-test BIST is performed during the second running phase. The second running phase and its time period can completely overlap, or they can partially overlap.

[0057] It should be noted that the third logic built-in self-test BIST corresponding to the third self-test circuit 332 and the fourth logic built-in self-test BIST corresponding to the fourth self-test circuit 342 in this embodiment can both run in parallel with the BOOT phase. Furthermore, the second, third, and fourth logic built-in self-test BISTs running in parallel during the BOOT phase are operated by the corresponding second, third, and fourth self-test circuits 322, 332, and 342, respectively, and are different from the first circuit 311 used during the BOOT phase. Therefore, the multiple parallel tasks are performed by different circuits, and thus there is no interference between the parallel tasks, ensuring the independence of the multiple parallel tasks.

[0058] The number of self-test circuits in the parallel logic built-in self-test BIST during the boot phase is related to the boot phase duration. If the boot phase duration is short, only the second self-test circuit 322 can perform the second logic built-in self-test BIST. If the boot phase duration is long, both the second self-test circuit 322 and the third self-test circuit 332 can perform logic built-in self-tests, or the second self-test circuit 322, the third self-test circuit 332, and the fourth self-test circuit 342 can all perform logic built-in self-tests. This allows the logic built-in self-test BIST to be performed on the circuits used in the operation phase during the boot phase as much as possible, thereby minimizing the total boot time of the automotive-grade chip.

[0059] Integrated circuit 30 may further include a fifth circuit and a fifth self-test circuit that performs a fifth logic built-in self-test (BIST) on the fifth circuit. The fifth circuit is used to operate in a fourth operating phase, which is after the third operating phase. The fifth self-test circuit performs the fifth logic built-in self-test (BIST) before the fourth operating phase. Integrated circuit 30 may further include a sixth circuit and a sixth self-test circuit that performs a sixth logic built-in self-test (BIST) on the sixth circuit. The sixth circuit is used to operate in a fifth operating phase, which is after the fourth operating phase. The sixth self-test circuit performs the sixth logic built-in self-test (BIST) before the fifth operating phase.

[0060] In other words, the integrated circuit 30 includes N circuits and N self-test circuits that perform built-in logic self-tests (BISTs) on each circuit. The first circuit runs during the startup phase, the second circuit runs during the first operating phase, the third circuit runs during the second operating phase, and so on, with the Nth circuit running during the (N-1)th operating phase. In this embodiment, the Nth built-in logic self-test is performed before the (N-1)th operating phase. The N built-in logic self-tests are performed sequentially: the first built-in logic self-test precedes the second, the second precedes the third, and so on, with the (N-1)th built-in logic self-test preceding the Nth.

[0061] It is not difficult to see that the above embodiments are integrated circuit embodiments corresponding to the method embodiments, and the above embodiments can be implemented in conjunction with the integrated circuit embodiments. The relevant technical details mentioned in the integrated circuit embodiments are still valid in the above embodiments, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in the above embodiments can also be applied to the integrated circuit embodiments.

[0062] Another aspect of this application provides a radar chip, including an integrated circuit as described in any of the preceding embodiments.

[0063] It is not difficult to see that the above embodiments are chip embodiments corresponding to the circuit embodiments, and the above embodiments can be implemented in conjunction with the chip embodiments. The relevant technical details mentioned in the chip embodiments remain valid in the above embodiments, and will not be repeated here to avoid repetition. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to the chip embodiments.

[0064] Other embodiments of this application relate to a radar sensor, including: a carrier, an integrated circuit 30 disposed on the carrier, and an antenna disposed on the carrier, or the antenna and integrated circuit are integrated into a single device disposed on the carrier. The integrated circuit is connected to the antenna and is used to process the echo signal received by the antenna. The integrated circuit is the one provided in the foregoing embodiments.

[0065] When the antenna and integrated circuit are not integrated into a single device, the integrated circuit is connected to the antenna via a first transmission line, which can be a printed circuit board (PCB) trace. The carrier can be a printed circuit board (PCB), such as a development board, data acquisition board, or the motherboard of a device, etc., which will not be elaborated on here.

[0066] Since the structure and working principle of the integrated circuits included in the radar sensor have been described in detail in the above embodiments, they will not be repeated here.

[0067] It is not difficult to see that the above embodiments are device embodiments corresponding to the circuit embodiments, and the above embodiments can be implemented in conjunction with the circuit embodiments. The relevant technical details mentioned in the circuit embodiments remain valid in the above embodiments, and will not be repeated here to avoid repetition. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to the circuit embodiments.

[0068] This application provides an electronic device, which may include: a device body; and a radar sensor as described above disposed on the device body; wherein the radar sensor is used for target detection and / or communication to provide measurement information to the operation of the device body.

[0069] In some embodiments, the radar sensor may be disposed on the exterior of the device body; in other embodiments, the radar sensor may be disposed on the interior of the device body; and in still other embodiments, the radar sensor may be partially disposed on the interior and partially disposed on the exterior of the device body. This application does not limit the specific embodiments; the choice depends on the circumstances.

[0070] It should be noted that radar sensors can achieve functions such as target detection by transmitting and receiving radio signals, providing measurement information of the detected target to the device itself, thereby assisting or even controlling the operation of the device. Examples of measurement information include at least one of relative distance, relative speed, and relative angle.

[0071] In some embodiments, the device body described above can be a component or product applied in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments used to detect vital signs parameters and various devices equipped with such instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, intelligent medical devices, and consumer electronic devices.

[0072] In some embodiments, when the aforementioned device body is applied to an Advanced Driving Assistance System (ADAS), the radar sensor, as an on-board sensor, can provide various functional safety guarantees for the ADAS system, such as Automatic Emergency Braking (AEB), Blind Spot Detection (BSD), Lane Changing Assist (LCA), and Rear Cross Traffic Alert (RCTA).

[0073] Furthermore, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The terms "embodiment" or "example" appearing in various locations in the specification do not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0074] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A self-detection method applied in an integrated circuit, the method comprising: performing a first logic built-in self-test after a power-on phase and before a start-up phase of the integrated circuit; performing a second logic built-in self-test before a first run phase of the integrated circuit, the first run phase being after the start-up phase.

2. The self-detection method of claim 1, wherein, A time period of the second logic built-in self-test overlaps with a time period of the start-up phase.

3. The self-detection method of claim 1, wherein, performing a third logic built-in self-test before a second run phase of the integrated circuit, the second run phase being after the first run phase.

4. The self-detection method of claim 3, wherein, A time period of the third logic built-in self-test overlaps with a time period of the first run phase.

5. The self-detection method of claim 3, wherein, performing a fourth logic built-in self-test before a third run phase of the integrated circuit, the third run phase being after the second run phase.

6. The self-detection method of claim 5, wherein, performing the fourth logic built-in self-test after the second run phase.

7. The self-detection method of claim 1, wherein, performing an N+1 logic built-in self-test before an Nth run phase of the integrated circuit, N being a natural number greater than 1; the Nth run phase being after an (N-1)th run phase.

8. An integrated circuit, wherein, comprising: a first circuit, a second circuit, a first self-test circuit, a second self-test circuit; the first circuit is configured to operate in a start-up phase; the second circuit is configured to operate in a first run phase; the first run phase being after the start-up phase; the first self-test circuit is configured to perform a first logic built-in self-test on the first circuit after a power-on phase and before the start-up phase; the second self-test circuit is configured to perform a second logic built-in self-test on the second circuit before the first run phase.

9. The integrated circuit of claim 8, wherein, the integrated circuit further comprises: a third circuit, a third self-test circuit; the third circuit is configured to operate in a second run phase; the second run phase being after the first run phase; the third self-test circuit is configured to perform a third logic built-in self-test on the third circuit before the second run phase.

10. The integrated circuit of claim 9, wherein, the integrated circuit further comprises: a fourth circuit, a fourth self-test circuit; the fourth circuit is configured to operate in a third run phase; the third run phase being after the second run phase; the fourth self-test circuit is configured to perform a fourth logic built-in self-test on the fourth circuit before the third run phase.

11. A radar chip, wherein, comprising: the integrated circuit of any one of claims 8-10.

12. A radar sensor, wherein, comprising: a carrier; the integrated circuit of any one of claims 8-10 is disposed on the carrier; an antenna is disposed on the carrier, or the antenna is disposed on the carrier as an integrated device with the integrated circuit; wherein the integrated circuit is connected with the antenna for transmitting a radio frequency transmission signal and / or receiving a radio frequency reception signal.

13. An electronic device, comprising: comprising: a device body; the radar sensor of claim 12 is disposed on the device body; wherein the radar sensor is configured to provide measurement information.

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